1 /* 2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _SOC_DPORT_REG_H_ 7 #define _SOC_DPORT_REG_H_ 8 9 #include "soc.h" 10 11 #ifndef __ASSEMBLER__ 12 #include "dport_access.h" 13 #endif 14 15 /* Registers defined in this header file must be accessed using special macros, 16 * prefixed with DPORT_. See soc/dport_access.h file for details. 17 */ 18 19 #define DPORT_PRO_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x000) 20 /* DPORT_PRO_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */ 21 /*description: */ 22 #define DPORT_PRO_BOOT_REMAP (BIT(0)) 23 #define DPORT_PRO_BOOT_REMAP_M (BIT(0)) 24 #define DPORT_PRO_BOOT_REMAP_V 0x1 25 #define DPORT_PRO_BOOT_REMAP_S 0 26 27 #define DPORT_APP_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x004) 28 /* DPORT_APP_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */ 29 /*description: */ 30 #define DPORT_APP_BOOT_REMAP (BIT(0)) 31 #define DPORT_APP_BOOT_REMAP_M (BIT(0)) 32 #define DPORT_APP_BOOT_REMAP_V 0x1 33 #define DPORT_APP_BOOT_REMAP_S 0 34 35 #define DPORT_ACCESS_CHECK_REG (DR_REG_DPORT_BASE + 0x008) 36 /* DPORT_ACCESS_CHECK_APP : RO ;bitpos:[8] ;default: 1'b0 ; */ 37 /*description: */ 38 #define DPORT_ACCESS_CHECK_APP (BIT(8)) 39 #define DPORT_ACCESS_CHECK_APP_M (BIT(8)) 40 #define DPORT_ACCESS_CHECK_APP_V 0x1 41 #define DPORT_ACCESS_CHECK_APP_S 8 42 /* DPORT_ACCESS_CHECK_PRO : RO ;bitpos:[0] ;default: 1'b0 ; */ 43 /*description: */ 44 #define DPORT_ACCESS_CHECK_PRO (BIT(0)) 45 #define DPORT_ACCESS_CHECK_PRO_M (BIT(0)) 46 #define DPORT_ACCESS_CHECK_PRO_V 0x1 47 #define DPORT_ACCESS_CHECK_PRO_S 0 48 49 #define DPORT_PRO_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x00C) 50 /* DPORT_PRODPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 51 /*description: */ 52 #define DPORT_PRODPORT_APB_MASK0 0xFFFFFFFF 53 #define DPORT_PRODPORT_APB_MASK0_M ((DPORT_PRODPORT_APB_MASK0_V)<<(DPORT_PRODPORT_APB_MASK0_S)) 54 #define DPORT_PRODPORT_APB_MASK0_V 0xFFFFFFFF 55 #define DPORT_PRODPORT_APB_MASK0_S 0 56 57 #define DPORT_PRO_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x010) 58 /* DPORT_PRODPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 59 /*description: */ 60 #define DPORT_PRODPORT_APB_MASK1 0xFFFFFFFF 61 #define DPORT_PRODPORT_APB_MASK1_M ((DPORT_PRODPORT_APB_MASK1_V)<<(DPORT_PRODPORT_APB_MASK1_S)) 62 #define DPORT_PRODPORT_APB_MASK1_V 0xFFFFFFFF 63 #define DPORT_PRODPORT_APB_MASK1_S 0 64 65 #define DPORT_APP_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x014) 66 /* DPORT_APPDPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 67 /*description: */ 68 #define DPORT_APPDPORT_APB_MASK0 0xFFFFFFFF 69 #define DPORT_APPDPORT_APB_MASK0_M ((DPORT_APPDPORT_APB_MASK0_V)<<(DPORT_APPDPORT_APB_MASK0_S)) 70 #define DPORT_APPDPORT_APB_MASK0_V 0xFFFFFFFF 71 #define DPORT_APPDPORT_APB_MASK0_S 0 72 73 #define DPORT_APP_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x018) 74 /* DPORT_APPDPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 75 /*description: */ 76 #define DPORT_APPDPORT_APB_MASK1 0xFFFFFFFF 77 #define DPORT_APPDPORT_APB_MASK1_M ((DPORT_APPDPORT_APB_MASK1_V)<<(DPORT_APPDPORT_APB_MASK1_S)) 78 #define DPORT_APPDPORT_APB_MASK1_V 0xFFFFFFFF 79 #define DPORT_APPDPORT_APB_MASK1_S 0 80 81 #define DPORT_PERI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x01C) 82 /* DPORT_PERI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 83 /*description: */ 84 #define DPORT_PERI_CLK_EN 0xFFFFFFFF 85 #define DPORT_PERI_CLK_EN_M ((DPORT_PERI_CLK_EN_V)<<(DPORT_PERI_CLK_EN_S)) 86 #define DPORT_PERI_CLK_EN_V 0xFFFFFFFF 87 #define DPORT_PERI_CLK_EN_S 0 88 89 #define DPORT_PERI_RST_EN_REG (DR_REG_DPORT_BASE + 0x020) 90 /* DPORT_PERI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 91 /*description: */ 92 #define DPORT_PERI_RST_EN 0xFFFFFFFF 93 #define DPORT_PERI_RST_EN_M ((DPORT_PERI_RST_EN_V)<<(DPORT_PERI_RST_EN_S)) 94 #define DPORT_PERI_RST_EN_V 0xFFFFFFFF 95 #define DPORT_PERI_RST_EN_S 0 96 97 /* The following bits apply to DPORT_PERI_CLK_EN_REG, DPORT_PERI_RST_EN_REG 98 */ 99 #define DPORT_PERI_EN_AES (1<<0) 100 #define DPORT_PERI_EN_SHA (1<<1) 101 #define DPORT_PERI_EN_RSA (1<<2) 102 /* NB: Secure boot reset will hold SHA & AES in reset */ 103 #define DPORT_PERI_EN_SECUREBOOT (1<<3) 104 /* NB: Digital signature reset will hold AES & RSA in reset */ 105 #define DPORT_PERI_EN_DIGITAL_SIGNATURE (1<<4) 106 107 #define DPORT_WIFI_BB_CFG_REG (DR_REG_DPORT_BASE + 0x024) 108 /* DPORT_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 109 /*description: */ 110 #define DPORT_WIFI_BB_CFG 0xFFFFFFFF 111 #define DPORT_WIFI_BB_CFG_M ((DPORT_WIFI_BB_CFG_V)<<(DPORT_WIFI_BB_CFG_S)) 112 #define DPORT_WIFI_BB_CFG_V 0xFFFFFFFF 113 #define DPORT_WIFI_BB_CFG_S 0 114 115 #define DPORT_WIFI_BB_CFG_2_REG (DR_REG_DPORT_BASE + 0x028) 116 /* DPORT_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 117 /*description: */ 118 #define DPORT_WIFI_BB_CFG_2 0xFFFFFFFF 119 #define DPORT_WIFI_BB_CFG_2_M ((DPORT_WIFI_BB_CFG_2_V)<<(DPORT_WIFI_BB_CFG_2_S)) 120 #define DPORT_WIFI_BB_CFG_2_V 0xFFFFFFFF 121 #define DPORT_WIFI_BB_CFG_2_S 0 122 123 #define DPORT_APPCPU_CTRL_A_REG (DR_REG_DPORT_BASE + 0x02C) 124 /* DPORT_APPCPU_RESETTING : R/W ;bitpos:[0] ;default: 1'b1 ; */ 125 /*description: */ 126 #define DPORT_APPCPU_RESETTING (BIT(0)) 127 #define DPORT_APPCPU_RESETTING_M (BIT(0)) 128 #define DPORT_APPCPU_RESETTING_V 0x1 129 #define DPORT_APPCPU_RESETTING_S 0 130 131 #define DPORT_APPCPU_CTRL_B_REG (DR_REG_DPORT_BASE + 0x030) 132 /* DPORT_APPCPU_CLKGATE_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 133 /*description: */ 134 #define DPORT_APPCPU_CLKGATE_EN (BIT(0)) 135 #define DPORT_APPCPU_CLKGATE_EN_M (BIT(0)) 136 #define DPORT_APPCPU_CLKGATE_EN_V 0x1 137 #define DPORT_APPCPU_CLKGATE_EN_S 0 138 139 #define DPORT_APPCPU_CTRL_C_REG (DR_REG_DPORT_BASE + 0x034) 140 /* DPORT_APPCPU_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */ 141 /*description: */ 142 #define DPORT_APPCPU_RUNSTALL (BIT(0)) 143 #define DPORT_APPCPU_RUNSTALL_M (BIT(0)) 144 #define DPORT_APPCPU_RUNSTALL_V 0x1 145 #define DPORT_APPCPU_RUNSTALL_S 0 146 147 #define DPORT_APPCPU_CTRL_D_REG (DR_REG_DPORT_BASE + 0x038) 148 /* DPORT_APPCPU_BOOT_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 149 /*description: */ 150 #define DPORT_APPCPU_BOOT_ADDR 0xFFFFFFFF 151 #define DPORT_APPCPU_BOOT_ADDR_M ((DPORT_APPCPU_BOOT_ADDR_V)<<(DPORT_APPCPU_BOOT_ADDR_S)) 152 #define DPORT_APPCPU_BOOT_ADDR_V 0xFFFFFFFF 153 #define DPORT_APPCPU_BOOT_ADDR_S 0 154 155 #define DPORT_CPU_PER_CONF_REG (DR_REG_DPORT_BASE + 0x03C) 156 /* DPORT_FAST_CLK_RTC_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */ 157 /*description: */ 158 #define DPORT_FAST_CLK_RTC_SEL (BIT(3)) 159 #define DPORT_FAST_CLK_RTC_SEL_M (BIT(3)) 160 #define DPORT_FAST_CLK_RTC_SEL_V 0x1 161 #define DPORT_FAST_CLK_RTC_SEL_S 3 162 /* DPORT_LOWSPEED_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ 163 /*description: */ 164 #define DPORT_LOWSPEED_CLK_SEL (BIT(2)) 165 #define DPORT_LOWSPEED_CLK_SEL_M (BIT(2)) 166 #define DPORT_LOWSPEED_CLK_SEL_V 0x1 167 #define DPORT_LOWSPEED_CLK_SEL_S 2 168 /* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 169 /*description: */ 170 #define DPORT_CPUPERIOD_SEL 0x00000003 171 #define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S)) 172 #define DPORT_CPUPERIOD_SEL_V 0x3 173 #define DPORT_CPUPERIOD_SEL_S 0 174 175 #define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040) 176 /* DPORT_PRO_DRAM_HL : R/W ;bitpos:[16] ;default: 1'b0 ; */ 177 /*description: */ 178 #define DPORT_PRO_DRAM_HL (BIT(16)) 179 #define DPORT_PRO_DRAM_HL_M (BIT(16)) 180 #define DPORT_PRO_DRAM_HL_V 0x1 181 #define DPORT_PRO_DRAM_HL_S 16 182 /* DPORT_SLAVE_REQ : RO ;bitpos:[15] ;default: 1'b0 ; */ 183 /*description: */ 184 #define DPORT_SLAVE_REQ (BIT(15)) 185 #define DPORT_SLAVE_REQ_M (BIT(15)) 186 #define DPORT_SLAVE_REQ_V 0x1 187 #define DPORT_SLAVE_REQ_S 15 188 /* DPORT_AHB_SPI_REQ : RO ;bitpos:[14] ;default: 1'b0 ; */ 189 /*description: */ 190 #define DPORT_AHB_SPI_REQ (BIT(14)) 191 #define DPORT_AHB_SPI_REQ_M (BIT(14)) 192 #define DPORT_AHB_SPI_REQ_V 0x1 193 #define DPORT_AHB_SPI_REQ_S 14 194 /* DPORT_PRO_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */ 195 /*description: */ 196 #define DPORT_PRO_SLAVE_REQ (BIT(13)) 197 #define DPORT_PRO_SLAVE_REQ_M (BIT(13)) 198 #define DPORT_PRO_SLAVE_REQ_V 0x1 199 #define DPORT_PRO_SLAVE_REQ_S 13 200 /* DPORT_PRO_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */ 201 /*description: */ 202 #define DPORT_PRO_AHB_SPI_REQ (BIT(12)) 203 #define DPORT_PRO_AHB_SPI_REQ_M (BIT(12)) 204 #define DPORT_PRO_AHB_SPI_REQ_V 0x1 205 #define DPORT_PRO_AHB_SPI_REQ_S 12 206 /* DPORT_PRO_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */ 207 /*description: */ 208 #define DPORT_PRO_DRAM_SPLIT (BIT(11)) 209 #define DPORT_PRO_DRAM_SPLIT_M (BIT(11)) 210 #define DPORT_PRO_DRAM_SPLIT_V 0x1 211 #define DPORT_PRO_DRAM_SPLIT_S 11 212 /* DPORT_PRO_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 213 /*description: */ 214 #define DPORT_PRO_SINGLE_IRAM_ENA (BIT(10)) 215 #define DPORT_PRO_SINGLE_IRAM_ENA_M (BIT(10)) 216 #define DPORT_PRO_SINGLE_IRAM_ENA_V 0x1 217 #define DPORT_PRO_SINGLE_IRAM_ENA_S 10 218 /* DPORT_PRO_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ 219 /*description: */ 220 #define DPORT_PRO_CACHE_LOCK_3_EN (BIT(9)) 221 #define DPORT_PRO_CACHE_LOCK_3_EN_M (BIT(9)) 222 #define DPORT_PRO_CACHE_LOCK_3_EN_V 0x1 223 #define DPORT_PRO_CACHE_LOCK_3_EN_S 9 224 /* DPORT_PRO_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 225 /*description: */ 226 #define DPORT_PRO_CACHE_LOCK_2_EN (BIT(8)) 227 #define DPORT_PRO_CACHE_LOCK_2_EN_M (BIT(8)) 228 #define DPORT_PRO_CACHE_LOCK_2_EN_V 0x1 229 #define DPORT_PRO_CACHE_LOCK_2_EN_S 8 230 /* DPORT_PRO_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 231 /*description: */ 232 #define DPORT_PRO_CACHE_LOCK_1_EN (BIT(7)) 233 #define DPORT_PRO_CACHE_LOCK_1_EN_M (BIT(7)) 234 #define DPORT_PRO_CACHE_LOCK_1_EN_V 0x1 235 #define DPORT_PRO_CACHE_LOCK_1_EN_S 7 236 /* DPORT_PRO_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 237 /*description: */ 238 #define DPORT_PRO_CACHE_LOCK_0_EN (BIT(6)) 239 #define DPORT_PRO_CACHE_LOCK_0_EN_M (BIT(6)) 240 #define DPORT_PRO_CACHE_LOCK_0_EN_V 0x1 241 #define DPORT_PRO_CACHE_LOCK_0_EN_S 6 242 /* DPORT_PRO_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */ 243 /*description: */ 244 #define DPORT_PRO_CACHE_FLUSH_DONE (BIT(5)) 245 #define DPORT_PRO_CACHE_FLUSH_DONE_M (BIT(5)) 246 #define DPORT_PRO_CACHE_FLUSH_DONE_V 0x1 247 #define DPORT_PRO_CACHE_FLUSH_DONE_S 5 248 /* DPORT_PRO_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */ 249 /*description: */ 250 #define DPORT_PRO_CACHE_FLUSH_ENA (BIT(4)) 251 #define DPORT_PRO_CACHE_FLUSH_ENA_M (BIT(4)) 252 #define DPORT_PRO_CACHE_FLUSH_ENA_V 0x1 253 #define DPORT_PRO_CACHE_FLUSH_ENA_S 4 254 /* DPORT_PRO_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 255 /*description: */ 256 #define DPORT_PRO_CACHE_ENABLE (BIT(3)) 257 #define DPORT_PRO_CACHE_ENABLE_M (BIT(3)) 258 #define DPORT_PRO_CACHE_ENABLE_V 0x1 259 #define DPORT_PRO_CACHE_ENABLE_S 3 260 /* DPORT_PRO_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 261 /*description: */ 262 #define DPORT_PRO_CACHE_MODE (BIT(2)) 263 #define DPORT_PRO_CACHE_MODE_M (BIT(2)) 264 #define DPORT_PRO_CACHE_MODE_V 0x1 265 #define DPORT_PRO_CACHE_MODE_S 2 266 267 #define DPORT_PRO_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x044) 268 /* DPORT_PRO_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */ 269 /*description: */ 270 #define DPORT_PRO_CACHE_MMU_IA_CLR (BIT(13)) 271 #define DPORT_PRO_CACHE_MMU_IA_CLR_M (BIT(13)) 272 #define DPORT_PRO_CACHE_MMU_IA_CLR_V 0x1 273 #define DPORT_PRO_CACHE_MMU_IA_CLR_S 13 274 /* DPORT_PRO_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ 275 /*description: */ 276 #define DPORT_PRO_CMMU_PD (BIT(12)) 277 #define DPORT_PRO_CMMU_PD_M (BIT(12)) 278 #define DPORT_PRO_CMMU_PD_V 0x1 279 #define DPORT_PRO_CMMU_PD_S 12 280 /* DPORT_PRO_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */ 281 /*description: */ 282 #define DPORT_PRO_CMMU_FORCE_ON (BIT(11)) 283 #define DPORT_PRO_CMMU_FORCE_ON_M (BIT(11)) 284 #define DPORT_PRO_CMMU_FORCE_ON_V 0x1 285 #define DPORT_PRO_CMMU_FORCE_ON_S 11 286 /* DPORT_PRO_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */ 287 /*description: */ 288 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE 0x00000003 289 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE_M ((DPORT_PRO_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_PRO_CMMU_FLASH_PAGE_MODE_S)) 290 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE_V 0x3 291 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE_S 9 292 /* DPORT_PRO_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */ 293 /*description: */ 294 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE 0x00000007 295 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE_M ((DPORT_PRO_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_PRO_CMMU_SRAM_PAGE_MODE_S)) 296 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE_V 0x7 297 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE_S 6 298 /* DPORT_PRO_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */ 299 /*description: */ 300 #define DPORT_PRO_CACHE_MASK_OPSDRAM (BIT(5)) 301 #define DPORT_PRO_CACHE_MASK_OPSDRAM_M (BIT(5)) 302 #define DPORT_PRO_CACHE_MASK_OPSDRAM_V 0x1 303 #define DPORT_PRO_CACHE_MASK_OPSDRAM_S 5 304 /* DPORT_PRO_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */ 305 /*description: */ 306 #define DPORT_PRO_CACHE_MASK_DROM0 (BIT(4)) 307 #define DPORT_PRO_CACHE_MASK_DROM0_M (BIT(4)) 308 #define DPORT_PRO_CACHE_MASK_DROM0_V 0x1 309 #define DPORT_PRO_CACHE_MASK_DROM0_S 4 310 /* DPORT_PRO_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ 311 /*description: */ 312 #define DPORT_PRO_CACHE_MASK_DRAM1 (BIT(3)) 313 #define DPORT_PRO_CACHE_MASK_DRAM1_M (BIT(3)) 314 #define DPORT_PRO_CACHE_MASK_DRAM1_V 0x1 315 #define DPORT_PRO_CACHE_MASK_DRAM1_S 3 316 /* DPORT_PRO_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */ 317 /*description: */ 318 #define DPORT_PRO_CACHE_MASK_IROM0 (BIT(2)) 319 #define DPORT_PRO_CACHE_MASK_IROM0_M (BIT(2)) 320 #define DPORT_PRO_CACHE_MASK_IROM0_V 0x1 321 #define DPORT_PRO_CACHE_MASK_IROM0_S 2 322 /* DPORT_PRO_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ 323 /*description: */ 324 #define DPORT_PRO_CACHE_MASK_IRAM1 (BIT(1)) 325 #define DPORT_PRO_CACHE_MASK_IRAM1_M (BIT(1)) 326 #define DPORT_PRO_CACHE_MASK_IRAM1_V 0x1 327 #define DPORT_PRO_CACHE_MASK_IRAM1_S 1 328 /* DPORT_PRO_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ 329 /*description: */ 330 #define DPORT_PRO_CACHE_MASK_IRAM0 (BIT(0)) 331 #define DPORT_PRO_CACHE_MASK_IRAM0_M (BIT(0)) 332 #define DPORT_PRO_CACHE_MASK_IRAM0_V 0x1 333 #define DPORT_PRO_CACHE_MASK_IRAM0_S 0 334 335 #define DPORT_PRO_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x048) 336 /* DPORT_PRO_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 337 /*description: */ 338 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX 0x0000000F 339 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S)) 340 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V 0xF 341 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S 18 342 /* DPORT_PRO_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 343 /*description: */ 344 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN 0x0000000F 345 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S)) 346 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V 0xF 347 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S 14 348 /* DPORT_PRO_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 349 /*description: */ 350 #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE 0x00003FFF 351 #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S)) 352 #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF 353 #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S 0 354 355 #define DPORT_PRO_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x04C) 356 /* DPORT_PRO_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 357 /*description: */ 358 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX 0x0000000F 359 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S)) 360 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V 0xF 361 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S 18 362 /* DPORT_PRO_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 363 /*description: */ 364 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN 0x0000000F 365 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S)) 366 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V 0xF 367 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S 14 368 /* DPORT_PRO_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 369 /*description: */ 370 #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE 0x00003FFF 371 #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S)) 372 #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF 373 #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S 0 374 375 #define DPORT_PRO_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x050) 376 /* DPORT_PRO_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 377 /*description: */ 378 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX 0x0000000F 379 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S)) 380 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V 0xF 381 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S 18 382 /* DPORT_PRO_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 383 /*description: */ 384 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN 0x0000000F 385 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S)) 386 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V 0xF 387 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S 14 388 /* DPORT_PRO_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 389 /*description: */ 390 #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE 0x00003FFF 391 #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S)) 392 #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF 393 #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S 0 394 395 #define DPORT_PRO_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x054) 396 /* DPORT_PRO_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 397 /*description: */ 398 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX 0x0000000F 399 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S)) 400 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V 0xF 401 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S 18 402 /* DPORT_PRO_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 403 /*description: */ 404 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN 0x0000000F 405 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S)) 406 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V 0xF 407 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S 14 408 /* DPORT_PRO_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 409 /*description: */ 410 #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE 0x00003FFF 411 #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S)) 412 #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF 413 #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S 0 414 415 #define DPORT_APP_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x058) 416 /* DPORT_APP_DRAM_HL : R/W ;bitpos:[14] ;default: 1'b0 ; */ 417 /*description: */ 418 #define DPORT_APP_DRAM_HL (BIT(14)) 419 #define DPORT_APP_DRAM_HL_M (BIT(14)) 420 #define DPORT_APP_DRAM_HL_V 0x1 421 #define DPORT_APP_DRAM_HL_S 14 422 /* DPORT_APP_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */ 423 /*description: */ 424 #define DPORT_APP_SLAVE_REQ (BIT(13)) 425 #define DPORT_APP_SLAVE_REQ_M (BIT(13)) 426 #define DPORT_APP_SLAVE_REQ_V 0x1 427 #define DPORT_APP_SLAVE_REQ_S 13 428 /* DPORT_APP_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */ 429 /*description: */ 430 #define DPORT_APP_AHB_SPI_REQ (BIT(12)) 431 #define DPORT_APP_AHB_SPI_REQ_M (BIT(12)) 432 #define DPORT_APP_AHB_SPI_REQ_V 0x1 433 #define DPORT_APP_AHB_SPI_REQ_S 12 434 /* DPORT_APP_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */ 435 /*description: */ 436 #define DPORT_APP_DRAM_SPLIT (BIT(11)) 437 #define DPORT_APP_DRAM_SPLIT_M (BIT(11)) 438 #define DPORT_APP_DRAM_SPLIT_V 0x1 439 #define DPORT_APP_DRAM_SPLIT_S 11 440 /* DPORT_APP_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 441 /*description: */ 442 #define DPORT_APP_SINGLE_IRAM_ENA (BIT(10)) 443 #define DPORT_APP_SINGLE_IRAM_ENA_M (BIT(10)) 444 #define DPORT_APP_SINGLE_IRAM_ENA_V 0x1 445 #define DPORT_APP_SINGLE_IRAM_ENA_S 10 446 /* DPORT_APP_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ 447 /*description: */ 448 #define DPORT_APP_CACHE_LOCK_3_EN (BIT(9)) 449 #define DPORT_APP_CACHE_LOCK_3_EN_M (BIT(9)) 450 #define DPORT_APP_CACHE_LOCK_3_EN_V 0x1 451 #define DPORT_APP_CACHE_LOCK_3_EN_S 9 452 /* DPORT_APP_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 453 /*description: */ 454 #define DPORT_APP_CACHE_LOCK_2_EN (BIT(8)) 455 #define DPORT_APP_CACHE_LOCK_2_EN_M (BIT(8)) 456 #define DPORT_APP_CACHE_LOCK_2_EN_V 0x1 457 #define DPORT_APP_CACHE_LOCK_2_EN_S 8 458 /* DPORT_APP_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 459 /*description: */ 460 #define DPORT_APP_CACHE_LOCK_1_EN (BIT(7)) 461 #define DPORT_APP_CACHE_LOCK_1_EN_M (BIT(7)) 462 #define DPORT_APP_CACHE_LOCK_1_EN_V 0x1 463 #define DPORT_APP_CACHE_LOCK_1_EN_S 7 464 /* DPORT_APP_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 465 /*description: */ 466 #define DPORT_APP_CACHE_LOCK_0_EN (BIT(6)) 467 #define DPORT_APP_CACHE_LOCK_0_EN_M (BIT(6)) 468 #define DPORT_APP_CACHE_LOCK_0_EN_V 0x1 469 #define DPORT_APP_CACHE_LOCK_0_EN_S 6 470 /* DPORT_APP_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */ 471 /*description: */ 472 #define DPORT_APP_CACHE_FLUSH_DONE (BIT(5)) 473 #define DPORT_APP_CACHE_FLUSH_DONE_M (BIT(5)) 474 #define DPORT_APP_CACHE_FLUSH_DONE_V 0x1 475 #define DPORT_APP_CACHE_FLUSH_DONE_S 5 476 /* DPORT_APP_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */ 477 /*description: */ 478 #define DPORT_APP_CACHE_FLUSH_ENA (BIT(4)) 479 #define DPORT_APP_CACHE_FLUSH_ENA_M (BIT(4)) 480 #define DPORT_APP_CACHE_FLUSH_ENA_V 0x1 481 #define DPORT_APP_CACHE_FLUSH_ENA_S 4 482 /* DPORT_APP_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 483 /*description: */ 484 #define DPORT_APP_CACHE_ENABLE (BIT(3)) 485 #define DPORT_APP_CACHE_ENABLE_M (BIT(3)) 486 #define DPORT_APP_CACHE_ENABLE_V 0x1 487 #define DPORT_APP_CACHE_ENABLE_S 3 488 /* DPORT_APP_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 489 /*description: */ 490 #define DPORT_APP_CACHE_MODE (BIT(2)) 491 #define DPORT_APP_CACHE_MODE_M (BIT(2)) 492 #define DPORT_APP_CACHE_MODE_V 0x1 493 #define DPORT_APP_CACHE_MODE_S 2 494 495 #define DPORT_APP_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x05C) 496 /* DPORT_APP_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */ 497 /*description: */ 498 #define DPORT_APP_CACHE_MMU_IA_CLR (BIT(13)) 499 #define DPORT_APP_CACHE_MMU_IA_CLR_M (BIT(13)) 500 #define DPORT_APP_CACHE_MMU_IA_CLR_V 0x1 501 #define DPORT_APP_CACHE_MMU_IA_CLR_S 13 502 /* DPORT_APP_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ 503 /*description: */ 504 #define DPORT_APP_CMMU_PD (BIT(12)) 505 #define DPORT_APP_CMMU_PD_M (BIT(12)) 506 #define DPORT_APP_CMMU_PD_V 0x1 507 #define DPORT_APP_CMMU_PD_S 12 508 /* DPORT_APP_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */ 509 /*description: */ 510 #define DPORT_APP_CMMU_FORCE_ON (BIT(11)) 511 #define DPORT_APP_CMMU_FORCE_ON_M (BIT(11)) 512 #define DPORT_APP_CMMU_FORCE_ON_V 0x1 513 #define DPORT_APP_CMMU_FORCE_ON_S 11 514 /* DPORT_APP_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */ 515 /*description: */ 516 #define DPORT_APP_CMMU_FLASH_PAGE_MODE 0x00000003 517 #define DPORT_APP_CMMU_FLASH_PAGE_MODE_M ((DPORT_APP_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_APP_CMMU_FLASH_PAGE_MODE_S)) 518 #define DPORT_APP_CMMU_FLASH_PAGE_MODE_V 0x3 519 #define DPORT_APP_CMMU_FLASH_PAGE_MODE_S 9 520 /* DPORT_APP_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */ 521 /*description: */ 522 #define DPORT_APP_CMMU_SRAM_PAGE_MODE 0x00000007 523 #define DPORT_APP_CMMU_SRAM_PAGE_MODE_M ((DPORT_APP_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_APP_CMMU_SRAM_PAGE_MODE_S)) 524 #define DPORT_APP_CMMU_SRAM_PAGE_MODE_V 0x7 525 #define DPORT_APP_CMMU_SRAM_PAGE_MODE_S 6 526 /* DPORT_APP_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */ 527 /*description: */ 528 #define DPORT_APP_CACHE_MASK_OPSDRAM (BIT(5)) 529 #define DPORT_APP_CACHE_MASK_OPSDRAM_M (BIT(5)) 530 #define DPORT_APP_CACHE_MASK_OPSDRAM_V 0x1 531 #define DPORT_APP_CACHE_MASK_OPSDRAM_S 5 532 /* DPORT_APP_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */ 533 /*description: */ 534 #define DPORT_APP_CACHE_MASK_DROM0 (BIT(4)) 535 #define DPORT_APP_CACHE_MASK_DROM0_M (BIT(4)) 536 #define DPORT_APP_CACHE_MASK_DROM0_V 0x1 537 #define DPORT_APP_CACHE_MASK_DROM0_S 4 538 /* DPORT_APP_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ 539 /*description: */ 540 #define DPORT_APP_CACHE_MASK_DRAM1 (BIT(3)) 541 #define DPORT_APP_CACHE_MASK_DRAM1_M (BIT(3)) 542 #define DPORT_APP_CACHE_MASK_DRAM1_V 0x1 543 #define DPORT_APP_CACHE_MASK_DRAM1_S 3 544 /* DPORT_APP_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */ 545 /*description: */ 546 #define DPORT_APP_CACHE_MASK_IROM0 (BIT(2)) 547 #define DPORT_APP_CACHE_MASK_IROM0_M (BIT(2)) 548 #define DPORT_APP_CACHE_MASK_IROM0_V 0x1 549 #define DPORT_APP_CACHE_MASK_IROM0_S 2 550 /* DPORT_APP_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ 551 /*description: */ 552 #define DPORT_APP_CACHE_MASK_IRAM1 (BIT(1)) 553 #define DPORT_APP_CACHE_MASK_IRAM1_M (BIT(1)) 554 #define DPORT_APP_CACHE_MASK_IRAM1_V 0x1 555 #define DPORT_APP_CACHE_MASK_IRAM1_S 1 556 /* DPORT_APP_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ 557 /*description: */ 558 #define DPORT_APP_CACHE_MASK_IRAM0 (BIT(0)) 559 #define DPORT_APP_CACHE_MASK_IRAM0_M (BIT(0)) 560 #define DPORT_APP_CACHE_MASK_IRAM0_V 0x1 561 #define DPORT_APP_CACHE_MASK_IRAM0_S 0 562 563 #define DPORT_APP_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x060) 564 /* DPORT_APP_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 565 /*description: */ 566 #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX 0x0000000F 567 #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S)) 568 #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V 0xF 569 #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S 18 570 /* DPORT_APP_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 571 /*description: */ 572 #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN 0x0000000F 573 #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S)) 574 #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V 0xF 575 #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S 14 576 /* DPORT_APP_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 577 /*description: */ 578 #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE 0x00003FFF 579 #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S)) 580 #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF 581 #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S 0 582 583 #define DPORT_APP_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x064) 584 /* DPORT_APP_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 585 /*description: */ 586 #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX 0x0000000F 587 #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S)) 588 #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V 0xF 589 #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S 18 590 /* DPORT_APP_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 591 /*description: */ 592 #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN 0x0000000F 593 #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S)) 594 #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V 0xF 595 #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S 14 596 /* DPORT_APP_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 597 /*description: */ 598 #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE 0x00003FFF 599 #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S)) 600 #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF 601 #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S 0 602 603 #define DPORT_APP_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x068) 604 /* DPORT_APP_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 605 /*description: */ 606 #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX 0x0000000F 607 #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S)) 608 #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V 0xF 609 #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S 18 610 /* DPORT_APP_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 611 /*description: */ 612 #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN 0x0000000F 613 #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S)) 614 #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V 0xF 615 #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S 14 616 /* DPORT_APP_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 617 /*description: */ 618 #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE 0x00003FFF 619 #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S)) 620 #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF 621 #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S 0 622 623 #define DPORT_APP_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x06C) 624 /* DPORT_APP_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 625 /*description: */ 626 #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX 0x0000000F 627 #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S)) 628 #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V 0xF 629 #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S 18 630 /* DPORT_APP_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 631 /*description: */ 632 #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN 0x0000000F 633 #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S)) 634 #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V 0xF 635 #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S 14 636 /* DPORT_APP_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 637 /*description: */ 638 #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE 0x00003FFF 639 #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S)) 640 #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF 641 #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S 0 642 643 #define DPORT_TRACEMEM_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x070) 644 /* DPORT_TRACEMEM_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 645 /*description: */ 646 #define DPORT_TRACEMEM_MUX_MODE 0x00000003 647 #define DPORT_TRACEMEM_MUX_MODE_M ((DPORT_TRACEMEM_MUX_MODE_V)<<(DPORT_TRACEMEM_MUX_MODE_S)) 648 #define DPORT_TRACEMEM_MUX_MODE_V 0x3 649 #define DPORT_TRACEMEM_MUX_MODE_S 0 650 651 #define DPORT_PRO_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x074) 652 /* DPORT_PRO_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 653 /*description: */ 654 #define DPORT_PRO_TRACEMEM_ENA (BIT(0)) 655 #define DPORT_PRO_TRACEMEM_ENA_M (BIT(0)) 656 #define DPORT_PRO_TRACEMEM_ENA_V 0x1 657 #define DPORT_PRO_TRACEMEM_ENA_S 0 658 659 #define DPORT_APP_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x078) 660 /* DPORT_APP_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 661 /*description: */ 662 #define DPORT_APP_TRACEMEM_ENA (BIT(0)) 663 #define DPORT_APP_TRACEMEM_ENA_M (BIT(0)) 664 #define DPORT_APP_TRACEMEM_ENA_V 0x1 665 #define DPORT_APP_TRACEMEM_ENA_S 0 666 667 #define DPORT_CACHE_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x07C) 668 /* DPORT_CACHE_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 669 /*description: */ 670 #define DPORT_CACHE_MUX_MODE 0x00000003 671 #define DPORT_CACHE_MUX_MODE_M ((DPORT_CACHE_MUX_MODE_V)<<(DPORT_CACHE_MUX_MODE_S)) 672 #define DPORT_CACHE_MUX_MODE_V 0x3 673 #define DPORT_CACHE_MUX_MODE_S 0 674 675 #define DPORT_IMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x080) 676 /* DPORT_IMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ 677 /*description: */ 678 #define DPORT_IMMU_PAGE_MODE 0x00000003 679 #define DPORT_IMMU_PAGE_MODE_M ((DPORT_IMMU_PAGE_MODE_V)<<(DPORT_IMMU_PAGE_MODE_S)) 680 #define DPORT_IMMU_PAGE_MODE_V 0x3 681 #define DPORT_IMMU_PAGE_MODE_S 1 682 /* DPORT_INTERNAL_SRAM_IMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 683 /*description: */ 684 #define DPORT_INTERNAL_SRAM_IMMU_ENA (BIT(0)) 685 #define DPORT_INTERNAL_SRAM_IMMU_ENA_M (BIT(0)) 686 #define DPORT_INTERNAL_SRAM_IMMU_ENA_V 0x1 687 #define DPORT_INTERNAL_SRAM_IMMU_ENA_S 0 688 689 #define DPORT_DMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x084) 690 /* DPORT_DMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ 691 /*description: */ 692 #define DPORT_DMMU_PAGE_MODE 0x00000003 693 #define DPORT_DMMU_PAGE_MODE_M ((DPORT_DMMU_PAGE_MODE_V)<<(DPORT_DMMU_PAGE_MODE_S)) 694 #define DPORT_DMMU_PAGE_MODE_V 0x3 695 #define DPORT_DMMU_PAGE_MODE_S 1 696 /* DPORT_INTERNAL_SRAM_DMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 697 /*description: */ 698 #define DPORT_INTERNAL_SRAM_DMMU_ENA (BIT(0)) 699 #define DPORT_INTERNAL_SRAM_DMMU_ENA_M (BIT(0)) 700 #define DPORT_INTERNAL_SRAM_DMMU_ENA_V 0x1 701 #define DPORT_INTERNAL_SRAM_DMMU_ENA_S 0 702 703 #define DPORT_ROM_MPU_ENA_REG (DR_REG_DPORT_BASE + 0x088) 704 /* DPORT_APP_ROM_MPU_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 705 /*description: */ 706 #define DPORT_APP_ROM_MPU_ENA (BIT(2)) 707 #define DPORT_APP_ROM_MPU_ENA_M (BIT(2)) 708 #define DPORT_APP_ROM_MPU_ENA_V 0x1 709 #define DPORT_APP_ROM_MPU_ENA_S 2 710 /* DPORT_PRO_ROM_MPU_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 711 /*description: */ 712 #define DPORT_PRO_ROM_MPU_ENA (BIT(1)) 713 #define DPORT_PRO_ROM_MPU_ENA_M (BIT(1)) 714 #define DPORT_PRO_ROM_MPU_ENA_V 0x1 715 #define DPORT_PRO_ROM_MPU_ENA_S 1 716 /* DPORT_SHARE_ROM_MPU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 717 /*description: */ 718 #define DPORT_SHARE_ROM_MPU_ENA (BIT(0)) 719 #define DPORT_SHARE_ROM_MPU_ENA_M (BIT(0)) 720 #define DPORT_SHARE_ROM_MPU_ENA_V 0x1 721 #define DPORT_SHARE_ROM_MPU_ENA_S 0 722 723 #define DPORT_MEM_PD_MASK_REG (DR_REG_DPORT_BASE + 0x08C) 724 /* DPORT_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ 725 /*description: */ 726 #define DPORT_LSLP_MEM_PD_MASK (BIT(0)) 727 #define DPORT_LSLP_MEM_PD_MASK_M (BIT(0)) 728 #define DPORT_LSLP_MEM_PD_MASK_V 0x1 729 #define DPORT_LSLP_MEM_PD_MASK_S 0 730 731 #define DPORT_ROM_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x090) 732 /* DPORT_SHARE_ROM_PD : R/W ;bitpos:[7:2] ;default: 6'h0 ; */ 733 /*description: */ 734 #define DPORT_SHARE_ROM_PD 0x0000003F 735 #define DPORT_SHARE_ROM_PD_M ((DPORT_SHARE_ROM_PD_V)<<(DPORT_SHARE_ROM_PD_S)) 736 #define DPORT_SHARE_ROM_PD_V 0x3F 737 #define DPORT_SHARE_ROM_PD_S 2 738 /* DPORT_APP_ROM_PD : R/W ;bitpos:[1] ;default: 1'h0 ; */ 739 /*description: */ 740 #define DPORT_APP_ROM_PD (BIT(1)) 741 #define DPORT_APP_ROM_PD_M (BIT(1)) 742 #define DPORT_APP_ROM_PD_V 0x1 743 #define DPORT_APP_ROM_PD_S 1 744 /* DPORT_PRO_ROM_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */ 745 /*description: */ 746 #define DPORT_PRO_ROM_PD (BIT(0)) 747 #define DPORT_PRO_ROM_PD_M (BIT(0)) 748 #define DPORT_PRO_ROM_PD_V 0x1 749 #define DPORT_PRO_ROM_PD_S 0 750 751 #define DPORT_ROM_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x094) 752 /* DPORT_SHARE_ROM_FO : R/W ;bitpos:[7:2] ;default: 6'h0 ; */ 753 /*description: */ 754 #define DPORT_SHARE_ROM_FO 0x0000003F 755 #define DPORT_SHARE_ROM_FO_M ((DPORT_SHARE_ROM_FO_V)<<(DPORT_SHARE_ROM_FO_S)) 756 #define DPORT_SHARE_ROM_FO_V 0x3F 757 #define DPORT_SHARE_ROM_FO_S 2 758 /* DPORT_APP_ROM_FO : R/W ;bitpos:[1] ;default: 1'h1 ; */ 759 /*description: */ 760 #define DPORT_APP_ROM_FO (BIT(1)) 761 #define DPORT_APP_ROM_FO_M (BIT(1)) 762 #define DPORT_APP_ROM_FO_V 0x1 763 #define DPORT_APP_ROM_FO_S 1 764 /* DPORT_PRO_ROM_FO : R/W ;bitpos:[0] ;default: 1'h1 ; */ 765 /*description: */ 766 #define DPORT_PRO_ROM_FO (BIT(0)) 767 #define DPORT_PRO_ROM_FO_M (BIT(0)) 768 #define DPORT_PRO_ROM_FO_V 0x1 769 #define DPORT_PRO_ROM_FO_S 0 770 771 #define DPORT_SRAM_PD_CTRL_0_REG (DR_REG_DPORT_BASE + 0x098) 772 /* DPORT_SRAM_PD_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 773 /*description: */ 774 #define DPORT_SRAM_PD_0 0xFFFFFFFF 775 #define DPORT_SRAM_PD_0_M ((DPORT_SRAM_PD_0_V)<<(DPORT_SRAM_PD_0_S)) 776 #define DPORT_SRAM_PD_0_V 0xFFFFFFFF 777 #define DPORT_SRAM_PD_0_S 0 778 779 #define DPORT_SRAM_PD_CTRL_1_REG (DR_REG_DPORT_BASE + 0x09C) 780 /* DPORT_SRAM_PD_1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ 781 /*description: */ 782 #define DPORT_SRAM_PD_1 (BIT(0)) 783 #define DPORT_SRAM_PD_1_M (BIT(0)) 784 #define DPORT_SRAM_PD_1_V 0x1 785 #define DPORT_SRAM_PD_1_S 0 786 787 #define DPORT_SRAM_FO_CTRL_0_REG (DR_REG_DPORT_BASE + 0x0A0) 788 /* DPORT_SRAM_FO_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ 789 /*description: */ 790 #define DPORT_SRAM_FO_0 0xFFFFFFFF 791 #define DPORT_SRAM_FO_0_M ((DPORT_SRAM_FO_0_V)<<(DPORT_SRAM_FO_0_S)) 792 #define DPORT_SRAM_FO_0_V 0xFFFFFFFF 793 #define DPORT_SRAM_FO_0_S 0 794 795 #define DPORT_SRAM_FO_CTRL_1_REG (DR_REG_DPORT_BASE + 0x0A4) 796 /* DPORT_SRAM_FO_1 : R/W ;bitpos:[0] ;default: 1'h1 ; */ 797 /*description: */ 798 #define DPORT_SRAM_FO_1 (BIT(0)) 799 #define DPORT_SRAM_FO_1_M (BIT(0)) 800 #define DPORT_SRAM_FO_1_V 0x1 801 #define DPORT_SRAM_FO_1_S 0 802 803 #define DPORT_IRAM_DRAM_AHB_SEL_REG (DR_REG_DPORT_BASE + 0x0A8) 804 /* DPORT_MAC_DUMP_MODE : R/W ;bitpos:[6:5] ;default: 2'h0 ; */ 805 /*description: */ 806 #define DPORT_MAC_DUMP_MODE 0x00000003 807 #define DPORT_MAC_DUMP_MODE_M ((DPORT_MAC_DUMP_MODE_V)<<(DPORT_MAC_DUMP_MODE_S)) 808 #define DPORT_MAC_DUMP_MODE_V 0x3 809 #define DPORT_MAC_DUMP_MODE_S 5 810 /* DPORT_MASK_AHB : R/W ;bitpos:[4] ;default: 1'b0 ; */ 811 /*description: */ 812 #define DPORT_MASK_AHB (BIT(4)) 813 #define DPORT_MASK_AHB_M (BIT(4)) 814 #define DPORT_MASK_AHB_V 0x1 815 #define DPORT_MASK_AHB_S 4 816 /* DPORT_MASK_APP_DRAM : R/W ;bitpos:[3] ;default: 1'b0 ; */ 817 /*description: */ 818 #define DPORT_MASK_APP_DRAM (BIT(3)) 819 #define DPORT_MASK_APP_DRAM_M (BIT(3)) 820 #define DPORT_MASK_APP_DRAM_V 0x1 821 #define DPORT_MASK_APP_DRAM_S 3 822 /* DPORT_MASK_PRO_DRAM : R/W ;bitpos:[2] ;default: 1'b0 ; */ 823 /*description: */ 824 #define DPORT_MASK_PRO_DRAM (BIT(2)) 825 #define DPORT_MASK_PRO_DRAM_M (BIT(2)) 826 #define DPORT_MASK_PRO_DRAM_V 0x1 827 #define DPORT_MASK_PRO_DRAM_S 2 828 /* DPORT_MASK_APP_IRAM : R/W ;bitpos:[1] ;default: 1'b0 ; */ 829 /*description: */ 830 #define DPORT_MASK_APP_IRAM (BIT(1)) 831 #define DPORT_MASK_APP_IRAM_M (BIT(1)) 832 #define DPORT_MASK_APP_IRAM_V 0x1 833 #define DPORT_MASK_APP_IRAM_S 1 834 /* DPORT_MASK_PRO_IRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */ 835 /*description: */ 836 #define DPORT_MASK_PRO_IRAM (BIT(0)) 837 #define DPORT_MASK_PRO_IRAM_M (BIT(0)) 838 #define DPORT_MASK_PRO_IRAM_V 0x1 839 #define DPORT_MASK_PRO_IRAM_S 0 840 841 #define DPORT_TAG_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x0AC) 842 /* DPORT_APP_CACHE_TAG_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ 843 /*description: */ 844 #define DPORT_APP_CACHE_TAG_PD (BIT(9)) 845 #define DPORT_APP_CACHE_TAG_PD_M (BIT(9)) 846 #define DPORT_APP_CACHE_TAG_PD_V 0x1 847 #define DPORT_APP_CACHE_TAG_PD_S 9 848 /* DPORT_APP_CACHE_TAG_FORCE_ON : R/W ;bitpos:[8] ;default: 1'b1 ; */ 849 /*description: */ 850 #define DPORT_APP_CACHE_TAG_FORCE_ON (BIT(8)) 851 #define DPORT_APP_CACHE_TAG_FORCE_ON_M (BIT(8)) 852 #define DPORT_APP_CACHE_TAG_FORCE_ON_V 0x1 853 #define DPORT_APP_CACHE_TAG_FORCE_ON_S 8 854 /* DPORT_PRO_CACHE_TAG_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 855 /*description: */ 856 #define DPORT_PRO_CACHE_TAG_PD (BIT(1)) 857 #define DPORT_PRO_CACHE_TAG_PD_M (BIT(1)) 858 #define DPORT_PRO_CACHE_TAG_PD_V 0x1 859 #define DPORT_PRO_CACHE_TAG_PD_S 1 860 /* DPORT_PRO_CACHE_TAG_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ 861 /*description: */ 862 #define DPORT_PRO_CACHE_TAG_FORCE_ON (BIT(0)) 863 #define DPORT_PRO_CACHE_TAG_FORCE_ON_M (BIT(0)) 864 #define DPORT_PRO_CACHE_TAG_FORCE_ON_V 0x1 865 #define DPORT_PRO_CACHE_TAG_FORCE_ON_S 0 866 867 #define DPORT_AHB_LITE_MASK_REG (DR_REG_DPORT_BASE + 0x0B0) 868 /* DPORT_AHB_LITE_SDHOST_PID_REG : R/W ;bitpos:[13:11] ;default: 3'b0 ; */ 869 /*description: */ 870 #define DPORT_AHB_LITE_SDHOST_PID_REG 0x00000007 871 #define DPORT_AHB_LITE_SDHOST_PID_REG_M ((DPORT_AHB_LITE_SDHOST_PID_REG_V)<<(DPORT_AHB_LITE_SDHOST_PID_REG_S)) 872 #define DPORT_AHB_LITE_SDHOST_PID_REG_V 0x7 873 #define DPORT_AHB_LITE_SDHOST_PID_REG_S 11 874 /* DPORT_AHB_LITE_MASK_APPDPORT : R/W ;bitpos:[10] ;default: 1'b0 ; */ 875 /*description: */ 876 #define DPORT_AHB_LITE_MASK_APPDPORT (BIT(10)) 877 #define DPORT_AHB_LITE_MASK_APPDPORT_M (BIT(10)) 878 #define DPORT_AHB_LITE_MASK_APPDPORT_V 0x1 879 #define DPORT_AHB_LITE_MASK_APPDPORT_S 10 880 /* DPORT_AHB_LITE_MASK_PRODPORT : R/W ;bitpos:[9] ;default: 1'b0 ; */ 881 /*description: */ 882 #define DPORT_AHB_LITE_MASK_PRODPORT (BIT(9)) 883 #define DPORT_AHB_LITE_MASK_PRODPORT_M (BIT(9)) 884 #define DPORT_AHB_LITE_MASK_PRODPORT_V 0x1 885 #define DPORT_AHB_LITE_MASK_PRODPORT_S 9 886 /* DPORT_AHB_LITE_MASK_SDIO : R/W ;bitpos:[8] ;default: 1'b0 ; */ 887 /*description: */ 888 #define DPORT_AHB_LITE_MASK_SDIO (BIT(8)) 889 #define DPORT_AHB_LITE_MASK_SDIO_M (BIT(8)) 890 #define DPORT_AHB_LITE_MASK_SDIO_V 0x1 891 #define DPORT_AHB_LITE_MASK_SDIO_S 8 892 /* DPORT_AHB_LITE_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */ 893 /*description: */ 894 #define DPORT_AHB_LITE_MASK_APP (BIT(4)) 895 #define DPORT_AHB_LITE_MASK_APP_M (BIT(4)) 896 #define DPORT_AHB_LITE_MASK_APP_V 0x1 897 #define DPORT_AHB_LITE_MASK_APP_S 4 898 /* DPORT_AHB_LITE_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */ 899 /*description: */ 900 #define DPORT_AHB_LITE_MASK_PRO (BIT(0)) 901 #define DPORT_AHB_LITE_MASK_PRO_M (BIT(0)) 902 #define DPORT_AHB_LITE_MASK_PRO_V 0x1 903 #define DPORT_AHB_LITE_MASK_PRO_S 0 904 905 #define DPORT_AHB_MPU_TABLE_0_REG (DR_REG_DPORT_BASE + 0x0B4) 906 /* DPORT_AHB_ACCESS_GRANT_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ 907 /*description: */ 908 #define DPORT_AHB_ACCESS_GRANT_0 0xFFFFFFFF 909 #define DPORT_AHB_ACCESS_GRANT_0_M ((DPORT_AHB_ACCESS_GRANT_0_V)<<(DPORT_AHB_ACCESS_GRANT_0_S)) 910 #define DPORT_AHB_ACCESS_GRANT_0_V 0xFFFFFFFF 911 #define DPORT_AHB_ACCESS_GRANT_0_S 0 912 913 #define DPORT_AHB_MPU_TABLE_1_REG (DR_REG_DPORT_BASE + 0x0B8) 914 /* DPORT_AHB_ACCESS_GRANT_1 : R/W ;bitpos:[8:0] ;default: 9'h1ff ; */ 915 /*description: */ 916 #define DPORT_AHB_ACCESS_GRANT_1 0x000001FF 917 #define DPORT_AHB_ACCESS_GRANT_1_M ((DPORT_AHB_ACCESS_GRANT_1_V)<<(DPORT_AHB_ACCESS_GRANT_1_S)) 918 #define DPORT_AHB_ACCESS_GRANT_1_V 0x1FF 919 #define DPORT_AHB_ACCESS_GRANT_1_S 0 920 921 #define DPORT_HOST_INF_SEL_REG (DR_REG_DPORT_BASE + 0x0BC) 922 /* DPORT_LINK_DEVICE_SEL : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ 923 /*description: */ 924 #define DPORT_LINK_DEVICE_SEL 0x000000FF 925 #define DPORT_LINK_DEVICE_SEL_M ((DPORT_LINK_DEVICE_SEL_V)<<(DPORT_LINK_DEVICE_SEL_S)) 926 #define DPORT_LINK_DEVICE_SEL_V 0xFF 927 #define DPORT_LINK_DEVICE_SEL_S 8 928 /* DPORT_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ 929 /*description: */ 930 #define DPORT_PERI_IO_SWAP 0x000000FF 931 #define DPORT_PERI_IO_SWAP_M ((DPORT_PERI_IO_SWAP_V)<<(DPORT_PERI_IO_SWAP_S)) 932 #define DPORT_PERI_IO_SWAP_V 0xFF 933 #define DPORT_PERI_IO_SWAP_S 0 934 935 #define DPORT_PERIP_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0C0) 936 /* DPORT_PERIP_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hf9c1e06f ; */ 937 /*description: */ 938 #define DPORT_PERIP_CLK_EN 0xFFFFFFFF 939 #define DPORT_PERIP_CLK_EN_M ((DPORT_PERIP_CLK_EN_V)<<(DPORT_PERIP_CLK_EN_S)) 940 #define DPORT_PERIP_CLK_EN_V 0xFFFFFFFF 941 #define DPORT_PERIP_CLK_EN_S 0 942 943 #define DPORT_PWM3_CLK_EN (BIT(26)) 944 #define DPORT_PWM2_CLK_EN (BIT(25)) 945 #define DPORT_UART_MEM_CLK_EN (BIT(24)) 946 #define DPORT_UART2_CLK_EN (BIT(23)) 947 #define DPORT_SPI_DMA_CLK_EN (BIT(22)) 948 #define DPORT_I2S1_CLK_EN (BIT(21)) 949 #define DPORT_PWM1_CLK_EN (BIT(20)) 950 #define DPORT_TWAI_CLK_EN (BIT(19)) 951 #define DPORT_CAN_CLK_EN DPORT_TWAI_CLK_EN 952 #define DPORT_I2C_EXT1_CLK_EN (BIT(18)) 953 #define DPORT_PWM0_CLK_EN (BIT(17)) 954 #define DPORT_SPI3_CLK_EN (BIT(16)) 955 #define DPORT_TIMERGROUP1_CLK_EN (BIT(15)) 956 #define DPORT_EFUSE_CLK_EN (BIT(14)) 957 #define DPORT_TIMERGROUP_CLK_EN (BIT(13)) 958 #define DPORT_UHCI1_CLK_EN (BIT(12)) 959 #define DPORT_LEDC_CLK_EN (BIT(11)) 960 #define DPORT_PCNT_CLK_EN (BIT(10)) 961 #define DPORT_RMT_CLK_EN (BIT(9)) 962 #define DPORT_UHCI0_CLK_EN (BIT(8)) 963 #define DPORT_I2C_EXT0_CLK_EN (BIT(7)) 964 #define DPORT_SPI2_CLK_EN (BIT(6)) 965 #define DPORT_UART1_CLK_EN (BIT(5)) 966 #define DPORT_I2S0_CLK_EN (BIT(4)) 967 #define DPORT_WDG_CLK_EN (BIT(3)) 968 #define DPORT_UART_CLK_EN (BIT(2)) 969 #define DPORT_SPI01_CLK_EN (BIT(1)) 970 #define DPORT_TIMERS_CLK_EN (BIT(0)) 971 #define DPORT_PERIP_RST_EN_REG (DR_REG_DPORT_BASE + 0x0C4) 972 /* DPORT_PERIP_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 973 /*description: */ 974 #define DPORT_PERIP_RST 0xFFFFFFFF 975 #define DPORT_PERIP_RST_M ((DPORT_PERIP_RST_V)<<(DPORT_PERIP_RST_S)) 976 #define DPORT_PERIP_RST_V 0xFFFFFFFF 977 #define DPORT_PERIP_RST_S 0 978 #define DPORT_PWM3_RST (BIT(26)) 979 #define DPORT_PWM2_RST (BIT(25)) 980 #define DPORT_UART_MEM_RST (BIT(24)) 981 #define DPORT_UART2_RST (BIT(23)) 982 #define DPORT_SPI_DMA_RST (BIT(22)) 983 #define DPORT_I2S1_RST (BIT(21)) 984 #define DPORT_PWM1_RST (BIT(20)) 985 #define DPORT_TWAI_RST (BIT(19)) 986 #define DPORT_CAN_RST DPORT_TWAI_RST 987 #define DPORT_I2C_EXT1_RST (BIT(18)) 988 #define DPORT_PWM0_RST (BIT(17)) 989 #define DPORT_SPI3_RST (BIT(16)) 990 #define DPORT_TIMERGROUP1_RST (BIT(15)) 991 #define DPORT_EFUSE_RST (BIT(14)) 992 #define DPORT_TIMERGROUP_RST (BIT(13)) 993 #define DPORT_UHCI1_RST (BIT(12)) 994 #define DPORT_LEDC_RST (BIT(11)) 995 #define DPORT_PCNT_RST (BIT(10)) 996 #define DPORT_RMT_RST (BIT(9)) 997 #define DPORT_UHCI0_RST (BIT(8)) 998 #define DPORT_I2C_EXT0_RST (BIT(7)) 999 #define DPORT_SPI2_RST (BIT(6)) 1000 #define DPORT_UART1_RST (BIT(5)) 1001 #define DPORT_I2S0_RST (BIT(4)) 1002 #define DPORT_WDG_RST (BIT(3)) 1003 #define DPORT_UART_RST (BIT(2)) 1004 #define DPORT_SPI01_RST (BIT(1)) 1005 #define DPORT_TIMERS_RST (BIT(0)) 1006 #define DPORT_SLAVE_SPI_CONFIG_REG (DR_REG_DPORT_BASE + 0x0C8) 1007 /* DPORT_SPI_DECRYPT_ENABLE : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1008 /*description: */ 1009 #define DPORT_SPI_DECRYPT_ENABLE (BIT(12)) 1010 #define DPORT_SPI_DECRYPT_ENABLE_M (BIT(12)) 1011 #define DPORT_SPI_DECRYPT_ENABLE_V 0x1 1012 #define DPORT_SPI_DECRYPT_ENABLE_S 12 1013 /* DPORT_SPI_ENCRYPT_ENABLE : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1014 /*description: */ 1015 #define DPORT_SPI_ENCRYPT_ENABLE (BIT(8)) 1016 #define DPORT_SPI_ENCRYPT_ENABLE_M (BIT(8)) 1017 #define DPORT_SPI_ENCRYPT_ENABLE_V 0x1 1018 #define DPORT_SPI_ENCRYPT_ENABLE_S 8 1019 /* DPORT_SLAVE_SPI_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1020 /*description: */ 1021 #define DPORT_SLAVE_SPI_MASK_APP (BIT(4)) 1022 #define DPORT_SLAVE_SPI_MASK_APP_M (BIT(4)) 1023 #define DPORT_SLAVE_SPI_MASK_APP_V 0x1 1024 #define DPORT_SLAVE_SPI_MASK_APP_S 4 1025 /* DPORT_SLAVE_SPI_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1026 /*description: */ 1027 #define DPORT_SLAVE_SPI_MASK_PRO (BIT(0)) 1028 #define DPORT_SLAVE_SPI_MASK_PRO_M (BIT(0)) 1029 #define DPORT_SLAVE_SPI_MASK_PRO_V 0x1 1030 #define DPORT_SLAVE_SPI_MASK_PRO_S 0 1031 1032 #define DPORT_WIFI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0CC) 1033 /* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ 1034 /*description: */ 1035 #define DPORT_WIFI_CLK_EN 0xFFFFFFFF 1036 #define DPORT_WIFI_CLK_EN_M ((DPORT_WIFI_CLK_EN_V)<<(DPORT_WIFI_CLK_EN_S)) 1037 #define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF 1038 #define DPORT_WIFI_CLK_EN_S 0 1039 1040 /* Mask for all Wifi clock bits - 1, 2, 10 */ 1041 #define DPORT_WIFI_CLK_WIFI_EN 0x00000406 1042 #define DPORT_WIFI_CLK_WIFI_EN_M ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S)) 1043 #define DPORT_WIFI_CLK_WIFI_EN_V 0x406 1044 #define DPORT_WIFI_CLK_WIFI_EN_S 0 1045 /* Mask for all Bluetooth clock bits - 11, 16, 17 */ 1046 #define DPORT_WIFI_CLK_BT_EN 0x61 1047 #define DPORT_WIFI_CLK_BT_EN_M ((DPORT_WIFI_CLK_BT_EN_V)<<(DPORT_WIFI_CLK_BT_EN_S)) 1048 #define DPORT_WIFI_CLK_BT_EN_V 0x61 1049 #define DPORT_WIFI_CLK_BT_EN_S 11 1050 /* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */ 1051 #define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9 1052 //bluetooth baseband bit11 1053 #define DPORT_BT_BASEBAND_EN BIT(11) 1054 //bluetooth LC bit16 and bit17 1055 #define DPORT_BT_LC_EN (BIT(16)|BIT(17)) 1056 1057 /* Remaining single bit clock masks */ 1058 #define DPORT_WIFI_CLK_SDIOSLAVE_EN BIT(4) 1059 #define DPORT_WIFI_CLK_UNUSED_BIT5 BIT(5) 1060 #define DPORT_WIFI_CLK_UNUSED_BIT12 BIT(12) 1061 #define DPORT_WIFI_CLK_SDIO_HOST_EN BIT(13) 1062 #define DPORT_WIFI_CLK_EMAC_EN BIT(14) 1063 #define DPORT_WIFI_CLK_RNG_EN BIT(15) 1064 1065 #define DPORT_CORE_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0) 1066 /* DPORT_CORE_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1067 /*description: */ 1068 #define DPORT_WIFIBB_RST BIT(0) 1069 #define DPORT_FE_RST BIT(1) 1070 #define DPORT_WIFIMAC_RST BIT(2) 1071 #define DPORT_BTBB_RST BIT(3) 1072 #define DPORT_BTMAC_RST BIT(4) 1073 #define DPORT_SDIO_RST BIT(5) 1074 #define DPORT_SDIO_HOST_RST BIT(6) 1075 #define DPORT_EMAC_RST BIT(7) 1076 #define DPORT_MACPWR_RST BIT(8) 1077 #define DPORT_RW_BTMAC_RST BIT(9) 1078 #define DPORT_RW_BTLP_RST BIT(10) 1079 1080 //ESP32 should not reset FE in esp_wifi_bt_power_domain_on(). 1081 //The FE of ESP32 is not in the WIFI PD power domain. 1082 //When turning off WIFI PD, the FE will not power down, so phy_wakeup_init() did not rewrite the FE register. 1083 #define MODEM_RESET_FIELD_WHEN_PU (DPORT_WIFIBB_RST | \ 1084 DPORT_WIFIMAC_RST | \ 1085 DPORT_BTBB_RST | \ 1086 DPORT_BTMAC_RST | \ 1087 DPORT_RW_BTMAC_RST) 1088 1089 #define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_DPORT_BASE + 0x0D4) 1090 /* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1091 /*description: */ 1092 #define DPORT_BTEXTWAKEUP_REQ (BIT(12)) 1093 #define DPORT_BTEXTWAKEUP_REQ_M (BIT(12)) 1094 #define DPORT_BTEXTWAKEUP_REQ_V 0x1 1095 #define DPORT_BTEXTWAKEUP_REQ_S 12 1096 /* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ 1097 /*description: */ 1098 #define DPORT_BT_LPCK_DIV_NUM 0x00000FFF 1099 #define DPORT_BT_LPCK_DIV_NUM_M ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S)) 1100 #define DPORT_BT_LPCK_DIV_NUM_V 0xFFF 1101 #define DPORT_BT_LPCK_DIV_NUM_S 0 1102 1103 #define DPORT_BT_LPCK_DIV_FRAC_REG (DR_REG_DPORT_BASE + 0x0D8) 1104 /* DPORT_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ 1105 /*description: */ 1106 #define DPORT_LPCLK_SEL_XTAL32K (BIT(27)) 1107 #define DPORT_LPCLK_SEL_XTAL32K_M (BIT(27)) 1108 #define DPORT_LPCLK_SEL_XTAL32K_V 0x1 1109 #define DPORT_LPCLK_SEL_XTAL32K_S 27 1110 /* DPORT_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ 1111 /*description: */ 1112 #define DPORT_LPCLK_SEL_XTAL (BIT(26)) 1113 #define DPORT_LPCLK_SEL_XTAL_M (BIT(26)) 1114 #define DPORT_LPCLK_SEL_XTAL_V 0x1 1115 #define DPORT_LPCLK_SEL_XTAL_S 26 1116 /* DPORT_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ 1117 /*description: */ 1118 #define DPORT_LPCLK_SEL_8M (BIT(25)) 1119 #define DPORT_LPCLK_SEL_8M_M (BIT(25)) 1120 #define DPORT_LPCLK_SEL_8M_V 0x1 1121 #define DPORT_LPCLK_SEL_8M_S 25 1122 /* DPORT_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ 1123 /*description: */ 1124 #define DPORT_LPCLK_SEL_RTC_SLOW (BIT(24)) 1125 #define DPORT_LPCLK_SEL_RTC_SLOW_M (BIT(24)) 1126 #define DPORT_LPCLK_SEL_RTC_SLOW_V 0x1 1127 #define DPORT_LPCLK_SEL_RTC_SLOW_S 24 1128 /* DPORT_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ 1129 /*description: */ 1130 #define DPORT_BT_LPCK_DIV_A 0x00000FFF 1131 #define DPORT_BT_LPCK_DIV_A_M ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S)) 1132 #define DPORT_BT_LPCK_DIV_A_V 0xFFF 1133 #define DPORT_BT_LPCK_DIV_A_S 12 1134 /* DPORT_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ 1135 /*description: */ 1136 #define DPORT_BT_LPCK_DIV_B 0x00000FFF 1137 #define DPORT_BT_LPCK_DIV_B_M ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S)) 1138 #define DPORT_BT_LPCK_DIV_B_V 0xFFF 1139 #define DPORT_BT_LPCK_DIV_B_S 0 1140 1141 #define DPORT_CPU_INTR_FROM_CPU_0_REG (DR_REG_DPORT_BASE + 0x0DC) 1142 /* DPORT_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1143 /*description: */ 1144 #define DPORT_CPU_INTR_FROM_CPU_0 (BIT(0)) 1145 #define DPORT_CPU_INTR_FROM_CPU_0_M (BIT(0)) 1146 #define DPORT_CPU_INTR_FROM_CPU_0_V 0x1 1147 #define DPORT_CPU_INTR_FROM_CPU_0_S 0 1148 1149 #define DPORT_CPU_INTR_FROM_CPU_1_REG (DR_REG_DPORT_BASE + 0x0E0) 1150 /* DPORT_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1151 /*description: */ 1152 #define DPORT_CPU_INTR_FROM_CPU_1 (BIT(0)) 1153 #define DPORT_CPU_INTR_FROM_CPU_1_M (BIT(0)) 1154 #define DPORT_CPU_INTR_FROM_CPU_1_V 0x1 1155 #define DPORT_CPU_INTR_FROM_CPU_1_S 0 1156 1157 #define SYSTEM_CPU_INTR_FROM_CPU_2_REG DPORT_CPU_INTR_FROM_CPU_2_REG 1158 #define SYSTEM_CPU_INTR_FROM_CPU_2 DPORT_CPU_INTR_FROM_CPU_2 1159 #define DPORT_CPU_INTR_FROM_CPU_2_REG (DR_REG_DPORT_BASE + 0x0E4) 1160 /* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1161 /*description: */ 1162 #define DPORT_CPU_INTR_FROM_CPU_2 (BIT(0)) 1163 #define DPORT_CPU_INTR_FROM_CPU_2_M (BIT(0)) 1164 #define DPORT_CPU_INTR_FROM_CPU_2_V 0x1 1165 #define DPORT_CPU_INTR_FROM_CPU_2_S 0 1166 1167 #define SYSTEM_CPU_INTR_FROM_CPU_3_REG DPORT_CPU_INTR_FROM_CPU_3_REG 1168 #define SYSTEM_CPU_INTR_FROM_CPU_3 DPORT_CPU_INTR_FROM_CPU_3 1169 #define DPORT_CPU_INTR_FROM_CPU_3_REG (DR_REG_DPORT_BASE + 0x0E8) 1170 /* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1171 /*description: */ 1172 #define DPORT_CPU_INTR_FROM_CPU_3 (BIT(0)) 1173 #define DPORT_CPU_INTR_FROM_CPU_3_M (BIT(0)) 1174 #define DPORT_CPU_INTR_FROM_CPU_3_V 0x1 1175 #define DPORT_CPU_INTR_FROM_CPU_3_S 0 1176 1177 #define DPORT_PRO_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0EC) 1178 /* DPORT_PRO_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1179 /*description: */ 1180 #define DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF 1181 #define DPORT_PRO_INTR_STATUS_0_M ((DPORT_PRO_INTR_STATUS_0_V)<<(DPORT_PRO_INTR_STATUS_0_S)) 1182 #define DPORT_PRO_INTR_STATUS_0_V 0xFFFFFFFF 1183 #define DPORT_PRO_INTR_STATUS_0_S 0 1184 1185 #define DPORT_PRO_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0F0) 1186 /* DPORT_PRO_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1187 /*description: */ 1188 #define DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF 1189 #define DPORT_PRO_INTR_STATUS_1_M ((DPORT_PRO_INTR_STATUS_1_V)<<(DPORT_PRO_INTR_STATUS_1_S)) 1190 #define DPORT_PRO_INTR_STATUS_1_V 0xFFFFFFFF 1191 #define DPORT_PRO_INTR_STATUS_1_S 0 1192 1193 #define DPORT_PRO_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x0F4) 1194 /* DPORT_PRO_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1195 /*description: */ 1196 #define DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF 1197 #define DPORT_PRO_INTR_STATUS_2_M ((DPORT_PRO_INTR_STATUS_2_V)<<(DPORT_PRO_INTR_STATUS_2_S)) 1198 #define DPORT_PRO_INTR_STATUS_2_V 0xFFFFFFFF 1199 #define DPORT_PRO_INTR_STATUS_2_S 0 1200 1201 #define DPORT_APP_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0F8) 1202 /* DPORT_APP_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1203 /*description: */ 1204 #define DPORT_APP_INTR_STATUS_0 0xFFFFFFFF 1205 #define DPORT_APP_INTR_STATUS_0_M ((DPORT_APP_INTR_STATUS_0_V)<<(DPORT_APP_INTR_STATUS_0_S)) 1206 #define DPORT_APP_INTR_STATUS_0_V 0xFFFFFFFF 1207 #define DPORT_APP_INTR_STATUS_0_S 0 1208 1209 #define DPORT_APP_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0FC) 1210 /* DPORT_APP_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1211 /*description: */ 1212 #define DPORT_APP_INTR_STATUS_1 0xFFFFFFFF 1213 #define DPORT_APP_INTR_STATUS_1_M ((DPORT_APP_INTR_STATUS_1_V)<<(DPORT_APP_INTR_STATUS_1_S)) 1214 #define DPORT_APP_INTR_STATUS_1_V 0xFFFFFFFF 1215 #define DPORT_APP_INTR_STATUS_1_S 0 1216 1217 #define DPORT_APP_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x100) 1218 /* DPORT_APP_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1219 /*description: */ 1220 #define DPORT_APP_INTR_STATUS_2 0xFFFFFFFF 1221 #define DPORT_APP_INTR_STATUS_2_M ((DPORT_APP_INTR_STATUS_2_V)<<(DPORT_APP_INTR_STATUS_2_S)) 1222 #define DPORT_APP_INTR_STATUS_2_V 0xFFFFFFFF 1223 #define DPORT_APP_INTR_STATUS_2_S 0 1224 1225 #define DPORT_PRO_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x104) 1226 /* DPORT_PRO_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1227 /*description: */ 1228 #define DPORT_PRO_MAC_INTR_MAP 0x0000001F 1229 #define DPORT_PRO_MAC_INTR_MAP_M ((DPORT_PRO_MAC_INTR_MAP_V)<<(DPORT_PRO_MAC_INTR_MAP_S)) 1230 #define DPORT_PRO_MAC_INTR_MAP_V 0x1F 1231 #define DPORT_PRO_MAC_INTR_MAP_S 0 1232 1233 #define DPORT_PRO_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x108) 1234 /* DPORT_PRO_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1235 /*description: */ 1236 #define DPORT_PRO_MAC_NMI_MAP 0x0000001F 1237 #define DPORT_PRO_MAC_NMI_MAP_M ((DPORT_PRO_MAC_NMI_MAP_V)<<(DPORT_PRO_MAC_NMI_MAP_S)) 1238 #define DPORT_PRO_MAC_NMI_MAP_V 0x1F 1239 #define DPORT_PRO_MAC_NMI_MAP_S 0 1240 1241 #define DPORT_PRO_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x10C) 1242 /* DPORT_PRO_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1243 /*description: */ 1244 #define DPORT_PRO_BB_INT_MAP 0x0000001F 1245 #define DPORT_PRO_BB_INT_MAP_M ((DPORT_PRO_BB_INT_MAP_V)<<(DPORT_PRO_BB_INT_MAP_S)) 1246 #define DPORT_PRO_BB_INT_MAP_V 0x1F 1247 #define DPORT_PRO_BB_INT_MAP_S 0 1248 1249 #define DPORT_PRO_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x110) 1250 /* DPORT_PRO_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1251 /*description: */ 1252 #define DPORT_PRO_BT_MAC_INT_MAP 0x0000001F 1253 #define DPORT_PRO_BT_MAC_INT_MAP_M ((DPORT_PRO_BT_MAC_INT_MAP_V)<<(DPORT_PRO_BT_MAC_INT_MAP_S)) 1254 #define DPORT_PRO_BT_MAC_INT_MAP_V 0x1F 1255 #define DPORT_PRO_BT_MAC_INT_MAP_S 0 1256 1257 #define DPORT_PRO_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x114) 1258 /* DPORT_PRO_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1259 /*description: */ 1260 #define DPORT_PRO_BT_BB_INT_MAP 0x0000001F 1261 #define DPORT_PRO_BT_BB_INT_MAP_M ((DPORT_PRO_BT_BB_INT_MAP_V)<<(DPORT_PRO_BT_BB_INT_MAP_S)) 1262 #define DPORT_PRO_BT_BB_INT_MAP_V 0x1F 1263 #define DPORT_PRO_BT_BB_INT_MAP_S 0 1264 1265 #define DPORT_PRO_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x118) 1266 /* DPORT_PRO_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1267 /*description: */ 1268 #define DPORT_PRO_BT_BB_NMI_MAP 0x0000001F 1269 #define DPORT_PRO_BT_BB_NMI_MAP_M ((DPORT_PRO_BT_BB_NMI_MAP_V)<<(DPORT_PRO_BT_BB_NMI_MAP_S)) 1270 #define DPORT_PRO_BT_BB_NMI_MAP_V 0x1F 1271 #define DPORT_PRO_BT_BB_NMI_MAP_S 0 1272 1273 #define DPORT_PRO_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x11C) 1274 /* DPORT_PRO_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1275 /*description: */ 1276 #define DPORT_PRO_RWBT_IRQ_MAP 0x0000001F 1277 #define DPORT_PRO_RWBT_IRQ_MAP_M ((DPORT_PRO_RWBT_IRQ_MAP_V)<<(DPORT_PRO_RWBT_IRQ_MAP_S)) 1278 #define DPORT_PRO_RWBT_IRQ_MAP_V 0x1F 1279 #define DPORT_PRO_RWBT_IRQ_MAP_S 0 1280 1281 #define DPORT_PRO_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x120) 1282 /* DPORT_PRO_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1283 /*description: */ 1284 #define DPORT_PRO_RWBLE_IRQ_MAP 0x0000001F 1285 #define DPORT_PRO_RWBLE_IRQ_MAP_M ((DPORT_PRO_RWBLE_IRQ_MAP_V)<<(DPORT_PRO_RWBLE_IRQ_MAP_S)) 1286 #define DPORT_PRO_RWBLE_IRQ_MAP_V 0x1F 1287 #define DPORT_PRO_RWBLE_IRQ_MAP_S 0 1288 1289 #define DPORT_PRO_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x124) 1290 /* DPORT_PRO_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1291 /*description: */ 1292 #define DPORT_PRO_RWBT_NMI_MAP 0x0000001F 1293 #define DPORT_PRO_RWBT_NMI_MAP_M ((DPORT_PRO_RWBT_NMI_MAP_V)<<(DPORT_PRO_RWBT_NMI_MAP_S)) 1294 #define DPORT_PRO_RWBT_NMI_MAP_V 0x1F 1295 #define DPORT_PRO_RWBT_NMI_MAP_S 0 1296 1297 #define DPORT_PRO_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x128) 1298 /* DPORT_PRO_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1299 /*description: */ 1300 #define DPORT_PRO_RWBLE_NMI_MAP 0x0000001F 1301 #define DPORT_PRO_RWBLE_NMI_MAP_M ((DPORT_PRO_RWBLE_NMI_MAP_V)<<(DPORT_PRO_RWBLE_NMI_MAP_S)) 1302 #define DPORT_PRO_RWBLE_NMI_MAP_V 0x1F 1303 #define DPORT_PRO_RWBLE_NMI_MAP_S 0 1304 1305 #define DPORT_PRO_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x12C) 1306 /* DPORT_PRO_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1307 /*description: */ 1308 #define DPORT_PRO_SLC0_INTR_MAP 0x0000001F 1309 #define DPORT_PRO_SLC0_INTR_MAP_M ((DPORT_PRO_SLC0_INTR_MAP_V)<<(DPORT_PRO_SLC0_INTR_MAP_S)) 1310 #define DPORT_PRO_SLC0_INTR_MAP_V 0x1F 1311 #define DPORT_PRO_SLC0_INTR_MAP_S 0 1312 1313 #define DPORT_PRO_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x130) 1314 /* DPORT_PRO_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1315 /*description: */ 1316 #define DPORT_PRO_SLC1_INTR_MAP 0x0000001F 1317 #define DPORT_PRO_SLC1_INTR_MAP_M ((DPORT_PRO_SLC1_INTR_MAP_V)<<(DPORT_PRO_SLC1_INTR_MAP_S)) 1318 #define DPORT_PRO_SLC1_INTR_MAP_V 0x1F 1319 #define DPORT_PRO_SLC1_INTR_MAP_S 0 1320 1321 #define DPORT_PRO_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x134) 1322 /* DPORT_PRO_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1323 /*description: */ 1324 #define DPORT_PRO_UHCI0_INTR_MAP 0x0000001F 1325 #define DPORT_PRO_UHCI0_INTR_MAP_M ((DPORT_PRO_UHCI0_INTR_MAP_V)<<(DPORT_PRO_UHCI0_INTR_MAP_S)) 1326 #define DPORT_PRO_UHCI0_INTR_MAP_V 0x1F 1327 #define DPORT_PRO_UHCI0_INTR_MAP_S 0 1328 1329 #define DPORT_PRO_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x138) 1330 /* DPORT_PRO_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1331 /*description: */ 1332 #define DPORT_PRO_UHCI1_INTR_MAP 0x0000001F 1333 #define DPORT_PRO_UHCI1_INTR_MAP_M ((DPORT_PRO_UHCI1_INTR_MAP_V)<<(DPORT_PRO_UHCI1_INTR_MAP_S)) 1334 #define DPORT_PRO_UHCI1_INTR_MAP_V 0x1F 1335 #define DPORT_PRO_UHCI1_INTR_MAP_S 0 1336 1337 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x13C) 1338 /* DPORT_PRO_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1339 /*description: */ 1340 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F 1341 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T0_LEVEL_INT_MAP_S)) 1342 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_V 0x1F 1343 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S 0 1344 1345 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x140) 1346 /* DPORT_PRO_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1347 /*description: */ 1348 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F 1349 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T1_LEVEL_INT_MAP_S)) 1350 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_V 0x1F 1351 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S 0 1352 1353 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x144) 1354 /* DPORT_PRO_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1355 /*description: */ 1356 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F 1357 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S)) 1358 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V 0x1F 1359 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S 0 1360 1361 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x148) 1362 /* DPORT_PRO_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1363 /*description: */ 1364 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F 1365 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S)) 1366 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V 0x1F 1367 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S 0 1368 1369 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x14C) 1370 /* DPORT_PRO_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1371 /*description: */ 1372 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F 1373 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S)) 1374 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V 0x1F 1375 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S 0 1376 1377 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x150) 1378 /* DPORT_PRO_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1379 /*description: */ 1380 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F 1381 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S)) 1382 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V 0x1F 1383 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S 0 1384 1385 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x154) 1386 /* DPORT_PRO_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1387 /*description: */ 1388 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F 1389 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S)) 1390 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V 0x1F 1391 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0 1392 1393 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x158) 1394 /* DPORT_PRO_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1395 /*description: */ 1396 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F 1397 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S)) 1398 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V 0x1F 1399 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0 1400 1401 #define DPORT_PRO_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x15C) 1402 /* DPORT_PRO_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1403 /*description: */ 1404 #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP 0x0000001F 1405 #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S)) 1406 #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V 0x1F 1407 #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S 0 1408 1409 #define DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x160) 1410 /* DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1411 /*description: */ 1412 #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F 1413 #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S)) 1414 #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F 1415 #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 1416 1417 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x164) 1418 /* DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1419 /*description: */ 1420 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F 1421 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S)) 1422 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V 0x1F 1423 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0 1424 1425 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x168) 1426 /* DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1427 /*description: */ 1428 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F 1429 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S)) 1430 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V 0x1F 1431 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0 1432 1433 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x16C) 1434 /* DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1435 /*description: */ 1436 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F 1437 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S)) 1438 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V 0x1F 1439 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0 1440 1441 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x170) 1442 /* DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1443 /*description: */ 1444 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F 1445 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S)) 1446 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V 0x1F 1447 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0 1448 1449 #define DPORT_PRO_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x174) 1450 /* DPORT_PRO_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1451 /*description: */ 1452 #define DPORT_PRO_SPI_INTR_0_MAP 0x0000001F 1453 #define DPORT_PRO_SPI_INTR_0_MAP_M ((DPORT_PRO_SPI_INTR_0_MAP_V)<<(DPORT_PRO_SPI_INTR_0_MAP_S)) 1454 #define DPORT_PRO_SPI_INTR_0_MAP_V 0x1F 1455 #define DPORT_PRO_SPI_INTR_0_MAP_S 0 1456 1457 #define DPORT_PRO_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x178) 1458 /* DPORT_PRO_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1459 /*description: */ 1460 #define DPORT_PRO_SPI_INTR_1_MAP 0x0000001F 1461 #define DPORT_PRO_SPI_INTR_1_MAP_M ((DPORT_PRO_SPI_INTR_1_MAP_V)<<(DPORT_PRO_SPI_INTR_1_MAP_S)) 1462 #define DPORT_PRO_SPI_INTR_1_MAP_V 0x1F 1463 #define DPORT_PRO_SPI_INTR_1_MAP_S 0 1464 1465 #define DPORT_PRO_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x17C) 1466 /* DPORT_PRO_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1467 /*description: */ 1468 #define DPORT_PRO_SPI_INTR_2_MAP 0x0000001F 1469 #define DPORT_PRO_SPI_INTR_2_MAP_M ((DPORT_PRO_SPI_INTR_2_MAP_V)<<(DPORT_PRO_SPI_INTR_2_MAP_S)) 1470 #define DPORT_PRO_SPI_INTR_2_MAP_V 0x1F 1471 #define DPORT_PRO_SPI_INTR_2_MAP_S 0 1472 1473 #define DPORT_PRO_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x180) 1474 /* DPORT_PRO_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1475 /*description: */ 1476 #define DPORT_PRO_SPI_INTR_3_MAP 0x0000001F 1477 #define DPORT_PRO_SPI_INTR_3_MAP_M ((DPORT_PRO_SPI_INTR_3_MAP_V)<<(DPORT_PRO_SPI_INTR_3_MAP_S)) 1478 #define DPORT_PRO_SPI_INTR_3_MAP_V 0x1F 1479 #define DPORT_PRO_SPI_INTR_3_MAP_S 0 1480 1481 #define DPORT_PRO_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x184) 1482 /* DPORT_PRO_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1483 /*description: */ 1484 #define DPORT_PRO_I2S0_INT_MAP 0x0000001F 1485 #define DPORT_PRO_I2S0_INT_MAP_M ((DPORT_PRO_I2S0_INT_MAP_V)<<(DPORT_PRO_I2S0_INT_MAP_S)) 1486 #define DPORT_PRO_I2S0_INT_MAP_V 0x1F 1487 #define DPORT_PRO_I2S0_INT_MAP_S 0 1488 1489 #define DPORT_PRO_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x188) 1490 /* DPORT_PRO_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1491 /*description: */ 1492 #define DPORT_PRO_I2S1_INT_MAP 0x0000001F 1493 #define DPORT_PRO_I2S1_INT_MAP_M ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S)) 1494 #define DPORT_PRO_I2S1_INT_MAP_V 0x1F 1495 #define DPORT_PRO_I2S1_INT_MAP_S 0 1496 1497 #define DPORT_PRO_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x18C) 1498 /* DPORT_PRO_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1499 /*description: */ 1500 #define DPORT_PRO_UART_INTR_MAP 0x0000001F 1501 #define DPORT_PRO_UART_INTR_MAP_M ((DPORT_PRO_UART_INTR_MAP_V)<<(DPORT_PRO_UART_INTR_MAP_S)) 1502 #define DPORT_PRO_UART_INTR_MAP_V 0x1F 1503 #define DPORT_PRO_UART_INTR_MAP_S 0 1504 1505 #define DPORT_PRO_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x190) 1506 /* DPORT_PRO_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1507 /*description: */ 1508 #define DPORT_PRO_UART1_INTR_MAP 0x0000001F 1509 #define DPORT_PRO_UART1_INTR_MAP_M ((DPORT_PRO_UART1_INTR_MAP_V)<<(DPORT_PRO_UART1_INTR_MAP_S)) 1510 #define DPORT_PRO_UART1_INTR_MAP_V 0x1F 1511 #define DPORT_PRO_UART1_INTR_MAP_S 0 1512 1513 #define DPORT_PRO_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x194) 1514 /* DPORT_PRO_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1515 /*description: */ 1516 #define DPORT_PRO_UART2_INTR_MAP 0x0000001F 1517 #define DPORT_PRO_UART2_INTR_MAP_M ((DPORT_PRO_UART2_INTR_MAP_V)<<(DPORT_PRO_UART2_INTR_MAP_S)) 1518 #define DPORT_PRO_UART2_INTR_MAP_V 0x1F 1519 #define DPORT_PRO_UART2_INTR_MAP_S 0 1520 1521 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x198) 1522 /* DPORT_PRO_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1523 /*description: */ 1524 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP 0x0000001F 1525 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S)) 1526 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V 0x1F 1527 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S 0 1528 1529 #define DPORT_PRO_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x19C) 1530 /* DPORT_PRO_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1531 /*description: */ 1532 #define DPORT_PRO_EMAC_INT_MAP 0x0000001F 1533 #define DPORT_PRO_EMAC_INT_MAP_M ((DPORT_PRO_EMAC_INT_MAP_V)<<(DPORT_PRO_EMAC_INT_MAP_S)) 1534 #define DPORT_PRO_EMAC_INT_MAP_V 0x1F 1535 #define DPORT_PRO_EMAC_INT_MAP_S 0 1536 1537 #define DPORT_PRO_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A0) 1538 /* DPORT_PRO_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1539 /*description: */ 1540 #define DPORT_PRO_PWM0_INTR_MAP 0x0000001F 1541 #define DPORT_PRO_PWM0_INTR_MAP_M ((DPORT_PRO_PWM0_INTR_MAP_V)<<(DPORT_PRO_PWM0_INTR_MAP_S)) 1542 #define DPORT_PRO_PWM0_INTR_MAP_V 0x1F 1543 #define DPORT_PRO_PWM0_INTR_MAP_S 0 1544 1545 #define DPORT_PRO_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A4) 1546 /* DPORT_PRO_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1547 /*description: */ 1548 #define DPORT_PRO_PWM1_INTR_MAP 0x0000001F 1549 #define DPORT_PRO_PWM1_INTR_MAP_M ((DPORT_PRO_PWM1_INTR_MAP_V)<<(DPORT_PRO_PWM1_INTR_MAP_S)) 1550 #define DPORT_PRO_PWM1_INTR_MAP_V 0x1F 1551 #define DPORT_PRO_PWM1_INTR_MAP_S 0 1552 1553 #define DPORT_PRO_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A8) 1554 /* DPORT_PRO_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1555 /*description: */ 1556 #define DPORT_PRO_PWM2_INTR_MAP 0x0000001F 1557 #define DPORT_PRO_PWM2_INTR_MAP_M ((DPORT_PRO_PWM2_INTR_MAP_V)<<(DPORT_PRO_PWM2_INTR_MAP_S)) 1558 #define DPORT_PRO_PWM2_INTR_MAP_V 0x1F 1559 #define DPORT_PRO_PWM2_INTR_MAP_S 0 1560 1561 #define DPORT_PRO_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1AC) 1562 /* DPORT_PRO_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1563 /*description: */ 1564 #define DPORT_PRO_PWM3_INTR_MAP 0x0000001F 1565 #define DPORT_PRO_PWM3_INTR_MAP_M ((DPORT_PRO_PWM3_INTR_MAP_V)<<(DPORT_PRO_PWM3_INTR_MAP_S)) 1566 #define DPORT_PRO_PWM3_INTR_MAP_V 0x1F 1567 #define DPORT_PRO_PWM3_INTR_MAP_S 0 1568 1569 #define DPORT_PRO_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B0) 1570 /* DPORT_PRO_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1571 /*description: */ 1572 #define DPORT_PRO_LEDC_INT_MAP 0x0000001F 1573 #define DPORT_PRO_LEDC_INT_MAP_M ((DPORT_PRO_LEDC_INT_MAP_V)<<(DPORT_PRO_LEDC_INT_MAP_S)) 1574 #define DPORT_PRO_LEDC_INT_MAP_V 0x1F 1575 #define DPORT_PRO_LEDC_INT_MAP_S 0 1576 1577 #define DPORT_PRO_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B4) 1578 /* DPORT_PRO_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1579 /*description: */ 1580 #define DPORT_PRO_EFUSE_INT_MAP 0x0000001F 1581 #define DPORT_PRO_EFUSE_INT_MAP_M ((DPORT_PRO_EFUSE_INT_MAP_V)<<(DPORT_PRO_EFUSE_INT_MAP_S)) 1582 #define DPORT_PRO_EFUSE_INT_MAP_V 0x1F 1583 #define DPORT_PRO_EFUSE_INT_MAP_S 0 1584 1585 #define DPORT_PRO_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B8) 1586 /* DPORT_PRO_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1587 /*description: */ 1588 #define DPORT_PRO_CAN_INT_MAP 0x0000001F 1589 #define DPORT_PRO_CAN_INT_MAP_M ((DPORT_PRO_CAN_INT_MAP_V)<<(DPORT_PRO_CAN_INT_MAP_S)) 1590 #define DPORT_PRO_CAN_INT_MAP_V 0x1F 1591 #define DPORT_PRO_CAN_INT_MAP_S 0 1592 1593 #define DPORT_PRO_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1BC) 1594 /* DPORT_PRO_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1595 /*description: */ 1596 #define DPORT_PRO_RTC_CORE_INTR_MAP 0x0000001F 1597 #define DPORT_PRO_RTC_CORE_INTR_MAP_M ((DPORT_PRO_RTC_CORE_INTR_MAP_V)<<(DPORT_PRO_RTC_CORE_INTR_MAP_S)) 1598 #define DPORT_PRO_RTC_CORE_INTR_MAP_V 0x1F 1599 #define DPORT_PRO_RTC_CORE_INTR_MAP_S 0 1600 1601 #define DPORT_PRO_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C0) 1602 /* DPORT_PRO_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1603 /*description: */ 1604 #define DPORT_PRO_RMT_INTR_MAP 0x0000001F 1605 #define DPORT_PRO_RMT_INTR_MAP_M ((DPORT_PRO_RMT_INTR_MAP_V)<<(DPORT_PRO_RMT_INTR_MAP_S)) 1606 #define DPORT_PRO_RMT_INTR_MAP_V 0x1F 1607 #define DPORT_PRO_RMT_INTR_MAP_S 0 1608 1609 #define DPORT_PRO_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C4) 1610 /* DPORT_PRO_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1611 /*description: */ 1612 #define DPORT_PRO_PCNT_INTR_MAP 0x0000001F 1613 #define DPORT_PRO_PCNT_INTR_MAP_M ((DPORT_PRO_PCNT_INTR_MAP_V)<<(DPORT_PRO_PCNT_INTR_MAP_S)) 1614 #define DPORT_PRO_PCNT_INTR_MAP_V 0x1F 1615 #define DPORT_PRO_PCNT_INTR_MAP_S 0 1616 1617 #define DPORT_PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C8) 1618 /* DPORT_PRO_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1619 /*description: */ 1620 #define DPORT_PRO_I2C_EXT0_INTR_MAP 0x0000001F 1621 #define DPORT_PRO_I2C_EXT0_INTR_MAP_M ((DPORT_PRO_I2C_EXT0_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT0_INTR_MAP_S)) 1622 #define DPORT_PRO_I2C_EXT0_INTR_MAP_V 0x1F 1623 #define DPORT_PRO_I2C_EXT0_INTR_MAP_S 0 1624 1625 #define DPORT_PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1CC) 1626 /* DPORT_PRO_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1627 /*description: */ 1628 #define DPORT_PRO_I2C_EXT1_INTR_MAP 0x0000001F 1629 #define DPORT_PRO_I2C_EXT1_INTR_MAP_M ((DPORT_PRO_I2C_EXT1_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT1_INTR_MAP_S)) 1630 #define DPORT_PRO_I2C_EXT1_INTR_MAP_V 0x1F 1631 #define DPORT_PRO_I2C_EXT1_INTR_MAP_S 0 1632 1633 #define DPORT_PRO_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1D0) 1634 /* DPORT_PRO_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1635 /*description: */ 1636 #define DPORT_PRO_RSA_INTR_MAP 0x0000001F 1637 #define DPORT_PRO_RSA_INTR_MAP_M ((DPORT_PRO_RSA_INTR_MAP_V)<<(DPORT_PRO_RSA_INTR_MAP_S)) 1638 #define DPORT_PRO_RSA_INTR_MAP_V 0x1F 1639 #define DPORT_PRO_RSA_INTR_MAP_S 0 1640 1641 #define DPORT_PRO_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D4) 1642 /* DPORT_PRO_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1643 /*description: */ 1644 #define DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F 1645 #define DPORT_PRO_SPI1_DMA_INT_MAP_M ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S)) 1646 #define DPORT_PRO_SPI1_DMA_INT_MAP_V 0x1F 1647 #define DPORT_PRO_SPI1_DMA_INT_MAP_S 0 1648 1649 #define DPORT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D8) 1650 /* DPORT_PRO_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1651 /*description: */ 1652 #define DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F 1653 #define DPORT_PRO_SPI2_DMA_INT_MAP_M ((DPORT_PRO_SPI2_DMA_INT_MAP_V)<<(DPORT_PRO_SPI2_DMA_INT_MAP_S)) 1654 #define DPORT_PRO_SPI2_DMA_INT_MAP_V 0x1F 1655 #define DPORT_PRO_SPI2_DMA_INT_MAP_S 0 1656 1657 #define DPORT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1DC) 1658 /* DPORT_PRO_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1659 /*description: */ 1660 #define DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F 1661 #define DPORT_PRO_SPI3_DMA_INT_MAP_M ((DPORT_PRO_SPI3_DMA_INT_MAP_V)<<(DPORT_PRO_SPI3_DMA_INT_MAP_S)) 1662 #define DPORT_PRO_SPI3_DMA_INT_MAP_V 0x1F 1663 #define DPORT_PRO_SPI3_DMA_INT_MAP_S 0 1664 1665 #define DPORT_PRO_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1E0) 1666 /* DPORT_PRO_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1667 /*description: */ 1668 #define DPORT_PRO_WDG_INT_MAP 0x0000001F 1669 #define DPORT_PRO_WDG_INT_MAP_M ((DPORT_PRO_WDG_INT_MAP_V)<<(DPORT_PRO_WDG_INT_MAP_S)) 1670 #define DPORT_PRO_WDG_INT_MAP_V 0x1F 1671 #define DPORT_PRO_WDG_INT_MAP_S 0 1672 1673 #define DPORT_PRO_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x1E4) 1674 /* DPORT_PRO_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1675 /*description: */ 1676 #define DPORT_PRO_TIMER_INT1_MAP 0x0000001F 1677 #define DPORT_PRO_TIMER_INT1_MAP_M ((DPORT_PRO_TIMER_INT1_MAP_V)<<(DPORT_PRO_TIMER_INT1_MAP_S)) 1678 #define DPORT_PRO_TIMER_INT1_MAP_V 0x1F 1679 #define DPORT_PRO_TIMER_INT1_MAP_S 0 1680 1681 #define DPORT_PRO_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x1E8) 1682 /* DPORT_PRO_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1683 /*description: */ 1684 #define DPORT_PRO_TIMER_INT2_MAP 0x0000001F 1685 #define DPORT_PRO_TIMER_INT2_MAP_M ((DPORT_PRO_TIMER_INT2_MAP_V)<<(DPORT_PRO_TIMER_INT2_MAP_S)) 1686 #define DPORT_PRO_TIMER_INT2_MAP_V 0x1F 1687 #define DPORT_PRO_TIMER_INT2_MAP_S 0 1688 1689 #define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1EC) 1690 /* DPORT_PRO_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1691 /*description: */ 1692 #define DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F 1693 #define DPORT_PRO_TG_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T0_EDGE_INT_MAP_S)) 1694 #define DPORT_PRO_TG_T0_EDGE_INT_MAP_V 0x1F 1695 #define DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0 1696 1697 #define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F0) 1698 /* DPORT_PRO_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1699 /*description: */ 1700 #define DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F 1701 #define DPORT_PRO_TG_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T1_EDGE_INT_MAP_S)) 1702 #define DPORT_PRO_TG_T1_EDGE_INT_MAP_V 0x1F 1703 #define DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0 1704 1705 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F4) 1706 /* DPORT_PRO_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1707 /*description: */ 1708 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F 1709 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_WDT_EDGE_INT_MAP_S)) 1710 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_V 0x1F 1711 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0 1712 1713 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F8) 1714 /* DPORT_PRO_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1715 /*description: */ 1716 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F 1717 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_LACT_EDGE_INT_MAP_S)) 1718 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_V 0x1F 1719 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0 1720 1721 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1FC) 1722 /* DPORT_PRO_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1723 /*description: */ 1724 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F 1725 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T0_EDGE_INT_MAP_S)) 1726 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_V 0x1F 1727 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0 1728 1729 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x200) 1730 /* DPORT_PRO_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1731 /*description: */ 1732 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F 1733 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T1_EDGE_INT_MAP_S)) 1734 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_V 0x1F 1735 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0 1736 1737 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x204) 1738 /* DPORT_PRO_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1739 /*description: */ 1740 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F 1741 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S)) 1742 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V 0x1F 1743 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0 1744 1745 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x208) 1746 /* DPORT_PRO_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1747 /*description: */ 1748 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F 1749 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S)) 1750 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V 0x1F 1751 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0 1752 1753 #define DPORT_PRO_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x20C) 1754 /* DPORT_PRO_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1755 /*description: */ 1756 #define DPORT_PRO_MMU_IA_INT_MAP 0x0000001F 1757 #define DPORT_PRO_MMU_IA_INT_MAP_M ((DPORT_PRO_MMU_IA_INT_MAP_V)<<(DPORT_PRO_MMU_IA_INT_MAP_S)) 1758 #define DPORT_PRO_MMU_IA_INT_MAP_V 0x1F 1759 #define DPORT_PRO_MMU_IA_INT_MAP_S 0 1760 1761 #define DPORT_PRO_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x210) 1762 /* DPORT_PRO_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1763 /*description: */ 1764 #define DPORT_PRO_MPU_IA_INT_MAP 0x0000001F 1765 #define DPORT_PRO_MPU_IA_INT_MAP_M ((DPORT_PRO_MPU_IA_INT_MAP_V)<<(DPORT_PRO_MPU_IA_INT_MAP_S)) 1766 #define DPORT_PRO_MPU_IA_INT_MAP_V 0x1F 1767 #define DPORT_PRO_MPU_IA_INT_MAP_S 0 1768 1769 #define DPORT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x214) 1770 /* DPORT_PRO_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1771 /*description: */ 1772 #define DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F 1773 #define DPORT_PRO_CACHE_IA_INT_MAP_M ((DPORT_PRO_CACHE_IA_INT_MAP_V)<<(DPORT_PRO_CACHE_IA_INT_MAP_S)) 1774 #define DPORT_PRO_CACHE_IA_INT_MAP_V 0x1F 1775 #define DPORT_PRO_CACHE_IA_INT_MAP_S 0 1776 1777 #define DPORT_APP_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x218) 1778 /* DPORT_APP_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1779 /*description: */ 1780 #define DPORT_APP_MAC_INTR_MAP 0x0000001F 1781 #define DPORT_APP_MAC_INTR_MAP_M ((DPORT_APP_MAC_INTR_MAP_V)<<(DPORT_APP_MAC_INTR_MAP_S)) 1782 #define DPORT_APP_MAC_INTR_MAP_V 0x1F 1783 #define DPORT_APP_MAC_INTR_MAP_S 0 1784 1785 #define DPORT_APP_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x21C) 1786 /* DPORT_APP_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1787 /*description: */ 1788 #define DPORT_APP_MAC_NMI_MAP 0x0000001F 1789 #define DPORT_APP_MAC_NMI_MAP_M ((DPORT_APP_MAC_NMI_MAP_V)<<(DPORT_APP_MAC_NMI_MAP_S)) 1790 #define DPORT_APP_MAC_NMI_MAP_V 0x1F 1791 #define DPORT_APP_MAC_NMI_MAP_S 0 1792 1793 #define DPORT_APP_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x220) 1794 /* DPORT_APP_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1795 /*description: */ 1796 #define DPORT_APP_BB_INT_MAP 0x0000001F 1797 #define DPORT_APP_BB_INT_MAP_M ((DPORT_APP_BB_INT_MAP_V)<<(DPORT_APP_BB_INT_MAP_S)) 1798 #define DPORT_APP_BB_INT_MAP_V 0x1F 1799 #define DPORT_APP_BB_INT_MAP_S 0 1800 1801 #define DPORT_APP_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x224) 1802 /* DPORT_APP_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1803 /*description: */ 1804 #define DPORT_APP_BT_MAC_INT_MAP 0x0000001F 1805 #define DPORT_APP_BT_MAC_INT_MAP_M ((DPORT_APP_BT_MAC_INT_MAP_V)<<(DPORT_APP_BT_MAC_INT_MAP_S)) 1806 #define DPORT_APP_BT_MAC_INT_MAP_V 0x1F 1807 #define DPORT_APP_BT_MAC_INT_MAP_S 0 1808 1809 #define DPORT_APP_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x228) 1810 /* DPORT_APP_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1811 /*description: */ 1812 #define DPORT_APP_BT_BB_INT_MAP 0x0000001F 1813 #define DPORT_APP_BT_BB_INT_MAP_M ((DPORT_APP_BT_BB_INT_MAP_V)<<(DPORT_APP_BT_BB_INT_MAP_S)) 1814 #define DPORT_APP_BT_BB_INT_MAP_V 0x1F 1815 #define DPORT_APP_BT_BB_INT_MAP_S 0 1816 1817 #define DPORT_APP_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x22C) 1818 /* DPORT_APP_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1819 /*description: */ 1820 #define DPORT_APP_BT_BB_NMI_MAP 0x0000001F 1821 #define DPORT_APP_BT_BB_NMI_MAP_M ((DPORT_APP_BT_BB_NMI_MAP_V)<<(DPORT_APP_BT_BB_NMI_MAP_S)) 1822 #define DPORT_APP_BT_BB_NMI_MAP_V 0x1F 1823 #define DPORT_APP_BT_BB_NMI_MAP_S 0 1824 1825 #define DPORT_APP_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x230) 1826 /* DPORT_APP_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1827 /*description: */ 1828 #define DPORT_APP_RWBT_IRQ_MAP 0x0000001F 1829 #define DPORT_APP_RWBT_IRQ_MAP_M ((DPORT_APP_RWBT_IRQ_MAP_V)<<(DPORT_APP_RWBT_IRQ_MAP_S)) 1830 #define DPORT_APP_RWBT_IRQ_MAP_V 0x1F 1831 #define DPORT_APP_RWBT_IRQ_MAP_S 0 1832 1833 #define DPORT_APP_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x234) 1834 /* DPORT_APP_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1835 /*description: */ 1836 #define DPORT_APP_RWBLE_IRQ_MAP 0x0000001F 1837 #define DPORT_APP_RWBLE_IRQ_MAP_M ((DPORT_APP_RWBLE_IRQ_MAP_V)<<(DPORT_APP_RWBLE_IRQ_MAP_S)) 1838 #define DPORT_APP_RWBLE_IRQ_MAP_V 0x1F 1839 #define DPORT_APP_RWBLE_IRQ_MAP_S 0 1840 1841 #define DPORT_APP_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x238) 1842 /* DPORT_APP_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1843 /*description: */ 1844 #define DPORT_APP_RWBT_NMI_MAP 0x0000001F 1845 #define DPORT_APP_RWBT_NMI_MAP_M ((DPORT_APP_RWBT_NMI_MAP_V)<<(DPORT_APP_RWBT_NMI_MAP_S)) 1846 #define DPORT_APP_RWBT_NMI_MAP_V 0x1F 1847 #define DPORT_APP_RWBT_NMI_MAP_S 0 1848 1849 #define DPORT_APP_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x23C) 1850 /* DPORT_APP_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1851 /*description: */ 1852 #define DPORT_APP_RWBLE_NMI_MAP 0x0000001F 1853 #define DPORT_APP_RWBLE_NMI_MAP_M ((DPORT_APP_RWBLE_NMI_MAP_V)<<(DPORT_APP_RWBLE_NMI_MAP_S)) 1854 #define DPORT_APP_RWBLE_NMI_MAP_V 0x1F 1855 #define DPORT_APP_RWBLE_NMI_MAP_S 0 1856 1857 #define DPORT_APP_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x240) 1858 /* DPORT_APP_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1859 /*description: */ 1860 #define DPORT_APP_SLC0_INTR_MAP 0x0000001F 1861 #define DPORT_APP_SLC0_INTR_MAP_M ((DPORT_APP_SLC0_INTR_MAP_V)<<(DPORT_APP_SLC0_INTR_MAP_S)) 1862 #define DPORT_APP_SLC0_INTR_MAP_V 0x1F 1863 #define DPORT_APP_SLC0_INTR_MAP_S 0 1864 1865 #define DPORT_APP_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x244) 1866 /* DPORT_APP_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1867 /*description: */ 1868 #define DPORT_APP_SLC1_INTR_MAP 0x0000001F 1869 #define DPORT_APP_SLC1_INTR_MAP_M ((DPORT_APP_SLC1_INTR_MAP_V)<<(DPORT_APP_SLC1_INTR_MAP_S)) 1870 #define DPORT_APP_SLC1_INTR_MAP_V 0x1F 1871 #define DPORT_APP_SLC1_INTR_MAP_S 0 1872 1873 #define DPORT_APP_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x248) 1874 /* DPORT_APP_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1875 /*description: */ 1876 #define DPORT_APP_UHCI0_INTR_MAP 0x0000001F 1877 #define DPORT_APP_UHCI0_INTR_MAP_M ((DPORT_APP_UHCI0_INTR_MAP_V)<<(DPORT_APP_UHCI0_INTR_MAP_S)) 1878 #define DPORT_APP_UHCI0_INTR_MAP_V 0x1F 1879 #define DPORT_APP_UHCI0_INTR_MAP_S 0 1880 1881 #define DPORT_APP_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x24C) 1882 /* DPORT_APP_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1883 /*description: */ 1884 #define DPORT_APP_UHCI1_INTR_MAP 0x0000001F 1885 #define DPORT_APP_UHCI1_INTR_MAP_M ((DPORT_APP_UHCI1_INTR_MAP_V)<<(DPORT_APP_UHCI1_INTR_MAP_S)) 1886 #define DPORT_APP_UHCI1_INTR_MAP_V 0x1F 1887 #define DPORT_APP_UHCI1_INTR_MAP_S 0 1888 1889 #define DPORT_APP_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x250) 1890 /* DPORT_APP_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1891 /*description: */ 1892 #define DPORT_APP_TG_T0_LEVEL_INT_MAP 0x0000001F 1893 #define DPORT_APP_TG_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T0_LEVEL_INT_MAP_S)) 1894 #define DPORT_APP_TG_T0_LEVEL_INT_MAP_V 0x1F 1895 #define DPORT_APP_TG_T0_LEVEL_INT_MAP_S 0 1896 1897 #define DPORT_APP_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x254) 1898 /* DPORT_APP_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1899 /*description: */ 1900 #define DPORT_APP_TG_T1_LEVEL_INT_MAP 0x0000001F 1901 #define DPORT_APP_TG_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T1_LEVEL_INT_MAP_S)) 1902 #define DPORT_APP_TG_T1_LEVEL_INT_MAP_V 0x1F 1903 #define DPORT_APP_TG_T1_LEVEL_INT_MAP_S 0 1904 1905 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x258) 1906 /* DPORT_APP_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1907 /*description: */ 1908 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP 0x0000001F 1909 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_WDT_LEVEL_INT_MAP_S)) 1910 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_V 0x1F 1911 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_S 0 1912 1913 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x25C) 1914 /* DPORT_APP_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1915 /*description: */ 1916 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP 0x0000001F 1917 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_LACT_LEVEL_INT_MAP_S)) 1918 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_V 0x1F 1919 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_S 0 1920 1921 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x260) 1922 /* DPORT_APP_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1923 /*description: */ 1924 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP 0x0000001F 1925 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T0_LEVEL_INT_MAP_S)) 1926 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_V 0x1F 1927 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_S 0 1928 1929 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x264) 1930 /* DPORT_APP_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1931 /*description: */ 1932 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP 0x0000001F 1933 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T1_LEVEL_INT_MAP_S)) 1934 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_V 0x1F 1935 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_S 0 1936 1937 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x268) 1938 /* DPORT_APP_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1939 /*description: */ 1940 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP 0x0000001F 1941 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S)) 1942 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V 0x1F 1943 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S 0 1944 1945 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x26C) 1946 /* DPORT_APP_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1947 /*description: */ 1948 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP 0x0000001F 1949 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S)) 1950 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V 0x1F 1951 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S 0 1952 1953 #define DPORT_APP_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x270) 1954 /* DPORT_APP_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1955 /*description: */ 1956 #define DPORT_APP_GPIO_INTERRUPT_APP_MAP 0x0000001F 1957 #define DPORT_APP_GPIO_INTERRUPT_APP_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_MAP_S)) 1958 #define DPORT_APP_GPIO_INTERRUPT_APP_MAP_V 0x1F 1959 #define DPORT_APP_GPIO_INTERRUPT_APP_MAP_S 0 1960 1961 #define DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x274) 1962 /* DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1963 /*description: */ 1964 #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F 1965 #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S)) 1966 #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F 1967 #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S 0 1968 1969 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x278) 1970 /* DPORT_APP_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1971 /*description: */ 1972 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP 0x0000001F 1973 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S)) 1974 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V 0x1F 1975 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S 0 1976 1977 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x27C) 1978 /* DPORT_APP_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1979 /*description: */ 1980 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP 0x0000001F 1981 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S)) 1982 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V 0x1F 1983 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S 0 1984 1985 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x280) 1986 /* DPORT_APP_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1987 /*description: */ 1988 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP 0x0000001F 1989 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S)) 1990 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V 0x1F 1991 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S 0 1992 1993 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x284) 1994 /* DPORT_APP_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1995 /*description: */ 1996 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP 0x0000001F 1997 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S)) 1998 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V 0x1F 1999 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S 0 2000 2001 #define DPORT_APP_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x288) 2002 /* DPORT_APP_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2003 /*description: */ 2004 #define DPORT_APP_SPI_INTR_0_MAP 0x0000001F 2005 #define DPORT_APP_SPI_INTR_0_MAP_M ((DPORT_APP_SPI_INTR_0_MAP_V)<<(DPORT_APP_SPI_INTR_0_MAP_S)) 2006 #define DPORT_APP_SPI_INTR_0_MAP_V 0x1F 2007 #define DPORT_APP_SPI_INTR_0_MAP_S 0 2008 2009 #define DPORT_APP_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x28C) 2010 /* DPORT_APP_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2011 /*description: */ 2012 #define DPORT_APP_SPI_INTR_1_MAP 0x0000001F 2013 #define DPORT_APP_SPI_INTR_1_MAP_M ((DPORT_APP_SPI_INTR_1_MAP_V)<<(DPORT_APP_SPI_INTR_1_MAP_S)) 2014 #define DPORT_APP_SPI_INTR_1_MAP_V 0x1F 2015 #define DPORT_APP_SPI_INTR_1_MAP_S 0 2016 2017 #define DPORT_APP_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x290) 2018 /* DPORT_APP_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2019 /*description: */ 2020 #define DPORT_APP_SPI_INTR_2_MAP 0x0000001F 2021 #define DPORT_APP_SPI_INTR_2_MAP_M ((DPORT_APP_SPI_INTR_2_MAP_V)<<(DPORT_APP_SPI_INTR_2_MAP_S)) 2022 #define DPORT_APP_SPI_INTR_2_MAP_V 0x1F 2023 #define DPORT_APP_SPI_INTR_2_MAP_S 0 2024 2025 #define DPORT_APP_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x294) 2026 /* DPORT_APP_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2027 /*description: */ 2028 #define DPORT_APP_SPI_INTR_3_MAP 0x0000001F 2029 #define DPORT_APP_SPI_INTR_3_MAP_M ((DPORT_APP_SPI_INTR_3_MAP_V)<<(DPORT_APP_SPI_INTR_3_MAP_S)) 2030 #define DPORT_APP_SPI_INTR_3_MAP_V 0x1F 2031 #define DPORT_APP_SPI_INTR_3_MAP_S 0 2032 2033 #define DPORT_APP_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x298) 2034 /* DPORT_APP_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2035 /*description: */ 2036 #define DPORT_APP_I2S0_INT_MAP 0x0000001F 2037 #define DPORT_APP_I2S0_INT_MAP_M ((DPORT_APP_I2S0_INT_MAP_V)<<(DPORT_APP_I2S0_INT_MAP_S)) 2038 #define DPORT_APP_I2S0_INT_MAP_V 0x1F 2039 #define DPORT_APP_I2S0_INT_MAP_S 0 2040 2041 #define DPORT_APP_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x29C) 2042 /* DPORT_APP_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2043 /*description: */ 2044 #define DPORT_APP_I2S1_INT_MAP 0x0000001F 2045 #define DPORT_APP_I2S1_INT_MAP_M ((DPORT_APP_I2S1_INT_MAP_V)<<(DPORT_APP_I2S1_INT_MAP_S)) 2046 #define DPORT_APP_I2S1_INT_MAP_V 0x1F 2047 #define DPORT_APP_I2S1_INT_MAP_S 0 2048 2049 #define DPORT_APP_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A0) 2050 /* DPORT_APP_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2051 /*description: */ 2052 #define DPORT_APP_UART_INTR_MAP 0x0000001F 2053 #define DPORT_APP_UART_INTR_MAP_M ((DPORT_APP_UART_INTR_MAP_V)<<(DPORT_APP_UART_INTR_MAP_S)) 2054 #define DPORT_APP_UART_INTR_MAP_V 0x1F 2055 #define DPORT_APP_UART_INTR_MAP_S 0 2056 2057 #define DPORT_APP_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A4) 2058 /* DPORT_APP_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2059 /*description: */ 2060 #define DPORT_APP_UART1_INTR_MAP 0x0000001F 2061 #define DPORT_APP_UART1_INTR_MAP_M ((DPORT_APP_UART1_INTR_MAP_V)<<(DPORT_APP_UART1_INTR_MAP_S)) 2062 #define DPORT_APP_UART1_INTR_MAP_V 0x1F 2063 #define DPORT_APP_UART1_INTR_MAP_S 0 2064 2065 #define DPORT_APP_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A8) 2066 /* DPORT_APP_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2067 /*description: */ 2068 #define DPORT_APP_UART2_INTR_MAP 0x0000001F 2069 #define DPORT_APP_UART2_INTR_MAP_M ((DPORT_APP_UART2_INTR_MAP_V)<<(DPORT_APP_UART2_INTR_MAP_S)) 2070 #define DPORT_APP_UART2_INTR_MAP_V 0x1F 2071 #define DPORT_APP_UART2_INTR_MAP_S 0 2072 2073 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x2AC) 2074 /* DPORT_APP_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2075 /*description: */ 2076 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP 0x0000001F 2077 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S)) 2078 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V 0x1F 2079 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S 0 2080 2081 #define DPORT_APP_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2B0) 2082 /* DPORT_APP_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2083 /*description: */ 2084 #define DPORT_APP_EMAC_INT_MAP 0x0000001F 2085 #define DPORT_APP_EMAC_INT_MAP_M ((DPORT_APP_EMAC_INT_MAP_V)<<(DPORT_APP_EMAC_INT_MAP_S)) 2086 #define DPORT_APP_EMAC_INT_MAP_V 0x1F 2087 #define DPORT_APP_EMAC_INT_MAP_S 0 2088 2089 #define DPORT_APP_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B4) 2090 /* DPORT_APP_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2091 /*description: */ 2092 #define DPORT_APP_PWM0_INTR_MAP 0x0000001F 2093 #define DPORT_APP_PWM0_INTR_MAP_M ((DPORT_APP_PWM0_INTR_MAP_V)<<(DPORT_APP_PWM0_INTR_MAP_S)) 2094 #define DPORT_APP_PWM0_INTR_MAP_V 0x1F 2095 #define DPORT_APP_PWM0_INTR_MAP_S 0 2096 2097 #define DPORT_APP_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B8) 2098 /* DPORT_APP_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2099 /*description: */ 2100 #define DPORT_APP_PWM1_INTR_MAP 0x0000001F 2101 #define DPORT_APP_PWM1_INTR_MAP_M ((DPORT_APP_PWM1_INTR_MAP_V)<<(DPORT_APP_PWM1_INTR_MAP_S)) 2102 #define DPORT_APP_PWM1_INTR_MAP_V 0x1F 2103 #define DPORT_APP_PWM1_INTR_MAP_S 0 2104 2105 #define DPORT_APP_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2BC) 2106 /* DPORT_APP_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2107 /*description: */ 2108 #define DPORT_APP_PWM2_INTR_MAP 0x0000001F 2109 #define DPORT_APP_PWM2_INTR_MAP_M ((DPORT_APP_PWM2_INTR_MAP_V)<<(DPORT_APP_PWM2_INTR_MAP_S)) 2110 #define DPORT_APP_PWM2_INTR_MAP_V 0x1F 2111 #define DPORT_APP_PWM2_INTR_MAP_S 0 2112 2113 #define DPORT_APP_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2C0) 2114 /* DPORT_APP_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2115 /*description: */ 2116 #define DPORT_APP_PWM3_INTR_MAP 0x0000001F 2117 #define DPORT_APP_PWM3_INTR_MAP_M ((DPORT_APP_PWM3_INTR_MAP_V)<<(DPORT_APP_PWM3_INTR_MAP_S)) 2118 #define DPORT_APP_PWM3_INTR_MAP_V 0x1F 2119 #define DPORT_APP_PWM3_INTR_MAP_S 0 2120 2121 #define DPORT_APP_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C4) 2122 /* DPORT_APP_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2123 /*description: */ 2124 #define DPORT_APP_LEDC_INT_MAP 0x0000001F 2125 #define DPORT_APP_LEDC_INT_MAP_M ((DPORT_APP_LEDC_INT_MAP_V)<<(DPORT_APP_LEDC_INT_MAP_S)) 2126 #define DPORT_APP_LEDC_INT_MAP_V 0x1F 2127 #define DPORT_APP_LEDC_INT_MAP_S 0 2128 2129 #define DPORT_APP_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C8) 2130 /* DPORT_APP_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2131 /*description: */ 2132 #define DPORT_APP_EFUSE_INT_MAP 0x0000001F 2133 #define DPORT_APP_EFUSE_INT_MAP_M ((DPORT_APP_EFUSE_INT_MAP_V)<<(DPORT_APP_EFUSE_INT_MAP_S)) 2134 #define DPORT_APP_EFUSE_INT_MAP_V 0x1F 2135 #define DPORT_APP_EFUSE_INT_MAP_S 0 2136 2137 #define DPORT_APP_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2CC) 2138 /* DPORT_APP_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2139 /*description: */ 2140 #define DPORT_APP_CAN_INT_MAP 0x0000001F 2141 #define DPORT_APP_CAN_INT_MAP_M ((DPORT_APP_CAN_INT_MAP_V)<<(DPORT_APP_CAN_INT_MAP_S)) 2142 #define DPORT_APP_CAN_INT_MAP_V 0x1F 2143 #define DPORT_APP_CAN_INT_MAP_S 0 2144 2145 #define DPORT_APP_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D0) 2146 /* DPORT_APP_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2147 /*description: */ 2148 #define DPORT_APP_RTC_CORE_INTR_MAP 0x0000001F 2149 #define DPORT_APP_RTC_CORE_INTR_MAP_M ((DPORT_APP_RTC_CORE_INTR_MAP_V)<<(DPORT_APP_RTC_CORE_INTR_MAP_S)) 2150 #define DPORT_APP_RTC_CORE_INTR_MAP_V 0x1F 2151 #define DPORT_APP_RTC_CORE_INTR_MAP_S 0 2152 2153 #define DPORT_APP_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D4) 2154 /* DPORT_APP_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2155 /*description: */ 2156 #define DPORT_APP_RMT_INTR_MAP 0x0000001F 2157 #define DPORT_APP_RMT_INTR_MAP_M ((DPORT_APP_RMT_INTR_MAP_V)<<(DPORT_APP_RMT_INTR_MAP_S)) 2158 #define DPORT_APP_RMT_INTR_MAP_V 0x1F 2159 #define DPORT_APP_RMT_INTR_MAP_S 0 2160 2161 #define DPORT_APP_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D8) 2162 /* DPORT_APP_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2163 /*description: */ 2164 #define DPORT_APP_PCNT_INTR_MAP 0x0000001F 2165 #define DPORT_APP_PCNT_INTR_MAP_M ((DPORT_APP_PCNT_INTR_MAP_V)<<(DPORT_APP_PCNT_INTR_MAP_S)) 2166 #define DPORT_APP_PCNT_INTR_MAP_V 0x1F 2167 #define DPORT_APP_PCNT_INTR_MAP_S 0 2168 2169 #define DPORT_APP_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2DC) 2170 /* DPORT_APP_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2171 /*description: */ 2172 #define DPORT_APP_I2C_EXT0_INTR_MAP 0x0000001F 2173 #define DPORT_APP_I2C_EXT0_INTR_MAP_M ((DPORT_APP_I2C_EXT0_INTR_MAP_V)<<(DPORT_APP_I2C_EXT0_INTR_MAP_S)) 2174 #define DPORT_APP_I2C_EXT0_INTR_MAP_V 0x1F 2175 #define DPORT_APP_I2C_EXT0_INTR_MAP_S 0 2176 2177 #define DPORT_APP_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E0) 2178 /* DPORT_APP_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2179 /*description: */ 2180 #define DPORT_APP_I2C_EXT1_INTR_MAP 0x0000001F 2181 #define DPORT_APP_I2C_EXT1_INTR_MAP_M ((DPORT_APP_I2C_EXT1_INTR_MAP_V)<<(DPORT_APP_I2C_EXT1_INTR_MAP_S)) 2182 #define DPORT_APP_I2C_EXT1_INTR_MAP_V 0x1F 2183 #define DPORT_APP_I2C_EXT1_INTR_MAP_S 0 2184 2185 #define DPORT_APP_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E4) 2186 /* DPORT_APP_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2187 /*description: */ 2188 #define DPORT_APP_RSA_INTR_MAP 0x0000001F 2189 #define DPORT_APP_RSA_INTR_MAP_M ((DPORT_APP_RSA_INTR_MAP_V)<<(DPORT_APP_RSA_INTR_MAP_S)) 2190 #define DPORT_APP_RSA_INTR_MAP_V 0x1F 2191 #define DPORT_APP_RSA_INTR_MAP_S 0 2192 2193 #define DPORT_APP_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2E8) 2194 /* DPORT_APP_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2195 /*description: */ 2196 #define DPORT_APP_SPI1_DMA_INT_MAP 0x0000001F 2197 #define DPORT_APP_SPI1_DMA_INT_MAP_M ((DPORT_APP_SPI1_DMA_INT_MAP_V)<<(DPORT_APP_SPI1_DMA_INT_MAP_S)) 2198 #define DPORT_APP_SPI1_DMA_INT_MAP_V 0x1F 2199 #define DPORT_APP_SPI1_DMA_INT_MAP_S 0 2200 2201 #define DPORT_APP_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2EC) 2202 /* DPORT_APP_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2203 /*description: */ 2204 #define DPORT_APP_SPI2_DMA_INT_MAP 0x0000001F 2205 #define DPORT_APP_SPI2_DMA_INT_MAP_M ((DPORT_APP_SPI2_DMA_INT_MAP_V)<<(DPORT_APP_SPI2_DMA_INT_MAP_S)) 2206 #define DPORT_APP_SPI2_DMA_INT_MAP_V 0x1F 2207 #define DPORT_APP_SPI2_DMA_INT_MAP_S 0 2208 2209 #define DPORT_APP_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F0) 2210 /* DPORT_APP_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2211 /*description: */ 2212 #define DPORT_APP_SPI3_DMA_INT_MAP 0x0000001F 2213 #define DPORT_APP_SPI3_DMA_INT_MAP_M ((DPORT_APP_SPI3_DMA_INT_MAP_V)<<(DPORT_APP_SPI3_DMA_INT_MAP_S)) 2214 #define DPORT_APP_SPI3_DMA_INT_MAP_V 0x1F 2215 #define DPORT_APP_SPI3_DMA_INT_MAP_S 0 2216 2217 #define DPORT_APP_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F4) 2218 /* DPORT_APP_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2219 /*description: */ 2220 #define DPORT_APP_WDG_INT_MAP 0x0000001F 2221 #define DPORT_APP_WDG_INT_MAP_M ((DPORT_APP_WDG_INT_MAP_V)<<(DPORT_APP_WDG_INT_MAP_S)) 2222 #define DPORT_APP_WDG_INT_MAP_V 0x1F 2223 #define DPORT_APP_WDG_INT_MAP_S 0 2224 2225 #define DPORT_APP_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x2F8) 2226 /* DPORT_APP_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2227 /*description: */ 2228 #define DPORT_APP_TIMER_INT1_MAP 0x0000001F 2229 #define DPORT_APP_TIMER_INT1_MAP_M ((DPORT_APP_TIMER_INT1_MAP_V)<<(DPORT_APP_TIMER_INT1_MAP_S)) 2230 #define DPORT_APP_TIMER_INT1_MAP_V 0x1F 2231 #define DPORT_APP_TIMER_INT1_MAP_S 0 2232 2233 #define DPORT_APP_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x2FC) 2234 /* DPORT_APP_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2235 /*description: */ 2236 #define DPORT_APP_TIMER_INT2_MAP 0x0000001F 2237 #define DPORT_APP_TIMER_INT2_MAP_M ((DPORT_APP_TIMER_INT2_MAP_V)<<(DPORT_APP_TIMER_INT2_MAP_S)) 2238 #define DPORT_APP_TIMER_INT2_MAP_V 0x1F 2239 #define DPORT_APP_TIMER_INT2_MAP_S 0 2240 2241 #define DPORT_APP_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x300) 2242 /* DPORT_APP_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2243 /*description: */ 2244 #define DPORT_APP_TG_T0_EDGE_INT_MAP 0x0000001F 2245 #define DPORT_APP_TG_T0_EDGE_INT_MAP_M ((DPORT_APP_TG_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T0_EDGE_INT_MAP_S)) 2246 #define DPORT_APP_TG_T0_EDGE_INT_MAP_V 0x1F 2247 #define DPORT_APP_TG_T0_EDGE_INT_MAP_S 0 2248 2249 #define DPORT_APP_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x304) 2250 /* DPORT_APP_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2251 /*description: */ 2252 #define DPORT_APP_TG_T1_EDGE_INT_MAP 0x0000001F 2253 #define DPORT_APP_TG_T1_EDGE_INT_MAP_M ((DPORT_APP_TG_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T1_EDGE_INT_MAP_S)) 2254 #define DPORT_APP_TG_T1_EDGE_INT_MAP_V 0x1F 2255 #define DPORT_APP_TG_T1_EDGE_INT_MAP_S 0 2256 2257 #define DPORT_APP_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x308) 2258 /* DPORT_APP_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2259 /*description: */ 2260 #define DPORT_APP_TG_WDT_EDGE_INT_MAP 0x0000001F 2261 #define DPORT_APP_TG_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_WDT_EDGE_INT_MAP_S)) 2262 #define DPORT_APP_TG_WDT_EDGE_INT_MAP_V 0x1F 2263 #define DPORT_APP_TG_WDT_EDGE_INT_MAP_S 0 2264 2265 #define DPORT_APP_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x30C) 2266 /* DPORT_APP_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2267 /*description: */ 2268 #define DPORT_APP_TG_LACT_EDGE_INT_MAP 0x0000001F 2269 #define DPORT_APP_TG_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_LACT_EDGE_INT_MAP_S)) 2270 #define DPORT_APP_TG_LACT_EDGE_INT_MAP_V 0x1F 2271 #define DPORT_APP_TG_LACT_EDGE_INT_MAP_S 0 2272 2273 #define DPORT_APP_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x310) 2274 /* DPORT_APP_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2275 /*description: */ 2276 #define DPORT_APP_TG1_T0_EDGE_INT_MAP 0x0000001F 2277 #define DPORT_APP_TG1_T0_EDGE_INT_MAP_M ((DPORT_APP_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T0_EDGE_INT_MAP_S)) 2278 #define DPORT_APP_TG1_T0_EDGE_INT_MAP_V 0x1F 2279 #define DPORT_APP_TG1_T0_EDGE_INT_MAP_S 0 2280 2281 #define DPORT_APP_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x314) 2282 /* DPORT_APP_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2283 /*description: */ 2284 #define DPORT_APP_TG1_T1_EDGE_INT_MAP 0x0000001F 2285 #define DPORT_APP_TG1_T1_EDGE_INT_MAP_M ((DPORT_APP_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T1_EDGE_INT_MAP_S)) 2286 #define DPORT_APP_TG1_T1_EDGE_INT_MAP_V 0x1F 2287 #define DPORT_APP_TG1_T1_EDGE_INT_MAP_S 0 2288 2289 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x318) 2290 /* DPORT_APP_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2291 /*description: */ 2292 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP 0x0000001F 2293 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_WDT_EDGE_INT_MAP_S)) 2294 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_V 0x1F 2295 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_S 0 2296 2297 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x31C) 2298 /* DPORT_APP_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2299 /*description: */ 2300 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP 0x0000001F 2301 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_LACT_EDGE_INT_MAP_S)) 2302 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_V 0x1F 2303 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_S 0 2304 2305 #define DPORT_APP_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x320) 2306 /* DPORT_APP_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2307 /*description: */ 2308 #define DPORT_APP_MMU_IA_INT_MAP 0x0000001F 2309 #define DPORT_APP_MMU_IA_INT_MAP_M ((DPORT_APP_MMU_IA_INT_MAP_V)<<(DPORT_APP_MMU_IA_INT_MAP_S)) 2310 #define DPORT_APP_MMU_IA_INT_MAP_V 0x1F 2311 #define DPORT_APP_MMU_IA_INT_MAP_S 0 2312 2313 #define DPORT_APP_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x324) 2314 /* DPORT_APP_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2315 /*description: */ 2316 #define DPORT_APP_MPU_IA_INT_MAP 0x0000001F 2317 #define DPORT_APP_MPU_IA_INT_MAP_M ((DPORT_APP_MPU_IA_INT_MAP_V)<<(DPORT_APP_MPU_IA_INT_MAP_S)) 2318 #define DPORT_APP_MPU_IA_INT_MAP_V 0x1F 2319 #define DPORT_APP_MPU_IA_INT_MAP_S 0 2320 2321 #define DPORT_APP_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x328) 2322 /* DPORT_APP_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2323 /*description: */ 2324 #define DPORT_APP_CACHE_IA_INT_MAP 0x0000001F 2325 #define DPORT_APP_CACHE_IA_INT_MAP_M ((DPORT_APP_CACHE_IA_INT_MAP_V)<<(DPORT_APP_CACHE_IA_INT_MAP_S)) 2326 #define DPORT_APP_CACHE_IA_INT_MAP_V 0x1F 2327 #define DPORT_APP_CACHE_IA_INT_MAP_S 0 2328 2329 #define DPORT_AHBLITE_MPU_TABLE_UART_REG (DR_REG_DPORT_BASE + 0x32C) 2330 /* DPORT_UART_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2331 /*description: */ 2332 #define DPORT_UART_ACCESS_GRANT_CONFIG 0x0000003F 2333 #define DPORT_UART_ACCESS_GRANT_CONFIG_M ((DPORT_UART_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART_ACCESS_GRANT_CONFIG_S)) 2334 #define DPORT_UART_ACCESS_GRANT_CONFIG_V 0x3F 2335 #define DPORT_UART_ACCESS_GRANT_CONFIG_S 0 2336 2337 #define DPORT_AHBLITE_MPU_TABLE_SPI1_REG (DR_REG_DPORT_BASE + 0x330) 2338 /* DPORT_SPI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2339 /*description: */ 2340 #define DPORT_SPI1_ACCESS_GRANT_CONFIG 0x0000003F 2341 #define DPORT_SPI1_ACCESS_GRANT_CONFIG_M ((DPORT_SPI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI1_ACCESS_GRANT_CONFIG_S)) 2342 #define DPORT_SPI1_ACCESS_GRANT_CONFIG_V 0x3F 2343 #define DPORT_SPI1_ACCESS_GRANT_CONFIG_S 0 2344 2345 #define DPORT_AHBLITE_MPU_TABLE_SPI0_REG (DR_REG_DPORT_BASE + 0x334) 2346 /* DPORT_SPI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2347 /*description: */ 2348 #define DPORT_SPI0_ACCESS_GRANT_CONFIG 0x0000003F 2349 #define DPORT_SPI0_ACCESS_GRANT_CONFIG_M ((DPORT_SPI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI0_ACCESS_GRANT_CONFIG_S)) 2350 #define DPORT_SPI0_ACCESS_GRANT_CONFIG_V 0x3F 2351 #define DPORT_SPI0_ACCESS_GRANT_CONFIG_S 0 2352 2353 #define DPORT_AHBLITE_MPU_TABLE_GPIO_REG (DR_REG_DPORT_BASE + 0x338) 2354 /* DPORT_GPIO_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2355 /*description: */ 2356 #define DPORT_GPIO_ACCESS_GRANT_CONFIG 0x0000003F 2357 #define DPORT_GPIO_ACCESS_GRANT_CONFIG_M ((DPORT_GPIO_ACCESS_GRANT_CONFIG_V)<<(DPORT_GPIO_ACCESS_GRANT_CONFIG_S)) 2358 #define DPORT_GPIO_ACCESS_GRANT_CONFIG_V 0x3F 2359 #define DPORT_GPIO_ACCESS_GRANT_CONFIG_S 0 2360 2361 #define DPORT_AHBLITE_MPU_TABLE_FE2_REG (DR_REG_DPORT_BASE + 0x33C) 2362 /* DPORT_FE2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2363 /*description: */ 2364 #define DPORT_FE2_ACCESS_GRANT_CONFIG 0x0000003F 2365 #define DPORT_FE2_ACCESS_GRANT_CONFIG_M ((DPORT_FE2_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE2_ACCESS_GRANT_CONFIG_S)) 2366 #define DPORT_FE2_ACCESS_GRANT_CONFIG_V 0x3F 2367 #define DPORT_FE2_ACCESS_GRANT_CONFIG_S 0 2368 2369 #define DPORT_AHBLITE_MPU_TABLE_FE_REG (DR_REG_DPORT_BASE + 0x340) 2370 /* DPORT_FE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2371 /*description: */ 2372 #define DPORT_FE_ACCESS_GRANT_CONFIG 0x0000003F 2373 #define DPORT_FE_ACCESS_GRANT_CONFIG_M ((DPORT_FE_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE_ACCESS_GRANT_CONFIG_S)) 2374 #define DPORT_FE_ACCESS_GRANT_CONFIG_V 0x3F 2375 #define DPORT_FE_ACCESS_GRANT_CONFIG_S 0 2376 2377 #define DPORT_AHBLITE_MPU_TABLE_TIMER_REG (DR_REG_DPORT_BASE + 0x344) 2378 /* DPORT_TIMER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2379 /*description: */ 2380 #define DPORT_TIMER_ACCESS_GRANT_CONFIG 0x0000003F 2381 #define DPORT_TIMER_ACCESS_GRANT_CONFIG_M ((DPORT_TIMER_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMER_ACCESS_GRANT_CONFIG_S)) 2382 #define DPORT_TIMER_ACCESS_GRANT_CONFIG_V 0x3F 2383 #define DPORT_TIMER_ACCESS_GRANT_CONFIG_S 0 2384 2385 #define DPORT_AHBLITE_MPU_TABLE_RTC_REG (DR_REG_DPORT_BASE + 0x348) 2386 /* DPORT_RTC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2387 /*description: */ 2388 #define DPORT_RTC_ACCESS_GRANT_CONFIG 0x0000003F 2389 #define DPORT_RTC_ACCESS_GRANT_CONFIG_M ((DPORT_RTC_ACCESS_GRANT_CONFIG_V)<<(DPORT_RTC_ACCESS_GRANT_CONFIG_S)) 2390 #define DPORT_RTC_ACCESS_GRANT_CONFIG_V 0x3F 2391 #define DPORT_RTC_ACCESS_GRANT_CONFIG_S 0 2392 2393 #define DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG (DR_REG_DPORT_BASE + 0x34C) 2394 /* DPORT_IOMUX_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2395 /*description: */ 2396 #define DPORT_IOMUX_ACCESS_GRANT_CONFIG 0x0000003F 2397 #define DPORT_IOMUX_ACCESS_GRANT_CONFIG_M ((DPORT_IOMUX_ACCESS_GRANT_CONFIG_V)<<(DPORT_IOMUX_ACCESS_GRANT_CONFIG_S)) 2398 #define DPORT_IOMUX_ACCESS_GRANT_CONFIG_V 0x3F 2399 #define DPORT_IOMUX_ACCESS_GRANT_CONFIG_S 0 2400 2401 #define DPORT_AHBLITE_MPU_TABLE_WDG_REG (DR_REG_DPORT_BASE + 0x350) 2402 /* DPORT_WDG_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2403 /*description: */ 2404 #define DPORT_WDG_ACCESS_GRANT_CONFIG 0x0000003F 2405 #define DPORT_WDG_ACCESS_GRANT_CONFIG_M ((DPORT_WDG_ACCESS_GRANT_CONFIG_V)<<(DPORT_WDG_ACCESS_GRANT_CONFIG_S)) 2406 #define DPORT_WDG_ACCESS_GRANT_CONFIG_V 0x3F 2407 #define DPORT_WDG_ACCESS_GRANT_CONFIG_S 0 2408 2409 #define DPORT_AHBLITE_MPU_TABLE_HINF_REG (DR_REG_DPORT_BASE + 0x354) 2410 /* DPORT_HINF_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2411 /*description: */ 2412 #define DPORT_HINF_ACCESS_GRANT_CONFIG 0x0000003F 2413 #define DPORT_HINF_ACCESS_GRANT_CONFIG_M ((DPORT_HINF_ACCESS_GRANT_CONFIG_V)<<(DPORT_HINF_ACCESS_GRANT_CONFIG_S)) 2414 #define DPORT_HINF_ACCESS_GRANT_CONFIG_V 0x3F 2415 #define DPORT_HINF_ACCESS_GRANT_CONFIG_S 0 2416 2417 #define DPORT_AHBLITE_MPU_TABLE_UHCI1_REG (DR_REG_DPORT_BASE + 0x358) 2418 /* DPORT_UHCI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2419 /*description: */ 2420 #define DPORT_UHCI1_ACCESS_GRANT_CONFIG 0x0000003F 2421 #define DPORT_UHCI1_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI1_ACCESS_GRANT_CONFIG_S)) 2422 #define DPORT_UHCI1_ACCESS_GRANT_CONFIG_V 0x3F 2423 #define DPORT_UHCI1_ACCESS_GRANT_CONFIG_S 0 2424 2425 #define DPORT_AHBLITE_MPU_TABLE_MISC_REG (DR_REG_DPORT_BASE + 0x35C) 2426 /* DPORT_MISC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2427 /*description: */ 2428 #define DPORT_MISC_ACCESS_GRANT_CONFIG 0x0000003F 2429 #define DPORT_MISC_ACCESS_GRANT_CONFIG_M ((DPORT_MISC_ACCESS_GRANT_CONFIG_V)<<(DPORT_MISC_ACCESS_GRANT_CONFIG_S)) 2430 #define DPORT_MISC_ACCESS_GRANT_CONFIG_V 0x3F 2431 #define DPORT_MISC_ACCESS_GRANT_CONFIG_S 0 2432 2433 #define DPORT_AHBLITE_MPU_TABLE_I2C_REG (DR_REG_DPORT_BASE + 0x360) 2434 /* DPORT_I2C_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2435 /*description: */ 2436 #define DPORT_I2C_ACCESS_GRANT_CONFIG 0x0000003F 2437 #define DPORT_I2C_ACCESS_GRANT_CONFIG_M ((DPORT_I2C_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2C_ACCESS_GRANT_CONFIG_S)) 2438 #define DPORT_I2C_ACCESS_GRANT_CONFIG_V 0x3F 2439 #define DPORT_I2C_ACCESS_GRANT_CONFIG_S 0 2440 2441 #define DPORT_AHBLITE_MPU_TABLE_I2S0_REG (DR_REG_DPORT_BASE + 0x364) 2442 /* DPORT_I2S0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2443 /*description: */ 2444 #define DPORT_I2S0_ACCESS_GRANT_CONFIG 0x0000003F 2445 #define DPORT_I2S0_ACCESS_GRANT_CONFIG_M ((DPORT_I2S0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S0_ACCESS_GRANT_CONFIG_S)) 2446 #define DPORT_I2S0_ACCESS_GRANT_CONFIG_V 0x3F 2447 #define DPORT_I2S0_ACCESS_GRANT_CONFIG_S 0 2448 2449 #define DPORT_AHBLITE_MPU_TABLE_UART1_REG (DR_REG_DPORT_BASE + 0x368) 2450 /* DPORT_UART1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2451 /*description: */ 2452 #define DPORT_UART1_ACCESS_GRANT_CONFIG 0x0000003F 2453 #define DPORT_UART1_ACCESS_GRANT_CONFIG_M ((DPORT_UART1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART1_ACCESS_GRANT_CONFIG_S)) 2454 #define DPORT_UART1_ACCESS_GRANT_CONFIG_V 0x3F 2455 #define DPORT_UART1_ACCESS_GRANT_CONFIG_S 0 2456 2457 #define DPORT_AHBLITE_MPU_TABLE_BT_REG (DR_REG_DPORT_BASE + 0x36C) 2458 /* DPORT_BT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2459 /*description: */ 2460 #define DPORT_BT_ACCESS_GRANT_CONFIG 0x0000003F 2461 #define DPORT_BT_ACCESS_GRANT_CONFIG_M ((DPORT_BT_ACCESS_GRANT_CONFIG_V)<<(DPORT_BT_ACCESS_GRANT_CONFIG_S)) 2462 #define DPORT_BT_ACCESS_GRANT_CONFIG_V 0x3F 2463 #define DPORT_BT_ACCESS_GRANT_CONFIG_S 0 2464 2465 #define DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG (DR_REG_DPORT_BASE + 0x370) 2466 /* DPORT_BTBUFFER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2467 /*description: */ 2468 #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG 0x0000003F 2469 #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_M ((DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S)) 2470 #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V 0x3F 2471 #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S 0 2472 2473 #define DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG (DR_REG_DPORT_BASE + 0x374) 2474 /* DPORT_I2CEXT0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2475 /*description: */ 2476 #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG 0x0000003F 2477 #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S)) 2478 #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V 0x3F 2479 #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S 0 2480 2481 #define DPORT_AHBLITE_MPU_TABLE_UHCI0_REG (DR_REG_DPORT_BASE + 0x378) 2482 /* DPORT_UHCI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2483 /*description: */ 2484 #define DPORT_UHCI0_ACCESS_GRANT_CONFIG 0x0000003F 2485 #define DPORT_UHCI0_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI0_ACCESS_GRANT_CONFIG_S)) 2486 #define DPORT_UHCI0_ACCESS_GRANT_CONFIG_V 0x3F 2487 #define DPORT_UHCI0_ACCESS_GRANT_CONFIG_S 0 2488 2489 #define DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG (DR_REG_DPORT_BASE + 0x37C) 2490 /* DPORT_SLCHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2491 /*description: */ 2492 #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG 0x0000003F 2493 #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S)) 2494 #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V 0x3F 2495 #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S 0 2496 2497 #define DPORT_AHBLITE_MPU_TABLE_RMT_REG (DR_REG_DPORT_BASE + 0x380) 2498 /* DPORT_RMT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2499 /*description: */ 2500 #define DPORT_RMT_ACCESS_GRANT_CONFIG 0x0000003F 2501 #define DPORT_RMT_ACCESS_GRANT_CONFIG_M ((DPORT_RMT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RMT_ACCESS_GRANT_CONFIG_S)) 2502 #define DPORT_RMT_ACCESS_GRANT_CONFIG_V 0x3F 2503 #define DPORT_RMT_ACCESS_GRANT_CONFIG_S 0 2504 2505 #define DPORT_AHBLITE_MPU_TABLE_PCNT_REG (DR_REG_DPORT_BASE + 0x384) 2506 /* DPORT_PCNT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2507 /*description: */ 2508 #define DPORT_PCNT_ACCESS_GRANT_CONFIG 0x0000003F 2509 #define DPORT_PCNT_ACCESS_GRANT_CONFIG_M ((DPORT_PCNT_ACCESS_GRANT_CONFIG_V)<<(DPORT_PCNT_ACCESS_GRANT_CONFIG_S)) 2510 #define DPORT_PCNT_ACCESS_GRANT_CONFIG_V 0x3F 2511 #define DPORT_PCNT_ACCESS_GRANT_CONFIG_S 0 2512 2513 #define DPORT_AHBLITE_MPU_TABLE_SLC_REG (DR_REG_DPORT_BASE + 0x388) 2514 /* DPORT_SLC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2515 /*description: */ 2516 #define DPORT_SLC_ACCESS_GRANT_CONFIG 0x0000003F 2517 #define DPORT_SLC_ACCESS_GRANT_CONFIG_M ((DPORT_SLC_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLC_ACCESS_GRANT_CONFIG_S)) 2518 #define DPORT_SLC_ACCESS_GRANT_CONFIG_V 0x3F 2519 #define DPORT_SLC_ACCESS_GRANT_CONFIG_S 0 2520 2521 #define DPORT_AHBLITE_MPU_TABLE_LEDC_REG (DR_REG_DPORT_BASE + 0x38C) 2522 /* DPORT_LEDC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2523 /*description: */ 2524 #define DPORT_LEDC_ACCESS_GRANT_CONFIG 0x0000003F 2525 #define DPORT_LEDC_ACCESS_GRANT_CONFIG_M ((DPORT_LEDC_ACCESS_GRANT_CONFIG_V)<<(DPORT_LEDC_ACCESS_GRANT_CONFIG_S)) 2526 #define DPORT_LEDC_ACCESS_GRANT_CONFIG_V 0x3F 2527 #define DPORT_LEDC_ACCESS_GRANT_CONFIG_S 0 2528 2529 #define DPORT_AHBLITE_MPU_TABLE_EFUSE_REG (DR_REG_DPORT_BASE + 0x390) 2530 /* DPORT_EFUSE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2531 /*description: */ 2532 #define DPORT_EFUSE_ACCESS_GRANT_CONFIG 0x0000003F 2533 #define DPORT_EFUSE_ACCESS_GRANT_CONFIG_M ((DPORT_EFUSE_ACCESS_GRANT_CONFIG_V)<<(DPORT_EFUSE_ACCESS_GRANT_CONFIG_S)) 2534 #define DPORT_EFUSE_ACCESS_GRANT_CONFIG_V 0x3F 2535 #define DPORT_EFUSE_ACCESS_GRANT_CONFIG_S 0 2536 2537 #define DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG (DR_REG_DPORT_BASE + 0x394) 2538 /* DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2539 /*description: */ 2540 #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG 0x0000003F 2541 #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_M ((DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S)) 2542 #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V 0x3F 2543 #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S 0 2544 2545 #define DPORT_AHBLITE_MPU_TABLE_BB_REG (DR_REG_DPORT_BASE + 0x398) 2546 /* DPORT_BB_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2547 /*description: */ 2548 #define DPORT_BB_ACCESS_GRANT_CONFIG 0x0000003F 2549 #define DPORT_BB_ACCESS_GRANT_CONFIG_M ((DPORT_BB_ACCESS_GRANT_CONFIG_V)<<(DPORT_BB_ACCESS_GRANT_CONFIG_S)) 2550 #define DPORT_BB_ACCESS_GRANT_CONFIG_V 0x3F 2551 #define DPORT_BB_ACCESS_GRANT_CONFIG_S 0 2552 2553 #define DPORT_AHBLITE_MPU_TABLE_PWM0_REG (DR_REG_DPORT_BASE + 0x39C) 2554 /* DPORT_PWM0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2555 /*description: */ 2556 #define DPORT_PWM0_ACCESS_GRANT_CONFIG 0x0000003F 2557 #define DPORT_PWM0_ACCESS_GRANT_CONFIG_M ((DPORT_PWM0_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM0_ACCESS_GRANT_CONFIG_S)) 2558 #define DPORT_PWM0_ACCESS_GRANT_CONFIG_V 0x3F 2559 #define DPORT_PWM0_ACCESS_GRANT_CONFIG_S 0 2560 2561 #define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG (DR_REG_DPORT_BASE + 0x3A0) 2562 /* DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2563 /*description: */ 2564 #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG 0x0000003F 2565 #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S)) 2566 #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V 0x3F 2567 #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S 0 2568 2569 #define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG (DR_REG_DPORT_BASE + 0x3A4) 2570 /* DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2571 /*description: */ 2572 #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG 0x0000003F 2573 #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S)) 2574 #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V 0x3F 2575 #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S 0 2576 2577 #define DPORT_AHBLITE_MPU_TABLE_SPI2_REG (DR_REG_DPORT_BASE + 0x3A8) 2578 /* DPORT_SPI2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2579 /*description: */ 2580 #define DPORT_SPI2_ACCESS_GRANT_CONFIG 0x0000003F 2581 #define DPORT_SPI2_ACCESS_GRANT_CONFIG_M ((DPORT_SPI2_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI2_ACCESS_GRANT_CONFIG_S)) 2582 #define DPORT_SPI2_ACCESS_GRANT_CONFIG_V 0x3F 2583 #define DPORT_SPI2_ACCESS_GRANT_CONFIG_S 0 2584 2585 #define DPORT_AHBLITE_MPU_TABLE_SPI3_REG (DR_REG_DPORT_BASE + 0x3AC) 2586 /* DPORT_SPI3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2587 /*description: */ 2588 #define DPORT_SPI3_ACCESS_GRANT_CONFIG 0x0000003F 2589 #define DPORT_SPI3_ACCESS_GRANT_CONFIG_M ((DPORT_SPI3_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI3_ACCESS_GRANT_CONFIG_S)) 2590 #define DPORT_SPI3_ACCESS_GRANT_CONFIG_V 0x3F 2591 #define DPORT_SPI3_ACCESS_GRANT_CONFIG_S 0 2592 2593 #define DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG (DR_REG_DPORT_BASE + 0x3B0) 2594 /* DPORT_APBCTRL_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2595 /*description: */ 2596 #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG 0x0000003F 2597 #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_M ((DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V)<<(DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S)) 2598 #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V 0x3F 2599 #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S 0 2600 2601 #define DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG (DR_REG_DPORT_BASE + 0x3B4) 2602 /* DPORT_I2CEXT1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2603 /*description: */ 2604 #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG 0x0000003F 2605 #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S)) 2606 #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V 0x3F 2607 #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S 0 2608 2609 #define DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG (DR_REG_DPORT_BASE + 0x3B8) 2610 /* DPORT_SDIOHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2611 /*description: */ 2612 #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG 0x0000003F 2613 #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S)) 2614 #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V 0x3F 2615 #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S 0 2616 2617 #define DPORT_AHBLITE_MPU_TABLE_EMAC_REG (DR_REG_DPORT_BASE + 0x3BC) 2618 /* DPORT_EMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2619 /*description: */ 2620 #define DPORT_EMAC_ACCESS_GRANT_CONFIG 0x0000003F 2621 #define DPORT_EMAC_ACCESS_GRANT_CONFIG_M ((DPORT_EMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_EMAC_ACCESS_GRANT_CONFIG_S)) 2622 #define DPORT_EMAC_ACCESS_GRANT_CONFIG_V 0x3F 2623 #define DPORT_EMAC_ACCESS_GRANT_CONFIG_S 0 2624 2625 #define DPORT_AHBLITE_MPU_TABLE_CAN_REG (DR_REG_DPORT_BASE + 0x3C0) 2626 /* DPORT_CAN_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2627 /*description: */ 2628 #define DPORT_CAN_ACCESS_GRANT_CONFIG 0x0000003F 2629 #define DPORT_CAN_ACCESS_GRANT_CONFIG_M ((DPORT_CAN_ACCESS_GRANT_CONFIG_V)<<(DPORT_CAN_ACCESS_GRANT_CONFIG_S)) 2630 #define DPORT_CAN_ACCESS_GRANT_CONFIG_V 0x3F 2631 #define DPORT_CAN_ACCESS_GRANT_CONFIG_S 0 2632 2633 #define DPORT_AHBLITE_MPU_TABLE_PWM1_REG (DR_REG_DPORT_BASE + 0x3C4) 2634 /* DPORT_PWM1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2635 /*description: */ 2636 #define DPORT_PWM1_ACCESS_GRANT_CONFIG 0x0000003F 2637 #define DPORT_PWM1_ACCESS_GRANT_CONFIG_M ((DPORT_PWM1_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM1_ACCESS_GRANT_CONFIG_S)) 2638 #define DPORT_PWM1_ACCESS_GRANT_CONFIG_V 0x3F 2639 #define DPORT_PWM1_ACCESS_GRANT_CONFIG_S 0 2640 2641 #define DPORT_AHBLITE_MPU_TABLE_I2S1_REG (DR_REG_DPORT_BASE + 0x3C8) 2642 /* DPORT_I2S1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2643 /*description: */ 2644 #define DPORT_I2S1_ACCESS_GRANT_CONFIG 0x0000003F 2645 #define DPORT_I2S1_ACCESS_GRANT_CONFIG_M ((DPORT_I2S1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S1_ACCESS_GRANT_CONFIG_S)) 2646 #define DPORT_I2S1_ACCESS_GRANT_CONFIG_V 0x3F 2647 #define DPORT_I2S1_ACCESS_GRANT_CONFIG_S 0 2648 2649 #define DPORT_AHBLITE_MPU_TABLE_UART2_REG (DR_REG_DPORT_BASE + 0x3CC) 2650 /* DPORT_UART2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2651 /*description: */ 2652 #define DPORT_UART2_ACCESS_GRANT_CONFIG 0x0000003F 2653 #define DPORT_UART2_ACCESS_GRANT_CONFIG_M ((DPORT_UART2_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART2_ACCESS_GRANT_CONFIG_S)) 2654 #define DPORT_UART2_ACCESS_GRANT_CONFIG_V 0x3F 2655 #define DPORT_UART2_ACCESS_GRANT_CONFIG_S 0 2656 2657 #define DPORT_AHBLITE_MPU_TABLE_PWM2_REG (DR_REG_DPORT_BASE + 0x3D0) 2658 /* DPORT_PWM2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2659 /*description: */ 2660 #define DPORT_PWM2_ACCESS_GRANT_CONFIG 0x0000003F 2661 #define DPORT_PWM2_ACCESS_GRANT_CONFIG_M ((DPORT_PWM2_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM2_ACCESS_GRANT_CONFIG_S)) 2662 #define DPORT_PWM2_ACCESS_GRANT_CONFIG_V 0x3F 2663 #define DPORT_PWM2_ACCESS_GRANT_CONFIG_S 0 2664 2665 #define DPORT_AHBLITE_MPU_TABLE_PWM3_REG (DR_REG_DPORT_BASE + 0x3D4) 2666 /* DPORT_PWM3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2667 /*description: */ 2668 #define DPORT_PWM3_ACCESS_GRANT_CONFIG 0x0000003F 2669 #define DPORT_PWM3_ACCESS_GRANT_CONFIG_M ((DPORT_PWM3_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM3_ACCESS_GRANT_CONFIG_S)) 2670 #define DPORT_PWM3_ACCESS_GRANT_CONFIG_V 0x3F 2671 #define DPORT_PWM3_ACCESS_GRANT_CONFIG_S 0 2672 2673 #define DPORT_AHBLITE_MPU_TABLE_RWBT_REG (DR_REG_DPORT_BASE + 0x3D8) 2674 /* DPORT_RWBT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2675 /*description: */ 2676 #define DPORT_RWBT_ACCESS_GRANT_CONFIG 0x0000003F 2677 #define DPORT_RWBT_ACCESS_GRANT_CONFIG_M ((DPORT_RWBT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RWBT_ACCESS_GRANT_CONFIG_S)) 2678 #define DPORT_RWBT_ACCESS_GRANT_CONFIG_V 0x3F 2679 #define DPORT_RWBT_ACCESS_GRANT_CONFIG_S 0 2680 2681 #define DPORT_AHBLITE_MPU_TABLE_BTMAC_REG (DR_REG_DPORT_BASE + 0x3DC) 2682 /* DPORT_BTMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2683 /*description: */ 2684 #define DPORT_BTMAC_ACCESS_GRANT_CONFIG 0x0000003F 2685 #define DPORT_BTMAC_ACCESS_GRANT_CONFIG_M ((DPORT_BTMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTMAC_ACCESS_GRANT_CONFIG_S)) 2686 #define DPORT_BTMAC_ACCESS_GRANT_CONFIG_V 0x3F 2687 #define DPORT_BTMAC_ACCESS_GRANT_CONFIG_S 0 2688 2689 #define DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG (DR_REG_DPORT_BASE + 0x3E0) 2690 /* DPORT_WIFIMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2691 /*description: */ 2692 #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG 0x0000003F 2693 #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_M ((DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S)) 2694 #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V 0x3F 2695 #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S 0 2696 2697 #define DPORT_AHBLITE_MPU_TABLE_PWR_REG (DR_REG_DPORT_BASE + 0x3E4) 2698 /* DPORT_PWR_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2699 /*description: */ 2700 #define DPORT_PWR_ACCESS_GRANT_CONFIG 0x0000003F 2701 #define DPORT_PWR_ACCESS_GRANT_CONFIG_M ((DPORT_PWR_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWR_ACCESS_GRANT_CONFIG_S)) 2702 #define DPORT_PWR_ACCESS_GRANT_CONFIG_V 0x3F 2703 #define DPORT_PWR_ACCESS_GRANT_CONFIG_S 0 2704 2705 #define DPORT_MEM_ACCESS_DBUG0_REG (DR_REG_DPORT_BASE + 0x3E8) 2706 /* DPORT_INTERNAL_SRAM_MMU_MULTI_HIT : RO ;bitpos:[29:26] ;default: 4'b0 ; */ 2707 /*description: */ 2708 #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT 0x0000000F 2709 #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_M ((DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V)<<(DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S)) 2710 #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V 0xF 2711 #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S 26 2712 /* DPORT_INTERNAL_SRAM_IA : RO ;bitpos:[25:14] ;default: 12'b0 ; */ 2713 /*description: */ 2714 #define DPORT_INTERNAL_SRAM_IA 0x00000FFF 2715 #define DPORT_INTERNAL_SRAM_IA_M ((DPORT_INTERNAL_SRAM_IA_V)<<(DPORT_INTERNAL_SRAM_IA_S)) 2716 #define DPORT_INTERNAL_SRAM_IA_V 0xFFF 2717 #define DPORT_INTERNAL_SRAM_IA_S 14 2718 /* DPORT_INTERNAL_SRAM_MMU_AD : RO ;bitpos:[13:10] ;default: 4'b0 ; */ 2719 /*description: */ 2720 #define DPORT_INTERNAL_SRAM_MMU_AD 0x0000000F 2721 #define DPORT_INTERNAL_SRAM_MMU_AD_M ((DPORT_INTERNAL_SRAM_MMU_AD_V)<<(DPORT_INTERNAL_SRAM_MMU_AD_S)) 2722 #define DPORT_INTERNAL_SRAM_MMU_AD_V 0xF 2723 #define DPORT_INTERNAL_SRAM_MMU_AD_S 10 2724 /* DPORT_SHARE_ROM_IA : RO ;bitpos:[9:6] ;default: 4'b0 ; */ 2725 /*description: */ 2726 #define DPORT_SHARE_ROM_IA 0x0000000F 2727 #define DPORT_SHARE_ROM_IA_M ((DPORT_SHARE_ROM_IA_V)<<(DPORT_SHARE_ROM_IA_S)) 2728 #define DPORT_SHARE_ROM_IA_V 0xF 2729 #define DPORT_SHARE_ROM_IA_S 6 2730 /* DPORT_SHARE_ROM_MPU_AD : RO ;bitpos:[5:4] ;default: 2'b0 ; */ 2731 /*description: */ 2732 #define DPORT_SHARE_ROM_MPU_AD 0x00000003 2733 #define DPORT_SHARE_ROM_MPU_AD_M ((DPORT_SHARE_ROM_MPU_AD_V)<<(DPORT_SHARE_ROM_MPU_AD_S)) 2734 #define DPORT_SHARE_ROM_MPU_AD_V 0x3 2735 #define DPORT_SHARE_ROM_MPU_AD_S 4 2736 /* DPORT_APP_ROM_IA : RO ;bitpos:[3] ;default: 1'b0 ; */ 2737 /*description: */ 2738 #define DPORT_APP_ROM_IA (BIT(3)) 2739 #define DPORT_APP_ROM_IA_M (BIT(3)) 2740 #define DPORT_APP_ROM_IA_V 0x1 2741 #define DPORT_APP_ROM_IA_S 3 2742 /* DPORT_APP_ROM_MPU_AD : RO ;bitpos:[2] ;default: 1'b0 ; */ 2743 /*description: */ 2744 #define DPORT_APP_ROM_MPU_AD (BIT(2)) 2745 #define DPORT_APP_ROM_MPU_AD_M (BIT(2)) 2746 #define DPORT_APP_ROM_MPU_AD_V 0x1 2747 #define DPORT_APP_ROM_MPU_AD_S 2 2748 /* DPORT_PRO_ROM_IA : RO ;bitpos:[1] ;default: 1'b0 ; */ 2749 /*description: */ 2750 #define DPORT_PRO_ROM_IA (BIT(1)) 2751 #define DPORT_PRO_ROM_IA_M (BIT(1)) 2752 #define DPORT_PRO_ROM_IA_V 0x1 2753 #define DPORT_PRO_ROM_IA_S 1 2754 /* DPORT_PRO_ROM_MPU_AD : RO ;bitpos:[0] ;default: 1'b0 ; */ 2755 /*description: */ 2756 #define DPORT_PRO_ROM_MPU_AD (BIT(0)) 2757 #define DPORT_PRO_ROM_MPU_AD_M (BIT(0)) 2758 #define DPORT_PRO_ROM_MPU_AD_V 0x1 2759 #define DPORT_PRO_ROM_MPU_AD_S 0 2760 2761 #define DPORT_MEM_ACCESS_DBUG1_REG (DR_REG_DPORT_BASE + 0x3EC) 2762 /* DPORT_AHBLITE_IA : RO ;bitpos:[10] ;default: 1'b0 ; */ 2763 /*description: */ 2764 #define DPORT_AHBLITE_IA (BIT(10)) 2765 #define DPORT_AHBLITE_IA_M (BIT(10)) 2766 #define DPORT_AHBLITE_IA_V 0x1 2767 #define DPORT_AHBLITE_IA_S 10 2768 /* DPORT_AHBLITE_ACCESS_DENY : RO ;bitpos:[9] ;default: 1'b0 ; */ 2769 /*description: */ 2770 #define DPORT_AHBLITE_ACCESS_DENY (BIT(9)) 2771 #define DPORT_AHBLITE_ACCESS_DENY_M (BIT(9)) 2772 #define DPORT_AHBLITE_ACCESS_DENY_V 0x1 2773 #define DPORT_AHBLITE_ACCESS_DENY_S 9 2774 /* DPORT_AHB_ACCESS_DENY : RO ;bitpos:[8] ;default: 1'b0 ; */ 2775 /*description: */ 2776 #define DPORT_AHB_ACCESS_DENY (BIT(8)) 2777 #define DPORT_AHB_ACCESS_DENY_M (BIT(8)) 2778 #define DPORT_AHB_ACCESS_DENY_V 0x1 2779 #define DPORT_AHB_ACCESS_DENY_S 8 2780 /* DPORT_PIDGEN_IA : RO ;bitpos:[7:6] ;default: 2'b0 ; */ 2781 /*description: */ 2782 #define DPORT_PIDGEN_IA 0x00000003 2783 #define DPORT_PIDGEN_IA_M ((DPORT_PIDGEN_IA_V)<<(DPORT_PIDGEN_IA_S)) 2784 #define DPORT_PIDGEN_IA_V 0x3 2785 #define DPORT_PIDGEN_IA_S 6 2786 /* DPORT_ARB_IA : RO ;bitpos:[5:4] ;default: 2'b0 ; */ 2787 /*description: */ 2788 #define DPORT_ARB_IA 0x00000003 2789 #define DPORT_ARB_IA_M ((DPORT_ARB_IA_V)<<(DPORT_ARB_IA_S)) 2790 #define DPORT_ARB_IA_V 0x3 2791 #define DPORT_ARB_IA_S 4 2792 /* DPORT_INTERNAL_SRAM_MMU_MISS : RO ;bitpos:[3:0] ;default: 4'b0 ; */ 2793 /*description: */ 2794 #define DPORT_INTERNAL_SRAM_MMU_MISS 0x0000000F 2795 #define DPORT_INTERNAL_SRAM_MMU_MISS_M ((DPORT_INTERNAL_SRAM_MMU_MISS_V)<<(DPORT_INTERNAL_SRAM_MMU_MISS_S)) 2796 #define DPORT_INTERNAL_SRAM_MMU_MISS_V 0xF 2797 #define DPORT_INTERNAL_SRAM_MMU_MISS_S 0 2798 2799 #define DPORT_PRO_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x3F0) 2800 /* DPORT_PRO_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */ 2801 /*description: */ 2802 #define DPORT_PRO_RX_END (BIT(23)) 2803 #define DPORT_PRO_RX_END_M (BIT(23)) 2804 #define DPORT_PRO_RX_END_V 0x1 2805 #define DPORT_PRO_RX_END_S 23 2806 /* DPORT_PRO_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */ 2807 /*description: */ 2808 #define DPORT_PRO_SLAVE_WDATA_V (BIT(22)) 2809 #define DPORT_PRO_SLAVE_WDATA_V_M (BIT(22)) 2810 #define DPORT_PRO_SLAVE_WDATA_V_V 0x1 2811 #define DPORT_PRO_SLAVE_WDATA_V_S 22 2812 /* DPORT_PRO_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */ 2813 /*description: */ 2814 #define DPORT_PRO_SLAVE_WR (BIT(21)) 2815 #define DPORT_PRO_SLAVE_WR_M (BIT(21)) 2816 #define DPORT_PRO_SLAVE_WR_V 0x1 2817 #define DPORT_PRO_SLAVE_WR_S 21 2818 /* DPORT_PRO_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */ 2819 /*description: */ 2820 #define DPORT_PRO_TX_END (BIT(20)) 2821 #define DPORT_PRO_TX_END_M (BIT(20)) 2822 #define DPORT_PRO_TX_END_V 0x1 2823 #define DPORT_PRO_TX_END_S 20 2824 /* DPORT_PRO_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */ 2825 /*description: */ 2826 #define DPORT_PRO_WR_BAK_TO_READ (BIT(19)) 2827 #define DPORT_PRO_WR_BAK_TO_READ_M (BIT(19)) 2828 #define DPORT_PRO_WR_BAK_TO_READ_V 0x1 2829 #define DPORT_PRO_WR_BAK_TO_READ_S 19 2830 /* DPORT_PRO_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */ 2831 /*description: */ 2832 #define DPORT_PRO_CACHE_STATE 0x00000FFF 2833 #define DPORT_PRO_CACHE_STATE_M ((DPORT_PRO_CACHE_STATE_V)<<(DPORT_PRO_CACHE_STATE_S)) 2834 #define DPORT_PRO_CACHE_STATE_V 0xFFF 2835 #define DPORT_PRO_CACHE_STATE_S 7 2836 /* DPORT_PRO_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */ 2837 /*description: */ 2838 #define DPORT_PRO_CACHE_IA 0x0000003F 2839 #define DPORT_PRO_CACHE_IA_M ((DPORT_PRO_CACHE_IA_V)<<(DPORT_PRO_CACHE_IA_S)) 2840 #define DPORT_PRO_CACHE_IA_V 0x3F 2841 #define DPORT_PRO_CACHE_IA_S 1 2842 /* DPORT_PRO_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */ 2843 /*description: */ 2844 #define DPORT_PRO_CACHE_MMU_IA (BIT(0)) 2845 #define DPORT_PRO_CACHE_MMU_IA_M (BIT(0)) 2846 #define DPORT_PRO_CACHE_MMU_IA_V 0x1 2847 #define DPORT_PRO_CACHE_MMU_IA_S 0 2848 2849 #define DPORT_PRO_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x3F4) 2850 /* DPORT_PRO_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 2851 /*description: */ 2852 #define DPORT_PRO_CTAG_RAM_RDATA 0xFFFFFFFF 2853 #define DPORT_PRO_CTAG_RAM_RDATA_M ((DPORT_PRO_CTAG_RAM_RDATA_V)<<(DPORT_PRO_CTAG_RAM_RDATA_S)) 2854 #define DPORT_PRO_CTAG_RAM_RDATA_V 0xFFFFFFFF 2855 #define DPORT_PRO_CTAG_RAM_RDATA_S 0 2856 2857 #define DPORT_PRO_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x3F8) 2858 /* DPORT_PRO_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */ 2859 /*description: */ 2860 #define DPORT_PRO_CACHE_VADDR 0x07FFFFFF 2861 #define DPORT_PRO_CACHE_VADDR_M ((DPORT_PRO_CACHE_VADDR_V)<<(DPORT_PRO_CACHE_VADDR_S)) 2862 #define DPORT_PRO_CACHE_VADDR_V 0x7FFFFFF 2863 #define DPORT_PRO_CACHE_VADDR_S 0 2864 2865 #define DPORT_PRO_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x3FC) 2866 /* DPORT_PRO_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */ 2867 /*description: */ 2868 #define DPORT_PRO_CACHE_IRAM0_PID_ERROR (BIT(15)) 2869 #define DPORT_PRO_CACHE_IRAM0_PID_ERROR_M (BIT(15)) 2870 #define DPORT_PRO_CACHE_IRAM0_PID_ERROR_V 0x1 2871 #define DPORT_PRO_CACHE_IRAM0_PID_ERROR_S 15 2872 /* DPORT_PRO_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */ 2873 /*description: */ 2874 #define DPORT_PRO_CPU_DISABLED_CACHE_IA 0x0000003F 2875 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_M ((DPORT_PRO_CPU_DISABLED_CACHE_IA_V)<<(DPORT_PRO_CPU_DISABLED_CACHE_IA_S)) 2876 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_V 0x3F 2877 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_S 9 2878 /* This is the contents of DPORT_PRO_CPU_DISABLED_CACHE_IA field expanded */ 2879 /* The following bits will be set upon invalid access for different memory 2880 * regions: */ 2881 /* Port of the APP CPU cache when cache is used in high/low or odd/even mode */ 2882 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE BIT(9) 2883 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_M BIT(9) 2884 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_V 1 2885 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_S 9 2886 /* DRAM1: 0x3F80_0000 ~ 0x3FBF_FFFF(R/W) */ 2887 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1 BIT(10) 2888 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_M BIT(10) 2889 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_V 1 2890 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_S 10 2891 /* IROM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */ 2892 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0 BIT(11) 2893 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_M BIT(11) 2894 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_V 1 2895 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_S 11 2896 /* IRAM1: 0x4040_0000 ~ 0x407F_FFFF(RO) */ 2897 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1 BIT(12) 2898 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_M BIT(12) 2899 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_V 1 2900 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_S 12 2901 /* IRAM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */ 2902 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0 BIT(13) 2903 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_M BIT(13) 2904 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_V 1 2905 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_S 13 2906 /* DROM0: 0x3F40_0000 ~ 0x3F7F_FFFF (RO) */ 2907 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0 BIT(14) 2908 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_M BIT(14) 2909 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_V 1 2910 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_S 14 2911 2912 /* DPORT_PRO_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */ 2913 /*description: */ 2914 #define DPORT_PRO_MMU_RDATA 0x000001FF 2915 #define DPORT_PRO_MMU_RDATA_M ((DPORT_PRO_MMU_RDATA_V)<<(DPORT_PRO_MMU_RDATA_S)) 2916 #define DPORT_PRO_MMU_RDATA_V 0x1FF 2917 #define DPORT_PRO_MMU_RDATA_S 0 2918 2919 #define DPORT_PRO_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x400) 2920 /* DPORT_PRO_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 2921 /*description: */ 2922 #define DPORT_PRO_DRAM1ADDR0_IA 0x000FFFFF 2923 #define DPORT_PRO_DRAM1ADDR0_IA_M ((DPORT_PRO_DRAM1ADDR0_IA_V)<<(DPORT_PRO_DRAM1ADDR0_IA_S)) 2924 #define DPORT_PRO_DRAM1ADDR0_IA_V 0xFFFFF 2925 #define DPORT_PRO_DRAM1ADDR0_IA_S 0 2926 2927 #define DPORT_PRO_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x404) 2928 /* DPORT_PRO_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 2929 /*description: */ 2930 #define DPORT_PRO_DROM0ADDR0_IA 0x000FFFFF 2931 #define DPORT_PRO_DROM0ADDR0_IA_M ((DPORT_PRO_DROM0ADDR0_IA_V)<<(DPORT_PRO_DROM0ADDR0_IA_S)) 2932 #define DPORT_PRO_DROM0ADDR0_IA_V 0xFFFFF 2933 #define DPORT_PRO_DROM0ADDR0_IA_S 0 2934 2935 #define DPORT_PRO_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x408) 2936 /* DPORT_PRO_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 2937 /*description: */ 2938 #define DPORT_PRO_IRAM0ADDR_IA 0x000FFFFF 2939 #define DPORT_PRO_IRAM0ADDR_IA_M ((DPORT_PRO_IRAM0ADDR_IA_V)<<(DPORT_PRO_IRAM0ADDR_IA_S)) 2940 #define DPORT_PRO_IRAM0ADDR_IA_V 0xFFFFF 2941 #define DPORT_PRO_IRAM0ADDR_IA_S 0 2942 2943 #define DPORT_PRO_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x40C) 2944 /* DPORT_PRO_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 2945 /*description: */ 2946 #define DPORT_PRO_IRAM1ADDR_IA 0x000FFFFF 2947 #define DPORT_PRO_IRAM1ADDR_IA_M ((DPORT_PRO_IRAM1ADDR_IA_V)<<(DPORT_PRO_IRAM1ADDR_IA_S)) 2948 #define DPORT_PRO_IRAM1ADDR_IA_V 0xFFFFF 2949 #define DPORT_PRO_IRAM1ADDR_IA_S 0 2950 2951 #define DPORT_PRO_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x410) 2952 /* DPORT_PRO_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 2953 /*description: */ 2954 #define DPORT_PRO_IROM0ADDR_IA 0x000FFFFF 2955 #define DPORT_PRO_IROM0ADDR_IA_M ((DPORT_PRO_IROM0ADDR_IA_V)<<(DPORT_PRO_IROM0ADDR_IA_S)) 2956 #define DPORT_PRO_IROM0ADDR_IA_V 0xFFFFF 2957 #define DPORT_PRO_IROM0ADDR_IA_S 0 2958 2959 #define DPORT_PRO_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x414) 2960 /* DPORT_PRO_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 2961 /*description: */ 2962 #define DPORT_PRO_OPSDRAMADDR_IA 0x000FFFFF 2963 #define DPORT_PRO_OPSDRAMADDR_IA_M ((DPORT_PRO_OPSDRAMADDR_IA_V)<<(DPORT_PRO_OPSDRAMADDR_IA_S)) 2964 #define DPORT_PRO_OPSDRAMADDR_IA_V 0xFFFFF 2965 #define DPORT_PRO_OPSDRAMADDR_IA_S 0 2966 2967 #define DPORT_APP_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x418) 2968 /* DPORT_APP_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */ 2969 /*description: */ 2970 #define DPORT_APP_RX_END (BIT(23)) 2971 #define DPORT_APP_RX_END_M (BIT(23)) 2972 #define DPORT_APP_RX_END_V 0x1 2973 #define DPORT_APP_RX_END_S 23 2974 /* DPORT_APP_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */ 2975 /*description: */ 2976 #define DPORT_APP_SLAVE_WDATA_V (BIT(22)) 2977 #define DPORT_APP_SLAVE_WDATA_V_M (BIT(22)) 2978 #define DPORT_APP_SLAVE_WDATA_V_V 0x1 2979 #define DPORT_APP_SLAVE_WDATA_V_S 22 2980 /* DPORT_APP_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */ 2981 /*description: */ 2982 #define DPORT_APP_SLAVE_WR (BIT(21)) 2983 #define DPORT_APP_SLAVE_WR_M (BIT(21)) 2984 #define DPORT_APP_SLAVE_WR_V 0x1 2985 #define DPORT_APP_SLAVE_WR_S 21 2986 /* DPORT_APP_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */ 2987 /*description: */ 2988 #define DPORT_APP_TX_END (BIT(20)) 2989 #define DPORT_APP_TX_END_M (BIT(20)) 2990 #define DPORT_APP_TX_END_V 0x1 2991 #define DPORT_APP_TX_END_S 20 2992 /* DPORT_APP_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */ 2993 /*description: */ 2994 #define DPORT_APP_WR_BAK_TO_READ (BIT(19)) 2995 #define DPORT_APP_WR_BAK_TO_READ_M (BIT(19)) 2996 #define DPORT_APP_WR_BAK_TO_READ_V 0x1 2997 #define DPORT_APP_WR_BAK_TO_READ_S 19 2998 /* DPORT_APP_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */ 2999 /*description: */ 3000 #define DPORT_APP_CACHE_STATE 0x00000FFF 3001 #define DPORT_APP_CACHE_STATE_M ((DPORT_APP_CACHE_STATE_V)<<(DPORT_APP_CACHE_STATE_S)) 3002 #define DPORT_APP_CACHE_STATE_V 0xFFF 3003 #define DPORT_APP_CACHE_STATE_S 7 3004 /* DPORT_APP_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */ 3005 /*description: */ 3006 #define DPORT_APP_CACHE_IA 0x0000003F 3007 #define DPORT_APP_CACHE_IA_M ((DPORT_APP_CACHE_IA_V)<<(DPORT_APP_CACHE_IA_S)) 3008 #define DPORT_APP_CACHE_IA_V 0x3F 3009 #define DPORT_APP_CACHE_IA_S 1 3010 /* DPORT_APP_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */ 3011 /*description: */ 3012 #define DPORT_APP_CACHE_MMU_IA (BIT(0)) 3013 #define DPORT_APP_CACHE_MMU_IA_M (BIT(0)) 3014 #define DPORT_APP_CACHE_MMU_IA_V 0x1 3015 #define DPORT_APP_CACHE_MMU_IA_S 0 3016 3017 #define DPORT_APP_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x41C) 3018 /* DPORT_APP_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3019 /*description: */ 3020 #define DPORT_APP_CTAG_RAM_RDATA 0xFFFFFFFF 3021 #define DPORT_APP_CTAG_RAM_RDATA_M ((DPORT_APP_CTAG_RAM_RDATA_V)<<(DPORT_APP_CTAG_RAM_RDATA_S)) 3022 #define DPORT_APP_CTAG_RAM_RDATA_V 0xFFFFFFFF 3023 #define DPORT_APP_CTAG_RAM_RDATA_S 0 3024 3025 #define DPORT_APP_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x420) 3026 /* DPORT_APP_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */ 3027 /*description: */ 3028 #define DPORT_APP_CACHE_VADDR 0x07FFFFFF 3029 #define DPORT_APP_CACHE_VADDR_M ((DPORT_APP_CACHE_VADDR_V)<<(DPORT_APP_CACHE_VADDR_S)) 3030 #define DPORT_APP_CACHE_VADDR_V 0x7FFFFFF 3031 #define DPORT_APP_CACHE_VADDR_S 0 3032 3033 #define DPORT_APP_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x424) 3034 /* DPORT_APP_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */ 3035 /*description: */ 3036 #define DPORT_APP_CACHE_IRAM0_PID_ERROR (BIT(15)) 3037 #define DPORT_APP_CACHE_IRAM0_PID_ERROR_M (BIT(15)) 3038 #define DPORT_APP_CACHE_IRAM0_PID_ERROR_V 0x1 3039 #define DPORT_APP_CACHE_IRAM0_PID_ERROR_S 15 3040 /* DPORT_APP_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */ 3041 /*description: */ 3042 #define DPORT_APP_CPU_DISABLED_CACHE_IA 0x0000003F 3043 #define DPORT_APP_CPU_DISABLED_CACHE_IA_M ((DPORT_APP_CPU_DISABLED_CACHE_IA_V)<<(DPORT_APP_CPU_DISABLED_CACHE_IA_S)) 3044 #define DPORT_APP_CPU_DISABLED_CACHE_IA_V 0x3F 3045 #define DPORT_APP_CPU_DISABLED_CACHE_IA_S 9 3046 /* This is the contents of DPORT_APP_CPU_DISABLED_CACHE_IA field expanded */ 3047 /* The following bits will be set upon invalid access for different memory 3048 * regions: */ 3049 /* Port of the PRO CPU cache when cache is used in high/low or odd/even mode */ 3050 #define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE BIT(9) 3051 #define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_M BIT(9) 3052 #define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_V 1 3053 #define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_S 9 3054 /* DRAM1: 0x3F80_0000 ~ 0x3FBF_FFFF(R/W) */ 3055 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1 BIT(10) 3056 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_M BIT(10) 3057 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_V 1 3058 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_S 10 3059 /* IROM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */ 3060 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0 BIT(11) 3061 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_M BIT(11) 3062 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_V 1 3063 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_S 11 3064 /* IRAM1: 0x4040_0000 ~ 0x407F_FFFF(RO) */ 3065 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1 BIT(12) 3066 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_M BIT(12) 3067 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_V 1 3068 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_S 12 3069 /* IRAM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */ 3070 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0 BIT(13) 3071 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_M BIT(13) 3072 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_V 1 3073 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_S 13 3074 /* DROM0: 0x3F40_0000 ~ 0x3F7F_FFFF (RO) */ 3075 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0 BIT(14) 3076 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_M BIT(14) 3077 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_V 1 3078 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_S 14 3079 3080 /* DPORT_APP_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */ 3081 /*description: */ 3082 #define DPORT_APP_MMU_RDATA 0x000001FF 3083 #define DPORT_APP_MMU_RDATA_M ((DPORT_APP_MMU_RDATA_V)<<(DPORT_APP_MMU_RDATA_S)) 3084 #define DPORT_APP_MMU_RDATA_V 0x1FF 3085 #define DPORT_APP_MMU_RDATA_S 0 3086 3087 #define DPORT_APP_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x428) 3088 /* DPORT_APP_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 3089 /*description: */ 3090 #define DPORT_APP_DRAM1ADDR0_IA 0x000FFFFF 3091 #define DPORT_APP_DRAM1ADDR0_IA_M ((DPORT_APP_DRAM1ADDR0_IA_V)<<(DPORT_APP_DRAM1ADDR0_IA_S)) 3092 #define DPORT_APP_DRAM1ADDR0_IA_V 0xFFFFF 3093 #define DPORT_APP_DRAM1ADDR0_IA_S 0 3094 3095 #define DPORT_APP_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x42C) 3096 /* DPORT_APP_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 3097 /*description: */ 3098 #define DPORT_APP_DROM0ADDR0_IA 0x000FFFFF 3099 #define DPORT_APP_DROM0ADDR0_IA_M ((DPORT_APP_DROM0ADDR0_IA_V)<<(DPORT_APP_DROM0ADDR0_IA_S)) 3100 #define DPORT_APP_DROM0ADDR0_IA_V 0xFFFFF 3101 #define DPORT_APP_DROM0ADDR0_IA_S 0 3102 3103 #define DPORT_APP_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x430) 3104 /* DPORT_APP_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 3105 /*description: */ 3106 #define DPORT_APP_IRAM0ADDR_IA 0x000FFFFF 3107 #define DPORT_APP_IRAM0ADDR_IA_M ((DPORT_APP_IRAM0ADDR_IA_V)<<(DPORT_APP_IRAM0ADDR_IA_S)) 3108 #define DPORT_APP_IRAM0ADDR_IA_V 0xFFFFF 3109 #define DPORT_APP_IRAM0ADDR_IA_S 0 3110 3111 #define DPORT_APP_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x434) 3112 /* DPORT_APP_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 3113 /*description: */ 3114 #define DPORT_APP_IRAM1ADDR_IA 0x000FFFFF 3115 #define DPORT_APP_IRAM1ADDR_IA_M ((DPORT_APP_IRAM1ADDR_IA_V)<<(DPORT_APP_IRAM1ADDR_IA_S)) 3116 #define DPORT_APP_IRAM1ADDR_IA_V 0xFFFFF 3117 #define DPORT_APP_IRAM1ADDR_IA_S 0 3118 3119 #define DPORT_APP_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x438) 3120 /* DPORT_APP_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 3121 /*description: */ 3122 #define DPORT_APP_IROM0ADDR_IA 0x000FFFFF 3123 #define DPORT_APP_IROM0ADDR_IA_M ((DPORT_APP_IROM0ADDR_IA_V)<<(DPORT_APP_IROM0ADDR_IA_S)) 3124 #define DPORT_APP_IROM0ADDR_IA_V 0xFFFFF 3125 #define DPORT_APP_IROM0ADDR_IA_S 0 3126 3127 #define DPORT_APP_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x43C) 3128 /* DPORT_APP_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 3129 /*description: */ 3130 #define DPORT_APP_OPSDRAMADDR_IA 0x000FFFFF 3131 #define DPORT_APP_OPSDRAMADDR_IA_M ((DPORT_APP_OPSDRAMADDR_IA_V)<<(DPORT_APP_OPSDRAMADDR_IA_S)) 3132 #define DPORT_APP_OPSDRAMADDR_IA_V 0xFFFFF 3133 #define DPORT_APP_OPSDRAMADDR_IA_S 0 3134 3135 #define DPORT_PRO_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x440) 3136 /* DPORT_PRO_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */ 3137 /*description: */ 3138 #define DPORT_PRO_CPU_PDEBUG_ENABLE (BIT(8)) 3139 #define DPORT_PRO_CPU_PDEBUG_ENABLE_M (BIT(8)) 3140 #define DPORT_PRO_CPU_PDEBUG_ENABLE_V 0x1 3141 #define DPORT_PRO_CPU_PDEBUG_ENABLE_S 8 3142 /* DPORT_PRO_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ 3143 /*description: */ 3144 #define DPORT_PRO_CPU_RECORD_DISABLE (BIT(4)) 3145 #define DPORT_PRO_CPU_RECORD_DISABLE_M (BIT(4)) 3146 #define DPORT_PRO_CPU_RECORD_DISABLE_V 0x1 3147 #define DPORT_PRO_CPU_RECORD_DISABLE_S 4 3148 /* DPORT_PRO_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 3149 /*description: */ 3150 #define DPORT_PRO_CPU_RECORD_ENABLE (BIT(0)) 3151 #define DPORT_PRO_CPU_RECORD_ENABLE_M (BIT(0)) 3152 #define DPORT_PRO_CPU_RECORD_ENABLE_V 0x1 3153 #define DPORT_PRO_CPU_RECORD_ENABLE_S 0 3154 3155 #define DPORT_PRO_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x444) 3156 /* DPORT_PRO_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */ 3157 /*description: */ 3158 #define DPORT_PRO_CPU_RECORDING (BIT(0)) 3159 #define DPORT_PRO_CPU_RECORDING_M (BIT(0)) 3160 #define DPORT_PRO_CPU_RECORDING_V 0x1 3161 #define DPORT_PRO_CPU_RECORDING_S 0 3162 3163 #define DPORT_PRO_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x448) 3164 /* DPORT_RECORD_PRO_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */ 3165 /*description: */ 3166 #define DPORT_RECORD_PRO_PID 0x00000007 3167 #define DPORT_RECORD_PRO_PID_M ((DPORT_RECORD_PRO_PID_V)<<(DPORT_RECORD_PRO_PID_S)) 3168 #define DPORT_RECORD_PRO_PID_V 0x7 3169 #define DPORT_RECORD_PRO_PID_S 0 3170 3171 #define DPORT_PRO_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x44C) 3172 /* DPORT_RECORD_PRO_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3173 /*description: */ 3174 #define DPORT_RECORD_PRO_PDEBUGINST 0xFFFFFFFF 3175 #define DPORT_RECORD_PRO_PDEBUGINST_M ((DPORT_RECORD_PRO_PDEBUGINST_V)<<(DPORT_RECORD_PRO_PDEBUGINST_S)) 3176 #define DPORT_RECORD_PRO_PDEBUGINST_V 0xFFFFFFFF 3177 #define DPORT_RECORD_PRO_PDEBUGINST_S 0 3178 /* register layout: 3179 * SIZE [7..0] : Instructions normally complete in the W stage. The size of the instruction in the W is given 3180 * by this field in number of bytes. If it is 8’b0 in a given cycle the W stage has no completing 3181 * instruction. This is also known as a bubble cycle. Also see DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG. 3182 * ISRC [14..12] : Instruction source. 3183 ** LOOP [23..20] : Loopback status. 3184 ** CINTLEVEL [27..24]: CINTLEVEL. 3185 */ 3186 #define DPORT_RECORD_PDEBUGINST_SZ_M ((DPORT_RECORD_PDEBUGINST_SZ_V)<<(DPORT_RECORD_PDEBUGINST_SZ_S)) 3187 #define DPORT_RECORD_PDEBUGINST_SZ_V 0xFF 3188 #define DPORT_RECORD_PDEBUGINST_SZ_S 0 3189 #define DPORT_RECORD_PDEBUGINST_SZ(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_SZ_S) & DPORT_RECORD_PDEBUGINST_SZ_V) 3190 #define DPORT_RECORD_PDEBUGINST_ISRC_M ((DPORT_RECORD_PDEBUGINST_ISRC_V)<<(DPORT_RECORD_PDEBUGINST_ISRC_S)) 3191 #define DPORT_RECORD_PDEBUGINST_ISRC_V 0x07 3192 #define DPORT_RECORD_PDEBUGINST_ISRC_S 12 3193 #define DPORT_RECORD_PDEBUGINST_ISRC(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_ISRC_S) & DPORT_RECORD_PDEBUGINST_ISRC_V) 3194 // #define DPORT_RECORD_PDEBUGINST_LOOP_M ((DPORT_RECORD_PDEBUGINST_LOOP_V)<<(DPORT_RECORD_PDEBUGINST_LOOP_S)) 3195 // #define DPORT_RECORD_PDEBUGINST_LOOP_V 0x0F 3196 // #define DPORT_RECORD_PDEBUGINST_LOOP_S 20 3197 // #define DPORT_RECORD_PDEBUGINST_LOOP(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_LOOP_S) & DPORT_RECORD_PDEBUGINST_LOOP_V) 3198 #define DPORT_RECORD_PDEBUGINST_LOOP_REP (BIT(20)) /* loopback will occur */ 3199 #define DPORT_RECORD_PDEBUGINST_LOOP (BIT(21)) /* last inst of loop */ 3200 #define DPORT_RECORD_PDEBUGINST_CINTL_M ((DPORT_RECORD_PDEBUGINST_CINTL_V)<<(DPORT_RECORD_PDEBUGINST_CINTL_S)) 3201 #define DPORT_RECORD_PDEBUGINST_CINTL_V 0x0F 3202 #define DPORT_RECORD_PDEBUGINST_CINTL_S 24 3203 #define DPORT_RECORD_PDEBUGINST_CINTL(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_CINTL_S) & DPORT_RECORD_PDEBUGINST_CINTL_V) 3204 3205 #define DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x450) 3206 /* DPORT_RECORD_PRO_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ 3207 /*description: */ 3208 #define DPORT_RECORD_PRO_PDEBUGSTATUS 0x000000FF 3209 #define DPORT_RECORD_PRO_PDEBUGSTATUS_M ((DPORT_RECORD_PRO_PDEBUGSTATUS_V)<<(DPORT_RECORD_PRO_PDEBUGSTATUS_S)) 3210 #define DPORT_RECORD_PRO_PDEBUGSTATUS_V 0xFF 3211 #define DPORT_RECORD_PRO_PDEBUGSTATUS_S 0 3212 /* register layout: 3213 * BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0 3214 * INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0 3215 */ 3216 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_M ((DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)<<(DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S)) 3217 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V 0x3F 3218 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S 0 3219 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S) & DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V) 3220 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_PSO 0x00 /* Power shut off */ 3221 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP 0x02 /* Register dependency or resource conflict. See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */ 3222 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_CTL 0x04 /* Control transfer bubble */ 3223 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ICM 0x08 /* I-cache miss (incl uncached miss) */ 3224 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DCM 0x0C /* D-cache miss (excl uncached miss) */ 3225 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC0 0x10 /* Exception or interrupt (W stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. 3226 The virtual address of the instruction that was killed appears on DPORT_PRO_CPU_RECORD_PDEBUGPC_REG[31:0] */ 3227 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC1 0x11 /* Exception or interrupt (W+1 stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */ 3228 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_RPL 0x14 /* Instruction replay (other). DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG has the PC of the replaying instruction. */ 3229 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLB 0x18 /* HW ITLB refill. The refill address and data are available on 3230 DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */ 3231 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLBM 0x1A /* ITLB miss */ 3232 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLB 0x1C /* HW DTLB refill. The refill address and data are available on 3233 DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */ 3234 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLBM 0x1E /* DTLB miss */ 3235 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL 0x20 /* Stall . The cause of the global stall is further classified in the DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG. */ 3236 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_HWMEC 0x24 /* HW-corrected memory error */ 3237 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI 0x28 /* WAITI mode */ 3238 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_OTHER 0x3C /* all other bubbles */ 3239 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_M ((DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)<<(DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S)) 3240 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V 0x3F 3241 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S 0 3242 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S) & DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V) 3243 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_JX 0x00 /* JX */ 3244 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALLX 0x04 /* CALLX */ 3245 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CRET 0x08 /* All call returns */ 3246 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_ERET 0x0C /* All exception returns */ 3247 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_B 0x10 /* Branch taken or loop not taken */ 3248 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_J 0x14 /* J */ 3249 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALL 0x18 /* CALL */ 3250 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_BN 0x1C /* Branch not taken */ 3251 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_LOOP 0x20 /* Loop instruction (taken) */ 3252 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S32C1I 0x24 /* S32C1I. The address and load data (before the conditional store) are available on the LS signals*/ 3253 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WXSR2LB 0x28 /* WSR/XSR to LBEGIN */ 3254 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WSR2MMID 0x2C /* WSR to MMID */ 3255 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR 0x30 /* RSR or WSR (except MMID and LBEGIN) or XSR (except LBEGIN) */ 3256 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER 0x34 /* RER or WER */ 3257 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_DEF 0x3C /* Default */ 3258 3259 #define DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x454) 3260 /* DPORT_RECORD_PRO_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3261 /*description: */ 3262 #define DPORT_RECORD_PRO_PDEBUGDATA 0xFFFFFFFF 3263 #define DPORT_RECORD_PRO_PDEBUGDATA_M ((DPORT_RECORD_PRO_PDEBUGDATA_V)<<(DPORT_RECORD_PRO_PDEBUGDATA_S)) 3264 #define DPORT_RECORD_PRO_PDEBUGDATA_V 0xFFFFFFFF 3265 #define DPORT_RECORD_PRO_PDEBUGDATA_S 0 3266 /* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP: 3267 * 3268 * HALT [17]: HALT instruction (TX only) 3269 * MEMW [16]: MEMW, EXTW or EXCW instruction dependency 3270 * REG [12]: register dependencies or resource (e.g.TIE ports) conflicts 3271 * STR [11]: store release (instruction) dependency 3272 * LSU [8] : various LSU dependencies (MHT access, prefetch, cache access insts, s32c1i, etc) 3273 * OTHER[0] : all other hold dependencies resulting from data or resource dependencies 3274 */ 3275 #define DPORT_RECORD_PDEBUGDATA_DEP_HALT (BIT(17)) 3276 #define DPORT_RECORD_PDEBUGDATA_DEP_MEMW (BIT(16)) 3277 #define DPORT_RECORD_PDEBUGDATA_DEP_REG (BIT(12)) 3278 #define DPORT_RECORD_PDEBUGDATA_DEP_STR (BIT(11)) 3279 #define DPORT_RECORD_PDEBUGDATA_DEP_LSU (BIT(8)) 3280 #define DPORT_RECORD_PDEBUGDATA_DEP_OTHER (BIT(0)) 3281 /* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXCn: 3282 * 3283 * EXCCAUSE[21..16]: Processor exception cause 3284 * EXCVEC [4..0] : Encoded Exception Vector 3285 */ 3286 #define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_M ((DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)<<(DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S)) 3287 #define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V 0x3F 3288 #define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S 16 3289 #define DPORT_RECORD_PDEBUGDATA_EXCCAUSE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S) & DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V) 3290 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_M ((DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)<<(DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S)) 3291 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_V 0x1F 3292 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_S 0 3293 #define DPORT_RECORD_PDEBUGDATA_EXCVEC(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S) & DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V) 3294 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_NONE 0x00 /* no vector */ 3295 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_RST 0x01 /* Reset */ 3296 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_DBG 0x02 /* Debug (repl corresp level “n”) */ 3297 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_NMI 0x03 /* NMI (repl corresp level “n”) */ 3298 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_USR 0x04 /* User */ 3299 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_KRNL 0x05 /* Kernel */ 3300 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_DBL 0x06 /* Double */ 3301 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_EMEM 0x07 /* Memory Error */ 3302 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF4 0x0A /* Window Overflow 4 */ 3303 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF4 0x0B /* Window Underflow 4 */ 3304 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF8 0x0C /* Window Overflow 8 */ 3305 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF8 0x0D /* Window Underflow 8 */ 3306 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF12 0x0E /* Window Overflow 12 */ 3307 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF12 0x0F /* Window Underflow 12 */ 3308 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT2 0x10 /* Int Level 2 (n/a if debug/NMI) */ 3309 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT3 0x11 /* Int Level 3 (n/a if debug/NMI) */ 3310 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT4 0x12 /* Int Level 4 (n/a if debug/NMI) */ 3311 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT5 0x13 /* Int Level 5 (n/a if debug/NMI) */ 3312 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT6 0x14 /* Int Level 6 (n/a if debug/NMI) */ 3313 /* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL: 3314 * 3315 * ITERDIV[19] : Iterative divide stall. 3316 * ITERMUL[18] : Iterative multiply stall. 3317 * BANKCONFL[16]: Bank-conflict stall. 3318 * BPLOAD[15] : Bypass load stall. 3319 * LSPROC[14] : Load/store miss-processing stall. 3320 * L32R[13] : FastL32R stall. 3321 * BPIFETCH[12] : Bypass I fetch stall. 3322 * RUNSTALL[10] : RunStall. 3323 * TIE[9] : TIE port stall. 3324 * IPIF[8] : Instruction RAM inbound-PIF stall. 3325 * IRAMBUSY[7] : Instruction RAM/ROM busy stall. 3326 * ICM[6] : I-cache-miss stall. 3327 * LSU[4] : The LSU will stall the pipeline under various local memory access conflict situations. 3328 * DCM[3] : D-cache-miss stall. 3329 * BUFFCONFL[2] : Store buffer conflict stall. 3330 * BUFF[1] : Store buffer full stall. 3331 */ 3332 #define DPORT_RECORD_PDEBUGDATA_STALL_ITERDIV (BIT(19)) 3333 #define DPORT_RECORD_PDEBUGDATA_STALL_ITERMUL (BIT(18)) 3334 #define DPORT_RECORD_PDEBUGDATA_STALL_BANKCONFL (BIT(16)) 3335 #define DPORT_RECORD_PDEBUGDATA_STALL_BPLOAD (BIT(15)) 3336 #define DPORT_RECORD_PDEBUGDATA_STALL_LSPROC (BIT(14)) 3337 #define DPORT_RECORD_PDEBUGDATA_STALL_L32R (BIT(13)) 3338 #define DPORT_RECORD_PDEBUGDATA_STALL_BPIFETCH (BIT(12)) 3339 #define DPORT_RECORD_PDEBUGDATA_STALL_RUN (BIT(10)) 3340 #define DPORT_RECORD_PDEBUGDATA_STALL_TIE (BIT(9)) 3341 #define DPORT_RECORD_PDEBUGDATA_STALL_IPIF (BIT(8)) 3342 #define DPORT_RECORD_PDEBUGDATA_STALL_IRAMBUSY (BIT(7)) 3343 #define DPORT_RECORD_PDEBUGDATA_STALL_ICM (BIT(6)) 3344 #define DPORT_RECORD_PDEBUGDATA_STALL_LSU (BIT(4)) 3345 #define DPORT_RECORD_PDEBUGDATA_STALL_DCM (BIT(3)) 3346 #define DPORT_RECORD_PDEBUGDATA_STALL_BUFFCONFL (BIT(2)) 3347 #define DPORT_RECORD_PDEBUGDATA_STALL_BUFF (BIT(1)) 3348 /* register layout for DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR: 3349 * 3350 * XSR[10] : XSR Instruction 3351 * WSR[9] : WSR Instruction 3352 * RSR[8] : RSR Instruction 3353 * SR[7..0] : Special Register Number 3354 */ 3355 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_XSR (BIT(10)) 3356 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_WSR (BIT(9)) 3357 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_RSR (BIT(8)) 3358 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_M ((DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V)<<(DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S)) 3359 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V 0xFF 3360 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S 0 3361 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S) & DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V) 3362 /* register layout for DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER: 3363 * 3364 * ER[13..2]: ER Address 3365 * WER[1] : WER Instruction 3366 * RER[0] : RER Instruction 3367 */ 3368 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_M ((DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V)<<(DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S)) 3369 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V 0xFFF 3370 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S 2 3371 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S) & DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V) 3372 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_WER (BIT(1)) 3373 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_RER (BIT(0)) 3374 3375 3376 #define DPORT_PRO_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x458) 3377 /* DPORT_RECORD_PRO_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3378 /*description: */ 3379 #define DPORT_RECORD_PRO_PDEBUGPC 0xFFFFFFFF 3380 #define DPORT_RECORD_PRO_PDEBUGPC_M ((DPORT_RECORD_PRO_PDEBUGPC_V)<<(DPORT_RECORD_PRO_PDEBUGPC_S)) 3381 #define DPORT_RECORD_PRO_PDEBUGPC_V 0xFFFFFFFF 3382 #define DPORT_RECORD_PRO_PDEBUGPC_S 0 3383 3384 #define DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x45C) 3385 /* DPORT_RECORD_PRO_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3386 /*description: */ 3387 #define DPORT_RECORD_PRO_PDEBUGLS0STAT 0xFFFFFFFF 3388 #define DPORT_RECORD_PRO_PDEBUGLS0STAT_M ((DPORT_RECORD_PRO_PDEBUGLS0STAT_V)<<(DPORT_RECORD_PRO_PDEBUGLS0STAT_S)) 3389 #define DPORT_RECORD_PRO_PDEBUGLS0STAT_V 0xFFFFFFFF 3390 #define DPORT_RECORD_PRO_PDEBUGLS0STAT_S 0 3391 /* register layout: 3392 * TYPE [3..0] : Type of instruction in LS. 3393 * SZ [7..4] : Operand size. 3394 * DTLBM [8] : Data TLB miss. 3395 * DCM [9] : D-cache miss. 3396 * DCH [10] : D-cache hit. 3397 * UC [12] : Uncached. 3398 * WB [13] : Writeback. 3399 * COH [16] : Coherency. 3400 * STCOH [18..17]: Coherent state. 3401 * TGT [23..20] : Local target. 3402 */ 3403 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_M ((DPORT_RECORD_PDEBUGLS0STAT_TYPE_V)<<(DPORT_RECORD_PDEBUGLS0STAT_TYPE_S)) 3404 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_V 0x0F 3405 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_S 0 3406 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_TYPE_S) & DPORT_RECORD_PDEBUGLS0STAT_TYPE_V) 3407 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_NONE 0x00 /* neither */ 3408 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_ITLBR 0x01 /* hw itlb refill */ 3409 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_DTLBR 0x02 /* hw dtlb refill */ 3410 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_LD 0x05 /* load */ 3411 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_STR 0x06 /* store */ 3412 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_L32R 0x08 /* l32r */ 3413 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_S32CLI1 0x0A /* s32ci1 */ 3414 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_CTI 0x0C /* cache test inst */ 3415 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWXSR 0x0E /* rsr/wsr/xsr */ 3416 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWER 0x0F /* rer/wer */ 3417 #define DPORT_RECORD_PDEBUGLS0STAT_SZ_M ((DPORT_RECORD_PDEBUGLS0STAT_SZ_V)<<(DPORT_RECORD_PDEBUGLS0STAT_SZ_S)) 3418 #define DPORT_RECORD_PDEBUGLS0STAT_SZ_V 0x0F 3419 #define DPORT_RECORD_PDEBUGLS0STAT_SZ_S 4 3420 #define DPORT_RECORD_PDEBUGLS0STAT_SZ(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_SZ_S) & DPORT_RECORD_PDEBUGLS0STAT_SZ_V) 3421 #define DPORT_RECORD_PDEBUGLS0STAT_SZB(_r_) ((8<<DPORT_RECORD_PDEBUGLS0STAT_SZ(_r_))/8) // in bytes 3422 #define DPORT_RECORD_PDEBUGLS0STAT_DTLBM (BIT(8)) 3423 #define DPORT_RECORD_PDEBUGLS0STAT_DCM (BIT(9)) 3424 #define DPORT_RECORD_PDEBUGLS0STAT_DCH (BIT(10)) 3425 #define DPORT_RECORD_PDEBUGLS0STAT_UC (BIT(12)) 3426 #define DPORT_RECORD_PDEBUGLS0STAT_WB (BIT(13)) 3427 #define DPORT_RECORD_PDEBUGLS0STAT_COH (BIT(16)) 3428 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_M ((DPORT_RECORD_PDEBUGLS0STAT_STCOH_V)<<(DPORT_RECORD_PDEBUGLS0STAT_STCOH_S)) 3429 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_V 0x03 3430 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_S 17 3431 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_STCOH_S) & DPORT_RECORD_PDEBUGLS0STAT_STCOH_V) 3432 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_NONE 0x0 /* neither shared nor exclusive nor modified */ 3433 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_SHARED 0x1 /* shared */ 3434 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_EXCL 0x2 /* exclusive */ 3435 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_MOD 0x3 /* modified */ 3436 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_M ((DPORT_RECORD_PDEBUGLS0STAT_TGT_V)<<(DPORT_RECORD_PDEBUGLS0STAT_TGT_S)) 3437 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_V 0x0F 3438 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_S 20 3439 #define DPORT_RECORD_PDEBUGLS0STAT_TGT(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_TGT_S) & DPORT_RECORD_PDEBUGLS0STAT_TGT_V) 3440 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_EXT 0x0 /* not to local memory */ 3441 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM0 0x2 /* 001x: InstRAM (0/1) */ 3442 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM1 0x3 /* 001x: InstRAM (0/1) */ 3443 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM0 0x4 /* 010x: InstROM (0/1) */ 3444 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM1 0x5 /* 010x: InstROM (0/1) */ 3445 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM0 0x0A /* 101x: DataRAM (0/1) */ 3446 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM1 0x0B /* 101x: DataRAM (0/1) */ 3447 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM0 0xE /* 111x: DataROM (0/1) */ 3448 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM1 0xF /* 111x: DataROM (0/1) */ 3449 // #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM(_t_) (((_t_)&0xE)=0x2) /* 001x: InstRAM (0/1) */ 3450 // #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM(_t_) (((_t_)&0xE)=0x4) /* 010x: InstROM (0/1) */ 3451 // #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM(_t_) (((_t_)&0xE)=0x2) /* 101x: DataRAM (0/1) */ 3452 // #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM(_t_) (((_t_)&0xE)=0x2) /* 111x: DataROM (0/1) */ 3453 3454 #define DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x460) 3455 /* DPORT_RECORD_PRO_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3456 /*description: */ 3457 #define DPORT_RECORD_PRO_PDEBUGLS0ADDR 0xFFFFFFFF 3458 #define DPORT_RECORD_PRO_PDEBUGLS0ADDR_M ((DPORT_RECORD_PRO_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_PRO_PDEBUGLS0ADDR_S)) 3459 #define DPORT_RECORD_PRO_PDEBUGLS0ADDR_V 0xFFFFFFFF 3460 #define DPORT_RECORD_PRO_PDEBUGLS0ADDR_S 0 3461 3462 #define DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x464) 3463 /* DPORT_RECORD_PRO_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3464 /*description: */ 3465 #define DPORT_RECORD_PRO_PDEBUGLS0DATA 0xFFFFFFFF 3466 #define DPORT_RECORD_PRO_PDEBUGLS0DATA_M ((DPORT_RECORD_PRO_PDEBUGLS0DATA_V)<<(DPORT_RECORD_PRO_PDEBUGLS0DATA_S)) 3467 #define DPORT_RECORD_PRO_PDEBUGLS0DATA_V 0xFFFFFFFF 3468 #define DPORT_RECORD_PRO_PDEBUGLS0DATA_S 0 3469 3470 #define DPORT_APP_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x468) 3471 /* DPORT_APP_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */ 3472 /*description: */ 3473 #define DPORT_APP_CPU_PDEBUG_ENABLE (BIT(8)) 3474 #define DPORT_APP_CPU_PDEBUG_ENABLE_M (BIT(8)) 3475 #define DPORT_APP_CPU_PDEBUG_ENABLE_V 0x1 3476 #define DPORT_APP_CPU_PDEBUG_ENABLE_S 8 3477 /* DPORT_APP_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ 3478 /*description: */ 3479 #define DPORT_APP_CPU_RECORD_DISABLE (BIT(4)) 3480 #define DPORT_APP_CPU_RECORD_DISABLE_M (BIT(4)) 3481 #define DPORT_APP_CPU_RECORD_DISABLE_V 0x1 3482 #define DPORT_APP_CPU_RECORD_DISABLE_S 4 3483 /* DPORT_APP_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 3484 /*description: */ 3485 #define DPORT_APP_CPU_RECORD_ENABLE (BIT(0)) 3486 #define DPORT_APP_CPU_RECORD_ENABLE_M (BIT(0)) 3487 #define DPORT_APP_CPU_RECORD_ENABLE_V 0x1 3488 #define DPORT_APP_CPU_RECORD_ENABLE_S 0 3489 3490 #define DPORT_APP_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x46C) 3491 /* DPORT_APP_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */ 3492 /*description: */ 3493 #define DPORT_APP_CPU_RECORDING (BIT(0)) 3494 #define DPORT_APP_CPU_RECORDING_M (BIT(0)) 3495 #define DPORT_APP_CPU_RECORDING_V 0x1 3496 #define DPORT_APP_CPU_RECORDING_S 0 3497 3498 #define DPORT_APP_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x470) 3499 /* DPORT_RECORD_APP_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */ 3500 /*description: */ 3501 #define DPORT_RECORD_APP_PID 0x00000007 3502 #define DPORT_RECORD_APP_PID_M ((DPORT_RECORD_APP_PID_V)<<(DPORT_RECORD_APP_PID_S)) 3503 #define DPORT_RECORD_APP_PID_V 0x7 3504 #define DPORT_RECORD_APP_PID_S 0 3505 3506 #define DPORT_APP_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x474) 3507 /* DPORT_RECORD_APP_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3508 /*description: */ 3509 #define DPORT_RECORD_APP_PDEBUGINST 0xFFFFFFFF 3510 #define DPORT_RECORD_APP_PDEBUGINST_M ((DPORT_RECORD_APP_PDEBUGINST_V)<<(DPORT_RECORD_APP_PDEBUGINST_S)) 3511 #define DPORT_RECORD_APP_PDEBUGINST_V 0xFFFFFFFF 3512 #define DPORT_RECORD_APP_PDEBUGINST_S 0 3513 3514 #define DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x478) 3515 /* DPORT_RECORD_APP_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ 3516 /*description: */ 3517 #define DPORT_RECORD_APP_PDEBUGSTATUS 0x000000FF 3518 #define DPORT_RECORD_APP_PDEBUGSTATUS_M ((DPORT_RECORD_APP_PDEBUGSTATUS_V)<<(DPORT_RECORD_APP_PDEBUGSTATUS_S)) 3519 #define DPORT_RECORD_APP_PDEBUGSTATUS_V 0xFF 3520 #define DPORT_RECORD_APP_PDEBUGSTATUS_S 0 3521 3522 #define DPORT_APP_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x47C) 3523 /* DPORT_RECORD_APP_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3524 /*description: */ 3525 #define DPORT_RECORD_APP_PDEBUGDATA 0xFFFFFFFF 3526 #define DPORT_RECORD_APP_PDEBUGDATA_M ((DPORT_RECORD_APP_PDEBUGDATA_V)<<(DPORT_RECORD_APP_PDEBUGDATA_S)) 3527 #define DPORT_RECORD_APP_PDEBUGDATA_V 0xFFFFFFFF 3528 #define DPORT_RECORD_APP_PDEBUGDATA_S 0 3529 3530 #define DPORT_APP_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x480) 3531 /* DPORT_RECORD_APP_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3532 /*description: */ 3533 #define DPORT_RECORD_APP_PDEBUGPC 0xFFFFFFFF 3534 #define DPORT_RECORD_APP_PDEBUGPC_M ((DPORT_RECORD_APP_PDEBUGPC_V)<<(DPORT_RECORD_APP_PDEBUGPC_S)) 3535 #define DPORT_RECORD_APP_PDEBUGPC_V 0xFFFFFFFF 3536 #define DPORT_RECORD_APP_PDEBUGPC_S 0 3537 3538 #define DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x484) 3539 /* DPORT_RECORD_APP_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3540 /*description: */ 3541 #define DPORT_RECORD_APP_PDEBUGLS0STAT 0xFFFFFFFF 3542 #define DPORT_RECORD_APP_PDEBUGLS0STAT_M ((DPORT_RECORD_APP_PDEBUGLS0STAT_V)<<(DPORT_RECORD_APP_PDEBUGLS0STAT_S)) 3543 #define DPORT_RECORD_APP_PDEBUGLS0STAT_V 0xFFFFFFFF 3544 #define DPORT_RECORD_APP_PDEBUGLS0STAT_S 0 3545 3546 #define DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x488) 3547 /* DPORT_RECORD_APP_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3548 /*description: */ 3549 #define DPORT_RECORD_APP_PDEBUGLS0ADDR 0xFFFFFFFF 3550 #define DPORT_RECORD_APP_PDEBUGLS0ADDR_M ((DPORT_RECORD_APP_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_APP_PDEBUGLS0ADDR_S)) 3551 #define DPORT_RECORD_APP_PDEBUGLS0ADDR_V 0xFFFFFFFF 3552 #define DPORT_RECORD_APP_PDEBUGLS0ADDR_S 0 3553 3554 #define DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x48C) 3555 /* DPORT_RECORD_APP_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3556 /*description: */ 3557 #define DPORT_RECORD_APP_PDEBUGLS0DATA 0xFFFFFFFF 3558 #define DPORT_RECORD_APP_PDEBUGLS0DATA_M ((DPORT_RECORD_APP_PDEBUGLS0DATA_V)<<(DPORT_RECORD_APP_PDEBUGLS0DATA_S)) 3559 #define DPORT_RECORD_APP_PDEBUGLS0DATA_V 0xFFFFFFFF 3560 #define DPORT_RECORD_APP_PDEBUGLS0DATA_S 0 3561 3562 #define DPORT_RSA_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x490) 3563 /* DPORT_RSA_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ 3564 /*description: */ 3565 #define DPORT_RSA_PD (BIT(0)) 3566 #define DPORT_RSA_PD_M (BIT(0)) 3567 #define DPORT_RSA_PD_V 0x1 3568 #define DPORT_RSA_PD_S 0 3569 3570 #define DPORT_ROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x494) 3571 /* DPORT_ROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3572 /*description: */ 3573 #define DPORT_ROM_MPU_TABLE0 0x00000003 3574 #define DPORT_ROM_MPU_TABLE0_M ((DPORT_ROM_MPU_TABLE0_V)<<(DPORT_ROM_MPU_TABLE0_S)) 3575 #define DPORT_ROM_MPU_TABLE0_V 0x3 3576 #define DPORT_ROM_MPU_TABLE0_S 0 3577 3578 #define DPORT_ROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x498) 3579 /* DPORT_ROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3580 /*description: */ 3581 #define DPORT_ROM_MPU_TABLE1 0x00000003 3582 #define DPORT_ROM_MPU_TABLE1_M ((DPORT_ROM_MPU_TABLE1_V)<<(DPORT_ROM_MPU_TABLE1_S)) 3583 #define DPORT_ROM_MPU_TABLE1_V 0x3 3584 #define DPORT_ROM_MPU_TABLE1_S 0 3585 3586 #define DPORT_ROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x49C) 3587 /* DPORT_ROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3588 /*description: */ 3589 #define DPORT_ROM_MPU_TABLE2 0x00000003 3590 #define DPORT_ROM_MPU_TABLE2_M ((DPORT_ROM_MPU_TABLE2_V)<<(DPORT_ROM_MPU_TABLE2_S)) 3591 #define DPORT_ROM_MPU_TABLE2_V 0x3 3592 #define DPORT_ROM_MPU_TABLE2_S 0 3593 3594 #define DPORT_ROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4A0) 3595 /* DPORT_ROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3596 /*description: */ 3597 #define DPORT_ROM_MPU_TABLE3 0x00000003 3598 #define DPORT_ROM_MPU_TABLE3_M ((DPORT_ROM_MPU_TABLE3_V)<<(DPORT_ROM_MPU_TABLE3_S)) 3599 #define DPORT_ROM_MPU_TABLE3_V 0x3 3600 #define DPORT_ROM_MPU_TABLE3_S 0 3601 3602 #define DPORT_SHROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x4A4) 3603 /* DPORT_SHROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3604 /*description: */ 3605 #define DPORT_SHROM_MPU_TABLE0 0x00000003 3606 #define DPORT_SHROM_MPU_TABLE0_M ((DPORT_SHROM_MPU_TABLE0_V)<<(DPORT_SHROM_MPU_TABLE0_S)) 3607 #define DPORT_SHROM_MPU_TABLE0_V 0x3 3608 #define DPORT_SHROM_MPU_TABLE0_S 0 3609 3610 #define DPORT_SHROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x4A8) 3611 /* DPORT_SHROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3612 /*description: */ 3613 #define DPORT_SHROM_MPU_TABLE1 0x00000003 3614 #define DPORT_SHROM_MPU_TABLE1_M ((DPORT_SHROM_MPU_TABLE1_V)<<(DPORT_SHROM_MPU_TABLE1_S)) 3615 #define DPORT_SHROM_MPU_TABLE1_V 0x3 3616 #define DPORT_SHROM_MPU_TABLE1_S 0 3617 3618 #define DPORT_SHROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x4AC) 3619 /* DPORT_SHROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3620 /*description: */ 3621 #define DPORT_SHROM_MPU_TABLE2 0x00000003 3622 #define DPORT_SHROM_MPU_TABLE2_M ((DPORT_SHROM_MPU_TABLE2_V)<<(DPORT_SHROM_MPU_TABLE2_S)) 3623 #define DPORT_SHROM_MPU_TABLE2_V 0x3 3624 #define DPORT_SHROM_MPU_TABLE2_S 0 3625 3626 #define DPORT_SHROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4B0) 3627 /* DPORT_SHROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3628 /*description: */ 3629 #define DPORT_SHROM_MPU_TABLE3 0x00000003 3630 #define DPORT_SHROM_MPU_TABLE3_M ((DPORT_SHROM_MPU_TABLE3_V)<<(DPORT_SHROM_MPU_TABLE3_S)) 3631 #define DPORT_SHROM_MPU_TABLE3_V 0x3 3632 #define DPORT_SHROM_MPU_TABLE3_S 0 3633 3634 #define DPORT_SHROM_MPU_TABLE4_REG (DR_REG_DPORT_BASE + 0x4B4) 3635 /* DPORT_SHROM_MPU_TABLE4 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3636 /*description: */ 3637 #define DPORT_SHROM_MPU_TABLE4 0x00000003 3638 #define DPORT_SHROM_MPU_TABLE4_M ((DPORT_SHROM_MPU_TABLE4_V)<<(DPORT_SHROM_MPU_TABLE4_S)) 3639 #define DPORT_SHROM_MPU_TABLE4_V 0x3 3640 #define DPORT_SHROM_MPU_TABLE4_S 0 3641 3642 #define DPORT_SHROM_MPU_TABLE5_REG (DR_REG_DPORT_BASE + 0x4B8) 3643 /* DPORT_SHROM_MPU_TABLE5 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3644 /*description: */ 3645 #define DPORT_SHROM_MPU_TABLE5 0x00000003 3646 #define DPORT_SHROM_MPU_TABLE5_M ((DPORT_SHROM_MPU_TABLE5_V)<<(DPORT_SHROM_MPU_TABLE5_S)) 3647 #define DPORT_SHROM_MPU_TABLE5_V 0x3 3648 #define DPORT_SHROM_MPU_TABLE5_S 0 3649 3650 #define DPORT_SHROM_MPU_TABLE6_REG (DR_REG_DPORT_BASE + 0x4BC) 3651 /* DPORT_SHROM_MPU_TABLE6 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3652 /*description: */ 3653 #define DPORT_SHROM_MPU_TABLE6 0x00000003 3654 #define DPORT_SHROM_MPU_TABLE6_M ((DPORT_SHROM_MPU_TABLE6_V)<<(DPORT_SHROM_MPU_TABLE6_S)) 3655 #define DPORT_SHROM_MPU_TABLE6_V 0x3 3656 #define DPORT_SHROM_MPU_TABLE6_S 0 3657 3658 #define DPORT_SHROM_MPU_TABLE7_REG (DR_REG_DPORT_BASE + 0x4C0) 3659 /* DPORT_SHROM_MPU_TABLE7 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3660 /*description: */ 3661 #define DPORT_SHROM_MPU_TABLE7 0x00000003 3662 #define DPORT_SHROM_MPU_TABLE7_M ((DPORT_SHROM_MPU_TABLE7_V)<<(DPORT_SHROM_MPU_TABLE7_S)) 3663 #define DPORT_SHROM_MPU_TABLE7_V 0x3 3664 #define DPORT_SHROM_MPU_TABLE7_S 0 3665 3666 #define DPORT_SHROM_MPU_TABLE8_REG (DR_REG_DPORT_BASE + 0x4C4) 3667 /* DPORT_SHROM_MPU_TABLE8 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3668 /*description: */ 3669 #define DPORT_SHROM_MPU_TABLE8 0x00000003 3670 #define DPORT_SHROM_MPU_TABLE8_M ((DPORT_SHROM_MPU_TABLE8_V)<<(DPORT_SHROM_MPU_TABLE8_S)) 3671 #define DPORT_SHROM_MPU_TABLE8_V 0x3 3672 #define DPORT_SHROM_MPU_TABLE8_S 0 3673 3674 #define DPORT_SHROM_MPU_TABLE9_REG (DR_REG_DPORT_BASE + 0x4C8) 3675 /* DPORT_SHROM_MPU_TABLE9 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3676 /*description: */ 3677 #define DPORT_SHROM_MPU_TABLE9 0x00000003 3678 #define DPORT_SHROM_MPU_TABLE9_M ((DPORT_SHROM_MPU_TABLE9_V)<<(DPORT_SHROM_MPU_TABLE9_S)) 3679 #define DPORT_SHROM_MPU_TABLE9_V 0x3 3680 #define DPORT_SHROM_MPU_TABLE9_S 0 3681 3682 #define DPORT_SHROM_MPU_TABLE10_REG (DR_REG_DPORT_BASE + 0x4CC) 3683 /* DPORT_SHROM_MPU_TABLE10 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3684 /*description: */ 3685 #define DPORT_SHROM_MPU_TABLE10 0x00000003 3686 #define DPORT_SHROM_MPU_TABLE10_M ((DPORT_SHROM_MPU_TABLE10_V)<<(DPORT_SHROM_MPU_TABLE10_S)) 3687 #define DPORT_SHROM_MPU_TABLE10_V 0x3 3688 #define DPORT_SHROM_MPU_TABLE10_S 0 3689 3690 #define DPORT_SHROM_MPU_TABLE11_REG (DR_REG_DPORT_BASE + 0x4D0) 3691 /* DPORT_SHROM_MPU_TABLE11 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3692 /*description: */ 3693 #define DPORT_SHROM_MPU_TABLE11 0x00000003 3694 #define DPORT_SHROM_MPU_TABLE11_M ((DPORT_SHROM_MPU_TABLE11_V)<<(DPORT_SHROM_MPU_TABLE11_S)) 3695 #define DPORT_SHROM_MPU_TABLE11_V 0x3 3696 #define DPORT_SHROM_MPU_TABLE11_S 0 3697 3698 #define DPORT_SHROM_MPU_TABLE12_REG (DR_REG_DPORT_BASE + 0x4D4) 3699 /* DPORT_SHROM_MPU_TABLE12 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3700 /*description: */ 3701 #define DPORT_SHROM_MPU_TABLE12 0x00000003 3702 #define DPORT_SHROM_MPU_TABLE12_M ((DPORT_SHROM_MPU_TABLE12_V)<<(DPORT_SHROM_MPU_TABLE12_S)) 3703 #define DPORT_SHROM_MPU_TABLE12_V 0x3 3704 #define DPORT_SHROM_MPU_TABLE12_S 0 3705 3706 #define DPORT_SHROM_MPU_TABLE13_REG (DR_REG_DPORT_BASE + 0x4D8) 3707 /* DPORT_SHROM_MPU_TABLE13 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3708 /*description: */ 3709 #define DPORT_SHROM_MPU_TABLE13 0x00000003 3710 #define DPORT_SHROM_MPU_TABLE13_M ((DPORT_SHROM_MPU_TABLE13_V)<<(DPORT_SHROM_MPU_TABLE13_S)) 3711 #define DPORT_SHROM_MPU_TABLE13_V 0x3 3712 #define DPORT_SHROM_MPU_TABLE13_S 0 3713 3714 #define DPORT_SHROM_MPU_TABLE14_REG (DR_REG_DPORT_BASE + 0x4DC) 3715 /* DPORT_SHROM_MPU_TABLE14 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3716 /*description: */ 3717 #define DPORT_SHROM_MPU_TABLE14 0x00000003 3718 #define DPORT_SHROM_MPU_TABLE14_M ((DPORT_SHROM_MPU_TABLE14_V)<<(DPORT_SHROM_MPU_TABLE14_S)) 3719 #define DPORT_SHROM_MPU_TABLE14_V 0x3 3720 #define DPORT_SHROM_MPU_TABLE14_S 0 3721 3722 #define DPORT_SHROM_MPU_TABLE15_REG (DR_REG_DPORT_BASE + 0x4E0) 3723 /* DPORT_SHROM_MPU_TABLE15 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3724 /*description: */ 3725 #define DPORT_SHROM_MPU_TABLE15 0x00000003 3726 #define DPORT_SHROM_MPU_TABLE15_M ((DPORT_SHROM_MPU_TABLE15_V)<<(DPORT_SHROM_MPU_TABLE15_S)) 3727 #define DPORT_SHROM_MPU_TABLE15_V 0x3 3728 #define DPORT_SHROM_MPU_TABLE15_S 0 3729 3730 #define DPORT_SHROM_MPU_TABLE16_REG (DR_REG_DPORT_BASE + 0x4E4) 3731 /* DPORT_SHROM_MPU_TABLE16 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3732 /*description: */ 3733 #define DPORT_SHROM_MPU_TABLE16 0x00000003 3734 #define DPORT_SHROM_MPU_TABLE16_M ((DPORT_SHROM_MPU_TABLE16_V)<<(DPORT_SHROM_MPU_TABLE16_S)) 3735 #define DPORT_SHROM_MPU_TABLE16_V 0x3 3736 #define DPORT_SHROM_MPU_TABLE16_S 0 3737 3738 #define DPORT_SHROM_MPU_TABLE17_REG (DR_REG_DPORT_BASE + 0x4E8) 3739 /* DPORT_SHROM_MPU_TABLE17 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3740 /*description: */ 3741 #define DPORT_SHROM_MPU_TABLE17 0x00000003 3742 #define DPORT_SHROM_MPU_TABLE17_M ((DPORT_SHROM_MPU_TABLE17_V)<<(DPORT_SHROM_MPU_TABLE17_S)) 3743 #define DPORT_SHROM_MPU_TABLE17_V 0x3 3744 #define DPORT_SHROM_MPU_TABLE17_S 0 3745 3746 #define DPORT_SHROM_MPU_TABLE18_REG (DR_REG_DPORT_BASE + 0x4EC) 3747 /* DPORT_SHROM_MPU_TABLE18 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3748 /*description: */ 3749 #define DPORT_SHROM_MPU_TABLE18 0x00000003 3750 #define DPORT_SHROM_MPU_TABLE18_M ((DPORT_SHROM_MPU_TABLE18_V)<<(DPORT_SHROM_MPU_TABLE18_S)) 3751 #define DPORT_SHROM_MPU_TABLE18_V 0x3 3752 #define DPORT_SHROM_MPU_TABLE18_S 0 3753 3754 #define DPORT_SHROM_MPU_TABLE19_REG (DR_REG_DPORT_BASE + 0x4F0) 3755 /* DPORT_SHROM_MPU_TABLE19 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3756 /*description: */ 3757 #define DPORT_SHROM_MPU_TABLE19 0x00000003 3758 #define DPORT_SHROM_MPU_TABLE19_M ((DPORT_SHROM_MPU_TABLE19_V)<<(DPORT_SHROM_MPU_TABLE19_S)) 3759 #define DPORT_SHROM_MPU_TABLE19_V 0x3 3760 #define DPORT_SHROM_MPU_TABLE19_S 0 3761 3762 #define DPORT_SHROM_MPU_TABLE20_REG (DR_REG_DPORT_BASE + 0x4F4) 3763 /* DPORT_SHROM_MPU_TABLE20 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3764 /*description: */ 3765 #define DPORT_SHROM_MPU_TABLE20 0x00000003 3766 #define DPORT_SHROM_MPU_TABLE20_M ((DPORT_SHROM_MPU_TABLE20_V)<<(DPORT_SHROM_MPU_TABLE20_S)) 3767 #define DPORT_SHROM_MPU_TABLE20_V 0x3 3768 #define DPORT_SHROM_MPU_TABLE20_S 0 3769 3770 #define DPORT_SHROM_MPU_TABLE21_REG (DR_REG_DPORT_BASE + 0x4F8) 3771 /* DPORT_SHROM_MPU_TABLE21 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3772 /*description: */ 3773 #define DPORT_SHROM_MPU_TABLE21 0x00000003 3774 #define DPORT_SHROM_MPU_TABLE21_M ((DPORT_SHROM_MPU_TABLE21_V)<<(DPORT_SHROM_MPU_TABLE21_S)) 3775 #define DPORT_SHROM_MPU_TABLE21_V 0x3 3776 #define DPORT_SHROM_MPU_TABLE21_S 0 3777 3778 #define DPORT_SHROM_MPU_TABLE22_REG (DR_REG_DPORT_BASE + 0x4FC) 3779 /* DPORT_SHROM_MPU_TABLE22 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3780 /*description: */ 3781 #define DPORT_SHROM_MPU_TABLE22 0x00000003 3782 #define DPORT_SHROM_MPU_TABLE22_M ((DPORT_SHROM_MPU_TABLE22_V)<<(DPORT_SHROM_MPU_TABLE22_S)) 3783 #define DPORT_SHROM_MPU_TABLE22_V 0x3 3784 #define DPORT_SHROM_MPU_TABLE22_S 0 3785 3786 #define DPORT_SHROM_MPU_TABLE23_REG (DR_REG_DPORT_BASE + 0x500) 3787 /* DPORT_SHROM_MPU_TABLE23 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3788 /*description: */ 3789 #define DPORT_SHROM_MPU_TABLE23 0x00000003 3790 #define DPORT_SHROM_MPU_TABLE23_M ((DPORT_SHROM_MPU_TABLE23_V)<<(DPORT_SHROM_MPU_TABLE23_S)) 3791 #define DPORT_SHROM_MPU_TABLE23_V 0x3 3792 #define DPORT_SHROM_MPU_TABLE23_S 0 3793 3794 #define DPORT_IMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x504) 3795 /* DPORT_IMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */ 3796 /*description: */ 3797 #define DPORT_IMMU_TABLE0 0x0000007F 3798 #define DPORT_IMMU_TABLE0_M ((DPORT_IMMU_TABLE0_V)<<(DPORT_IMMU_TABLE0_S)) 3799 #define DPORT_IMMU_TABLE0_V 0x7F 3800 #define DPORT_IMMU_TABLE0_S 0 3801 3802 #define DPORT_IMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x508) 3803 /* DPORT_IMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ 3804 /*description: */ 3805 #define DPORT_IMMU_TABLE1 0x0000007F 3806 #define DPORT_IMMU_TABLE1_M ((DPORT_IMMU_TABLE1_V)<<(DPORT_IMMU_TABLE1_S)) 3807 #define DPORT_IMMU_TABLE1_V 0x7F 3808 #define DPORT_IMMU_TABLE1_S 0 3809 3810 #define DPORT_IMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x50C) 3811 /* DPORT_IMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */ 3812 /*description: */ 3813 #define DPORT_IMMU_TABLE2 0x0000007F 3814 #define DPORT_IMMU_TABLE2_M ((DPORT_IMMU_TABLE2_V)<<(DPORT_IMMU_TABLE2_S)) 3815 #define DPORT_IMMU_TABLE2_V 0x7F 3816 #define DPORT_IMMU_TABLE2_S 0 3817 3818 #define DPORT_IMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x510) 3819 /* DPORT_IMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */ 3820 /*description: */ 3821 #define DPORT_IMMU_TABLE3 0x0000007F 3822 #define DPORT_IMMU_TABLE3_M ((DPORT_IMMU_TABLE3_V)<<(DPORT_IMMU_TABLE3_S)) 3823 #define DPORT_IMMU_TABLE3_V 0x7F 3824 #define DPORT_IMMU_TABLE3_S 0 3825 3826 #define DPORT_IMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x514) 3827 /* DPORT_IMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */ 3828 /*description: */ 3829 #define DPORT_IMMU_TABLE4 0x0000007F 3830 #define DPORT_IMMU_TABLE4_M ((DPORT_IMMU_TABLE4_V)<<(DPORT_IMMU_TABLE4_S)) 3831 #define DPORT_IMMU_TABLE4_V 0x7F 3832 #define DPORT_IMMU_TABLE4_S 0 3833 3834 #define DPORT_IMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x518) 3835 /* DPORT_IMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */ 3836 /*description: */ 3837 #define DPORT_IMMU_TABLE5 0x0000007F 3838 #define DPORT_IMMU_TABLE5_M ((DPORT_IMMU_TABLE5_V)<<(DPORT_IMMU_TABLE5_S)) 3839 #define DPORT_IMMU_TABLE5_V 0x7F 3840 #define DPORT_IMMU_TABLE5_S 0 3841 3842 #define DPORT_IMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x51C) 3843 /* DPORT_IMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */ 3844 /*description: */ 3845 #define DPORT_IMMU_TABLE6 0x0000007F 3846 #define DPORT_IMMU_TABLE6_M ((DPORT_IMMU_TABLE6_V)<<(DPORT_IMMU_TABLE6_S)) 3847 #define DPORT_IMMU_TABLE6_V 0x7F 3848 #define DPORT_IMMU_TABLE6_S 0 3849 3850 #define DPORT_IMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x520) 3851 /* DPORT_IMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */ 3852 /*description: */ 3853 #define DPORT_IMMU_TABLE7 0x0000007F 3854 #define DPORT_IMMU_TABLE7_M ((DPORT_IMMU_TABLE7_V)<<(DPORT_IMMU_TABLE7_S)) 3855 #define DPORT_IMMU_TABLE7_V 0x7F 3856 #define DPORT_IMMU_TABLE7_S 0 3857 3858 #define DPORT_IMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x524) 3859 /* DPORT_IMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */ 3860 /*description: */ 3861 #define DPORT_IMMU_TABLE8 0x0000007F 3862 #define DPORT_IMMU_TABLE8_M ((DPORT_IMMU_TABLE8_V)<<(DPORT_IMMU_TABLE8_S)) 3863 #define DPORT_IMMU_TABLE8_V 0x7F 3864 #define DPORT_IMMU_TABLE8_S 0 3865 3866 #define DPORT_IMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x528) 3867 /* DPORT_IMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */ 3868 /*description: */ 3869 #define DPORT_IMMU_TABLE9 0x0000007F 3870 #define DPORT_IMMU_TABLE9_M ((DPORT_IMMU_TABLE9_V)<<(DPORT_IMMU_TABLE9_S)) 3871 #define DPORT_IMMU_TABLE9_V 0x7F 3872 #define DPORT_IMMU_TABLE9_S 0 3873 3874 #define DPORT_IMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x52C) 3875 /* DPORT_IMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */ 3876 /*description: */ 3877 #define DPORT_IMMU_TABLE10 0x0000007F 3878 #define DPORT_IMMU_TABLE10_M ((DPORT_IMMU_TABLE10_V)<<(DPORT_IMMU_TABLE10_S)) 3879 #define DPORT_IMMU_TABLE10_V 0x7F 3880 #define DPORT_IMMU_TABLE10_S 0 3881 3882 #define DPORT_IMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x530) 3883 /* DPORT_IMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */ 3884 /*description: */ 3885 #define DPORT_IMMU_TABLE11 0x0000007F 3886 #define DPORT_IMMU_TABLE11_M ((DPORT_IMMU_TABLE11_V)<<(DPORT_IMMU_TABLE11_S)) 3887 #define DPORT_IMMU_TABLE11_V 0x7F 3888 #define DPORT_IMMU_TABLE11_S 0 3889 3890 #define DPORT_IMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x534) 3891 /* DPORT_IMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */ 3892 /*description: */ 3893 #define DPORT_IMMU_TABLE12 0x0000007F 3894 #define DPORT_IMMU_TABLE12_M ((DPORT_IMMU_TABLE12_V)<<(DPORT_IMMU_TABLE12_S)) 3895 #define DPORT_IMMU_TABLE12_V 0x7F 3896 #define DPORT_IMMU_TABLE12_S 0 3897 3898 #define DPORT_IMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x538) 3899 /* DPORT_IMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */ 3900 /*description: */ 3901 #define DPORT_IMMU_TABLE13 0x0000007F 3902 #define DPORT_IMMU_TABLE13_M ((DPORT_IMMU_TABLE13_V)<<(DPORT_IMMU_TABLE13_S)) 3903 #define DPORT_IMMU_TABLE13_V 0x7F 3904 #define DPORT_IMMU_TABLE13_S 0 3905 3906 #define DPORT_IMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x53C) 3907 /* DPORT_IMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ 3908 /*description: */ 3909 #define DPORT_IMMU_TABLE14 0x0000007F 3910 #define DPORT_IMMU_TABLE14_M ((DPORT_IMMU_TABLE14_V)<<(DPORT_IMMU_TABLE14_S)) 3911 #define DPORT_IMMU_TABLE14_V 0x7F 3912 #define DPORT_IMMU_TABLE14_S 0 3913 3914 #define DPORT_IMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x540) 3915 /* DPORT_IMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */ 3916 /*description: */ 3917 #define DPORT_IMMU_TABLE15 0x0000007F 3918 #define DPORT_IMMU_TABLE15_M ((DPORT_IMMU_TABLE15_V)<<(DPORT_IMMU_TABLE15_S)) 3919 #define DPORT_IMMU_TABLE15_V 0x7F 3920 #define DPORT_IMMU_TABLE15_S 0 3921 3922 #define DPORT_DMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x544) 3923 /* DPORT_DMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */ 3924 /*description: */ 3925 #define DPORT_DMMU_TABLE0 0x0000007F 3926 #define DPORT_DMMU_TABLE0_M ((DPORT_DMMU_TABLE0_V)<<(DPORT_DMMU_TABLE0_S)) 3927 #define DPORT_DMMU_TABLE0_V 0x7F 3928 #define DPORT_DMMU_TABLE0_S 0 3929 3930 #define DPORT_DMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x548) 3931 /* DPORT_DMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ 3932 /*description: */ 3933 #define DPORT_DMMU_TABLE1 0x0000007F 3934 #define DPORT_DMMU_TABLE1_M ((DPORT_DMMU_TABLE1_V)<<(DPORT_DMMU_TABLE1_S)) 3935 #define DPORT_DMMU_TABLE1_V 0x7F 3936 #define DPORT_DMMU_TABLE1_S 0 3937 3938 #define DPORT_DMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x54C) 3939 /* DPORT_DMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */ 3940 /*description: */ 3941 #define DPORT_DMMU_TABLE2 0x0000007F 3942 #define DPORT_DMMU_TABLE2_M ((DPORT_DMMU_TABLE2_V)<<(DPORT_DMMU_TABLE2_S)) 3943 #define DPORT_DMMU_TABLE2_V 0x7F 3944 #define DPORT_DMMU_TABLE2_S 0 3945 3946 #define DPORT_DMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x550) 3947 /* DPORT_DMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */ 3948 /*description: */ 3949 #define DPORT_DMMU_TABLE3 0x0000007F 3950 #define DPORT_DMMU_TABLE3_M ((DPORT_DMMU_TABLE3_V)<<(DPORT_DMMU_TABLE3_S)) 3951 #define DPORT_DMMU_TABLE3_V 0x7F 3952 #define DPORT_DMMU_TABLE3_S 0 3953 3954 #define DPORT_DMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x554) 3955 /* DPORT_DMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */ 3956 /*description: */ 3957 #define DPORT_DMMU_TABLE4 0x0000007F 3958 #define DPORT_DMMU_TABLE4_M ((DPORT_DMMU_TABLE4_V)<<(DPORT_DMMU_TABLE4_S)) 3959 #define DPORT_DMMU_TABLE4_V 0x7F 3960 #define DPORT_DMMU_TABLE4_S 0 3961 3962 #define DPORT_DMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x558) 3963 /* DPORT_DMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */ 3964 /*description: */ 3965 #define DPORT_DMMU_TABLE5 0x0000007F 3966 #define DPORT_DMMU_TABLE5_M ((DPORT_DMMU_TABLE5_V)<<(DPORT_DMMU_TABLE5_S)) 3967 #define DPORT_DMMU_TABLE5_V 0x7F 3968 #define DPORT_DMMU_TABLE5_S 0 3969 3970 #define DPORT_DMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x55C) 3971 /* DPORT_DMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */ 3972 /*description: */ 3973 #define DPORT_DMMU_TABLE6 0x0000007F 3974 #define DPORT_DMMU_TABLE6_M ((DPORT_DMMU_TABLE6_V)<<(DPORT_DMMU_TABLE6_S)) 3975 #define DPORT_DMMU_TABLE6_V 0x7F 3976 #define DPORT_DMMU_TABLE6_S 0 3977 3978 #define DPORT_DMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x560) 3979 /* DPORT_DMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */ 3980 /*description: */ 3981 #define DPORT_DMMU_TABLE7 0x0000007F 3982 #define DPORT_DMMU_TABLE7_M ((DPORT_DMMU_TABLE7_V)<<(DPORT_DMMU_TABLE7_S)) 3983 #define DPORT_DMMU_TABLE7_V 0x7F 3984 #define DPORT_DMMU_TABLE7_S 0 3985 3986 #define DPORT_DMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x564) 3987 /* DPORT_DMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */ 3988 /*description: */ 3989 #define DPORT_DMMU_TABLE8 0x0000007F 3990 #define DPORT_DMMU_TABLE8_M ((DPORT_DMMU_TABLE8_V)<<(DPORT_DMMU_TABLE8_S)) 3991 #define DPORT_DMMU_TABLE8_V 0x7F 3992 #define DPORT_DMMU_TABLE8_S 0 3993 3994 #define DPORT_DMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x568) 3995 /* DPORT_DMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */ 3996 /*description: */ 3997 #define DPORT_DMMU_TABLE9 0x0000007F 3998 #define DPORT_DMMU_TABLE9_M ((DPORT_DMMU_TABLE9_V)<<(DPORT_DMMU_TABLE9_S)) 3999 #define DPORT_DMMU_TABLE9_V 0x7F 4000 #define DPORT_DMMU_TABLE9_S 0 4001 4002 #define DPORT_DMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x56C) 4003 /* DPORT_DMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */ 4004 /*description: */ 4005 #define DPORT_DMMU_TABLE10 0x0000007F 4006 #define DPORT_DMMU_TABLE10_M ((DPORT_DMMU_TABLE10_V)<<(DPORT_DMMU_TABLE10_S)) 4007 #define DPORT_DMMU_TABLE10_V 0x7F 4008 #define DPORT_DMMU_TABLE10_S 0 4009 4010 #define DPORT_DMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x570) 4011 /* DPORT_DMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */ 4012 /*description: */ 4013 #define DPORT_DMMU_TABLE11 0x0000007F 4014 #define DPORT_DMMU_TABLE11_M ((DPORT_DMMU_TABLE11_V)<<(DPORT_DMMU_TABLE11_S)) 4015 #define DPORT_DMMU_TABLE11_V 0x7F 4016 #define DPORT_DMMU_TABLE11_S 0 4017 4018 #define DPORT_DMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x574) 4019 /* DPORT_DMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */ 4020 /*description: */ 4021 #define DPORT_DMMU_TABLE12 0x0000007F 4022 #define DPORT_DMMU_TABLE12_M ((DPORT_DMMU_TABLE12_V)<<(DPORT_DMMU_TABLE12_S)) 4023 #define DPORT_DMMU_TABLE12_V 0x7F 4024 #define DPORT_DMMU_TABLE12_S 0 4025 4026 #define DPORT_DMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x578) 4027 /* DPORT_DMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */ 4028 /*description: */ 4029 #define DPORT_DMMU_TABLE13 0x0000007F 4030 #define DPORT_DMMU_TABLE13_M ((DPORT_DMMU_TABLE13_V)<<(DPORT_DMMU_TABLE13_S)) 4031 #define DPORT_DMMU_TABLE13_V 0x7F 4032 #define DPORT_DMMU_TABLE13_S 0 4033 4034 #define DPORT_DMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x57C) 4035 /* DPORT_DMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ 4036 /*description: */ 4037 #define DPORT_DMMU_TABLE14 0x0000007F 4038 #define DPORT_DMMU_TABLE14_M ((DPORT_DMMU_TABLE14_V)<<(DPORT_DMMU_TABLE14_S)) 4039 #define DPORT_DMMU_TABLE14_V 0x7F 4040 #define DPORT_DMMU_TABLE14_S 0 4041 4042 #define DPORT_DMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x580) 4043 /* DPORT_DMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */ 4044 /*description: */ 4045 #define DPORT_DMMU_TABLE15 0x0000007F 4046 #define DPORT_DMMU_TABLE15_M ((DPORT_DMMU_TABLE15_V)<<(DPORT_DMMU_TABLE15_S)) 4047 #define DPORT_DMMU_TABLE15_V 0x7F 4048 #define DPORT_DMMU_TABLE15_S 0 4049 4050 #define DPORT_PRO_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x584) 4051 /* DPORT_PRO_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */ 4052 /*description: */ 4053 #define DPORT_PRO_INTRUSION_RECORD_RESET_N (BIT(0)) 4054 #define DPORT_PRO_INTRUSION_RECORD_RESET_N_M (BIT(0)) 4055 #define DPORT_PRO_INTRUSION_RECORD_RESET_N_V 0x1 4056 #define DPORT_PRO_INTRUSION_RECORD_RESET_N_S 0 4057 4058 #define DPORT_PRO_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x588) 4059 /* DPORT_PRO_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */ 4060 /*description: */ 4061 #define DPORT_PRO_INTRUSION_RECORD 0x0000000F 4062 #define DPORT_PRO_INTRUSION_RECORD_M ((DPORT_PRO_INTRUSION_RECORD_V)<<(DPORT_PRO_INTRUSION_RECORD_S)) 4063 #define DPORT_PRO_INTRUSION_RECORD_V 0xF 4064 #define DPORT_PRO_INTRUSION_RECORD_S 0 4065 4066 #define DPORT_APP_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x58C) 4067 /* DPORT_APP_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */ 4068 /*description: */ 4069 #define DPORT_APP_INTRUSION_RECORD_RESET_N (BIT(0)) 4070 #define DPORT_APP_INTRUSION_RECORD_RESET_N_M (BIT(0)) 4071 #define DPORT_APP_INTRUSION_RECORD_RESET_N_V 0x1 4072 #define DPORT_APP_INTRUSION_RECORD_RESET_N_S 0 4073 4074 #define DPORT_APP_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x590) 4075 /* DPORT_APP_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */ 4076 /*description: */ 4077 #define DPORT_APP_INTRUSION_RECORD 0x0000000F 4078 #define DPORT_APP_INTRUSION_RECORD_M ((DPORT_APP_INTRUSION_RECORD_V)<<(DPORT_APP_INTRUSION_RECORD_S)) 4079 #define DPORT_APP_INTRUSION_RECORD_V 0xF 4080 #define DPORT_APP_INTRUSION_RECORD_S 0 4081 4082 #define DPORT_FRONT_END_MEM_PD_REG (DR_REG_DPORT_BASE + 0x594) 4083 /* DPORT_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 4084 /*description: */ 4085 #define DPORT_PBUS_MEM_FORCE_PD (BIT(3)) 4086 #define DPORT_PBUS_MEM_FORCE_PD_M (BIT(3)) 4087 #define DPORT_PBUS_MEM_FORCE_PD_V 0x1 4088 #define DPORT_PBUS_MEM_FORCE_PD_S 3 4089 /* DPORT_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 4090 /*description: */ 4091 #define DPORT_PBUS_MEM_FORCE_PU (BIT(2)) 4092 #define DPORT_PBUS_MEM_FORCE_PU_M (BIT(2)) 4093 #define DPORT_PBUS_MEM_FORCE_PU_V 0x1 4094 #define DPORT_PBUS_MEM_FORCE_PU_S 2 4095 /* DPORT_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 4096 /*description: */ 4097 #define DPORT_AGC_MEM_FORCE_PD (BIT(1)) 4098 #define DPORT_AGC_MEM_FORCE_PD_M (BIT(1)) 4099 #define DPORT_AGC_MEM_FORCE_PD_V 0x1 4100 #define DPORT_AGC_MEM_FORCE_PD_S 1 4101 /* DPORT_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ 4102 /*description: */ 4103 #define DPORT_AGC_MEM_FORCE_PU (BIT(0)) 4104 #define DPORT_AGC_MEM_FORCE_PU_M (BIT(0)) 4105 #define DPORT_AGC_MEM_FORCE_PU_V 0x1 4106 #define DPORT_AGC_MEM_FORCE_PU_S 0 4107 4108 #define DPORT_MMU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x598) 4109 /* DPORT_MMU_IA_INT_EN : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ 4110 /*description: */ 4111 #define DPORT_MMU_IA_INT_EN 0x00FFFFFF 4112 #define DPORT_MMU_IA_INT_EN_M ((DPORT_MMU_IA_INT_EN_V)<<(DPORT_MMU_IA_INT_EN_S)) 4113 #define DPORT_MMU_IA_INT_EN_V 0xFFFFFF 4114 #define DPORT_MMU_IA_INT_EN_S 0 4115 4116 #define DPORT_MPU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x59C) 4117 /* DPORT_MPU_IA_INT_EN : R/W ;bitpos:[16:0] ;default: 17'b0 ; */ 4118 /*description: */ 4119 #define DPORT_MPU_IA_INT_EN 0x0001FFFF 4120 #define DPORT_MPU_IA_INT_EN_M ((DPORT_MPU_IA_INT_EN_V)<<(DPORT_MPU_IA_INT_EN_S)) 4121 #define DPORT_MPU_IA_INT_EN_V 0x1FFFF 4122 #define DPORT_MPU_IA_INT_EN_S 0 4123 4124 #define DPORT_CACHE_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x5A0) 4125 /* DPORT_CACHE_IA_INT_EN : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ 4126 /*description: Interrupt enable bits for various invalid cache access reasons*/ 4127 #define DPORT_CACHE_IA_INT_EN 0x0FFFFFFF 4128 #define DPORT_CACHE_IA_INT_EN_M ((DPORT_CACHE_IA_INT_EN_V)<<(DPORT_CACHE_IA_INT_EN_S)) 4129 #define DPORT_CACHE_IA_INT_EN_V 0xFFFFFFF 4130 #define DPORT_CACHE_IA_INT_EN_S 0 4131 /* Contents of DPORT_CACHE_IA_INT_EN field: */ 4132 /* DPORT_CACHE_IA_INT_PRO_OPPOSITE : R/W ;bitpos:[19] ;default: 1'b0 ; */ 4133 /*description: PRO CPU invalid access to APP CPU cache when cache disabled */ 4134 #define DPORT_CACHE_IA_INT_PRO_OPPOSITE BIT(19) 4135 #define DPORT_CACHE_IA_INT_PRO_OPPOSITE_M BIT(19) 4136 #define DPORT_CACHE_IA_INT_PRO_OPPOSITE_V (1) 4137 #define DPORT_CACHE_IA_INT_PRO_OPPOSITE_S (19) 4138 /* DPORT_CACHE_IA_INT_PRO_DRAM1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ 4139 /*description: PRO CPU invalid access to DRAM1 when cache is disabled */ 4140 #define DPORT_CACHE_IA_INT_PRO_DRAM1 BIT(18) 4141 #define DPORT_CACHE_IA_INT_PRO_DRAM1_M BIT(18) 4142 #define DPORT_CACHE_IA_INT_PRO_DRAM1_V (1) 4143 #define DPORT_CACHE_IA_INT_PRO_DRAM1_S (18) 4144 /* DPORT_CACHE_IA_INT_PRO_IROM0 : R/W ;bitpos:[17] ;default: 1'b0 ; */ 4145 /*description: PRO CPU invalid access to IROM0 when cache is disabled */ 4146 #define DPORT_CACHE_IA_INT_PRO_IROM0 BIT(17) 4147 #define DPORT_CACHE_IA_INT_PRO_IROM0_M BIT(17) 4148 #define DPORT_CACHE_IA_INT_PRO_IROM0_V (1) 4149 #define DPORT_CACHE_IA_INT_PRO_IROM0_S (17) 4150 /* DPORT_CACHE_IA_INT_PRO_IRAM1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ 4151 /*description: PRO CPU invalid access to IRAM1 when cache is disabled */ 4152 #define DPORT_CACHE_IA_INT_PRO_IRAM1 BIT(16) 4153 #define DPORT_CACHE_IA_INT_PRO_IRAM1_M BIT(16) 4154 #define DPORT_CACHE_IA_INT_PRO_IRAM1_V (1) 4155 #define DPORT_CACHE_IA_INT_PRO_IRAM1_S (16) 4156 /* DPORT_CACHE_IA_INT_PRO_IRAM0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ 4157 /*description: PRO CPU invalid access to IRAM0 when cache is disabled */ 4158 #define DPORT_CACHE_IA_INT_PRO_IRAM0 BIT(15) 4159 #define DPORT_CACHE_IA_INT_PRO_IRAM0_M BIT(15) 4160 #define DPORT_CACHE_IA_INT_PRO_IRAM0_V (1) 4161 #define DPORT_CACHE_IA_INT_PRO_IRAM0_S (15) 4162 /* DPORT_CACHE_IA_INT_PRO_DROM0 : R/W ;bitpos:[14] ;default: 1'b0 ; */ 4163 /*description: PRO CPU invalid access to DROM0 when cache is disabled */ 4164 #define DPORT_CACHE_IA_INT_PRO_DROM0 BIT(14) 4165 #define DPORT_CACHE_IA_INT_PRO_DROM0_M BIT(14) 4166 #define DPORT_CACHE_IA_INT_PRO_DROM0_V (1) 4167 #define DPORT_CACHE_IA_INT_PRO_DROM0_S (14) 4168 /* DPORT_CACHE_IA_INT_APP_OPPOSITE : R/W ;bitpos:[5] ;default: 1'b0 ; */ 4169 /*description: APP CPU invalid access to APP CPU cache when cache disabled */ 4170 #define DPORT_CACHE_IA_INT_APP_OPPOSITE BIT(5) 4171 #define DPORT_CACHE_IA_INT_APP_OPPOSITE_M BIT(5) 4172 #define DPORT_CACHE_IA_INT_APP_OPPOSITE_V (1) 4173 #define DPORT_CACHE_IA_INT_APP_OPPOSITE_S (5) 4174 /* DPORT_CACHE_IA_INT_APP_DRAM1 : R/W ;bitpos:43] ;default: 1'b0 ; */ 4175 /*description: APP CPU invalid access to DRAM1 when cache is disabled */ 4176 #define DPORT_CACHE_IA_INT_APP_DRAM1 BIT(4) 4177 #define DPORT_CACHE_IA_INT_APP_DRAM1_M BIT(4) 4178 #define DPORT_CACHE_IA_INT_APP_DRAM1_V (1) 4179 #define DPORT_CACHE_IA_INT_APP_DRAM1_S (4) 4180 /* DPORT_CACHE_IA_INT_APP_IROM0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 4181 /*description: APP CPU invalid access to IROM0 when cache is disabled */ 4182 #define DPORT_CACHE_IA_INT_APP_IROM0 BIT(3) 4183 #define DPORT_CACHE_IA_INT_APP_IROM0_M BIT(3) 4184 #define DPORT_CACHE_IA_INT_APP_IROM0_V (1) 4185 #define DPORT_CACHE_IA_INT_APP_IROM0_S (3) 4186 /* DPORT_CACHE_IA_INT_APP_IRAM1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 4187 /*description: APP CPU invalid access to IRAM1 when cache is disabled */ 4188 #define DPORT_CACHE_IA_INT_APP_IRAM1 BIT(2) 4189 #define DPORT_CACHE_IA_INT_APP_IRAM1_M BIT(2) 4190 #define DPORT_CACHE_IA_INT_APP_IRAM1_V (1) 4191 #define DPORT_CACHE_IA_INT_APP_IRAM1_S (2) 4192 /* DPORT_CACHE_IA_INT_APP_IRAM0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ 4193 /*description: APP CPU invalid access to IRAM0 when cache is disabled */ 4194 #define DPORT_CACHE_IA_INT_APP_IRAM0 BIT(1) 4195 #define DPORT_CACHE_IA_INT_APP_IRAM0_M BIT(1) 4196 #define DPORT_CACHE_IA_INT_APP_IRAM0_V (1) 4197 #define DPORT_CACHE_IA_INT_APP_IRAM0_S (1) 4198 /* DPORT_CACHE_IA_INT_APP_DROM0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 4199 /*description: APP CPU invalid access to DROM0 when cache is disabled */ 4200 #define DPORT_CACHE_IA_INT_APP_DROM0 BIT(0) 4201 #define DPORT_CACHE_IA_INT_APP_DROM0_M BIT(0) 4202 #define DPORT_CACHE_IA_INT_APP_DROM0_V (1) 4203 #define DPORT_CACHE_IA_INT_APP_DROM0_S (0) 4204 4205 #define DPORT_SECURE_BOOT_CTRL_REG (DR_REG_DPORT_BASE + 0x5A4) 4206 /* DPORT_SW_BOOTLOADER_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ 4207 /*description: */ 4208 #define DPORT_SW_BOOTLOADER_SEL (BIT(0)) 4209 #define DPORT_SW_BOOTLOADER_SEL_M (BIT(0)) 4210 #define DPORT_SW_BOOTLOADER_SEL_V 0x1 4211 #define DPORT_SW_BOOTLOADER_SEL_S 0 4212 4213 #define DPORT_SPI_DMA_CHAN_SEL_REG (DR_REG_DPORT_BASE + 0x5A8) 4214 /* DPORT_SPI3_DMA_CHAN_SEL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */ 4215 /*description: */ 4216 #define DPORT_SPI3_DMA_CHAN_SEL 0x00000003 4217 #define DPORT_SPI3_DMA_CHAN_SEL_M ((DPORT_SPI3_DMA_CHAN_SEL_V)<<(DPORT_SPI3_DMA_CHAN_SEL_S)) 4218 #define DPORT_SPI3_DMA_CHAN_SEL_V 0x3 4219 #define DPORT_SPI3_DMA_CHAN_SEL_S 4 4220 /* DPORT_SPI2_DMA_CHAN_SEL : R/W ;bitpos:[3:2] ;default: 2'b00 ; */ 4221 /*description: */ 4222 #define DPORT_SPI2_DMA_CHAN_SEL 0x00000003 4223 #define DPORT_SPI2_DMA_CHAN_SEL_M ((DPORT_SPI2_DMA_CHAN_SEL_V)<<(DPORT_SPI2_DMA_CHAN_SEL_S)) 4224 #define DPORT_SPI2_DMA_CHAN_SEL_V 0x3 4225 #define DPORT_SPI2_DMA_CHAN_SEL_S 2 4226 /* DPORT_SPI1_DMA_CHAN_SEL : R/W ;bitpos:[1:0] ;default: 2'b00 ; */ 4227 /*description: */ 4228 #define DPORT_SPI1_DMA_CHAN_SEL 0x00000003 4229 #define DPORT_SPI1_DMA_CHAN_SEL_M ((DPORT_SPI1_DMA_CHAN_SEL_V)<<(DPORT_SPI1_DMA_CHAN_SEL_S)) 4230 #define DPORT_SPI1_DMA_CHAN_SEL_V 0x3 4231 #define DPORT_SPI1_DMA_CHAN_SEL_S 0 4232 4233 #define DPORT_PRO_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5AC) 4234 /* DPORT_PRO_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 4235 /*description: */ 4236 #define DPORT_PRO_OUT_VECBASE_SEL 0x00000003 4237 #define DPORT_PRO_OUT_VECBASE_SEL_M ((DPORT_PRO_OUT_VECBASE_SEL_V)<<(DPORT_PRO_OUT_VECBASE_SEL_S)) 4238 #define DPORT_PRO_OUT_VECBASE_SEL_V 0x3 4239 #define DPORT_PRO_OUT_VECBASE_SEL_S 0 4240 4241 #define DPORT_PRO_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B0) 4242 /* DPORT_PRO_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ 4243 /*description: */ 4244 #define DPORT_PRO_OUT_VECBASE_REG 0x003FFFFF 4245 #define DPORT_PRO_OUT_VECBASE_REG_M ((DPORT_PRO_OUT_VECBASE_REG_V)<<(DPORT_PRO_OUT_VECBASE_REG_S)) 4246 #define DPORT_PRO_OUT_VECBASE_REG_V 0x3FFFFF 4247 #define DPORT_PRO_OUT_VECBASE_REG_S 0 4248 4249 #define DPORT_APP_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5B4) 4250 /* DPORT_APP_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 4251 /*description: */ 4252 #define DPORT_APP_OUT_VECBASE_SEL 0x00000003 4253 #define DPORT_APP_OUT_VECBASE_SEL_M ((DPORT_APP_OUT_VECBASE_SEL_V)<<(DPORT_APP_OUT_VECBASE_SEL_S)) 4254 #define DPORT_APP_OUT_VECBASE_SEL_V 0x3 4255 #define DPORT_APP_OUT_VECBASE_SEL_S 0 4256 4257 #define DPORT_APP_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B8) 4258 /* DPORT_APP_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ 4259 /*description: */ 4260 #define DPORT_APP_OUT_VECBASE_REG 0x003FFFFF 4261 #define DPORT_APP_OUT_VECBASE_REG_M ((DPORT_APP_OUT_VECBASE_REG_V)<<(DPORT_APP_OUT_VECBASE_REG_S)) 4262 #define DPORT_APP_OUT_VECBASE_REG_V 0x3FFFFF 4263 #define DPORT_APP_OUT_VECBASE_REG_S 0 4264 4265 #define DPORT_DATE_REG (DR_REG_DPORT_BASE + 0xFFC) 4266 /* DPORT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605190 ; */ 4267 /*description: */ 4268 #define DPORT_DATE 0x0FFFFFFF 4269 #define DPORT_DATE_M ((DPORT_DATE_V)<<(DPORT_DATE_S)) 4270 #define DPORT_DATE_V 0xFFFFFFF 4271 #define DPORT_DATE_S 0 4272 #define DPORT_DPORT_DATE_VERSION 0x1605190 4273 4274 /* Flash MMU table for PRO CPU */ 4275 #define DPORT_PRO_FLASH_MMU_TABLE ((volatile uint32_t*) 0x3FF10000) 4276 4277 /* Flash MMU table for APP CPU */ 4278 #define DPORT_APP_FLASH_MMU_TABLE ((volatile uint32_t*) 0x3FF12000) 4279 4280 #define DPORT_FLASH_MMU_TABLE_SIZE 0x100 4281 4282 #define DPORT_FLASH_MMU_TABLE_INVALID_VAL 0x100 4283 4284 #define DPORT_MMU_ADDRESS_MASK 0xff 4285 4286 #define TRACEMEM_MUX_PROBLK0_APPBLK1 0 4287 #define TRACEMEM_MUX_BLK0_ONLY 1 4288 #define TRACEMEM_MUX_BLK1_ONLY 2 4289 #define TRACEMEM_MUX_PROBLK1_APPBLK0 3 4290 4291 #endif /*_SOC_DPORT_REG_H_ */ 4292
