1 // Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_SENSITIVE_REG_H_ 15 #define _SOC_SENSITIVE_REG_H_ 16 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 #include "soc.h" 22 #define DPORT_PMS_SDIO_0_REG (DR_REG_SENSITIVE_BASE + 0x000) 23 /* DPORT_PMS_SDIO_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 24 /*description: */ 25 #define DPORT_PMS_SDIO_LOCK (BIT(0)) 26 #define DPORT_PMS_SDIO_LOCK_M (BIT(0)) 27 #define DPORT_PMS_SDIO_LOCK_V 0x1 28 #define DPORT_PMS_SDIO_LOCK_S 0 29 30 #define DPORT_PMS_SDIO_1_REG (DR_REG_SENSITIVE_BASE + 0x004) 31 /* DPORT_PMS_SDIO_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 32 /*description: */ 33 #define DPORT_PMS_SDIO_DISABLE (BIT(0)) 34 #define DPORT_PMS_SDIO_DISABLE_M (BIT(0)) 35 #define DPORT_PMS_SDIO_DISABLE_V 0x1 36 #define DPORT_PMS_SDIO_DISABLE_S 0 37 38 #define DPORT_PMS_MAC_DUMP_0_REG (DR_REG_SENSITIVE_BASE + 0x008) 39 /* DPORT_PMS_MAC_DUMP_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 40 /*description: */ 41 #define DPORT_PMS_MAC_DUMP_LOCK (BIT(0)) 42 #define DPORT_PMS_MAC_DUMP_LOCK_M (BIT(0)) 43 #define DPORT_PMS_MAC_DUMP_LOCK_V 0x1 44 #define DPORT_PMS_MAC_DUMP_LOCK_S 0 45 46 #define DPORT_PMS_MAC_DUMP_1_REG (DR_REG_SENSITIVE_BASE + 0x00C) 47 /* DPORT_PMS_MAC_DUMP_CONNECT : R/W ;bitpos:[11:0] ;default: 12'b000011100100 ; */ 48 /*description: */ 49 #define DPORT_PMS_MAC_DUMP_CONNECT 0x00000FFF 50 #define DPORT_PMS_MAC_DUMP_CONNECT_M ((DPORT_PMS_MAC_DUMP_CONNECT_V)<<(DPORT_PMS_MAC_DUMP_CONNECT_S)) 51 #define DPORT_PMS_MAC_DUMP_CONNECT_V 0xFFF 52 #define DPORT_PMS_MAC_DUMP_CONNECT_S 0 53 54 #define DPORT_PMS_PRO_IRAM0_0_REG (DR_REG_SENSITIVE_BASE + 0x010) 55 /* DPORT_PMS_PRO_IRAM0_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 56 /*description: */ 57 #define DPORT_PMS_PRO_IRAM0_LOCK (BIT(0)) 58 #define DPORT_PMS_PRO_IRAM0_LOCK_M (BIT(0)) 59 #define DPORT_PMS_PRO_IRAM0_LOCK_V 0x1 60 #define DPORT_PMS_PRO_IRAM0_LOCK_S 0 61 62 #define DPORT_PMS_PRO_IRAM0_1_REG (DR_REG_SENSITIVE_BASE + 0x014) 63 /* DPORT_PMS_PRO_IRAM0_SRAM_3_W : R/W ;bitpos:[11] ;default: 1'b1 ; */ 64 /*description: */ 65 #define DPORT_PMS_PRO_IRAM0_SRAM_3_W (BIT(11)) 66 #define DPORT_PMS_PRO_IRAM0_SRAM_3_W_M (BIT(11)) 67 #define DPORT_PMS_PRO_IRAM0_SRAM_3_W_V 0x1 68 #define DPORT_PMS_PRO_IRAM0_SRAM_3_W_S 11 69 /* DPORT_PMS_PRO_IRAM0_SRAM_3_R : R/W ;bitpos:[10] ;default: 1'b1 ; */ 70 /*description: */ 71 #define DPORT_PMS_PRO_IRAM0_SRAM_3_R (BIT(10)) 72 #define DPORT_PMS_PRO_IRAM0_SRAM_3_R_M (BIT(10)) 73 #define DPORT_PMS_PRO_IRAM0_SRAM_3_R_V 0x1 74 #define DPORT_PMS_PRO_IRAM0_SRAM_3_R_S 10 75 /* DPORT_PMS_PRO_IRAM0_SRAM_3_F : R/W ;bitpos:[9] ;default: 1'b1 ; */ 76 /*description: */ 77 #define DPORT_PMS_PRO_IRAM0_SRAM_3_F (BIT(9)) 78 #define DPORT_PMS_PRO_IRAM0_SRAM_3_F_M (BIT(9)) 79 #define DPORT_PMS_PRO_IRAM0_SRAM_3_F_V 0x1 80 #define DPORT_PMS_PRO_IRAM0_SRAM_3_F_S 9 81 /* DPORT_PMS_PRO_IRAM0_SRAM_2_W : R/W ;bitpos:[8] ;default: 1'b1 ; */ 82 /*description: */ 83 #define DPORT_PMS_PRO_IRAM0_SRAM_2_W (BIT(8)) 84 #define DPORT_PMS_PRO_IRAM0_SRAM_2_W_M (BIT(8)) 85 #define DPORT_PMS_PRO_IRAM0_SRAM_2_W_V 0x1 86 #define DPORT_PMS_PRO_IRAM0_SRAM_2_W_S 8 87 /* DPORT_PMS_PRO_IRAM0_SRAM_2_R : R/W ;bitpos:[7] ;default: 1'b1 ; */ 88 /*description: */ 89 #define DPORT_PMS_PRO_IRAM0_SRAM_2_R (BIT(7)) 90 #define DPORT_PMS_PRO_IRAM0_SRAM_2_R_M (BIT(7)) 91 #define DPORT_PMS_PRO_IRAM0_SRAM_2_R_V 0x1 92 #define DPORT_PMS_PRO_IRAM0_SRAM_2_R_S 7 93 /* DPORT_PMS_PRO_IRAM0_SRAM_2_F : R/W ;bitpos:[6] ;default: 1'b1 ; */ 94 /*description: */ 95 #define DPORT_PMS_PRO_IRAM0_SRAM_2_F (BIT(6)) 96 #define DPORT_PMS_PRO_IRAM0_SRAM_2_F_M (BIT(6)) 97 #define DPORT_PMS_PRO_IRAM0_SRAM_2_F_V 0x1 98 #define DPORT_PMS_PRO_IRAM0_SRAM_2_F_S 6 99 /* DPORT_PMS_PRO_IRAM0_SRAM_1_W : R/W ;bitpos:[5] ;default: 1'b1 ; */ 100 /*description: */ 101 #define DPORT_PMS_PRO_IRAM0_SRAM_1_W (BIT(5)) 102 #define DPORT_PMS_PRO_IRAM0_SRAM_1_W_M (BIT(5)) 103 #define DPORT_PMS_PRO_IRAM0_SRAM_1_W_V 0x1 104 #define DPORT_PMS_PRO_IRAM0_SRAM_1_W_S 5 105 /* DPORT_PMS_PRO_IRAM0_SRAM_1_R : R/W ;bitpos:[4] ;default: 1'b1 ; */ 106 /*description: */ 107 #define DPORT_PMS_PRO_IRAM0_SRAM_1_R (BIT(4)) 108 #define DPORT_PMS_PRO_IRAM0_SRAM_1_R_M (BIT(4)) 109 #define DPORT_PMS_PRO_IRAM0_SRAM_1_R_V 0x1 110 #define DPORT_PMS_PRO_IRAM0_SRAM_1_R_S 4 111 /* DPORT_PMS_PRO_IRAM0_SRAM_1_F : R/W ;bitpos:[3] ;default: 1'b1 ; */ 112 /*description: */ 113 #define DPORT_PMS_PRO_IRAM0_SRAM_1_F (BIT(3)) 114 #define DPORT_PMS_PRO_IRAM0_SRAM_1_F_M (BIT(3)) 115 #define DPORT_PMS_PRO_IRAM0_SRAM_1_F_V 0x1 116 #define DPORT_PMS_PRO_IRAM0_SRAM_1_F_S 3 117 /* DPORT_PMS_PRO_IRAM0_SRAM_0_W : R/W ;bitpos:[2] ;default: 1'b1 ; */ 118 /*description: */ 119 #define DPORT_PMS_PRO_IRAM0_SRAM_0_W (BIT(2)) 120 #define DPORT_PMS_PRO_IRAM0_SRAM_0_W_M (BIT(2)) 121 #define DPORT_PMS_PRO_IRAM0_SRAM_0_W_V 0x1 122 #define DPORT_PMS_PRO_IRAM0_SRAM_0_W_S 2 123 /* DPORT_PMS_PRO_IRAM0_SRAM_0_R : R/W ;bitpos:[1] ;default: 1'b1 ; */ 124 /*description: */ 125 #define DPORT_PMS_PRO_IRAM0_SRAM_0_R (BIT(1)) 126 #define DPORT_PMS_PRO_IRAM0_SRAM_0_R_M (BIT(1)) 127 #define DPORT_PMS_PRO_IRAM0_SRAM_0_R_V 0x1 128 #define DPORT_PMS_PRO_IRAM0_SRAM_0_R_S 1 129 /* DPORT_PMS_PRO_IRAM0_SRAM_0_F : R/W ;bitpos:[0] ;default: 1'b1 ; */ 130 /*description: */ 131 #define DPORT_PMS_PRO_IRAM0_SRAM_0_F (BIT(0)) 132 #define DPORT_PMS_PRO_IRAM0_SRAM_0_F_M (BIT(0)) 133 #define DPORT_PMS_PRO_IRAM0_SRAM_0_F_V 0x1 134 #define DPORT_PMS_PRO_IRAM0_SRAM_0_F_S 0 135 136 #define DPORT_PMS_PRO_IRAM0_2_REG (DR_REG_SENSITIVE_BASE + 0x018) 137 /* DPORT_PMS_PRO_IRAM0_SRAM_4_H_W : R/W ;bitpos:[22] ;default: 1'b1 ; */ 138 /*description: */ 139 #define DPORT_PMS_PRO_IRAM0_SRAM_4_H_W (BIT(22)) 140 #define DPORT_PMS_PRO_IRAM0_SRAM_4_H_W_M (BIT(22)) 141 #define DPORT_PMS_PRO_IRAM0_SRAM_4_H_W_V 0x1 142 #define DPORT_PMS_PRO_IRAM0_SRAM_4_H_W_S 22 143 /* DPORT_PMS_PRO_IRAM0_SRAM_4_H_R : R/W ;bitpos:[21] ;default: 1'b1 ; */ 144 /*description: */ 145 #define DPORT_PMS_PRO_IRAM0_SRAM_4_H_R (BIT(21)) 146 #define DPORT_PMS_PRO_IRAM0_SRAM_4_H_R_M (BIT(21)) 147 #define DPORT_PMS_PRO_IRAM0_SRAM_4_H_R_V 0x1 148 #define DPORT_PMS_PRO_IRAM0_SRAM_4_H_R_S 21 149 /* DPORT_PMS_PRO_IRAM0_SRAM_4_H_F : R/W ;bitpos:[20] ;default: 1'b1 ; */ 150 /*description: */ 151 #define DPORT_PMS_PRO_IRAM0_SRAM_4_H_F (BIT(20)) 152 #define DPORT_PMS_PRO_IRAM0_SRAM_4_H_F_M (BIT(20)) 153 #define DPORT_PMS_PRO_IRAM0_SRAM_4_H_F_V 0x1 154 #define DPORT_PMS_PRO_IRAM0_SRAM_4_H_F_S 20 155 /* DPORT_PMS_PRO_IRAM0_SRAM_4_L_W : R/W ;bitpos:[19] ;default: 1'b1 ; */ 156 /*description: */ 157 #define DPORT_PMS_PRO_IRAM0_SRAM_4_L_W (BIT(19)) 158 #define DPORT_PMS_PRO_IRAM0_SRAM_4_L_W_M (BIT(19)) 159 #define DPORT_PMS_PRO_IRAM0_SRAM_4_L_W_V 0x1 160 #define DPORT_PMS_PRO_IRAM0_SRAM_4_L_W_S 19 161 /* DPORT_PMS_PRO_IRAM0_SRAM_4_L_R : R/W ;bitpos:[18] ;default: 1'b1 ; */ 162 /*description: */ 163 #define DPORT_PMS_PRO_IRAM0_SRAM_4_L_R (BIT(18)) 164 #define DPORT_PMS_PRO_IRAM0_SRAM_4_L_R_M (BIT(18)) 165 #define DPORT_PMS_PRO_IRAM0_SRAM_4_L_R_V 0x1 166 #define DPORT_PMS_PRO_IRAM0_SRAM_4_L_R_S 18 167 /* DPORT_PMS_PRO_IRAM0_SRAM_4_L_F : R/W ;bitpos:[17] ;default: 1'b1 ; */ 168 /*description: */ 169 #define DPORT_PMS_PRO_IRAM0_SRAM_4_L_F (BIT(17)) 170 #define DPORT_PMS_PRO_IRAM0_SRAM_4_L_F_M (BIT(17)) 171 #define DPORT_PMS_PRO_IRAM0_SRAM_4_L_F_V 0x1 172 #define DPORT_PMS_PRO_IRAM0_SRAM_4_L_F_S 17 173 /* DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR : R/W ;bitpos:[16:0] ;default: 17'b0 ; */ 174 /*description: */ 175 #define DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR 0x0001FFFF 176 #define DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_M ((DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_V)<<(DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_S)) 177 #define DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_V 0x1FFFF 178 #define DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_S 0 179 180 #define DPORT_PMS_PRO_IRAM0_3_REG (DR_REG_SENSITIVE_BASE + 0x01C) 181 /* DPORT_PMS_PRO_IRAM0_RTCFAST_H_W : R/W ;bitpos:[16] ;default: 1'b1 ; */ 182 /*description: */ 183 #define DPORT_PMS_PRO_IRAM0_RTCFAST_H_W (BIT(16)) 184 #define DPORT_PMS_PRO_IRAM0_RTCFAST_H_W_M (BIT(16)) 185 #define DPORT_PMS_PRO_IRAM0_RTCFAST_H_W_V 0x1 186 #define DPORT_PMS_PRO_IRAM0_RTCFAST_H_W_S 16 187 /* DPORT_PMS_PRO_IRAM0_RTCFAST_H_R : R/W ;bitpos:[15] ;default: 1'b1 ; */ 188 /*description: */ 189 #define DPORT_PMS_PRO_IRAM0_RTCFAST_H_R (BIT(15)) 190 #define DPORT_PMS_PRO_IRAM0_RTCFAST_H_R_M (BIT(15)) 191 #define DPORT_PMS_PRO_IRAM0_RTCFAST_H_R_V 0x1 192 #define DPORT_PMS_PRO_IRAM0_RTCFAST_H_R_S 15 193 /* DPORT_PMS_PRO_IRAM0_RTCFAST_H_F : R/W ;bitpos:[14] ;default: 1'b1 ; */ 194 /*description: */ 195 #define DPORT_PMS_PRO_IRAM0_RTCFAST_H_F (BIT(14)) 196 #define DPORT_PMS_PRO_IRAM0_RTCFAST_H_F_M (BIT(14)) 197 #define DPORT_PMS_PRO_IRAM0_RTCFAST_H_F_V 0x1 198 #define DPORT_PMS_PRO_IRAM0_RTCFAST_H_F_S 14 199 /* DPORT_PMS_PRO_IRAM0_RTCFAST_L_W : R/W ;bitpos:[13] ;default: 1'b1 ; */ 200 /*description: */ 201 #define DPORT_PMS_PRO_IRAM0_RTCFAST_L_W (BIT(13)) 202 #define DPORT_PMS_PRO_IRAM0_RTCFAST_L_W_M (BIT(13)) 203 #define DPORT_PMS_PRO_IRAM0_RTCFAST_L_W_V 0x1 204 #define DPORT_PMS_PRO_IRAM0_RTCFAST_L_W_S 13 205 /* DPORT_PMS_PRO_IRAM0_RTCFAST_L_R : R/W ;bitpos:[12] ;default: 1'b1 ; */ 206 /*description: */ 207 #define DPORT_PMS_PRO_IRAM0_RTCFAST_L_R (BIT(12)) 208 #define DPORT_PMS_PRO_IRAM0_RTCFAST_L_R_M (BIT(12)) 209 #define DPORT_PMS_PRO_IRAM0_RTCFAST_L_R_V 0x1 210 #define DPORT_PMS_PRO_IRAM0_RTCFAST_L_R_S 12 211 /* DPORT_PMS_PRO_IRAM0_RTCFAST_L_F : R/W ;bitpos:[11] ;default: 1'b1 ; */ 212 /*description: */ 213 #define DPORT_PMS_PRO_IRAM0_RTCFAST_L_F (BIT(11)) 214 #define DPORT_PMS_PRO_IRAM0_RTCFAST_L_F_M (BIT(11)) 215 #define DPORT_PMS_PRO_IRAM0_RTCFAST_L_F_V 0x1 216 #define DPORT_PMS_PRO_IRAM0_RTCFAST_L_F_S 11 217 /* DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR : R/W ;bitpos:[10:0] ;default: 11'b0 ; */ 218 /*description: */ 219 #define DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR 0x000007FF 220 #define DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_M ((DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_V)<<(DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_S)) 221 #define DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_V 0x7FF 222 #define DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_S 0 223 224 #define DPORT_PMS_PRO_IRAM0_4_REG (DR_REG_SENSITIVE_BASE + 0x020) 225 /* DPORT_PMS_PRO_IRAM0_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */ 226 /*description: */ 227 #define DPORT_PMS_PRO_IRAM0_ILG_INTR (BIT(2)) 228 #define DPORT_PMS_PRO_IRAM0_ILG_INTR_M (BIT(2)) 229 #define DPORT_PMS_PRO_IRAM0_ILG_INTR_V 0x1 230 #define DPORT_PMS_PRO_IRAM0_ILG_INTR_S 2 231 /* DPORT_PMS_PRO_IRAM0_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 232 /*description: */ 233 #define DPORT_PMS_PRO_IRAM0_ILG_EN (BIT(1)) 234 #define DPORT_PMS_PRO_IRAM0_ILG_EN_M (BIT(1)) 235 #define DPORT_PMS_PRO_IRAM0_ILG_EN_V 0x1 236 #define DPORT_PMS_PRO_IRAM0_ILG_EN_S 1 237 /* DPORT_PMS_PRO_IRAM0_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ 238 /*description: */ 239 #define DPORT_PMS_PRO_IRAM0_ILG_CLR (BIT(0)) 240 #define DPORT_PMS_PRO_IRAM0_ILG_CLR_M (BIT(0)) 241 #define DPORT_PMS_PRO_IRAM0_ILG_CLR_V 0x1 242 #define DPORT_PMS_PRO_IRAM0_ILG_CLR_S 0 243 244 #define DPORT_PMS_PRO_IRAM0_5_REG (DR_REG_SENSITIVE_BASE + 0x024) 245 /* DPORT_PMS_PRO_IRAM0_ILG_ST : RO ;bitpos:[21:0] ;default: 22'b0 ; */ 246 /*description: */ 247 #define DPORT_PMS_PRO_IRAM0_ILG_ST 0x003FFFFF 248 #define DPORT_PMS_PRO_IRAM0_ILG_ST_M ((DPORT_PMS_PRO_IRAM0_ILG_ST_V)<<(DPORT_PMS_PRO_IRAM0_ILG_ST_S)) 249 #define DPORT_PMS_PRO_IRAM0_ILG_ST_V 0x3FFFFF 250 #define DPORT_PMS_PRO_IRAM0_ILG_ST_S 0 251 252 #define DPORT_PMS_PRO_DRAM0_0_REG (DR_REG_SENSITIVE_BASE + 0x028) 253 /* DPORT_PMS_PRO_DRAM0_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 254 /*description: */ 255 #define DPORT_PMS_PRO_DRAM0_LOCK (BIT(0)) 256 #define DPORT_PMS_PRO_DRAM0_LOCK_M (BIT(0)) 257 #define DPORT_PMS_PRO_DRAM0_LOCK_V 0x1 258 #define DPORT_PMS_PRO_DRAM0_LOCK_S 0 259 260 #define DPORT_PMS_PRO_DRAM0_1_REG (DR_REG_SENSITIVE_BASE + 0x02C) 261 /* DPORT_PMS_PRO_DRAM0_SRAM_4_H_W : R/W ;bitpos:[28] ;default: 1'b1 ; */ 262 /*description: */ 263 #define DPORT_PMS_PRO_DRAM0_SRAM_4_H_W (BIT(28)) 264 #define DPORT_PMS_PRO_DRAM0_SRAM_4_H_W_M (BIT(28)) 265 #define DPORT_PMS_PRO_DRAM0_SRAM_4_H_W_V 0x1 266 #define DPORT_PMS_PRO_DRAM0_SRAM_4_H_W_S 28 267 /* DPORT_PMS_PRO_DRAM0_SRAM_4_H_R : R/W ;bitpos:[27] ;default: 1'b1 ; */ 268 /*description: */ 269 #define DPORT_PMS_PRO_DRAM0_SRAM_4_H_R (BIT(27)) 270 #define DPORT_PMS_PRO_DRAM0_SRAM_4_H_R_M (BIT(27)) 271 #define DPORT_PMS_PRO_DRAM0_SRAM_4_H_R_V 0x1 272 #define DPORT_PMS_PRO_DRAM0_SRAM_4_H_R_S 27 273 /* DPORT_PMS_PRO_DRAM0_SRAM_4_L_W : R/W ;bitpos:[26] ;default: 1'b1 ; */ 274 /*description: */ 275 #define DPORT_PMS_PRO_DRAM0_SRAM_4_L_W (BIT(26)) 276 #define DPORT_PMS_PRO_DRAM0_SRAM_4_L_W_M (BIT(26)) 277 #define DPORT_PMS_PRO_DRAM0_SRAM_4_L_W_V 0x1 278 #define DPORT_PMS_PRO_DRAM0_SRAM_4_L_W_S 26 279 /* DPORT_PMS_PRO_DRAM0_SRAM_4_L_R : R/W ;bitpos:[25] ;default: 1'b1 ; */ 280 /*description: */ 281 #define DPORT_PMS_PRO_DRAM0_SRAM_4_L_R (BIT(25)) 282 #define DPORT_PMS_PRO_DRAM0_SRAM_4_L_R_M (BIT(25)) 283 #define DPORT_PMS_PRO_DRAM0_SRAM_4_L_R_V 0x1 284 #define DPORT_PMS_PRO_DRAM0_SRAM_4_L_R_S 25 285 /* DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR : R/W ;bitpos:[24:8] ;default: 17'b0 ; */ 286 /*description: */ 287 #define DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR 0x0001FFFF 288 #define DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_M ((DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_V)<<(DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_S)) 289 #define DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_V 0x1FFFF 290 #define DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_S 8 291 /* DPORT_PMS_PRO_DRAM0_SRAM_3_W : R/W ;bitpos:[7] ;default: 1'b1 ; */ 292 /*description: */ 293 #define DPORT_PMS_PRO_DRAM0_SRAM_3_W (BIT(7)) 294 #define DPORT_PMS_PRO_DRAM0_SRAM_3_W_M (BIT(7)) 295 #define DPORT_PMS_PRO_DRAM0_SRAM_3_W_V 0x1 296 #define DPORT_PMS_PRO_DRAM0_SRAM_3_W_S 7 297 /* DPORT_PMS_PRO_DRAM0_SRAM_3_R : R/W ;bitpos:[6] ;default: 1'b1 ; */ 298 /*description: */ 299 #define DPORT_PMS_PRO_DRAM0_SRAM_3_R (BIT(6)) 300 #define DPORT_PMS_PRO_DRAM0_SRAM_3_R_M (BIT(6)) 301 #define DPORT_PMS_PRO_DRAM0_SRAM_3_R_V 0x1 302 #define DPORT_PMS_PRO_DRAM0_SRAM_3_R_S 6 303 /* DPORT_PMS_PRO_DRAM0_SRAM_2_W : R/W ;bitpos:[5] ;default: 1'b1 ; */ 304 /*description: */ 305 #define DPORT_PMS_PRO_DRAM0_SRAM_2_W (BIT(5)) 306 #define DPORT_PMS_PRO_DRAM0_SRAM_2_W_M (BIT(5)) 307 #define DPORT_PMS_PRO_DRAM0_SRAM_2_W_V 0x1 308 #define DPORT_PMS_PRO_DRAM0_SRAM_2_W_S 5 309 /* DPORT_PMS_PRO_DRAM0_SRAM_2_R : R/W ;bitpos:[4] ;default: 1'b1 ; */ 310 /*description: */ 311 #define DPORT_PMS_PRO_DRAM0_SRAM_2_R (BIT(4)) 312 #define DPORT_PMS_PRO_DRAM0_SRAM_2_R_M (BIT(4)) 313 #define DPORT_PMS_PRO_DRAM0_SRAM_2_R_V 0x1 314 #define DPORT_PMS_PRO_DRAM0_SRAM_2_R_S 4 315 /* DPORT_PMS_PRO_DRAM0_SRAM_1_W : R/W ;bitpos:[3] ;default: 1'b1 ; */ 316 /*description: */ 317 #define DPORT_PMS_PRO_DRAM0_SRAM_1_W (BIT(3)) 318 #define DPORT_PMS_PRO_DRAM0_SRAM_1_W_M (BIT(3)) 319 #define DPORT_PMS_PRO_DRAM0_SRAM_1_W_V 0x1 320 #define DPORT_PMS_PRO_DRAM0_SRAM_1_W_S 3 321 /* DPORT_PMS_PRO_DRAM0_SRAM_1_R : R/W ;bitpos:[2] ;default: 1'b1 ; */ 322 /*description: */ 323 #define DPORT_PMS_PRO_DRAM0_SRAM_1_R (BIT(2)) 324 #define DPORT_PMS_PRO_DRAM0_SRAM_1_R_M (BIT(2)) 325 #define DPORT_PMS_PRO_DRAM0_SRAM_1_R_V 0x1 326 #define DPORT_PMS_PRO_DRAM0_SRAM_1_R_S 2 327 /* DPORT_PMS_PRO_DRAM0_SRAM_0_W : R/W ;bitpos:[1] ;default: 1'b1 ; */ 328 /*description: */ 329 #define DPORT_PMS_PRO_DRAM0_SRAM_0_W (BIT(1)) 330 #define DPORT_PMS_PRO_DRAM0_SRAM_0_W_M (BIT(1)) 331 #define DPORT_PMS_PRO_DRAM0_SRAM_0_W_V 0x1 332 #define DPORT_PMS_PRO_DRAM0_SRAM_0_W_S 1 333 /* DPORT_PMS_PRO_DRAM0_SRAM_0_R : R/W ;bitpos:[0] ;default: 1'b1 ; */ 334 /*description: */ 335 #define DPORT_PMS_PRO_DRAM0_SRAM_0_R (BIT(0)) 336 #define DPORT_PMS_PRO_DRAM0_SRAM_0_R_M (BIT(0)) 337 #define DPORT_PMS_PRO_DRAM0_SRAM_0_R_V 0x1 338 #define DPORT_PMS_PRO_DRAM0_SRAM_0_R_S 0 339 340 #define DPORT_PMS_PRO_DRAM0_2_REG (DR_REG_SENSITIVE_BASE + 0x030) 341 /* DPORT_PMS_PRO_DRAM0_RTCFAST_H_W : R/W ;bitpos:[14] ;default: 1'b1 ; */ 342 /*description: */ 343 #define DPORT_PMS_PRO_DRAM0_RTCFAST_H_W (BIT(14)) 344 #define DPORT_PMS_PRO_DRAM0_RTCFAST_H_W_M (BIT(14)) 345 #define DPORT_PMS_PRO_DRAM0_RTCFAST_H_W_V 0x1 346 #define DPORT_PMS_PRO_DRAM0_RTCFAST_H_W_S 14 347 /* DPORT_PMS_PRO_DRAM0_RTCFAST_H_R : R/W ;bitpos:[13] ;default: 1'b1 ; */ 348 /*description: */ 349 #define DPORT_PMS_PRO_DRAM0_RTCFAST_H_R (BIT(13)) 350 #define DPORT_PMS_PRO_DRAM0_RTCFAST_H_R_M (BIT(13)) 351 #define DPORT_PMS_PRO_DRAM0_RTCFAST_H_R_V 0x1 352 #define DPORT_PMS_PRO_DRAM0_RTCFAST_H_R_S 13 353 /* DPORT_PMS_PRO_DRAM0_RTCFAST_L_W : R/W ;bitpos:[12] ;default: 1'b1 ; */ 354 /*description: */ 355 #define DPORT_PMS_PRO_DRAM0_RTCFAST_L_W (BIT(12)) 356 #define DPORT_PMS_PRO_DRAM0_RTCFAST_L_W_M (BIT(12)) 357 #define DPORT_PMS_PRO_DRAM0_RTCFAST_L_W_V 0x1 358 #define DPORT_PMS_PRO_DRAM0_RTCFAST_L_W_S 12 359 /* DPORT_PMS_PRO_DRAM0_RTCFAST_L_R : R/W ;bitpos:[11] ;default: 1'b1 ; */ 360 /*description: */ 361 #define DPORT_PMS_PRO_DRAM0_RTCFAST_L_R (BIT(11)) 362 #define DPORT_PMS_PRO_DRAM0_RTCFAST_L_R_M (BIT(11)) 363 #define DPORT_PMS_PRO_DRAM0_RTCFAST_L_R_V 0x1 364 #define DPORT_PMS_PRO_DRAM0_RTCFAST_L_R_S 11 365 /* DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR : R/W ;bitpos:[10:0] ;default: 11'b0 ; */ 366 /*description: */ 367 #define DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR 0x000007FF 368 #define DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_M ((DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_V)<<(DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_S)) 369 #define DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_V 0x7FF 370 #define DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_S 0 371 372 #define DPORT_PMS_PRO_DRAM0_3_REG (DR_REG_SENSITIVE_BASE + 0x034) 373 /* DPORT_PMS_PRO_DRAM0_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */ 374 /*description: */ 375 #define DPORT_PMS_PRO_DRAM0_ILG_INTR (BIT(2)) 376 #define DPORT_PMS_PRO_DRAM0_ILG_INTR_M (BIT(2)) 377 #define DPORT_PMS_PRO_DRAM0_ILG_INTR_V 0x1 378 #define DPORT_PMS_PRO_DRAM0_ILG_INTR_S 2 379 /* DPORT_PMS_PRO_DRAM0_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 380 /*description: */ 381 #define DPORT_PMS_PRO_DRAM0_ILG_EN (BIT(1)) 382 #define DPORT_PMS_PRO_DRAM0_ILG_EN_M (BIT(1)) 383 #define DPORT_PMS_PRO_DRAM0_ILG_EN_V 0x1 384 #define DPORT_PMS_PRO_DRAM0_ILG_EN_S 1 385 /* DPORT_PMS_PRO_DRAM0_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ 386 /*description: */ 387 #define DPORT_PMS_PRO_DRAM0_ILG_CLR (BIT(0)) 388 #define DPORT_PMS_PRO_DRAM0_ILG_CLR_M (BIT(0)) 389 #define DPORT_PMS_PRO_DRAM0_ILG_CLR_V 0x1 390 #define DPORT_PMS_PRO_DRAM0_ILG_CLR_S 0 391 392 #define DPORT_PMS_PRO_DRAM0_4_REG (DR_REG_SENSITIVE_BASE + 0x038) 393 /* DPORT_PMS_PRO_DRAM0_ILG_ST : RO ;bitpos:[25:0] ;default: 26'b0 ; */ 394 /*description: */ 395 #define DPORT_PMS_PRO_DRAM0_ILG_ST 0x03FFFFFF 396 #define DPORT_PMS_PRO_DRAM0_ILG_ST_M ((DPORT_PMS_PRO_DRAM0_ILG_ST_V)<<(DPORT_PMS_PRO_DRAM0_ILG_ST_S)) 397 #define DPORT_PMS_PRO_DRAM0_ILG_ST_V 0x3FFFFFF 398 #define DPORT_PMS_PRO_DRAM0_ILG_ST_S 0 399 400 #define DPORT_PMS_PRO_DPORT_0_REG (DR_REG_SENSITIVE_BASE + 0x03C) 401 /* DPORT_PMS_PRO_DPORT_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 402 /*description: */ 403 #define DPORT_PMS_PRO_DPORT_LOCK (BIT(0)) 404 #define DPORT_PMS_PRO_DPORT_LOCK_M (BIT(0)) 405 #define DPORT_PMS_PRO_DPORT_LOCK_V 0x1 406 #define DPORT_PMS_PRO_DPORT_LOCK_S 0 407 408 #define DPORT_PMS_PRO_DPORT_1_REG (DR_REG_SENSITIVE_BASE + 0x040) 409 /* DPORT_PMS_PRO_DPORT_RESERVE_FIFO_VALID : R/W ;bitpos:[19:16] ;default: 4'b0000 ; */ 410 /*description: */ 411 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_VALID 0x0000000F 412 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_VALID_M ((DPORT_PMS_PRO_DPORT_RESERVE_FIFO_VALID_V)<<(DPORT_PMS_PRO_DPORT_RESERVE_FIFO_VALID_S)) 413 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_VALID_V 0xF 414 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_VALID_S 16 415 /* DPORT_PMS_PRO_DPORT_RTCSLOW_H_W : R/W ;bitpos:[15] ;default: 1'b1 ; */ 416 /*description: */ 417 #define DPORT_PMS_PRO_DPORT_RTCSLOW_H_W (BIT(15)) 418 #define DPORT_PMS_PRO_DPORT_RTCSLOW_H_W_M (BIT(15)) 419 #define DPORT_PMS_PRO_DPORT_RTCSLOW_H_W_V 0x1 420 #define DPORT_PMS_PRO_DPORT_RTCSLOW_H_W_S 15 421 /* DPORT_PMS_PRO_DPORT_RTCSLOW_H_R : R/W ;bitpos:[14] ;default: 1'b1 ; */ 422 /*description: */ 423 #define DPORT_PMS_PRO_DPORT_RTCSLOW_H_R (BIT(14)) 424 #define DPORT_PMS_PRO_DPORT_RTCSLOW_H_R_M (BIT(14)) 425 #define DPORT_PMS_PRO_DPORT_RTCSLOW_H_R_V 0x1 426 #define DPORT_PMS_PRO_DPORT_RTCSLOW_H_R_S 14 427 /* DPORT_PMS_PRO_DPORT_RTCSLOW_L_W : R/W ;bitpos:[13] ;default: 1'b1 ; */ 428 /*description: */ 429 #define DPORT_PMS_PRO_DPORT_RTCSLOW_L_W (BIT(13)) 430 #define DPORT_PMS_PRO_DPORT_RTCSLOW_L_W_M (BIT(13)) 431 #define DPORT_PMS_PRO_DPORT_RTCSLOW_L_W_V 0x1 432 #define DPORT_PMS_PRO_DPORT_RTCSLOW_L_W_S 13 433 /* DPORT_PMS_PRO_DPORT_RTCSLOW_L_R : R/W ;bitpos:[12] ;default: 1'b1 ; */ 434 /*description: */ 435 #define DPORT_PMS_PRO_DPORT_RTCSLOW_L_R (BIT(12)) 436 #define DPORT_PMS_PRO_DPORT_RTCSLOW_L_R_M (BIT(12)) 437 #define DPORT_PMS_PRO_DPORT_RTCSLOW_L_R_V 0x1 438 #define DPORT_PMS_PRO_DPORT_RTCSLOW_L_R_S 12 439 /* DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR : R/W ;bitpos:[11:1] ;default: 11'b0 ; */ 440 /*description: */ 441 #define DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR 0x000007FF 442 #define DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_M ((DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_V)<<(DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_S)) 443 #define DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_V 0x7FF 444 #define DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_S 1 445 /* DPORT_PMS_PRO_DPORT_APB_PERIPHERAL_FORBID : R/W ;bitpos:[0] ;default: 1'b0 ; */ 446 /*description: */ 447 #define DPORT_PMS_PRO_DPORT_APB_PERIPHERAL_FORBID (BIT(0)) 448 #define DPORT_PMS_PRO_DPORT_APB_PERIPHERAL_FORBID_M (BIT(0)) 449 #define DPORT_PMS_PRO_DPORT_APB_PERIPHERAL_FORBID_V 0x1 450 #define DPORT_PMS_PRO_DPORT_APB_PERIPHERAL_FORBID_S 0 451 452 #define DPORT_PMS_PRO_DPORT_2_REG (DR_REG_SENSITIVE_BASE + 0x044) 453 /* DPORT_PMS_PRO_DPORT_RESERVE_FIFO_0 : R/W ;bitpos:[17:0] ;default: 18'h0 ; */ 454 /*description: */ 455 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_0 0x0003FFFF 456 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_0_M ((DPORT_PMS_PRO_DPORT_RESERVE_FIFO_0_V)<<(DPORT_PMS_PRO_DPORT_RESERVE_FIFO_0_S)) 457 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_0_V 0x3FFFF 458 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_0_S 0 459 460 #define DPORT_PMS_PRO_DPORT_3_REG (DR_REG_SENSITIVE_BASE + 0x048) 461 /* DPORT_PMS_PRO_DPORT_RESERVE_FIFO_1 : R/W ;bitpos:[17:0] ;default: 18'h0 ; */ 462 /*description: */ 463 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_1 0x0003FFFF 464 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_1_M ((DPORT_PMS_PRO_DPORT_RESERVE_FIFO_1_V)<<(DPORT_PMS_PRO_DPORT_RESERVE_FIFO_1_S)) 465 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_1_V 0x3FFFF 466 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_1_S 0 467 468 #define DPORT_PMS_PRO_DPORT_4_REG (DR_REG_SENSITIVE_BASE + 0x04C) 469 /* DPORT_PMS_PRO_DPORT_RESERVE_FIFO_2 : R/W ;bitpos:[17:0] ;default: 18'h0 ; */ 470 /*description: */ 471 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_2 0x0003FFFF 472 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_2_M ((DPORT_PMS_PRO_DPORT_RESERVE_FIFO_2_V)<<(DPORT_PMS_PRO_DPORT_RESERVE_FIFO_2_S)) 473 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_2_V 0x3FFFF 474 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_2_S 0 475 476 #define DPORT_PMS_PRO_DPORT_5_REG (DR_REG_SENSITIVE_BASE + 0x050) 477 /* DPORT_PMS_PRO_DPORT_RESERVE_FIFO_3 : R/W ;bitpos:[17:0] ;default: 18'h0 ; */ 478 /*description: */ 479 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_3 0x0003FFFF 480 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_3_M ((DPORT_PMS_PRO_DPORT_RESERVE_FIFO_3_V)<<(DPORT_PMS_PRO_DPORT_RESERVE_FIFO_3_S)) 481 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_3_V 0x3FFFF 482 #define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_3_S 0 483 484 #define DPORT_PMS_PRO_DPORT_6_REG (DR_REG_SENSITIVE_BASE + 0x054) 485 /* DPORT_PMS_PRO_DPORT_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */ 486 /*description: */ 487 #define DPORT_PMS_PRO_DPORT_ILG_INTR (BIT(2)) 488 #define DPORT_PMS_PRO_DPORT_ILG_INTR_M (BIT(2)) 489 #define DPORT_PMS_PRO_DPORT_ILG_INTR_V 0x1 490 #define DPORT_PMS_PRO_DPORT_ILG_INTR_S 2 491 /* DPORT_PMS_PRO_DPORT_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 492 /*description: */ 493 #define DPORT_PMS_PRO_DPORT_ILG_EN (BIT(1)) 494 #define DPORT_PMS_PRO_DPORT_ILG_EN_M (BIT(1)) 495 #define DPORT_PMS_PRO_DPORT_ILG_EN_V 0x1 496 #define DPORT_PMS_PRO_DPORT_ILG_EN_S 1 497 /* DPORT_PMS_PRO_DPORT_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ 498 /*description: */ 499 #define DPORT_PMS_PRO_DPORT_ILG_CLR (BIT(0)) 500 #define DPORT_PMS_PRO_DPORT_ILG_CLR_M (BIT(0)) 501 #define DPORT_PMS_PRO_DPORT_ILG_CLR_V 0x1 502 #define DPORT_PMS_PRO_DPORT_ILG_CLR_S 0 503 504 #define DPORT_PMS_PRO_DPORT_7_REG (DR_REG_SENSITIVE_BASE + 0x058) 505 /* DPORT_PMS_PRO_DPORT_ILG_ST : RO ;bitpos:[25:0] ;default: 26'b0 ; */ 506 /*description: */ 507 #define DPORT_PMS_PRO_DPORT_ILG_ST 0x03FFFFFF 508 #define DPORT_PMS_PRO_DPORT_ILG_ST_M ((DPORT_PMS_PRO_DPORT_ILG_ST_V)<<(DPORT_PMS_PRO_DPORT_ILG_ST_S)) 509 #define DPORT_PMS_PRO_DPORT_ILG_ST_V 0x3FFFFFF 510 #define DPORT_PMS_PRO_DPORT_ILG_ST_S 0 511 512 #define DPORT_PMS_PRO_AHB_0_REG (DR_REG_SENSITIVE_BASE + 0x05C) 513 /* DPORT_PMS_PRO_AHB_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 514 /*description: */ 515 #define DPORT_PMS_PRO_AHB_LOCK (BIT(0)) 516 #define DPORT_PMS_PRO_AHB_LOCK_M (BIT(0)) 517 #define DPORT_PMS_PRO_AHB_LOCK_V 0x1 518 #define DPORT_PMS_PRO_AHB_LOCK_S 0 519 520 #define DPORT_PMS_PRO_AHB_1_REG (DR_REG_SENSITIVE_BASE + 0x060) 521 /* DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W : R/W ;bitpos:[16] ;default: 1'b1 ; */ 522 /*description: */ 523 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W (BIT(16)) 524 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W_M (BIT(16)) 525 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W_V 0x1 526 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W_S 16 527 /* DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R : R/W ;bitpos:[15] ;default: 1'b1 ; */ 528 /*description: */ 529 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R (BIT(15)) 530 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R_M (BIT(15)) 531 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R_V 0x1 532 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R_S 15 533 /* DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F : R/W ;bitpos:[14] ;default: 1'b1 ; */ 534 /*description: */ 535 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F (BIT(14)) 536 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F_M (BIT(14)) 537 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F_V 0x1 538 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F_S 14 539 /* DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W : R/W ;bitpos:[13] ;default: 1'b1 ; */ 540 /*description: */ 541 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W (BIT(13)) 542 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W_M (BIT(13)) 543 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W_V 0x1 544 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W_S 13 545 /* DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R : R/W ;bitpos:[12] ;default: 1'b1 ; */ 546 /*description: */ 547 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R (BIT(12)) 548 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R_M (BIT(12)) 549 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R_V 0x1 550 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R_S 12 551 /* DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F : R/W ;bitpos:[11] ;default: 1'b1 ; */ 552 /*description: */ 553 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F (BIT(11)) 554 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F_M (BIT(11)) 555 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F_V 0x1 556 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F_S 11 557 /* DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR : R/W ;bitpos:[10:0] ;default: 11'b0 ; */ 558 /*description: */ 559 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR 0x000007FF 560 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_M ((DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_V)<<(DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_S)) 561 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_V 0x7FF 562 #define DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_S 0 563 564 #define DPORT_PMS_PRO_AHB_2_REG (DR_REG_SENSITIVE_BASE + 0x064) 565 /* DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W : R/W ;bitpos:[16] ;default: 1'b1 ; */ 566 /*description: */ 567 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W (BIT(16)) 568 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W_M (BIT(16)) 569 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W_V 0x1 570 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W_S 16 571 /* DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R : R/W ;bitpos:[15] ;default: 1'b1 ; */ 572 /*description: */ 573 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R (BIT(15)) 574 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R_M (BIT(15)) 575 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R_V 0x1 576 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R_S 15 577 /* DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F : R/W ;bitpos:[14] ;default: 1'b1 ; */ 578 /*description: */ 579 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F (BIT(14)) 580 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F_M (BIT(14)) 581 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F_V 0x1 582 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F_S 14 583 /* DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W : R/W ;bitpos:[13] ;default: 1'b1 ; */ 584 /*description: */ 585 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W (BIT(13)) 586 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W_M (BIT(13)) 587 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W_V 0x1 588 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W_S 13 589 /* DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R : R/W ;bitpos:[12] ;default: 1'b1 ; */ 590 /*description: */ 591 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R (BIT(12)) 592 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R_M (BIT(12)) 593 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R_V 0x1 594 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R_S 12 595 /* DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F : R/W ;bitpos:[11] ;default: 1'b1 ; */ 596 /*description: */ 597 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F (BIT(11)) 598 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F_M (BIT(11)) 599 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F_V 0x1 600 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F_S 11 601 /* DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR : R/W ;bitpos:[10:0] ;default: 11'b0 ; */ 602 /*description: */ 603 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR 0x000007FF 604 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_M ((DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_V)<<(DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_S)) 605 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_V 0x7FF 606 #define DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_S 0 607 608 #define DPORT_PMS_PRO_AHB_3_REG (DR_REG_SENSITIVE_BASE + 0x068) 609 /* DPORT_PMS_PRO_AHB_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */ 610 /*description: */ 611 #define DPORT_PMS_PRO_AHB_ILG_INTR (BIT(2)) 612 #define DPORT_PMS_PRO_AHB_ILG_INTR_M (BIT(2)) 613 #define DPORT_PMS_PRO_AHB_ILG_INTR_V 0x1 614 #define DPORT_PMS_PRO_AHB_ILG_INTR_S 2 615 /* DPORT_PMS_PRO_AHB_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 616 /*description: */ 617 #define DPORT_PMS_PRO_AHB_ILG_EN (BIT(1)) 618 #define DPORT_PMS_PRO_AHB_ILG_EN_M (BIT(1)) 619 #define DPORT_PMS_PRO_AHB_ILG_EN_V 0x1 620 #define DPORT_PMS_PRO_AHB_ILG_EN_S 1 621 /* DPORT_PMS_PRO_AHB_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ 622 /*description: */ 623 #define DPORT_PMS_PRO_AHB_ILG_CLR (BIT(0)) 624 #define DPORT_PMS_PRO_AHB_ILG_CLR_M (BIT(0)) 625 #define DPORT_PMS_PRO_AHB_ILG_CLR_V 0x1 626 #define DPORT_PMS_PRO_AHB_ILG_CLR_S 0 627 628 #define DPORT_PMS_PRO_AHB_4_REG (DR_REG_SENSITIVE_BASE + 0x06C) 629 /* DPORT_PMS_PRO_AHB_ILG_ST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 630 /*description: */ 631 #define DPORT_PMS_PRO_AHB_ILG_ST 0xFFFFFFFF 632 #define DPORT_PMS_PRO_AHB_ILG_ST_M ((DPORT_PMS_PRO_AHB_ILG_ST_V)<<(DPORT_PMS_PRO_AHB_ILG_ST_S)) 633 #define DPORT_PMS_PRO_AHB_ILG_ST_V 0xFFFFFFFF 634 #define DPORT_PMS_PRO_AHB_ILG_ST_S 0 635 636 #define DPORT_PMS_PRO_TRACE_0_REG (DR_REG_SENSITIVE_BASE + 0x070) 637 /* DPORT_PMS_PRO_TRACE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 638 /*description: */ 639 #define DPORT_PMS_PRO_TRACE_LOCK (BIT(0)) 640 #define DPORT_PMS_PRO_TRACE_LOCK_M (BIT(0)) 641 #define DPORT_PMS_PRO_TRACE_LOCK_V 0x1 642 #define DPORT_PMS_PRO_TRACE_LOCK_S 0 643 644 #define DPORT_PMS_PRO_TRACE_1_REG (DR_REG_SENSITIVE_BASE + 0x074) 645 /* DPORT_PMS_PRO_TRACE_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 646 /*description: */ 647 #define DPORT_PMS_PRO_TRACE_DISABLE (BIT(0)) 648 #define DPORT_PMS_PRO_TRACE_DISABLE_M (BIT(0)) 649 #define DPORT_PMS_PRO_TRACE_DISABLE_V 0x1 650 #define DPORT_PMS_PRO_TRACE_DISABLE_S 0 651 652 #define DPORT_PMS_PRO_CACHE_0_REG (DR_REG_SENSITIVE_BASE + 0x078) 653 /* DPORT_PMS_PRO_CACHE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 654 /*description: */ 655 #define DPORT_PMS_PRO_CACHE_LOCK (BIT(0)) 656 #define DPORT_PMS_PRO_CACHE_LOCK_M (BIT(0)) 657 #define DPORT_PMS_PRO_CACHE_LOCK_V 0x1 658 #define DPORT_PMS_PRO_CACHE_LOCK_S 0 659 660 #define DPORT_PMS_PRO_CACHE_1_REG (DR_REG_SENSITIVE_BASE + 0x07C) 661 /* DPORT_PMS_PRO_CACHE_CONNECT : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ 662 /*description: */ 663 #define DPORT_PMS_PRO_CACHE_CONNECT 0x0000FFFF 664 #define DPORT_PMS_PRO_CACHE_CONNECT_M ((DPORT_PMS_PRO_CACHE_CONNECT_V)<<(DPORT_PMS_PRO_CACHE_CONNECT_S)) 665 #define DPORT_PMS_PRO_CACHE_CONNECT_V 0xFFFF 666 #define DPORT_PMS_PRO_CACHE_CONNECT_S 0 667 668 #define DPORT_PMS_PRO_CACHE_2_REG (DR_REG_SENSITIVE_BASE + 0x080) 669 /* DPORT_PMS_PRO_CACHE_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */ 670 /*description: */ 671 #define DPORT_PMS_PRO_CACHE_ILG_INTR (BIT(2)) 672 #define DPORT_PMS_PRO_CACHE_ILG_INTR_M (BIT(2)) 673 #define DPORT_PMS_PRO_CACHE_ILG_INTR_V 0x1 674 #define DPORT_PMS_PRO_CACHE_ILG_INTR_S 2 675 /* DPORT_PMS_PRO_CACHE_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 676 /*description: */ 677 #define DPORT_PMS_PRO_CACHE_ILG_EN (BIT(1)) 678 #define DPORT_PMS_PRO_CACHE_ILG_EN_M (BIT(1)) 679 #define DPORT_PMS_PRO_CACHE_ILG_EN_V 0x1 680 #define DPORT_PMS_PRO_CACHE_ILG_EN_S 1 681 /* DPORT_PMS_PRO_CACHE_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ 682 /*description: */ 683 #define DPORT_PMS_PRO_CACHE_ILG_CLR (BIT(0)) 684 #define DPORT_PMS_PRO_CACHE_ILG_CLR_M (BIT(0)) 685 #define DPORT_PMS_PRO_CACHE_ILG_CLR_V 0x1 686 #define DPORT_PMS_PRO_CACHE_ILG_CLR_S 0 687 688 #define DPORT_PMS_PRO_CACHE_3_REG (DR_REG_SENSITIVE_BASE + 0x084) 689 /* DPORT_PMS_PRO_CACHE_ILG_ST_I : RO ;bitpos:[16:0] ;default: 17'b0 ; */ 690 /*description: */ 691 #define DPORT_PMS_PRO_CACHE_ILG_ST_I 0x0001FFFF 692 #define DPORT_PMS_PRO_CACHE_ILG_ST_I_M ((DPORT_PMS_PRO_CACHE_ILG_ST_I_V)<<(DPORT_PMS_PRO_CACHE_ILG_ST_I_S)) 693 #define DPORT_PMS_PRO_CACHE_ILG_ST_I_V 0x1FFFF 694 #define DPORT_PMS_PRO_CACHE_ILG_ST_I_S 0 695 696 #define DPORT_PMS_PRO_CACHE_4_REG (DR_REG_SENSITIVE_BASE + 0x088) 697 /* DPORT_PMS_PRO_CACHE_ILG_ST_D : RO ;bitpos:[16:0] ;default: 17'b0 ; */ 698 /*description: */ 699 #define DPORT_PMS_PRO_CACHE_ILG_ST_D 0x0001FFFF 700 #define DPORT_PMS_PRO_CACHE_ILG_ST_D_M ((DPORT_PMS_PRO_CACHE_ILG_ST_D_V)<<(DPORT_PMS_PRO_CACHE_ILG_ST_D_S)) 701 #define DPORT_PMS_PRO_CACHE_ILG_ST_D_V 0x1FFFF 702 #define DPORT_PMS_PRO_CACHE_ILG_ST_D_S 0 703 704 #define DPORT_PMS_DMA_APB_I_0_REG (DR_REG_SENSITIVE_BASE + 0x08C) 705 /* DPORT_PMS_DMA_APB_I_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 706 /*description: */ 707 #define DPORT_PMS_DMA_APB_I_LOCK (BIT(0)) 708 #define DPORT_PMS_DMA_APB_I_LOCK_M (BIT(0)) 709 #define DPORT_PMS_DMA_APB_I_LOCK_V 0x1 710 #define DPORT_PMS_DMA_APB_I_LOCK_S 0 711 712 #define DPORT_PMS_DMA_APB_I_1_REG (DR_REG_SENSITIVE_BASE + 0x090) 713 /* DPORT_PMS_DMA_APB_I_SRAM_4_H_W : R/W ;bitpos:[28] ;default: 1'b1 ; */ 714 /*description: */ 715 #define DPORT_PMS_DMA_APB_I_SRAM_4_H_W (BIT(28)) 716 #define DPORT_PMS_DMA_APB_I_SRAM_4_H_W_M (BIT(28)) 717 #define DPORT_PMS_DMA_APB_I_SRAM_4_H_W_V 0x1 718 #define DPORT_PMS_DMA_APB_I_SRAM_4_H_W_S 28 719 /* DPORT_PMS_DMA_APB_I_SRAM_4_H_R : R/W ;bitpos:[27] ;default: 1'b1 ; */ 720 /*description: */ 721 #define DPORT_PMS_DMA_APB_I_SRAM_4_H_R (BIT(27)) 722 #define DPORT_PMS_DMA_APB_I_SRAM_4_H_R_M (BIT(27)) 723 #define DPORT_PMS_DMA_APB_I_SRAM_4_H_R_V 0x1 724 #define DPORT_PMS_DMA_APB_I_SRAM_4_H_R_S 27 725 /* DPORT_PMS_DMA_APB_I_SRAM_4_L_W : R/W ;bitpos:[26] ;default: 1'b1 ; */ 726 /*description: */ 727 #define DPORT_PMS_DMA_APB_I_SRAM_4_L_W (BIT(26)) 728 #define DPORT_PMS_DMA_APB_I_SRAM_4_L_W_M (BIT(26)) 729 #define DPORT_PMS_DMA_APB_I_SRAM_4_L_W_V 0x1 730 #define DPORT_PMS_DMA_APB_I_SRAM_4_L_W_S 26 731 /* DPORT_PMS_DMA_APB_I_SRAM_4_L_R : R/W ;bitpos:[25] ;default: 1'b1 ; */ 732 /*description: */ 733 #define DPORT_PMS_DMA_APB_I_SRAM_4_L_R (BIT(25)) 734 #define DPORT_PMS_DMA_APB_I_SRAM_4_L_R_M (BIT(25)) 735 #define DPORT_PMS_DMA_APB_I_SRAM_4_L_R_V 0x1 736 #define DPORT_PMS_DMA_APB_I_SRAM_4_L_R_S 25 737 /* DPORT_PMS_DMA_APB_I_SRAM_4_SPLTADDR : R/W ;bitpos:[24:8] ;default: 17'b0 ; */ 738 /*description: */ 739 #define DPORT_PMS_DMA_APB_I_SRAM_4_SPLTADDR 0x0001FFFF 740 #define DPORT_PMS_DMA_APB_I_SRAM_4_SPLTADDR_M ((DPORT_PMS_DMA_APB_I_SRAM_4_SPLTADDR_V)<<(DPORT_PMS_DMA_APB_I_SRAM_4_SPLTADDR_S)) 741 #define DPORT_PMS_DMA_APB_I_SRAM_4_SPLTADDR_V 0x1FFFF 742 #define DPORT_PMS_DMA_APB_I_SRAM_4_SPLTADDR_S 8 743 /* DPORT_PMS_DMA_APB_I_SRAM_3_W : R/W ;bitpos:[7] ;default: 1'b1 ; */ 744 /*description: */ 745 #define DPORT_PMS_DMA_APB_I_SRAM_3_W (BIT(7)) 746 #define DPORT_PMS_DMA_APB_I_SRAM_3_W_M (BIT(7)) 747 #define DPORT_PMS_DMA_APB_I_SRAM_3_W_V 0x1 748 #define DPORT_PMS_DMA_APB_I_SRAM_3_W_S 7 749 /* DPORT_PMS_DMA_APB_I_SRAM_3_R : R/W ;bitpos:[6] ;default: 1'b1 ; */ 750 /*description: */ 751 #define DPORT_PMS_DMA_APB_I_SRAM_3_R (BIT(6)) 752 #define DPORT_PMS_DMA_APB_I_SRAM_3_R_M (BIT(6)) 753 #define DPORT_PMS_DMA_APB_I_SRAM_3_R_V 0x1 754 #define DPORT_PMS_DMA_APB_I_SRAM_3_R_S 6 755 /* DPORT_PMS_DMA_APB_I_SRAM_2_W : R/W ;bitpos:[5] ;default: 1'b1 ; */ 756 /*description: */ 757 #define DPORT_PMS_DMA_APB_I_SRAM_2_W (BIT(5)) 758 #define DPORT_PMS_DMA_APB_I_SRAM_2_W_M (BIT(5)) 759 #define DPORT_PMS_DMA_APB_I_SRAM_2_W_V 0x1 760 #define DPORT_PMS_DMA_APB_I_SRAM_2_W_S 5 761 /* DPORT_PMS_DMA_APB_I_SRAM_2_R : R/W ;bitpos:[4] ;default: 1'b1 ; */ 762 /*description: */ 763 #define DPORT_PMS_DMA_APB_I_SRAM_2_R (BIT(4)) 764 #define DPORT_PMS_DMA_APB_I_SRAM_2_R_M (BIT(4)) 765 #define DPORT_PMS_DMA_APB_I_SRAM_2_R_V 0x1 766 #define DPORT_PMS_DMA_APB_I_SRAM_2_R_S 4 767 /* DPORT_PMS_DMA_APB_I_SRAM_1_W : R/W ;bitpos:[3] ;default: 1'b1 ; */ 768 /*description: */ 769 #define DPORT_PMS_DMA_APB_I_SRAM_1_W (BIT(3)) 770 #define DPORT_PMS_DMA_APB_I_SRAM_1_W_M (BIT(3)) 771 #define DPORT_PMS_DMA_APB_I_SRAM_1_W_V 0x1 772 #define DPORT_PMS_DMA_APB_I_SRAM_1_W_S 3 773 /* DPORT_PMS_DMA_APB_I_SRAM_1_R : R/W ;bitpos:[2] ;default: 1'b1 ; */ 774 /*description: */ 775 #define DPORT_PMS_DMA_APB_I_SRAM_1_R (BIT(2)) 776 #define DPORT_PMS_DMA_APB_I_SRAM_1_R_M (BIT(2)) 777 #define DPORT_PMS_DMA_APB_I_SRAM_1_R_V 0x1 778 #define DPORT_PMS_DMA_APB_I_SRAM_1_R_S 2 779 /* DPORT_PMS_DMA_APB_I_SRAM_0_W : R/W ;bitpos:[1] ;default: 1'b1 ; */ 780 /*description: */ 781 #define DPORT_PMS_DMA_APB_I_SRAM_0_W (BIT(1)) 782 #define DPORT_PMS_DMA_APB_I_SRAM_0_W_M (BIT(1)) 783 #define DPORT_PMS_DMA_APB_I_SRAM_0_W_V 0x1 784 #define DPORT_PMS_DMA_APB_I_SRAM_0_W_S 1 785 /* DPORT_PMS_DMA_APB_I_SRAM_0_R : R/W ;bitpos:[0] ;default: 1'b1 ; */ 786 /*description: */ 787 #define DPORT_PMS_DMA_APB_I_SRAM_0_R (BIT(0)) 788 #define DPORT_PMS_DMA_APB_I_SRAM_0_R_M (BIT(0)) 789 #define DPORT_PMS_DMA_APB_I_SRAM_0_R_V 0x1 790 #define DPORT_PMS_DMA_APB_I_SRAM_0_R_S 0 791 792 #define DPORT_PMS_DMA_APB_I_2_REG (DR_REG_SENSITIVE_BASE + 0x094) 793 /* DPORT_PMS_DMA_APB_I_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */ 794 /*description: */ 795 #define DPORT_PMS_DMA_APB_I_ILG_INTR (BIT(2)) 796 #define DPORT_PMS_DMA_APB_I_ILG_INTR_M (BIT(2)) 797 #define DPORT_PMS_DMA_APB_I_ILG_INTR_V 0x1 798 #define DPORT_PMS_DMA_APB_I_ILG_INTR_S 2 799 /* DPORT_PMS_DMA_APB_I_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 800 /*description: */ 801 #define DPORT_PMS_DMA_APB_I_ILG_EN (BIT(1)) 802 #define DPORT_PMS_DMA_APB_I_ILG_EN_M (BIT(1)) 803 #define DPORT_PMS_DMA_APB_I_ILG_EN_V 0x1 804 #define DPORT_PMS_DMA_APB_I_ILG_EN_S 1 805 /* DPORT_PMS_DMA_APB_I_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ 806 /*description: */ 807 #define DPORT_PMS_DMA_APB_I_ILG_CLR (BIT(0)) 808 #define DPORT_PMS_DMA_APB_I_ILG_CLR_M (BIT(0)) 809 #define DPORT_PMS_DMA_APB_I_ILG_CLR_V 0x1 810 #define DPORT_PMS_DMA_APB_I_ILG_CLR_S 0 811 812 #define DPORT_PMS_DMA_APB_I_3_REG (DR_REG_SENSITIVE_BASE + 0x098) 813 /* DPORT_PMS_DMA_APB_I_ILG_ST : RO ;bitpos:[22:0] ;default: 23'b0 ; */ 814 /*description: */ 815 #define DPORT_PMS_DMA_APB_I_ILG_ST 0x007FFFFF 816 #define DPORT_PMS_DMA_APB_I_ILG_ST_M ((DPORT_PMS_DMA_APB_I_ILG_ST_V)<<(DPORT_PMS_DMA_APB_I_ILG_ST_S)) 817 #define DPORT_PMS_DMA_APB_I_ILG_ST_V 0x7FFFFF 818 #define DPORT_PMS_DMA_APB_I_ILG_ST_S 0 819 820 #define DPORT_PMS_DMA_RX_I_0_REG (DR_REG_SENSITIVE_BASE + 0x09C) 821 /* DPORT_PMS_DMA_RX_I_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 822 /*description: */ 823 #define DPORT_PMS_DMA_RX_I_LOCK (BIT(0)) 824 #define DPORT_PMS_DMA_RX_I_LOCK_M (BIT(0)) 825 #define DPORT_PMS_DMA_RX_I_LOCK_V 0x1 826 #define DPORT_PMS_DMA_RX_I_LOCK_S 0 827 828 #define DPORT_PMS_DMA_RX_I_1_REG (DR_REG_SENSITIVE_BASE + 0x0A0) 829 /* DPORT_PMS_DMA_RX_I_SRAM_4_H_W : R/W ;bitpos:[28] ;default: 1'b1 ; */ 830 /*description: */ 831 #define DPORT_PMS_DMA_RX_I_SRAM_4_H_W (BIT(28)) 832 #define DPORT_PMS_DMA_RX_I_SRAM_4_H_W_M (BIT(28)) 833 #define DPORT_PMS_DMA_RX_I_SRAM_4_H_W_V 0x1 834 #define DPORT_PMS_DMA_RX_I_SRAM_4_H_W_S 28 835 /* DPORT_PMS_DMA_RX_I_SRAM_4_H_R : R/W ;bitpos:[27] ;default: 1'b1 ; */ 836 /*description: */ 837 #define DPORT_PMS_DMA_RX_I_SRAM_4_H_R (BIT(27)) 838 #define DPORT_PMS_DMA_RX_I_SRAM_4_H_R_M (BIT(27)) 839 #define DPORT_PMS_DMA_RX_I_SRAM_4_H_R_V 0x1 840 #define DPORT_PMS_DMA_RX_I_SRAM_4_H_R_S 27 841 /* DPORT_PMS_DMA_RX_I_SRAM_4_L_W : R/W ;bitpos:[26] ;default: 1'b1 ; */ 842 /*description: */ 843 #define DPORT_PMS_DMA_RX_I_SRAM_4_L_W (BIT(26)) 844 #define DPORT_PMS_DMA_RX_I_SRAM_4_L_W_M (BIT(26)) 845 #define DPORT_PMS_DMA_RX_I_SRAM_4_L_W_V 0x1 846 #define DPORT_PMS_DMA_RX_I_SRAM_4_L_W_S 26 847 /* DPORT_PMS_DMA_RX_I_SRAM_4_L_R : R/W ;bitpos:[25] ;default: 1'b1 ; */ 848 /*description: */ 849 #define DPORT_PMS_DMA_RX_I_SRAM_4_L_R (BIT(25)) 850 #define DPORT_PMS_DMA_RX_I_SRAM_4_L_R_M (BIT(25)) 851 #define DPORT_PMS_DMA_RX_I_SRAM_4_L_R_V 0x1 852 #define DPORT_PMS_DMA_RX_I_SRAM_4_L_R_S 25 853 /* DPORT_PMS_DMA_RX_I_SRAM_4_SPLTADDR : R/W ;bitpos:[24:8] ;default: 17'b0 ; */ 854 /*description: */ 855 #define DPORT_PMS_DMA_RX_I_SRAM_4_SPLTADDR 0x0001FFFF 856 #define DPORT_PMS_DMA_RX_I_SRAM_4_SPLTADDR_M ((DPORT_PMS_DMA_RX_I_SRAM_4_SPLTADDR_V)<<(DPORT_PMS_DMA_RX_I_SRAM_4_SPLTADDR_S)) 857 #define DPORT_PMS_DMA_RX_I_SRAM_4_SPLTADDR_V 0x1FFFF 858 #define DPORT_PMS_DMA_RX_I_SRAM_4_SPLTADDR_S 8 859 /* DPORT_PMS_DMA_RX_I_SRAM_3_W : R/W ;bitpos:[7] ;default: 1'b1 ; */ 860 /*description: */ 861 #define DPORT_PMS_DMA_RX_I_SRAM_3_W (BIT(7)) 862 #define DPORT_PMS_DMA_RX_I_SRAM_3_W_M (BIT(7)) 863 #define DPORT_PMS_DMA_RX_I_SRAM_3_W_V 0x1 864 #define DPORT_PMS_DMA_RX_I_SRAM_3_W_S 7 865 /* DPORT_PMS_DMA_RX_I_SRAM_3_R : R/W ;bitpos:[6] ;default: 1'b1 ; */ 866 /*description: */ 867 #define DPORT_PMS_DMA_RX_I_SRAM_3_R (BIT(6)) 868 #define DPORT_PMS_DMA_RX_I_SRAM_3_R_M (BIT(6)) 869 #define DPORT_PMS_DMA_RX_I_SRAM_3_R_V 0x1 870 #define DPORT_PMS_DMA_RX_I_SRAM_3_R_S 6 871 /* DPORT_PMS_DMA_RX_I_SRAM_2_W : R/W ;bitpos:[5] ;default: 1'b1 ; */ 872 /*description: */ 873 #define DPORT_PMS_DMA_RX_I_SRAM_2_W (BIT(5)) 874 #define DPORT_PMS_DMA_RX_I_SRAM_2_W_M (BIT(5)) 875 #define DPORT_PMS_DMA_RX_I_SRAM_2_W_V 0x1 876 #define DPORT_PMS_DMA_RX_I_SRAM_2_W_S 5 877 /* DPORT_PMS_DMA_RX_I_SRAM_2_R : R/W ;bitpos:[4] ;default: 1'b1 ; */ 878 /*description: */ 879 #define DPORT_PMS_DMA_RX_I_SRAM_2_R (BIT(4)) 880 #define DPORT_PMS_DMA_RX_I_SRAM_2_R_M (BIT(4)) 881 #define DPORT_PMS_DMA_RX_I_SRAM_2_R_V 0x1 882 #define DPORT_PMS_DMA_RX_I_SRAM_2_R_S 4 883 /* DPORT_PMS_DMA_RX_I_SRAM_1_W : R/W ;bitpos:[3] ;default: 1'b1 ; */ 884 /*description: */ 885 #define DPORT_PMS_DMA_RX_I_SRAM_1_W (BIT(3)) 886 #define DPORT_PMS_DMA_RX_I_SRAM_1_W_M (BIT(3)) 887 #define DPORT_PMS_DMA_RX_I_SRAM_1_W_V 0x1 888 #define DPORT_PMS_DMA_RX_I_SRAM_1_W_S 3 889 /* DPORT_PMS_DMA_RX_I_SRAM_1_R : R/W ;bitpos:[2] ;default: 1'b1 ; */ 890 /*description: */ 891 #define DPORT_PMS_DMA_RX_I_SRAM_1_R (BIT(2)) 892 #define DPORT_PMS_DMA_RX_I_SRAM_1_R_M (BIT(2)) 893 #define DPORT_PMS_DMA_RX_I_SRAM_1_R_V 0x1 894 #define DPORT_PMS_DMA_RX_I_SRAM_1_R_S 2 895 /* DPORT_PMS_DMA_RX_I_SRAM_0_W : R/W ;bitpos:[1] ;default: 1'b1 ; */ 896 /*description: */ 897 #define DPORT_PMS_DMA_RX_I_SRAM_0_W (BIT(1)) 898 #define DPORT_PMS_DMA_RX_I_SRAM_0_W_M (BIT(1)) 899 #define DPORT_PMS_DMA_RX_I_SRAM_0_W_V 0x1 900 #define DPORT_PMS_DMA_RX_I_SRAM_0_W_S 1 901 /* DPORT_PMS_DMA_RX_I_SRAM_0_R : R/W ;bitpos:[0] ;default: 1'b1 ; */ 902 /*description: */ 903 #define DPORT_PMS_DMA_RX_I_SRAM_0_R (BIT(0)) 904 #define DPORT_PMS_DMA_RX_I_SRAM_0_R_M (BIT(0)) 905 #define DPORT_PMS_DMA_RX_I_SRAM_0_R_V 0x1 906 #define DPORT_PMS_DMA_RX_I_SRAM_0_R_S 0 907 908 #define DPORT_PMS_DMA_RX_I_2_REG (DR_REG_SENSITIVE_BASE + 0x0A4) 909 /* DPORT_PMS_DMA_RX_I_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */ 910 /*description: */ 911 #define DPORT_PMS_DMA_RX_I_ILG_INTR (BIT(2)) 912 #define DPORT_PMS_DMA_RX_I_ILG_INTR_M (BIT(2)) 913 #define DPORT_PMS_DMA_RX_I_ILG_INTR_V 0x1 914 #define DPORT_PMS_DMA_RX_I_ILG_INTR_S 2 915 /* DPORT_PMS_DMA_RX_I_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 916 /*description: */ 917 #define DPORT_PMS_DMA_RX_I_ILG_EN (BIT(1)) 918 #define DPORT_PMS_DMA_RX_I_ILG_EN_M (BIT(1)) 919 #define DPORT_PMS_DMA_RX_I_ILG_EN_V 0x1 920 #define DPORT_PMS_DMA_RX_I_ILG_EN_S 1 921 /* DPORT_PMS_DMA_RX_I_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ 922 /*description: */ 923 #define DPORT_PMS_DMA_RX_I_ILG_CLR (BIT(0)) 924 #define DPORT_PMS_DMA_RX_I_ILG_CLR_M (BIT(0)) 925 #define DPORT_PMS_DMA_RX_I_ILG_CLR_V 0x1 926 #define DPORT_PMS_DMA_RX_I_ILG_CLR_S 0 927 928 #define DPORT_PMS_DMA_RX_I_3_REG (DR_REG_SENSITIVE_BASE + 0x0A8) 929 /* DPORT_PMS_DMA_RX_I_ILG_ST : RO ;bitpos:[22:0] ;default: 23'b0 ; */ 930 /*description: */ 931 #define DPORT_PMS_DMA_RX_I_ILG_ST 0x007FFFFF 932 #define DPORT_PMS_DMA_RX_I_ILG_ST_M ((DPORT_PMS_DMA_RX_I_ILG_ST_V)<<(DPORT_PMS_DMA_RX_I_ILG_ST_S)) 933 #define DPORT_PMS_DMA_RX_I_ILG_ST_V 0x7FFFFF 934 #define DPORT_PMS_DMA_RX_I_ILG_ST_S 0 935 936 #define DPORT_PMS_DMA_TX_I_0_REG (DR_REG_SENSITIVE_BASE + 0x0AC) 937 /* DPORT_PMS_DMA_TX_I_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 938 /*description: */ 939 #define DPORT_PMS_DMA_TX_I_LOCK (BIT(0)) 940 #define DPORT_PMS_DMA_TX_I_LOCK_M (BIT(0)) 941 #define DPORT_PMS_DMA_TX_I_LOCK_V 0x1 942 #define DPORT_PMS_DMA_TX_I_LOCK_S 0 943 944 #define DPORT_PMS_DMA_TX_I_1_REG (DR_REG_SENSITIVE_BASE + 0x0B0) 945 /* DPORT_PMS_DMA_TX_I_SRAM_4_H_W : R/W ;bitpos:[28] ;default: 1'b1 ; */ 946 /*description: */ 947 #define DPORT_PMS_DMA_TX_I_SRAM_4_H_W (BIT(28)) 948 #define DPORT_PMS_DMA_TX_I_SRAM_4_H_W_M (BIT(28)) 949 #define DPORT_PMS_DMA_TX_I_SRAM_4_H_W_V 0x1 950 #define DPORT_PMS_DMA_TX_I_SRAM_4_H_W_S 28 951 /* DPORT_PMS_DMA_TX_I_SRAM_4_H_R : R/W ;bitpos:[27] ;default: 1'b1 ; */ 952 /*description: */ 953 #define DPORT_PMS_DMA_TX_I_SRAM_4_H_R (BIT(27)) 954 #define DPORT_PMS_DMA_TX_I_SRAM_4_H_R_M (BIT(27)) 955 #define DPORT_PMS_DMA_TX_I_SRAM_4_H_R_V 0x1 956 #define DPORT_PMS_DMA_TX_I_SRAM_4_H_R_S 27 957 /* DPORT_PMS_DMA_TX_I_SRAM_4_L_W : R/W ;bitpos:[26] ;default: 1'b1 ; */ 958 /*description: */ 959 #define DPORT_PMS_DMA_TX_I_SRAM_4_L_W (BIT(26)) 960 #define DPORT_PMS_DMA_TX_I_SRAM_4_L_W_M (BIT(26)) 961 #define DPORT_PMS_DMA_TX_I_SRAM_4_L_W_V 0x1 962 #define DPORT_PMS_DMA_TX_I_SRAM_4_L_W_S 26 963 /* DPORT_PMS_DMA_TX_I_SRAM_4_L_R : R/W ;bitpos:[25] ;default: 1'b1 ; */ 964 /*description: */ 965 #define DPORT_PMS_DMA_TX_I_SRAM_4_L_R (BIT(25)) 966 #define DPORT_PMS_DMA_TX_I_SRAM_4_L_R_M (BIT(25)) 967 #define DPORT_PMS_DMA_TX_I_SRAM_4_L_R_V 0x1 968 #define DPORT_PMS_DMA_TX_I_SRAM_4_L_R_S 25 969 /* DPORT_PMS_DMA_TX_I_SRAM_4_SPLTADDR : R/W ;bitpos:[24:8] ;default: 17'b0 ; */ 970 /*description: */ 971 #define DPORT_PMS_DMA_TX_I_SRAM_4_SPLTADDR 0x0001FFFF 972 #define DPORT_PMS_DMA_TX_I_SRAM_4_SPLTADDR_M ((DPORT_PMS_DMA_TX_I_SRAM_4_SPLTADDR_V)<<(DPORT_PMS_DMA_TX_I_SRAM_4_SPLTADDR_S)) 973 #define DPORT_PMS_DMA_TX_I_SRAM_4_SPLTADDR_V 0x1FFFF 974 #define DPORT_PMS_DMA_TX_I_SRAM_4_SPLTADDR_S 8 975 /* DPORT_PMS_DMA_TX_I_SRAM_3_W : R/W ;bitpos:[7] ;default: 1'b1 ; */ 976 /*description: */ 977 #define DPORT_PMS_DMA_TX_I_SRAM_3_W (BIT(7)) 978 #define DPORT_PMS_DMA_TX_I_SRAM_3_W_M (BIT(7)) 979 #define DPORT_PMS_DMA_TX_I_SRAM_3_W_V 0x1 980 #define DPORT_PMS_DMA_TX_I_SRAM_3_W_S 7 981 /* DPORT_PMS_DMA_TX_I_SRAM_3_R : R/W ;bitpos:[6] ;default: 1'b1 ; */ 982 /*description: */ 983 #define DPORT_PMS_DMA_TX_I_SRAM_3_R (BIT(6)) 984 #define DPORT_PMS_DMA_TX_I_SRAM_3_R_M (BIT(6)) 985 #define DPORT_PMS_DMA_TX_I_SRAM_3_R_V 0x1 986 #define DPORT_PMS_DMA_TX_I_SRAM_3_R_S 6 987 /* DPORT_PMS_DMA_TX_I_SRAM_2_W : R/W ;bitpos:[5] ;default: 1'b1 ; */ 988 /*description: */ 989 #define DPORT_PMS_DMA_TX_I_SRAM_2_W (BIT(5)) 990 #define DPORT_PMS_DMA_TX_I_SRAM_2_W_M (BIT(5)) 991 #define DPORT_PMS_DMA_TX_I_SRAM_2_W_V 0x1 992 #define DPORT_PMS_DMA_TX_I_SRAM_2_W_S 5 993 /* DPORT_PMS_DMA_TX_I_SRAM_2_R : R/W ;bitpos:[4] ;default: 1'b1 ; */ 994 /*description: */ 995 #define DPORT_PMS_DMA_TX_I_SRAM_2_R (BIT(4)) 996 #define DPORT_PMS_DMA_TX_I_SRAM_2_R_M (BIT(4)) 997 #define DPORT_PMS_DMA_TX_I_SRAM_2_R_V 0x1 998 #define DPORT_PMS_DMA_TX_I_SRAM_2_R_S 4 999 /* DPORT_PMS_DMA_TX_I_SRAM_1_W : R/W ;bitpos:[3] ;default: 1'b1 ; */ 1000 /*description: */ 1001 #define DPORT_PMS_DMA_TX_I_SRAM_1_W (BIT(3)) 1002 #define DPORT_PMS_DMA_TX_I_SRAM_1_W_M (BIT(3)) 1003 #define DPORT_PMS_DMA_TX_I_SRAM_1_W_V 0x1 1004 #define DPORT_PMS_DMA_TX_I_SRAM_1_W_S 3 1005 /* DPORT_PMS_DMA_TX_I_SRAM_1_R : R/W ;bitpos:[2] ;default: 1'b1 ; */ 1006 /*description: */ 1007 #define DPORT_PMS_DMA_TX_I_SRAM_1_R (BIT(2)) 1008 #define DPORT_PMS_DMA_TX_I_SRAM_1_R_M (BIT(2)) 1009 #define DPORT_PMS_DMA_TX_I_SRAM_1_R_V 0x1 1010 #define DPORT_PMS_DMA_TX_I_SRAM_1_R_S 2 1011 /* DPORT_PMS_DMA_TX_I_SRAM_0_W : R/W ;bitpos:[1] ;default: 1'b1 ; */ 1012 /*description: */ 1013 #define DPORT_PMS_DMA_TX_I_SRAM_0_W (BIT(1)) 1014 #define DPORT_PMS_DMA_TX_I_SRAM_0_W_M (BIT(1)) 1015 #define DPORT_PMS_DMA_TX_I_SRAM_0_W_V 0x1 1016 #define DPORT_PMS_DMA_TX_I_SRAM_0_W_S 1 1017 /* DPORT_PMS_DMA_TX_I_SRAM_0_R : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1018 /*description: */ 1019 #define DPORT_PMS_DMA_TX_I_SRAM_0_R (BIT(0)) 1020 #define DPORT_PMS_DMA_TX_I_SRAM_0_R_M (BIT(0)) 1021 #define DPORT_PMS_DMA_TX_I_SRAM_0_R_V 0x1 1022 #define DPORT_PMS_DMA_TX_I_SRAM_0_R_S 0 1023 1024 #define DPORT_PMS_DMA_TX_I_2_REG (DR_REG_SENSITIVE_BASE + 0x0B4) 1025 /* DPORT_PMS_DMA_TX_I_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */ 1026 /*description: */ 1027 #define DPORT_PMS_DMA_TX_I_ILG_INTR (BIT(2)) 1028 #define DPORT_PMS_DMA_TX_I_ILG_INTR_M (BIT(2)) 1029 #define DPORT_PMS_DMA_TX_I_ILG_INTR_V 0x1 1030 #define DPORT_PMS_DMA_TX_I_ILG_INTR_S 2 1031 /* DPORT_PMS_DMA_TX_I_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1032 /*description: */ 1033 #define DPORT_PMS_DMA_TX_I_ILG_EN (BIT(1)) 1034 #define DPORT_PMS_DMA_TX_I_ILG_EN_M (BIT(1)) 1035 #define DPORT_PMS_DMA_TX_I_ILG_EN_V 0x1 1036 #define DPORT_PMS_DMA_TX_I_ILG_EN_S 1 1037 /* DPORT_PMS_DMA_TX_I_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1038 /*description: */ 1039 #define DPORT_PMS_DMA_TX_I_ILG_CLR (BIT(0)) 1040 #define DPORT_PMS_DMA_TX_I_ILG_CLR_M (BIT(0)) 1041 #define DPORT_PMS_DMA_TX_I_ILG_CLR_V 0x1 1042 #define DPORT_PMS_DMA_TX_I_ILG_CLR_S 0 1043 1044 #define DPORT_PMS_DMA_TX_I_3_REG (DR_REG_SENSITIVE_BASE + 0x0B8) 1045 /* DPORT_PMS_DMA_TX_I_ILG_ST : RO ;bitpos:[22:0] ;default: 23'b0 ; */ 1046 /*description: */ 1047 #define DPORT_PMS_DMA_TX_I_ILG_ST 0x007FFFFF 1048 #define DPORT_PMS_DMA_TX_I_ILG_ST_M ((DPORT_PMS_DMA_TX_I_ILG_ST_V)<<(DPORT_PMS_DMA_TX_I_ILG_ST_S)) 1049 #define DPORT_PMS_DMA_TX_I_ILG_ST_V 0x7FFFFF 1050 #define DPORT_PMS_DMA_TX_I_ILG_ST_S 0 1051 1052 #define DPORT_PRO_BOOT_LOCATION_0_REG (DR_REG_SENSITIVE_BASE + 0x0BC) 1053 /* DPORT_PRO_BOOT_LOCATION_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1054 /*description: */ 1055 #define DPORT_PRO_BOOT_LOCATION_LOCK (BIT(0)) 1056 #define DPORT_PRO_BOOT_LOCATION_LOCK_M (BIT(0)) 1057 #define DPORT_PRO_BOOT_LOCATION_LOCK_V 0x1 1058 #define DPORT_PRO_BOOT_LOCATION_LOCK_S 0 1059 1060 #define DPORT_PRO_BOOT_LOCATION_1_REG (DR_REG_SENSITIVE_BASE + 0x0C0) 1061 /* DPORT_PRO_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1062 /*description: */ 1063 #define DPORT_PRO_BOOT_REMAP (BIT(0)) 1064 #define DPORT_PRO_BOOT_REMAP_M (BIT(0)) 1065 #define DPORT_PRO_BOOT_REMAP_V 0x1 1066 #define DPORT_PRO_BOOT_REMAP_S 0 1067 1068 #define DPORT_CACHE_SOURCE_0_REG (DR_REG_SENSITIVE_BASE + 0x0C4) 1069 /* DPORT_CACHE_SOURCE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1070 /*description: */ 1071 #define DPORT_CACHE_SOURCE_LOCK (BIT(0)) 1072 #define DPORT_CACHE_SOURCE_LOCK_M (BIT(0)) 1073 #define DPORT_CACHE_SOURCE_LOCK_V 0x1 1074 #define DPORT_CACHE_SOURCE_LOCK_S 0 1075 1076 #define DPORT_CACHE_SOURCE_1_REG (DR_REG_SENSITIVE_BASE + 0x0C8) 1077 /* DPORT_PRO_CACHE_D_SOURCE_PRO_DROM0 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1078 /*description: */ 1079 #define DPORT_PRO_CACHE_D_SOURCE_PRO_DROM0 (BIT(5)) 1080 #define DPORT_PRO_CACHE_D_SOURCE_PRO_DROM0_M (BIT(5)) 1081 #define DPORT_PRO_CACHE_D_SOURCE_PRO_DROM0_V 0x1 1082 #define DPORT_PRO_CACHE_D_SOURCE_PRO_DROM0_S 5 1083 /* DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1084 /*description: */ 1085 #define DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT (BIT(4)) 1086 #define DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT_M (BIT(4)) 1087 #define DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT_V 0x1 1088 #define DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT_S 4 1089 /* DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1090 /*description: */ 1091 #define DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0 (BIT(3)) 1092 #define DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0_M (BIT(3)) 1093 #define DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0_V 0x1 1094 #define DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0_S 3 1095 /* DPORT_PRO_CACHE_I_SOURCE_PRO_DROM0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1096 /*description: */ 1097 #define DPORT_PRO_CACHE_I_SOURCE_PRO_DROM0 (BIT(2)) 1098 #define DPORT_PRO_CACHE_I_SOURCE_PRO_DROM0_M (BIT(2)) 1099 #define DPORT_PRO_CACHE_I_SOURCE_PRO_DROM0_V 0x1 1100 #define DPORT_PRO_CACHE_I_SOURCE_PRO_DROM0_S 2 1101 /* DPORT_PRO_CACHE_I_SOURCE_PRO_IROM0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1102 /*description: */ 1103 #define DPORT_PRO_CACHE_I_SOURCE_PRO_IROM0 (BIT(1)) 1104 #define DPORT_PRO_CACHE_I_SOURCE_PRO_IROM0_M (BIT(1)) 1105 #define DPORT_PRO_CACHE_I_SOURCE_PRO_IROM0_V 0x1 1106 #define DPORT_PRO_CACHE_I_SOURCE_PRO_IROM0_S 1 1107 /* DPORT_PRO_CACHE_I_SOURCE_PRO_IRAM1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1108 /*description: */ 1109 #define DPORT_PRO_CACHE_I_SOURCE_PRO_IRAM1 (BIT(0)) 1110 #define DPORT_PRO_CACHE_I_SOURCE_PRO_IRAM1_M (BIT(0)) 1111 #define DPORT_PRO_CACHE_I_SOURCE_PRO_IRAM1_V 0x1 1112 #define DPORT_PRO_CACHE_I_SOURCE_PRO_IRAM1_S 0 1113 1114 #define DPORT_APB_PERIPHERAL_0_REG (DR_REG_SENSITIVE_BASE + 0x0CC) 1115 /* DPORT_APB_PERIPHERAL_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1116 /*description: */ 1117 #define DPORT_APB_PERIPHERAL_LOCK (BIT(0)) 1118 #define DPORT_APB_PERIPHERAL_LOCK_M (BIT(0)) 1119 #define DPORT_APB_PERIPHERAL_LOCK_V 0x1 1120 #define DPORT_APB_PERIPHERAL_LOCK_S 0 1121 1122 #define DPORT_APB_PERIPHERAL_1_REG (DR_REG_SENSITIVE_BASE + 0x0D0) 1123 /* DPORT_APB_PERIPHERAL_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1124 /*description: */ 1125 #define DPORT_APB_PERIPHERAL_SPLIT_BURST (BIT(0)) 1126 #define DPORT_APB_PERIPHERAL_SPLIT_BURST_M (BIT(0)) 1127 #define DPORT_APB_PERIPHERAL_SPLIT_BURST_V 0x1 1128 #define DPORT_APB_PERIPHERAL_SPLIT_BURST_S 0 1129 1130 #define DPORT_PMS_OCCUPY_0_REG (DR_REG_SENSITIVE_BASE + 0x0D4) 1131 /* DPORT_PMS_OCCUPY_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1132 /*description: */ 1133 #define DPORT_PMS_OCCUPY_LOCK (BIT(0)) 1134 #define DPORT_PMS_OCCUPY_LOCK_M (BIT(0)) 1135 #define DPORT_PMS_OCCUPY_LOCK_V 0x1 1136 #define DPORT_PMS_OCCUPY_LOCK_S 0 1137 1138 #define DPORT_PMS_OCCUPY_1_REG (DR_REG_SENSITIVE_BASE + 0x0D8) 1139 /* DPORT_PMS_OCCUPY_CACHE : R/W ;bitpos:[3:0] ;default: 4'b0000 ; */ 1140 /*description: */ 1141 #define DPORT_PMS_OCCUPY_CACHE 0x0000000F 1142 #define DPORT_PMS_OCCUPY_CACHE_M ((DPORT_PMS_OCCUPY_CACHE_V)<<(DPORT_PMS_OCCUPY_CACHE_S)) 1143 #define DPORT_PMS_OCCUPY_CACHE_V 0xF 1144 #define DPORT_PMS_OCCUPY_CACHE_S 0 1145 1146 #define DPORT_PMS_OCCUPY_2_REG (DR_REG_SENSITIVE_BASE + 0x0DC) 1147 /* DPORT_PMS_OCCUPY_MAC_DUMP : R/W ;bitpos:[3:0] ;default: 4'b0000 ; */ 1148 /*description: */ 1149 #define DPORT_PMS_OCCUPY_MAC_DUMP 0x0000000F 1150 #define DPORT_PMS_OCCUPY_MAC_DUMP_M ((DPORT_PMS_OCCUPY_MAC_DUMP_V)<<(DPORT_PMS_OCCUPY_MAC_DUMP_S)) 1151 #define DPORT_PMS_OCCUPY_MAC_DUMP_V 0xF 1152 #define DPORT_PMS_OCCUPY_MAC_DUMP_S 0 1153 1154 #define DPORT_PMS_OCCUPY_3_REG (DR_REG_SENSITIVE_BASE + 0x0E0) 1155 /* DPORT_PMS_OCCUPY_PRO_TRACE : R/W ;bitpos:[17:0] ;default: 18'b0 ; */ 1156 /*description: */ 1157 #define DPORT_PMS_OCCUPY_PRO_TRACE 0x0003FFFF 1158 #define DPORT_PMS_OCCUPY_PRO_TRACE_M ((DPORT_PMS_OCCUPY_PRO_TRACE_V)<<(DPORT_PMS_OCCUPY_PRO_TRACE_S)) 1159 #define DPORT_PMS_OCCUPY_PRO_TRACE_V 0x3FFFF 1160 #define DPORT_PMS_OCCUPY_PRO_TRACE_S 0 1161 1162 #define DPORT_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x0E4) 1163 /* DPORT_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1164 /*description: */ 1165 #define DPORT_CACHE_TAG_ACCESS_LOCK (BIT(0)) 1166 #define DPORT_CACHE_TAG_ACCESS_LOCK_M (BIT(0)) 1167 #define DPORT_CACHE_TAG_ACCESS_LOCK_V 0x1 1168 #define DPORT_CACHE_TAG_ACCESS_LOCK_S 0 1169 1170 #define DPORT_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x0E8) 1171 /* DPORT_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1172 /*description: */ 1173 #define DPORT_PRO_D_TAG_WR_ACS (BIT(3)) 1174 #define DPORT_PRO_D_TAG_WR_ACS_M (BIT(3)) 1175 #define DPORT_PRO_D_TAG_WR_ACS_V 0x1 1176 #define DPORT_PRO_D_TAG_WR_ACS_S 3 1177 /* DPORT_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1178 /*description: */ 1179 #define DPORT_PRO_D_TAG_RD_ACS (BIT(2)) 1180 #define DPORT_PRO_D_TAG_RD_ACS_M (BIT(2)) 1181 #define DPORT_PRO_D_TAG_RD_ACS_V 0x1 1182 #define DPORT_PRO_D_TAG_RD_ACS_S 2 1183 /* DPORT_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1184 /*description: */ 1185 #define DPORT_PRO_I_TAG_WR_ACS (BIT(1)) 1186 #define DPORT_PRO_I_TAG_WR_ACS_M (BIT(1)) 1187 #define DPORT_PRO_I_TAG_WR_ACS_V 0x1 1188 #define DPORT_PRO_I_TAG_WR_ACS_S 1 1189 /* DPORT_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1190 /*description: */ 1191 #define DPORT_PRO_I_TAG_RD_ACS (BIT(0)) 1192 #define DPORT_PRO_I_TAG_RD_ACS_M (BIT(0)) 1193 #define DPORT_PRO_I_TAG_RD_ACS_V 0x1 1194 #define DPORT_PRO_I_TAG_RD_ACS_S 0 1195 1196 #define DPORT_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x0EC) 1197 /* DPORT_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1198 /*description: */ 1199 #define DPORT_CACHE_MMU_ACCESS_LOCK (BIT(0)) 1200 #define DPORT_CACHE_MMU_ACCESS_LOCK_M (BIT(0)) 1201 #define DPORT_CACHE_MMU_ACCESS_LOCK_V 0x1 1202 #define DPORT_CACHE_MMU_ACCESS_LOCK_S 0 1203 1204 #define DPORT_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x0F0) 1205 /* DPORT_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */ 1206 /*description: */ 1207 #define DPORT_PRO_MMU_WR_ACS (BIT(1)) 1208 #define DPORT_PRO_MMU_WR_ACS_M (BIT(1)) 1209 #define DPORT_PRO_MMU_WR_ACS_V 0x1 1210 #define DPORT_PRO_MMU_WR_ACS_S 1 1211 /* DPORT_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1212 /*description: */ 1213 #define DPORT_PRO_MMU_RD_ACS (BIT(0)) 1214 #define DPORT_PRO_MMU_RD_ACS_M (BIT(0)) 1215 #define DPORT_PRO_MMU_RD_ACS_V 0x1 1216 #define DPORT_PRO_MMU_RD_ACS_S 0 1217 1218 #define DPORT_APB_PERIPHERAL_INTR_REG (DR_REG_SENSITIVE_BASE + 0x0F4) 1219 /* DPORT_APB_PERI_BYTE_ERROR_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */ 1220 /*description: */ 1221 #define DPORT_APB_PERI_BYTE_ERROR_INTR (BIT(2)) 1222 #define DPORT_APB_PERI_BYTE_ERROR_INTR_M (BIT(2)) 1223 #define DPORT_APB_PERI_BYTE_ERROR_INTR_V 0x1 1224 #define DPORT_APB_PERI_BYTE_ERROR_INTR_S 2 1225 /* DPORT_APB_PERI_BYTE_ERROR_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1226 /*description: */ 1227 #define DPORT_APB_PERI_BYTE_ERROR_EN (BIT(1)) 1228 #define DPORT_APB_PERI_BYTE_ERROR_EN_M (BIT(1)) 1229 #define DPORT_APB_PERI_BYTE_ERROR_EN_V 0x1 1230 #define DPORT_APB_PERI_BYTE_ERROR_EN_S 1 1231 /* DPORT_APB_PERI_BYTE_ERROR_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1232 /*description: */ 1233 #define DPORT_APB_PERI_BYTE_ERROR_CLR (BIT(0)) 1234 #define DPORT_APB_PERI_BYTE_ERROR_CLR_M (BIT(0)) 1235 #define DPORT_APB_PERI_BYTE_ERROR_CLR_V 0x1 1236 #define DPORT_APB_PERI_BYTE_ERROR_CLR_S 0 1237 1238 #define DPORT_APB_PERIPHERAL_STATUS_REG (DR_REG_SENSITIVE_BASE + 0x0F8) 1239 /* DPORT_APB_PERI_BYTE_ERROR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 1240 /*description: */ 1241 #define DPORT_APB_PERI_BYTE_ERROR_ADDR 0xFFFFFFFF 1242 #define DPORT_APB_PERI_BYTE_ERROR_ADDR_M ((DPORT_APB_PERI_BYTE_ERROR_ADDR_V)<<(DPORT_APB_PERI_BYTE_ERROR_ADDR_S)) 1243 #define DPORT_APB_PERI_BYTE_ERROR_ADDR_V 0xFFFFFFFF 1244 #define DPORT_APB_PERI_BYTE_ERROR_ADDR_S 0 1245 1246 #define DPORT_CPU_PERIPHERAL_INTR_REG (DR_REG_SENSITIVE_BASE + 0x0FC) 1247 /* DPORT_CPU_PERI_BYTE_ERROR_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */ 1248 /*description: */ 1249 #define DPORT_CPU_PERI_BYTE_ERROR_INTR (BIT(2)) 1250 #define DPORT_CPU_PERI_BYTE_ERROR_INTR_M (BIT(2)) 1251 #define DPORT_CPU_PERI_BYTE_ERROR_INTR_V 0x1 1252 #define DPORT_CPU_PERI_BYTE_ERROR_INTR_S 2 1253 /* DPORT_CPU_PERI_BYTE_ERROR_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1254 /*description: */ 1255 #define DPORT_CPU_PERI_BYTE_ERROR_EN (BIT(1)) 1256 #define DPORT_CPU_PERI_BYTE_ERROR_EN_M (BIT(1)) 1257 #define DPORT_CPU_PERI_BYTE_ERROR_EN_V 0x1 1258 #define DPORT_CPU_PERI_BYTE_ERROR_EN_S 1 1259 /* DPORT_CPU_PERI_BYTE_ERROR_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1260 /*description: */ 1261 #define DPORT_CPU_PERI_BYTE_ERROR_CLR (BIT(0)) 1262 #define DPORT_CPU_PERI_BYTE_ERROR_CLR_M (BIT(0)) 1263 #define DPORT_CPU_PERI_BYTE_ERROR_CLR_V 0x1 1264 #define DPORT_CPU_PERI_BYTE_ERROR_CLR_S 0 1265 1266 #define DPORT_CPU_PERIPHERAL_STATUS_REG (DR_REG_SENSITIVE_BASE + 0x100) 1267 /* DPORT_CPU_PERI_BYTE_ERROR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 1268 /*description: */ 1269 #define DPORT_CPU_PERI_BYTE_ERROR_ADDR 0xFFFFFFFF 1270 #define DPORT_CPU_PERI_BYTE_ERROR_ADDR_M ((DPORT_CPU_PERI_BYTE_ERROR_ADDR_V)<<(DPORT_CPU_PERI_BYTE_ERROR_ADDR_S)) 1271 #define DPORT_CPU_PERI_BYTE_ERROR_ADDR_V 0xFFFFFFFF 1272 #define DPORT_CPU_PERI_BYTE_ERROR_ADDR_S 0 1273 1274 #define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x104) 1275 /* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1276 /*description: */ 1277 #define SENSITIVE_CLK_EN (BIT(0)) 1278 #define SENSITIVE_CLK_EN_M (BIT(0)) 1279 #define SENSITIVE_CLK_EN_V 0x1 1280 #define SENSITIVE_CLK_EN_S 0 1281 1282 #define SENSITIVE_DATE_REG (DR_REG_SENSITIVE_BASE + 0xFFC) 1283 /* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905090 ; */ 1284 /*description: */ 1285 #define SENSITIVE_DATE 0x0FFFFFFF 1286 #define SENSITIVE_DATE_M ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S)) 1287 #define SENSITIVE_DATE_V 0xFFFFFFF 1288 #define SENSITIVE_DATE_S 0 1289 1290 #ifdef __cplusplus 1291 } 1292 #endif 1293 1294 #endif /*_SOC_SENSITIVE_REG_H_ */ 1295
