1 /* SPDX-License-Identifier: Apache-2.0 */
2 /*
3  * Copyright (c) 2023 Intel Corporation
4  *
5  * Author: Adrian Warecki <adrian.warecki@intel.com>
6  */
7 
8 #ifndef __INTEL_DAI_DRIVER_DMIC_REGS_ACE1X_H__
9 #define __INTEL_DAI_DRIVER_DMIC_REGS_ACE1X_H__
10 
11 /* Digital Mic Shim Registers */
12 
13 /* Digital Microphone Link Capability */
14 #define DMICLCAP_OFFSET				0x00
15 
16 /* Link Count */
17 #define DMICLCAP_LCOUNT				GENMASK(2, 0)
18 
19 /* Cross Link Type Sync Supported */
20 #define DMICLCAP_CLTSS				BIT(5)
21 
22 /* Link Synchronization Supported */
23 #define DMICLCAP_LSS				BIT(6)
24 
25 /* Stream Channel Mapping Supported */
26 #define DMICLCAP_SCMS				BIT(7)
27 
28 /* Master Link Clock Select */
29 #define DMICLCAP_MLCS				BIT(8)
30 
31 /* PREQ/WakeUp */
32 #define DMICLCAP_PW				BIT(26)
33 
34 /* Owner Select */
35 #define DMICLCAP_OSEL				BIT(27)
36 
37 /* Power Gating Domain */
38 #define DMICLCAP_PGD				GENMASK(30, 28)
39 
40 
41 /* Digital Microphone IP Pointer */
42 #define DMICIPPTR_OFFSET			0x08
43 
44 /* IP Pointer */
45 #define DMICIPPTR_PTR				GENMASK(20, 0)
46 
47 /* IP Version */
48 #define DMICIPPTR_VER				GENMASK(23, 21)
49 
50 
51 /* Digital Microphone Synchronization */
52 #define DMICSYNC_OFFSET				0x0C
53 
54 /* DMIC Sync Period */
55 #define DMICSYNC_SYNCPRD			GENMASK(14, 0)
56 
57 /* Sync Period Update */
58 #define DMICSYNC_SYNCPU				BIT(15)
59 
60 /* Command Sync */
61 #define DMICSYNC_CMDSYNC			BIT(16)
62 
63 /* Sync Go */
64 #define DMICSYNC_SYNCGO				BIT(24)
65 
66 /* Extended Sync Period */
67 #define DMICSYNC_ESYNCPRD			BIT(25)
68 
69 
70 /* Digital Microphone PCM Stream Capabilities */
71 #define DMICPCMSCAP_OFFSET			0x10
72 
73 /* Number of Input Streams Supported */
74 #define DMICPCMSCAP_ISS				GENMASK(3, 0)
75 
76 /* Number of Output Streams Supported */
77 #define DMICPCMSCAP_OSS				GENMASK(7, 4)
78 
79 /* Number of Bidirectional Streams Supported */
80 #define DMICPCMSCAP_BSS				GENMASK(12, 8)
81 
82 
83 /* Digital Microphone PCM Stream y Channel Map
84  *
85  * Offset: 12h + 02h * y
86  */
87 #define DMICPCMSyCM_OFFSET			0x12
88 #define DMICPCMSyCM_SIZE			0x02
89 
90 /* Lowest Channel */
91 #define DMICPCMSyCM_LCHAN			GENMASK(3, 0)
92 
93 /* Highest Channel */
94 #define DMICPCMSyCM_HCHAN			GENMASK(7, 4)
95 
96 /* Stream */
97 #define DMICPCMSyCM_STRM			GENMASK(13, 8)
98 
99 
100 /* Digital Microphone PCM Stream y Channel Count
101  *
102  * Offset: 18h + 02h * y
103  */
104 #define DMICPCMSyCHC_OFFSET			0x18
105 #define DMICPCMSyCHC_SIZE			0x02
106 
107 /* Number of Channel Supported */
108 #define DMICPCMSyCHC_CS				GENMASK(3, 0)
109 
110 
111 /* Digital Microphone Port y PDM SoundWire Map
112  *
113  * Offset: 20h + y * 02h
114  */
115 #define DMICPyPDMSM_OFFSET			0x20
116 #define DMICPyPDMSM_SIZE			0x02
117 
118 /* Left Channel SoundWire Bus Segment */
119 #define DMICPyPDMSM_LCSBS			GENMASK(1, 0)
120 
121 /* Right Channel SoundWire Bus Segment */
122 #define DMICPyPDMSM_RCSBS			GENMASK(3, 2)
123 
124 /* SoundWire Select */
125 #define DMICPyPDMSM_SNDWSEL			BIT(4)
126 
127 /* Stereo */
128 #define DMICPyPDMSM_STR				BIT(5)
129 
130 /* DMIC Link Control
131  *
132  * This register controls the specific link.
133  */
134 #define DMICLCTL_OFFSET		0x04
135 
136 /* Set Power Active */
137 #define DMICLCTL_SPA				BIT(0)
138 
139 /* Current Power Active */
140 #define DMICLCTL_CPA				BIT(8)
141 
142 /* Owner Select */
143 #define DMICLCTL_OSEL				GENMASK(25, 24)
144 
145 /* Force Clock Gating */
146 #define DMICLCTL_FCG				BIT(26)
147 
148 /* Master Link Clock Select */
149 #define DMICLCTL_MLCS				GENMASK(29, 27)
150 
151 /* Dynamic Clock Gating Disable */
152 #define DMICLCTL_DCGD				BIT(30)
153 
154 /* Idle Clock Gating Disable */
155 #define DMICLCTL_ICGD				BIT(31)
156 
157 #endif /* ! __INTEL_DAI_DRIVER_DMIC_REGS_ACE1X_H__ */
158