1 /** 2 ****************************************************************************** 3 * @file stm32f0xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F0xx_HAL_DMA_H 21 #define __STM32F0xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f0xx_hal_def.h" 29 30 /** @addtogroup STM32F0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief DMA Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 50 from memory to memory or from peripheral to memory. 51 This parameter can be a value of @ref DMA_Data_transfer_direction */ 52 53 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 54 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 55 56 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 57 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 58 59 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 60 This parameter can be a value of @ref DMA_Peripheral_data_size */ 61 62 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 63 This parameter can be a value of @ref DMA_Memory_data_size */ 64 65 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 66 This parameter can be a value of @ref DMA_mode 67 @note The circular buffer mode cannot be used if the memory-to-memory 68 data transfer is configured on the selected Channel */ 69 70 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 71 This parameter can be a value of @ref DMA_Priority_level */ 72 } DMA_InitTypeDef; 73 74 /** 75 * @brief HAL DMA State structures definition 76 */ 77 typedef enum 78 { 79 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 80 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 81 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 82 HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ 83 } HAL_DMA_StateTypeDef; 84 85 /** 86 * @brief HAL DMA Error Code structure definition 87 */ 88 typedef enum 89 { 90 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 91 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 92 } HAL_DMA_LevelCompleteTypeDef; 93 94 /** 95 * @brief HAL DMA Callback ID structure definition 96 */ 97 typedef enum 98 { 99 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 100 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 101 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 102 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 103 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 104 105 } HAL_DMA_CallbackIDTypeDef; 106 107 /** 108 * @brief DMA handle Structure definition 109 */ 110 typedef struct __DMA_HandleTypeDef 111 { 112 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 113 114 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 115 116 HAL_LockTypeDef Lock; /*!< DMA locking object */ 117 118 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 119 120 void *Parent; /*!< Parent object state */ 121 122 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 123 124 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ 125 126 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 127 128 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ 129 130 __IO uint32_t ErrorCode; /*!< DMA Error code */ 131 132 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 133 134 uint32_t ChannelIndex; /*!< DMA Channel Index */ 135 } DMA_HandleTypeDef; 136 137 /** 138 * @} 139 */ 140 141 /* Exported constants --------------------------------------------------------*/ 142 143 /** @defgroup DMA_Exported_Constants DMA Exported Constants 144 * @{ 145 */ 146 147 /** @defgroup DMA_Error_Code DMA Error Code 148 * @{ 149 */ 150 #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ 151 #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ 152 #define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */ 153 #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ 154 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ 155 /** 156 * @} 157 */ 158 159 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 160 * @{ 161 */ 162 #define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ 163 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ 164 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ 165 166 /** 167 * @} 168 */ 169 170 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 171 * @{ 172 */ 173 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ 174 #define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */ 175 /** 176 * @} 177 */ 178 179 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 180 * @{ 181 */ 182 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ 183 #define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */ 184 /** 185 * @} 186 */ 187 188 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 189 * @{ 190 */ 191 #define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */ 192 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ 193 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ 194 /** 195 * @} 196 */ 197 198 /** @defgroup DMA_Memory_data_size DMA Memory data size 199 * @{ 200 */ 201 #define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */ 202 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ 203 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ 204 /** 205 * @} 206 */ 207 208 /** @defgroup DMA_mode DMA mode 209 * @{ 210 */ 211 #define DMA_NORMAL (0x00000000U) /*!< Normal Mode */ 212 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ 213 /** 214 * @} 215 */ 216 217 /** @defgroup DMA_Priority_level DMA Priority level 218 * @{ 219 */ 220 #define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */ 221 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ 222 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ 223 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ 224 /** 225 * @} 226 */ 227 228 229 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 230 * @{ 231 */ 232 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) 233 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) 234 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) 235 /** 236 * @} 237 */ 238 239 /** @defgroup DMA_flag_definitions DMA flag definitions 240 * @{ 241 */ 242 243 #define DMA_FLAG_GL1 (0x00000001U) /*!< Channel 1 global interrupt flag */ 244 #define DMA_FLAG_TC1 (0x00000002U) /*!< Channel 1 transfer complete flag */ 245 #define DMA_FLAG_HT1 (0x00000004U) /*!< Channel 1 half transfer flag */ 246 #define DMA_FLAG_TE1 (0x00000008U) /*!< Channel 1 transfer error flag */ 247 #define DMA_FLAG_GL2 (0x00000010U) /*!< Channel 2 global interrupt flag */ 248 #define DMA_FLAG_TC2 (0x00000020U) /*!< Channel 2 transfer complete flag */ 249 #define DMA_FLAG_HT2 (0x00000040U) /*!< Channel 2 half transfer flag */ 250 #define DMA_FLAG_TE2 (0x00000080U) /*!< Channel 2 transfer error flag */ 251 #define DMA_FLAG_GL3 (0x00000100U) /*!< Channel 3 global interrupt flag */ 252 #define DMA_FLAG_TC3 (0x00000200U) /*!< Channel 3 transfer complete flag */ 253 #define DMA_FLAG_HT3 (0x00000400U) /*!< Channel 3 half transfer flag */ 254 #define DMA_FLAG_TE3 (0x00000800U) /*!< Channel 3 transfer error flag */ 255 #define DMA_FLAG_GL4 (0x00001000U) /*!< Channel 4 global interrupt flag */ 256 #define DMA_FLAG_TC4 (0x00002000U) /*!< Channel 4 transfer complete flag */ 257 #define DMA_FLAG_HT4 (0x00004000U) /*!< Channel 4 half transfer flag */ 258 #define DMA_FLAG_TE4 (0x00008000U) /*!< Channel 4 transfer error flag */ 259 #define DMA_FLAG_GL5 (0x00010000U) /*!< Channel 5 global interrupt flag */ 260 #define DMA_FLAG_TC5 (0x00020000U) /*!< Channel 5 transfer complete flag */ 261 #define DMA_FLAG_HT5 (0x00040000U) /*!< Channel 5 half transfer flag */ 262 #define DMA_FLAG_TE5 (0x00080000U) /*!< Channel 5 transfer error flag */ 263 #define DMA_FLAG_GL6 (0x00100000U) /*!< Channel 6 global interrupt flag */ 264 #define DMA_FLAG_TC6 (0x00200000U) /*!< Channel 6 transfer complete flag */ 265 #define DMA_FLAG_HT6 (0x00400000U) /*!< Channel 6 half transfer flag */ 266 #define DMA_FLAG_TE6 (0x00800000U) /*!< Channel 6 transfer error flag */ 267 #define DMA_FLAG_GL7 (0x01000000U) /*!< Channel 7 global interrupt flag */ 268 #define DMA_FLAG_TC7 (0x02000000U) /*!< Channel 7 transfer complete flag */ 269 #define DMA_FLAG_HT7 (0x04000000U) /*!< Channel 7 half transfer flag */ 270 #define DMA_FLAG_TE7 (0x08000000U) /*!< Channel 7 transfer error flag */ 271 272 /** 273 * @} 274 */ 275 276 #if defined(SYSCFG_CFGR1_DMA_RMP) 277 /** @defgroup HAL_DMA_remapping HAL DMA remapping 278 * Elements values convention: 0xYYYYYYYY 279 * - YYYYYYYY : Position in the SYSCFG register CFGR1 280 * @{ 281 */ 282 #define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap 283 0: No remap (ADC DMA requests mapped on DMA channel 1 284 1: Remap (ADC DMA requests mapped on DMA channel 2 */ 285 #define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap 286 0: No remap (USART1_TX DMA request mapped on DMA channel 2 287 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */ 288 #define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap 289 0: No remap (USART1_RX DMA request mapped on DMA channel 3 290 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */ 291 #define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap 292 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3) 293 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */ 294 #define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap 295 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 296 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */ 297 #if defined (STM32F070xB) 298 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only. 299 0: Disabled, need to remap before use 300 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ 301 302 #endif 303 304 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) 305 #define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only 306 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit) 307 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */ 308 #define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only 309 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit) 310 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */ 311 #define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only. 312 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively) 313 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ 314 #define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only. 315 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively) 316 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ 317 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only. 318 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively) 319 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ 320 #define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only. 321 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively) 322 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */ 323 #define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only. 324 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively) 325 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ 326 #define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only. 327 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively) 328 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ 329 #define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only. 330 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4) 331 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */ 332 #endif 333 334 /** 335 * @} 336 */ 337 338 #endif /* SYSCFG_CFGR1_DMA_RMP */ 339 /** 340 * @} 341 */ 342 343 /* Exported macro ------------------------------------------------------------*/ 344 /** @defgroup DMA_Exported_Macros DMA Exported Macros 345 * @{ 346 */ 347 348 /** @brief Reset DMA handle state 349 * @param __HANDLE__ DMA handle. 350 * @retval None 351 */ 352 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 353 354 /** 355 * @brief Enable the specified DMA Channel. 356 * @param __HANDLE__ DMA handle 357 * @retval None 358 */ 359 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 360 361 /** 362 * @brief Disable the specified DMA Channel. 363 * @param __HANDLE__ DMA handle 364 * @retval None 365 */ 366 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 367 368 369 /* Interrupt & Flag management */ 370 371 /** 372 * @brief Enables the specified DMA Channel interrupts. 373 * @param __HANDLE__ DMA handle 374 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 375 * This parameter can be any combination of the following values: 376 * @arg DMA_IT_TC: Transfer complete interrupt mask 377 * @arg DMA_IT_HT: Half transfer complete interrupt mask 378 * @arg DMA_IT_TE: Transfer error interrupt mask 379 * @retval None 380 */ 381 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 382 383 /** 384 * @brief Disables the specified DMA Channel interrupts. 385 * @param __HANDLE__ DMA handle 386 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 387 * This parameter can be any combination of the following values: 388 * @arg DMA_IT_TC: Transfer complete interrupt mask 389 * @arg DMA_IT_HT: Half transfer complete interrupt mask 390 * @arg DMA_IT_TE: Transfer error interrupt mask 391 * @retval None 392 */ 393 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 394 395 /** 396 * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. 397 * @param __HANDLE__ DMA handle 398 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 399 * This parameter can be one of the following values: 400 * @arg DMA_IT_TC: Transfer complete interrupt mask 401 * @arg DMA_IT_HT: Half transfer complete interrupt mask 402 * @arg DMA_IT_TE: Transfer error interrupt mask 403 * @retval The state of DMA_IT (SET or RESET). 404 */ 405 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 406 407 /** 408 * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. 409 * @param __HANDLE__ DMA handle 410 * 411 * @retval The number of remaining data units in the current DMA Channel transfer. 412 */ 413 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 414 415 #if defined(SYSCFG_CFGR1_DMA_RMP) 416 /** @brief DMA remapping enable/disable macros 417 * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping 418 */ 419 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ 420 SYSCFG->CFGR1 |= (__DMA_REMAP__); \ 421 }while(0) 422 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ 423 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ 424 }while(0) 425 #endif /* SYSCFG_CFGR1_DMA_RMP */ 426 427 /** 428 * @} 429 */ 430 431 /* Include DMA HAL Extension module */ 432 #include "stm32f0xx_hal_dma_ex.h" 433 434 /* Exported functions --------------------------------------------------------*/ 435 /** @addtogroup DMA_Exported_Functions 436 * @{ 437 */ 438 439 /** @addtogroup DMA_Exported_Functions_Group1 440 * @{ 441 */ 442 /* Initialization and de-initialization functions *****************************/ 443 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 444 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 445 /** 446 * @} 447 */ 448 449 /** @addtogroup DMA_Exported_Functions_Group2 450 * @{ 451 */ 452 /* Input and Output operation functions *****************************************************/ 453 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 454 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 455 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 456 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 457 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); 458 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 459 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 460 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 461 462 /** 463 * @} 464 */ 465 466 /** @addtogroup DMA_Exported_Functions_Group3 467 * @{ 468 */ 469 /* Peripheral State and Error functions ***************************************/ 470 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 471 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 472 /** 473 * @} 474 */ 475 476 /** 477 * @} 478 */ 479 480 /** @addtogroup DMA_Private_Macros 481 * @{ 482 */ 483 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 484 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 485 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 486 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 487 ((STATE) == DMA_PINC_DISABLE)) 488 489 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 490 ((STATE) == DMA_MINC_DISABLE)) 491 492 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 493 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 494 ((SIZE) == DMA_PDATAALIGN_WORD)) 495 496 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 497 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 498 ((SIZE) == DMA_MDATAALIGN_WORD )) 499 500 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 501 ((MODE) == DMA_CIRCULAR)) 502 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 503 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 504 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 505 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 506 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 507 508 #if defined(SYSCFG_CFGR1_DMA_RMP) 509 510 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) 511 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ 512 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ 513 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ 514 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ 515 ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \ 516 ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \ 517 ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \ 518 ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \ 519 ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \ 520 ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ 521 ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \ 522 ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \ 523 ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \ 524 ((RMP) == DMA_REMAP_TIM3_DMA_CH6)) 525 #elif defined (STM32F070xB) 526 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ 527 ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ 528 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ 529 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ 530 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ 531 ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) 532 #else 533 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ 534 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ 535 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ 536 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ 537 ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) 538 #endif 539 540 #endif /* SYSCFG_CFGR1_DMA_RMP */ 541 542 543 /** 544 * @} 545 */ 546 547 /** 548 * @} 549 */ 550 551 /** 552 * @} 553 */ 554 555 #ifdef __cplusplus 556 } 557 #endif 558 559 #endif /* __STM32F0xx_HAL_DMA_H */ 560 561 562
