1 /****************************************************************************** 2 * Filename: hw_dma_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_DMA_H__ 34 #define __HW_DMA_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // DMA component 40 // 41 //***************************************************************************** 42 // Status Register. 43 #define DMA_O_STATUS 0x00000000U 44 45 // Configuration Register. 46 #define DMA_O_CFG 0x00000004U 47 48 // Channel Control Data Base Pointer Register. 49 #define DMA_O_CTRL 0x00000008U 50 51 // Channel Alternate Control Data Base Pointer Register. 52 #define DMA_O_ALTCTRL 0x0000000CU 53 54 // Channel Wait On Request Status Register. 55 #define DMA_O_WAITONREQ 0x00000010U 56 57 // Channel Software Request Register. 58 #define DMA_O_SOFTREQ 0x00000014U 59 60 // Channel Set UseBurst Register. 61 #define DMA_O_SETBURST 0x00000018U 62 63 // Channel Clear UseBurst Register. 64 #define DMA_O_CLEARBURST 0x0000001CU 65 66 // Channel Set Request Mask Register. 67 #define DMA_O_SETREQMASK 0x00000020U 68 69 // Clear Channel Request Mask Register. 70 #define DMA_O_CLEARREQMASK 0x00000024U 71 72 // Set Channel Enable Register. 73 #define DMA_O_SETCHANNELEN 0x00000028U 74 75 // Clear Channel Enable Register. 76 #define DMA_O_CLEARCHANNELEN 0x0000002CU 77 78 // Channel Set Primary-Alternate Register. 79 #define DMA_O_SETCHNLPRIALT 0x00000030U 80 81 // Channel Clear Primary-Alternate Register. 82 #define DMA_O_CLEARCHNLPRIALT 0x00000034U 83 84 // Set Channel Priority Register. 85 #define DMA_O_SETCHNLPRIORITY 0x00000038U 86 87 // Clear Channel Priority Register. 88 #define DMA_O_CLEARCHNLPRIORITY 0x0000003CU 89 90 // Error Status and Clear Register. 91 #define DMA_O_ERROR 0x0000004CU 92 93 // Channel Request Done Register. 94 #define DMA_O_REQDONE 0x00000504U 95 96 // Channel Request Done Mask Register. 97 #define DMA_O_DONEMASK 0x00000520U 98 99 //***************************************************************************** 100 // 101 // Register: DMA_O_STATUS 102 // 103 //***************************************************************************** 104 // Field: [31:28] TEST 105 // 106 // 107 // 0x0: Controller does not include the integration test logic 108 // 0x1: Controller includes the integration test logic 109 // 0x2: Undefined 110 // ... 111 // 0xF: Undefined 112 #define DMA_STATUS_TEST_W 4U 113 #define DMA_STATUS_TEST_M 0xF0000000U 114 #define DMA_STATUS_TEST_S 28U 115 116 // Field: [20:16] TOTALCHANNELS 117 // 118 // Register value returns number of available uDMA channels minus one. For 119 // example a read out value of: 120 // 121 // 0x00: Show that the controller is configured to use 1 uDMA channel 122 // 0x01: Shows that the controller is configured to use 2 uDMA channels 123 // ... 124 // 0x1F: Shows that the controller is configured to use 32 uDMA channels 125 // (32-1=31=0x1F) 126 #define DMA_STATUS_TOTALCHANNELS_W 5U 127 #define DMA_STATUS_TOTALCHANNELS_M 0x001F0000U 128 #define DMA_STATUS_TOTALCHANNELS_S 16U 129 130 // Field: [7:4] STATE 131 // 132 // Current state of the control state machine. State can be one of the 133 // following: 134 // 135 // 0x0: Idle 136 // 0x1: Reading channel controller data 137 // 0x2: Reading source data end pointer 138 // 0x3: Reading destination data end pointer 139 // 0x4: Reading source data 140 // 0x5: Writing destination data 141 // 0x6: Waiting for uDMA request to clear 142 // 0x7: Writing channel controller data 143 // 0x8: Stalled 144 // 0x9: Done 145 // 0xA: Peripheral scatter-gather transition 146 // 0xB: Undefined 147 // ... 148 // 0xF: Undefined. 149 #define DMA_STATUS_STATE_W 4U 150 #define DMA_STATUS_STATE_M 0x000000F0U 151 #define DMA_STATUS_STATE_S 4U 152 153 // Field: [0] MASTERENABLE 154 // 155 // Shows the enable status of the controller as configured by CFG.MASTERENABLE: 156 // ENUMs: 157 // EN Controller is enabled 158 // DIS Controller is disabled 159 #define DMA_STATUS_MASTERENABLE 0x00000001U 160 #define DMA_STATUS_MASTERENABLE_M 0x00000001U 161 #define DMA_STATUS_MASTERENABLE_S 0U 162 #define DMA_STATUS_MASTERENABLE_EN 0x00000001U 163 #define DMA_STATUS_MASTERENABLE_DIS 0x00000000U 164 165 //***************************************************************************** 166 // 167 // Register: DMA_O_CFG 168 // 169 //***************************************************************************** 170 // Field: [7:5] PRTOCTRL 171 // 172 // Sets the AHB-Lite bus protocol protection state by controlling the AHB 173 // signal HProt[3:1] as follows: 174 // 175 // Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring. 176 // Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring. 177 // Bit [5] Controls HProt[1] to indicate if a privileged access is occurring. 178 // 179 // When bit [n] = 1 then the corresponding HProt bit is high. 180 // When bit [n] = 0 then the corresponding HProt bit is low. 181 // 182 // This field controls HProt[3:1] signal for all transactions initiated by uDMA 183 // except two transactions below: 184 // - the read from the address indicated by source address pointer 185 // - the write to the address indicated by destination address pointer 186 // HProt[3:1] for these two exceptions can be controlled by dedicated fields in 187 // the channel configutation descriptor. 188 #define DMA_CFG_PRTOCTRL_W 3U 189 #define DMA_CFG_PRTOCTRL_M 0x000000E0U 190 #define DMA_CFG_PRTOCTRL_S 5U 191 192 // Field: [0] MASTERENABLE 193 // 194 // Enables the controller. 195 // ENUMs: 196 // EN Enables the controller 197 // DIS Disables the controller 198 #define DMA_CFG_MASTERENABLE 0x00000001U 199 #define DMA_CFG_MASTERENABLE_M 0x00000001U 200 #define DMA_CFG_MASTERENABLE_S 0U 201 #define DMA_CFG_MASTERENABLE_EN 0x00000001U 202 #define DMA_CFG_MASTERENABLE_DIS 0x00000000U 203 204 //***************************************************************************** 205 // 206 // Register: DMA_O_CTRL 207 // 208 //***************************************************************************** 209 // Field: [31:8] BASEPTR 210 // 211 // This register point to the base address for the primary data structures of 212 // each uDMA channel. This is not stored in module, but in system memory, thus 213 // space must be allocated for this usage when uDMA is in usage 214 #define DMA_CTRL_BASEPTR_W 24U 215 #define DMA_CTRL_BASEPTR_M 0xFFFFFF00U 216 #define DMA_CTRL_BASEPTR_S 8U 217 218 //***************************************************************************** 219 // 220 // Register: DMA_O_ALTCTRL 221 // 222 //***************************************************************************** 223 // Field: [31:0] BASEPTR 224 // 225 // This register shows the base address for the alternate data structures and 226 // is calculated by module, thus read only 227 #define DMA_ALTCTRL_BASEPTR_W 32U 228 #define DMA_ALTCTRL_BASEPTR_M 0xFFFFFFFFU 229 #define DMA_ALTCTRL_BASEPTR_S 0U 230 231 //***************************************************************************** 232 // 233 // Register: DMA_O_WAITONREQ 234 // 235 //***************************************************************************** 236 // Field: [7:0] CHNLSTATUS 237 // 238 // Channel wait on request status: 239 // 240 // Bit [Ch] = 0: Once uDMA receives a single or burst request on channel Ch, 241 // this channel may come out of active state even if request is still present. 242 // Bit [Ch] = 1: Once uDMA receives a single or burst request on channel Ch, it 243 // keeps channel Ch in active state until the requests are deasserted. This 244 // handshake is necessary for channels where the requester is in an 245 // asynchronous domain or can run at slower clock speed than uDMA 246 #define DMA_WAITONREQ_CHNLSTATUS_W 8U 247 #define DMA_WAITONREQ_CHNLSTATUS_M 0x000000FFU 248 #define DMA_WAITONREQ_CHNLSTATUS_S 0U 249 250 //***************************************************************************** 251 // 252 // Register: DMA_O_SOFTREQ 253 // 254 //***************************************************************************** 255 // Field: [7:0] CHNLS 256 // 257 // Set the appropriate bit to generate a software uDMA request on the 258 // corresponding uDMA channel 259 // 260 // Bit [Ch] = 0: Does not create a uDMA request for channel Ch 261 // Bit [Ch] = 1: Creates a uDMA request for channel Ch 262 // 263 // Writing to a bit where a uDMA channel is not implemented does not create a 264 // uDMA request for that channel 265 #define DMA_SOFTREQ_CHNLS_W 8U 266 #define DMA_SOFTREQ_CHNLS_M 0x000000FFU 267 #define DMA_SOFTREQ_CHNLS_S 0U 268 269 //***************************************************************************** 270 // 271 // Register: DMA_O_SETBURST 272 // 273 //***************************************************************************** 274 // Field: [7:0] CHNLS 275 // 276 // Returns the useburst status, or disables individual channels from generating 277 // single uDMA requests. The value R is the arbitration rate and stored in the 278 // controller data structure. 279 // 280 // Read as: 281 // 282 // Bit [Ch] = 0: uDMA channel Ch responds to both burst and single requests on 283 // channel Ch. The controller performs 2^R, or single, bus transfers. 284 // 285 // Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer requests. 286 // The controller only responds to burst transfer requests and performs 2^R 287 // transfers. 288 // 289 // Write as: 290 // Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0. 291 // Bit [Ch] = 1: Disables single transfer requests on channel Ch. The 292 // controller performs 2^R transfers for burst requests. 293 // 294 // Writing to a bit where a uDMA channel is not implemented has no effect 295 #define DMA_SETBURST_CHNLS_W 8U 296 #define DMA_SETBURST_CHNLS_M 0x000000FFU 297 #define DMA_SETBURST_CHNLS_S 0U 298 299 //***************************************************************************** 300 // 301 // Register: DMA_O_CLEARBURST 302 // 303 //***************************************************************************** 304 // Field: [7:0] CHNLS 305 // 306 // Set the appropriate bit to enable single transfer requests. 307 // 308 // Write as: 309 // 310 // Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer 311 // requests. 312 // 313 // Bit [Ch] = 1: Enables single transfer requests on channel Ch. 314 // 315 // Writing to a bit where a uDMA channel is not implemented has no effect. 316 #define DMA_CLEARBURST_CHNLS_W 8U 317 #define DMA_CLEARBURST_CHNLS_M 0x000000FFU 318 #define DMA_CLEARBURST_CHNLS_S 0U 319 320 //***************************************************************************** 321 // 322 // Register: DMA_O_SETREQMASK 323 // 324 //***************************************************************************** 325 // Field: [7:0] CHNLS 326 // 327 // Returns the burst and single request mask status, or disables the 328 // corresponding channel from generating uDMA requests. 329 // 330 // Read as: 331 // Bit [Ch] = 0: External requests are enabled for channel Ch. 332 // Bit [Ch] = 1: External requests are disabled for channel Ch. 333 // 334 // Write as: 335 // Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable uDMA requests. 336 // Bit [Ch] = 1: Disables uDMA burst request channel [Ch] and uDMA single 337 // request channel [Ch] input from generating uDMA requests. 338 // 339 // Writing to a bit where a uDMA channel is not implemented has no effect 340 #define DMA_SETREQMASK_CHNLS_W 8U 341 #define DMA_SETREQMASK_CHNLS_M 0x000000FFU 342 #define DMA_SETREQMASK_CHNLS_S 0U 343 344 //***************************************************************************** 345 // 346 // Register: DMA_O_CLEARREQMASK 347 // 348 //***************************************************************************** 349 // Field: [7:0] CHNLS 350 // 351 // Set the appropriate bit to enable uDMA request for the channel. 352 // 353 // Write as: 354 // Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel Ch from 355 // generating requests. 356 // Bit [Ch] = 1: Enables channel [Ch] to generate uDMA requests. 357 // 358 // Writing to a bit where a uDMA channel is not implemented has no effect. 359 #define DMA_CLEARREQMASK_CHNLS_W 8U 360 #define DMA_CLEARREQMASK_CHNLS_M 0x000000FFU 361 #define DMA_CLEARREQMASK_CHNLS_S 0U 362 363 //***************************************************************************** 364 // 365 // Register: DMA_O_SETCHANNELEN 366 // 367 //***************************************************************************** 368 // Field: [7:0] CHNLS 369 // 370 // Returns the enable status of the channels, or enable the corresponding 371 // channels. 372 // 373 // Read as: 374 // Bit [Ch] = 0: Channel Ch is disabled. 375 // Bit [Ch] = 1: Channel Ch is enabled. 376 // 377 // Write as: 378 // Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel 379 // Bit [Ch] = 1: Enables channel Ch 380 // 381 // Writing to a bit where a uDMA channel is not implemented has no effect 382 #define DMA_SETCHANNELEN_CHNLS_W 8U 383 #define DMA_SETCHANNELEN_CHNLS_M 0x000000FFU 384 #define DMA_SETCHANNELEN_CHNLS_S 0U 385 386 //***************************************************************************** 387 // 388 // Register: DMA_O_CLEARCHANNELEN 389 // 390 //***************************************************************************** 391 // Field: [7:0] CHNLS 392 // 393 // Set the appropriate bit to disable the corresponding uDMA channel. 394 // 395 // Write as: 396 // Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable uDMA channels. 397 // Bit [Ch] = 1: Disables channel Ch 398 // 399 // Writing to a bit where a uDMA channel is not implemented has no effect 400 #define DMA_CLEARCHANNELEN_CHNLS_W 8U 401 #define DMA_CLEARCHANNELEN_CHNLS_M 0x000000FFU 402 #define DMA_CLEARCHANNELEN_CHNLS_S 0U 403 404 //***************************************************************************** 405 // 406 // Register: DMA_O_SETCHNLPRIALT 407 // 408 //***************************************************************************** 409 // Field: [7:0] CHNLS 410 // 411 // Returns the channel control data structure status, or selects the alternate 412 // data structure for the corresponding uDMA channel. 413 // 414 // Read as: 415 // Bit [Ch] = 0: uDMA channel Ch is using the primary data structure. 416 // Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure. 417 // 418 // Write as: 419 // Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel 420 // Bit [Ch] = 1: Selects the alternate data structure for channel Ch 421 // 422 // Writing to a bit where a uDMA channel is not implemented has no effect 423 #define DMA_SETCHNLPRIALT_CHNLS_W 8U 424 #define DMA_SETCHNLPRIALT_CHNLS_M 0x000000FFU 425 #define DMA_SETCHNLPRIALT_CHNLS_S 0U 426 427 //***************************************************************************** 428 // 429 // Register: DMA_O_CLEARCHNLPRIALT 430 // 431 //***************************************************************************** 432 // Field: [7:0] CHNLS 433 // 434 // Clears the appropriate bit to select the primary data structure for the 435 // corresponding uDMA channel. 436 // 437 // Write as: 438 // Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate 439 // data structure. 440 // Bit [Ch] = 1: Selects the primary data structure for channel Ch. 441 // 442 // Writing to a bit where a uDMA channel is not implemented has no effect 443 #define DMA_CLEARCHNLPRIALT_CHNLS_W 8U 444 #define DMA_CLEARCHNLPRIALT_CHNLS_M 0x000000FFU 445 #define DMA_CLEARCHNLPRIALT_CHNLS_S 0U 446 447 //***************************************************************************** 448 // 449 // Register: DMA_O_SETCHNLPRIORITY 450 // 451 //***************************************************************************** 452 // Field: [7:0] CHNLS 453 // 454 // Returns the channel priority mask status, or sets the channel priority to 455 // high. 456 // 457 // Read as: 458 // Bit [Ch] = 0: uDMA channel Ch is using the default priority level. 459 // Bit [Ch] = 1: uDMA channel Ch is using a high priority level. 460 // 461 // Write as: 462 // Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch 463 // to the default priority level. 464 // Bit [Ch] = 1: Channel Ch uses the high priority level. 465 // 466 // Writing to a bit where a uDMA channel is not implemented has no effect 467 #define DMA_SETCHNLPRIORITY_CHNLS_W 8U 468 #define DMA_SETCHNLPRIORITY_CHNLS_M 0x000000FFU 469 #define DMA_SETCHNLPRIORITY_CHNLS_S 0U 470 471 //***************************************************************************** 472 // 473 // Register: DMA_O_CLEARCHNLPRIORITY 474 // 475 //***************************************************************************** 476 // Field: [7:0] CHNLS 477 // 478 // Clear the appropriate bit to select the default priority level for the 479 // specified uDMA channel. 480 // 481 // Write as: 482 // Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to 483 // the high priority level. 484 // Bit [Ch] = 1: Channel Ch uses the default priority level. 485 // 486 // Writing to a bit where a uDMA channel is not implemented has no effect 487 #define DMA_CLEARCHNLPRIORITY_CHNLS_W 8U 488 #define DMA_CLEARCHNLPRIORITY_CHNLS_M 0x000000FFU 489 #define DMA_CLEARCHNLPRIORITY_CHNLS_S 0U 490 491 //***************************************************************************** 492 // 493 // Register: DMA_O_ERROR 494 // 495 //***************************************************************************** 496 // Field: [0] STATUS 497 // 498 // Returns the status of bus error flag in uDMA, or clears this bit 499 // 500 // Read as: 501 // 502 // 0: No bus error detected 503 // 1: Bus error detected 504 // 505 // Write as: 506 // 507 // 0: No effect, status of bus error flag is unchanged. 508 // 1: Clears the bus error flag. 509 #define DMA_ERROR_STATUS 0x00000001U 510 #define DMA_ERROR_STATUS_M 0x00000001U 511 #define DMA_ERROR_STATUS_S 0U 512 513 //***************************************************************************** 514 // 515 // Register: DMA_O_REQDONE 516 // 517 //***************************************************************************** 518 // Field: [7:0] CHNLS 519 // 520 // Reflects the uDMA done status for the given channel, channel [Ch]. It's a 521 // sticky done bit. Unless cleared by writing a 1, it holds the value of 1. 522 // 523 // Read as: 524 // Bit [Ch] = 0: Request has not completed for channel Ch 525 // Bit [Ch] = 1: Request has completed for the channel Ch 526 // 527 // Writing a 1 to individual bits would clear the corresponding bit. 528 // 529 // Write as: 530 // Bit [Ch] = 0: No effect. 531 // Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 532 #define DMA_REQDONE_CHNLS_W 8U 533 #define DMA_REQDONE_CHNLS_M 0x000000FFU 534 #define DMA_REQDONE_CHNLS_S 0U 535 536 //***************************************************************************** 537 // 538 // Register: DMA_O_DONEMASK 539 // 540 //***************************************************************************** 541 // Field: [7:0] CHNLS 542 // 543 // Controls the propagation of the uDMA done and active state to the assigned 544 // peripheral. Specifically used for software channels. 545 // 546 // Read as: 547 // Bit [Ch] = 0: uDMA done and active state for channel Ch is not blocked from 548 // reaching to the peripherals. 549 // Note that the uDMA done state for channel [Ch] is blocked from contributing 550 // to generation of combined uDMA done signal 551 // 552 // Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked from 553 // reaching to the peripherals. 554 // Note that the uDMA done state for channel [Ch] is not blocked from 555 // contributing to generation of combined uDMA done signal 556 // 557 // Write as: 558 // Bit [Ch] = 0: Allows uDMA done and active state to propagate to the 559 // peripherals. 560 // Note that this disables uDMA done state for channel [Ch] from contributing 561 // to generation of combined uDMA done signal 562 // 563 // Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the 564 // peripherals. 565 // Note that this enables uDMA done for channel [Ch] to contribute to 566 // generation of combined uDMA done signal. 567 #define DMA_DONEMASK_CHNLS_W 8U 568 #define DMA_DONEMASK_CHNLS_M 0x000000FFU 569 #define DMA_DONEMASK_CHNLS_S 0U 570 571 572 #endif // __DMA__ 573
