1 /* 2 * Copyright 2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GMAC_IP_DEVICE_REGISTERS_H 8 #define GMAC_IP_DEVICE_REGISTERS_H 9 10 /** 11 * @file 12 * 13 * @addtogroup GMAC_DRIVER_CONFIGURATION GMAC Driver Configuration 14 * @{ 15 */ 16 17 #ifdef __cplusplus 18 extern "C"{ 19 #endif 20 21 /*================================================================================================== 22 * INCLUDE FILES 23 * 1) system and project includes 24 * 2) needed interfaces from external units 25 * 3) internal and external interfaces from this unit 26 ==================================================================================================*/ 27 #include "Mcal.h" 28 #include "S32K344_EMAC.h" 29 #include "Emac_Ip_Wrapper.h" 30 #include "S32K344_DCM_GPR.h" 31 /*================================================================================================== 32 * SOURCE FILE VERSION INFORMATION 33 ==================================================================================================*/ 34 #define GMAC_IP_DEVICE_REGISTERS_VENDOR_ID 43 35 #define GMAC_IP_DEVICE_REGISTERS_AR_RELEASE_MAJOR_VERSION 4 36 #define GMAC_IP_DEVICE_REGISTERS_AR_RELEASE_MINOR_VERSION 7 37 #define GMAC_IP_DEVICE_REGISTERS_AR_RELEASE_REVISION_VERSION 0 38 #define GMAC_IP_DEVICE_REGISTERS_SW_MAJOR_VERSION 3 39 #define GMAC_IP_DEVICE_REGISTERS_SW_MINOR_VERSION 0 40 #define GMAC_IP_DEVICE_REGISTERS_SW_PATCH_VERSION 0 41 42 /*================================================================================================== 43 * FILE VERSION CHECKS 44 ==================================================================================================*/ 45 /* Checks against Emac_Ip_Wrapper.h */ 46 #if (GMAC_IP_DEVICE_REGISTERS_VENDOR_ID != EMAC_IP_WRAPPER_VENDOR_ID) 47 #error "Gmac_Ip_Device_Registers.h and Emac_Ip_Wrapper.h have different vendor ids" 48 #endif 49 #if (( GMAC_IP_DEVICE_REGISTERS_AR_RELEASE_MAJOR_VERSION != EMAC_IP_WRAPPER_AR_RELEASE_MAJOR_VERSION) || \ 50 ( GMAC_IP_DEVICE_REGISTERS_AR_RELEASE_MINOR_VERSION != EMAC_IP_WRAPPER_AR_RELEASE_MINOR_VERSION) || \ 51 ( GMAC_IP_DEVICE_REGISTERS_AR_RELEASE_REVISION_VERSION != EMAC_IP_WRAPPER_AR_RELEASE_REVISION_VERSION)) 52 #error "AUTOSAR Version Numbers of Gmac_Ip_Device_Registers.h and Emac_Ip_Wrapper.h are different" 53 #endif 54 #if (( GMAC_IP_DEVICE_REGISTERS_SW_MAJOR_VERSION != EMAC_IP_WRAPPER_SW_MAJOR_VERSION) || \ 55 ( GMAC_IP_DEVICE_REGISTERS_SW_MINOR_VERSION != EMAC_IP_WRAPPER_SW_MINOR_VERSION) || \ 56 ( GMAC_IP_DEVICE_REGISTERS_SW_PATCH_VERSION != EMAC_IP_WRAPPER_SW_PATCH_VERSION)) 57 #error "Software Version Numbers of Gmac_Ip_Device_Registers.h and Emac_Ip_Wrapper.h are different" 58 #endif 59 60 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 61 /* Checks against Mcal.h */ 62 #if ((GMAC_IP_DEVICE_REGISTERS_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \ 63 (GMAC_IP_DEVICE_REGISTERS_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION)) 64 #error "AUTOSAR Version Numbers of Gmac_Ip_Device_Registers.h and Mcal.h are different" 65 #endif 66 #endif 67 /*================================================================================================== 68 CONSTANTS 69 ==================================================================================================*/ 70 71 /*================================================================================================== 72 DEFINES AND MACROS 73 ==================================================================================================*/ 74 75 /** @cond DRIVER_INTERNAL_USE_ONLY */ 76 #define DMA_CH0_CONTROL_ADDR16 0x1100U 77 #define DMA_CH1_CONTROL_ADDR16 0x1180U 78 #define DMA_CH2_CONTROL_ADDR16 0x1200U 79 #define DMA_CH3_CONTROL_ADDR16 0x1280U 80 #define DMA_CH4_CONTROL_ADDR16 0x1300U 81 82 #define MTL_TXQ0_OPERATION_MODE_ADDR16 0x0D00U 83 #define MTL_TXQ1_OPERATION_MODE_ADDR16 0x0D40U 84 #define MTL_TXQ2_OPERATION_MODE_ADDR16 0x0D80U 85 #define MTL_TXQ3_OPERATION_MODE_ADDR16 0x0DC0U 86 #define MTL_TXQ4_OPERATION_MODE_ADDR16 0x0E00U 87 88 typedef struct 89 { 90 volatile uint32 DMA_CONTROL; 91 volatile uint32 DMA_TX_CONTROL; 92 volatile uint32 DMA_RX_CONTROL; 93 volatile uint8 RESERVED_1[8]; 94 volatile uint32 DMA_TXDESC_LIST_ADDRESS; 95 volatile uint8 RESERVED_2[4]; 96 volatile uint32 DMA_RXDESC_LIST_ADDRESS; 97 volatile uint32 DMA_TXDESC_TAIL_POINTER; 98 volatile uint8 RESERVED_3[4]; 99 volatile uint32 DMA_RXDESC_TAIL_POINTER; 100 volatile uint32 DMA_TXDESC_RING_LENGTH; 101 volatile uint32 DMA_RXDESC_RING_LENGTH; 102 volatile uint32 DMA_INTERRUPT_ENABLE; 103 volatile uint32 DMA_RX_INTERRUPT_WATCHDOG_TIMER; 104 volatile uint32 DMA_SLOT_FUNCTION_CONTROL_STATUS; 105 volatile uint8 RESERVED_4[4]; 106 volatile uint32 DMA_CURRENT_APP_TXDESC; 107 volatile uint8 RESERVED_5[4]; 108 volatile uint32 DMA_CURRENT_APP_RXDESC; 109 volatile uint8 RESERVED_6[4]; 110 volatile uint32 DMA_CURRENT_APP_TXBUFFER; 111 volatile uint8 RESERVED_7[4]; 112 volatile uint32 DMA_CURRENT_APP_RXBUFFER; 113 volatile uint32 DMA_STATUS; 114 volatile uint32 DMA_MISS_FRAME_CNT; 115 volatile uint32 DMA_RXP_ACCEPT_CNT; 116 volatile uint32 DMA_RX_ERI_CNT; 117 volatile uint8 RESERVED_8[16]; 118 } Gmac_Ip_ChannelType; 119 /** @endcond */ 120 121 /* @internal @brief Macro for different between header files */ 122 #define MAC_VLAN_TAG_DATA_REG MAC_VLAN_TAG.MAC_VLAN_TAG_DATA 123 #define MAC_VLAN_TAG_CTRL_REG MAC_VLAN.MAC_VLAN_TAG_CTRL 124 #define MAC_VLAN_INCL_REG MAC_VLAN_INCL.MAC_VLAN_INCL 125 126 /* @internal @brief Base addresses for the DMA channels */ 127 #define DEV_REG_GMAC_CH_BASE \ 128 { { \ 129 (Gmac_Ip_ChannelType *)(IP_GMAC_0_BASE + (uint32)DMA_CH0_CONTROL_ADDR16), \ 130 (Gmac_Ip_ChannelType *)(IP_GMAC_0_BASE + (uint32)DMA_CH1_CONTROL_ADDR16) \ 131 } } \ 132 133 134 /** @cond DRIVER_INTERNAL_USE_ONLY */ 135 typedef struct 136 { 137 volatile uint32 MTL_TXQ_OPERATION_MODE; 138 volatile const uint32 MTL_TXQ_UNDERFLOW; 139 volatile const uint32 MTL_TXQ_DEBUG; 140 uint8 RESERVED_1[4]; 141 volatile uint32 MTL_TXQ_ETS_CONTROL; /* Not available for Q0 */ 142 volatile const uint32 MTL_TXQ_ETS_STATUS; 143 volatile uint32 MTL_TXQ_QUANTUM_WEIGHT; 144 volatile uint32 MTL_TXQ_SENDSLOPECREDIT; /* Not available for Q0 */ 145 volatile uint32 MTL_TXQ_HICREDIT; /* Not available for Q0 */ 146 volatile uint32 MTL_TXQ_LOCREDIT; /* Not available for Q0 */ 147 uint8 RESERVED_2[4]; 148 volatile uint32 MTL_Q_INTERRUPT_CONTROL_STATUS; 149 volatile uint32 MTL_RXQ_OPERATION_MODE; 150 volatile const uint32 MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT; 151 volatile const uint32 MTL_RXQ_DEBUG; 152 volatile uint32 MTL_RXQ_CONTROL; 153 } Gmac_Ip_QueueType; 154 /** @endcond */ 155 156 /*! @internal @brief Base addresses for the MTL queues */ 157 #define DEV_REG_GMAC_QUEUE_BASE \ 158 { { \ 159 (Gmac_Ip_QueueType *)(IP_GMAC_0_BASE + (uint32)MTL_TXQ0_OPERATION_MODE_ADDR16), \ 160 (Gmac_Ip_QueueType *)(IP_GMAC_0_BASE + (uint32)MTL_TXQ1_OPERATION_MODE_ADDR16) \ 161 } } \ 162 163 /*================================================================================================== 164 ENUMS 165 ==================================================================================================*/ 166 167 /*================================================================================================== 168 STRUCTURES AND OTHER TYPEDEFS 169 ==================================================================================================*/ 170 171 /*================================================================================================== 172 GLOBAL VARIABLE DECLARATIONS 173 ==================================================================================================*/ 174 175 /*================================================================================================== 176 FUNCTION PROTOTYPES 177 ==================================================================================================*/ 178 179 #ifdef __cplusplus 180 } 181 #endif 182 183 /** @} */ 184 185 #endif /* GMAC_IP_DEVICE_REGISTERS_H */ 186
