1 /* 2 * Copyright (c) 2019-2022 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing software 11 * distributed under the License is distributed on an "AS IS" BASIS 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __PLATFORM_IRQ_H__ 18 #define __PLATFORM_IRQ_H__ 19 20 typedef enum _IRQn_Type { 21 NonMaskableInt_IRQn = -14, /* Non Maskable Interrupt */ 22 HardFault_IRQn = -13, /* HardFault Interrupt */ 23 MemoryManagement_IRQn = -12, /* Memory Management Interrupt */ 24 BusFault_IRQn = -11, /* Bus Fault Interrupt */ 25 UsageFault_IRQn = -10, /* Usage Fault Interrupt */ 26 SecureFault_IRQn = -9, /* Secure Fault Interrupt */ 27 SVCall_IRQn = -5, /* SV Call Interrupt */ 28 DebugMonitor_IRQn = -4, /* Debug Monitor Interrupt */ 29 PendSV_IRQn = -2, /* Pend SV Interrupt */ 30 SysTick_IRQn = -1, /* System Tick Interrupt */ 31 NONSEC_WATCHDOG_RESET_REQ_IRQn = 0, /* Non-Secure Watchdog Reset 32 * Request Interrupt 33 */ 34 NONSEC_WATCHDOG_IRQn = 1, /* Non-Secure Watchdog Interrupt */ 35 SLOWCLK_TIMER_IRQn = 2, /* SLOWCLK Timer Interrupt */ 36 TIMER0_IRQn = 3, /* TIMER 0 Interrupt */ 37 TIMER1_IRQn = 4, /* TIMER 1 Interrupt */ 38 TIMER2_IRQn = 5, /* TIMER 2 Interrupt */ 39 /* Reserved = 6:8, Reserved */ 40 MPC_IRQn = 9, /* MPC Combined (Secure) Interrupt */ 41 PPC_IRQn = 10, /* PPC Combined (Secure) Interrupt */ 42 MSC_IRQn = 11, /* MSC Combined (Secure) Interrput */ 43 BRIDGE_ERROR_IRQn = 12, /* Bridge Error Combined (Secure) Interrupt */ 44 /* Reserved = 13, Reserved */ 45 PPU_Combined_IRQn = 14, /* PPU Combined (Secure) Interrupt */ 46 /* Reserved = 15, Reserved */ 47 NPU0_IRQn = 16, /* NPU0 Interrupt */ 48 NPU1_IRQn = 17, /* NPU1 Interrupt */ 49 NPU2_IRQn = 18, /* NPU2 Interrupt */ 50 NPU3_IRQn = 19, /* NPU3 Interrupt */ 51 KMU_S_IRQn = 20, /* KMU (Secure) Interrupt */ 52 /* Reserved = 21:23, Reserved */ 53 DMA_Combined_S_IRQn = 24, /* DMA350 Combined (Secure) Interrupt */ 54 DMA_Combined_NS_IRQn = 25, /* DMA350 Combined (Non-Secure) Interrupt */ 55 DMA_Security_Violation_IRQn = 26, /* DMA350 Security Violation Interrupt */ 56 TIMER3_AON_IRQn = 27, /* TIMER 3 AON Interrupt */ 57 CPU0_CTI_0_IRQn = 28, /* CPU0 CTI IRQ 0 Interrupt */ 58 CPU0_CTI_1_IRQn = 29, /* CPU0 CTI IRQ 1 Interrupt */ 59 /* Reserved = 30:31, Reserved */ 60 SAM_Critical_Sec_Fault_S_IRQn = 32, /* SAM Critical Security Fault (Secure) Interrupt */ 61 SAM_Sec_Fault_S_IRQn = 33, /* SAM Security Fault (Secure) Interrupt */ 62 GPIO_Combined_S_IRQn = 34, /* GPIO Combined (Secure) Interrupt */ 63 SDC_IRQn = 35, /* Secure Debug channel Interrupt */ 64 FPU_IRQn = 36, /* FPU Exceptions */ 65 SRAM_TRAM_ECC_Err_Combined_S_IRQn = 37, 66 /* SRAM and TRAM Corrected ECC Error Combined (Secure) Interrupt */ 67 SIC_S_IRQn = 38, /* SICache (Secure) Interrupt */ 68 ATU_S_IRQn = 39, /* ATU (Secure) Interrupt */ 69 CMU_MHU0_Sender_IRQn = 40, /* CMU MHU0 Sender Interrupt */ 70 CMU_MHU0_Receiver_IRQn = 41, /* CMU MHU0 Receiver Interrupt */ 71 CMU_MHU1_Sender_IRQn = 42, /* CMU MHU1 Sender Interrupt */ 72 CMU_MHU1_Receiver_IRQn = 43, /* CMU MHU1 Receiver Interrupt */ 73 CMU_MHU2_Sender_IRQn = 44, /* CMU MHU2 Sender Interrupt */ 74 CMU_MHU2_Receiver_IRQn = 45, /* CMU MHU2 Receiver Interrupt */ 75 CMU_MHU3_Sender_IRQn = 46, /* CMU MHU3 Sender Interrupt */ 76 CMU_MHU3_Receiver_IRQn = 47, /* CMU MHU3 Receiver Interrupt */ 77 CMU_MHU4_Sender_IRQn = 48, /* CMU MHU4 Sender Interrupt */ 78 CMU_MHU4_Receiver_IRQn = 49, /* CMU MHU4 Receiver Interrupt */ 79 CMU_MHU5_Sender_IRQn = 50, /* CMU MHU5 Sender Interrupt */ 80 CMU_MHU5_Receiver_IRQn = 51, /* CMU MHU5 Receiver Interrupt */ 81 CMU_MHU6_Sender_IRQn = 52, /* CMU MHU6 Sender Interrupt */ 82 CMU_MHU6_Receiver_IRQn = 53, /* CMU MHU6 Receiver Interrupt */ 83 CMU_MHU7_Sender_IRQn = 54, /* CMU MHU7 Sender Interrupt */ 84 CMU_MHU7_Receiver_IRQn = 55, /* CMU MHU7 Receiver Interrupt */ 85 CMU_MHU8_Sender_IRQn = 56, /* CMU MHU8 Sender Interrupt */ 86 CMU_MHU8_Receiver_IRQn = 57, /* CMU MHU8 Receiver Interrupt */ 87 Crypto_Engine_S_IRQn = 58, /* Crypto Engine (Secure) Interrupt */ 88 SoC_System_Timer0_AON_IRQn = 59, /* SoC System Timer 0 AON Interrupt */ 89 SoC_System_Timer1_AON_IRQn = 60, /* SoC System Timer 1 AON Interrupt */ 90 /* Reserved = 61:95, Reserved */ 91 } IRQn_Type; 92 93 #endif /* __PLATFORM_IRQ_H__ */ 94
