DMA_CHX_INT_EN (definition) in projects: hal_nxp-3.5.0

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Searched defs:DMA_CHX_INT_EN (Results 1 – 25 of 27) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54016/
D	LPC54016.h	`4776 …__IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54618/
D	LPC54618.h	`5338 …__IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54616/
D	LPC54616.h	`5340 …__IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54018M/
D	LPC54018M.h	`5132 …__IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54018/
D	LPC54018.h	`5132 …__IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54606/
D	LPC54606.h	`5265 …__IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54608/
D	LPC54608.h	`5261 …__IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S018M/
D	LPC54S018M.h	`5540 …__IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S016/
D	LPC54S016.h	`5141 …__IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54628/
D	LPC54628.h	`5336 …__IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S018/
D	LPC54S018.h	`5540 …__IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1175/
D	MIMXRT1175_cm7.h	`36117 …__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interr… member`
D	MIMXRT1175_cm4.h	`36115 …__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interr… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1171/
D	MIMXRT1171.h	`36117 …__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interr… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1173/
D	MIMXRT1173_cm4.h	`38119 …__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interr… member`
D	MIMXRT1173_cm7.h	`38121 …__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interr… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1176/
D	MIMXRT1176_cm4.h	`38122 …__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interr… member`
D	MIMXRT1176_cm7.h	`38124 …__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interr… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1172/
D	MIMXRT1172.h	`38124 …__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interr… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/
D	MIMX9352_cm33.h	`22834 …__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interrupt Enable, array o… member`
D	MIMX9352_ca55.h	`20473 …__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interr… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML8/
D	MIMX8ML8_ca53.h	`34094 …__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interr… member`
D	MIMX8ML8_dsp.h	`32485 …__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interr… member`
D	MIMX8ML8_cm7.h	`34068 …__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interr… member`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML6/
D	MIMX8ML6_cm7.h	`34068 …__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interr… member`

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TraceRecorderSource-3.4.0
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