1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 57 /* ---------------------------------------------------------------------------- 58 -- MCU activation 59 ---------------------------------------------------------------------------- */ 60 61 /* Prevention from multiple including the same memory map */ 62 #if !defined(S32K344_COMMON_H_) /* Check if memory map has not been already included */ 63 #define S32K344_COMMON_H_ 64 #define MCU_S32K344 65 66 /* Check if another memory map has not been also included */ 67 #if (defined(MCU_ACTIVE)) 68 #error S32K344 memory map: There is already included another memory map. Only one memory map can be included. 69 #endif /* (defined(MCU_ACTIVE)) */ 70 #define MCU_ACTIVE 71 72 #include "BasicTypes.h" 73 74 /** Memory map major version (memory maps with equal major version number are 75 * compatible) */ 76 #define MCU_MEM_MAP_VERSION 0x0100U 77 /** Memory map minor version */ 78 #define MCU_MEM_MAP_VERSION_MINOR 0x0009U 79 80 /* ---------------------------------------------------------------------------- 81 -- Generic macros 82 ---------------------------------------------------------------------------- */ 83 84 /* IO definitions (access restrictions to peripheral registers) */ 85 /** 86 * IO Type Qualifiers are used 87 * \li to specify the access to peripheral variables. 88 * \li for automatic generation of peripheral register debug information. 89 */ 90 #ifndef __IO 91 #ifdef __cplusplus 92 #define __I volatile /*!< Defines 'read only' permissions */ 93 #else 94 #define __I volatile const /*!< Defines 'read only' permissions */ 95 #endif 96 #define __O volatile /*!< Defines 'write only' permissions */ 97 #define __IO volatile /*!< Defines 'read / write' permissions */ 98 #endif 99 100 101 /** 102 * @brief 32 bits memory read macro. 103 */ 104 #if !defined(REG_READ32) 105 #define REG_READ32(address) (*(volatile uint32_t*)(address)) 106 #endif 107 108 /** 109 * @brief 32 bits memory write macro. 110 */ 111 #if !defined(REG_WRITE32) 112 #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value)) 113 #endif 114 115 /** 116 * @brief 32 bits bits setting macro. 117 */ 118 #if !defined(REG_BIT_SET32) 119 #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask)) 120 #endif 121 122 /** 123 * @brief 32 bits bits clearing macro. 124 */ 125 #if !defined(REG_BIT_CLEAR32) 126 #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask)))) 127 #endif 128 129 /** 130 * @brief 32 bit clear bits and set with new value 131 * @note It is user's responsability to make sure that value has only "mask" bits set - (value&~mask)==0 132 */ 133 #if !defined(REG_RMW32) 134 #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value))))) 135 #endif 136 137 138 /* ---------------------------------------------------------------------------- 139 -- Interrupt vector numbers 140 ---------------------------------------------------------------------------- */ 141 142 /*! 143 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 144 * @{ 145 */ 146 147 /** Interrupt Number Definitions */ 148 #define NUMBER_OF_INT_VECTORS 229 /**< Number of interrupts in the Vector table */ 149 150 typedef enum { 151 /* Auxiliary constants */ 152 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 153 154 /* Core interrupts */ 155 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 156 HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */ 157 MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */ 158 BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */ 159 UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */ 160 SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */ 161 DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */ 162 PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */ 163 SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */ 164 165 /* Device specific interrupts */ 166 INT0_IRQn = 0, /**< CPU to CPU int0 */ 167 INT1_IRQn = 1, /**< CPU to CPU int1 */ 168 INT2_IRQn = 2, /**< CPU to CPU int2 */ 169 INT3_IRQn = 3, /**< CPU to CPU int3 */ 170 DMATCD0_IRQn = 4, /**< DMA transfer complete and error CH0 */ 171 DMATCD1_IRQn = 5, /**< DMA transfer complete and error CH1 */ 172 DMATCD2_IRQn = 6, /**< DMA transfer complete and error CH2 */ 173 DMATCD3_IRQn = 7, /**< DMA transfer complete and error CH3 */ 174 DMATCD4_IRQn = 8, /**< DMA transfer complete and error CH4 */ 175 DMATCD5_IRQn = 9, /**< DMA transfer complete and error CH5 */ 176 DMATCD6_IRQn = 10, /**< DMA transfer complete and error CH6 */ 177 DMATCD7_IRQn = 11, /**< DMA transfer complete and error CH7 */ 178 DMATCD8_IRQn = 12, /**< DMA transfer complete and error CH8 */ 179 DMATCD9_IRQn = 13, /**< DMA transfer complete and error CH9 */ 180 DMATCD10_IRQn = 14, /**< DMA transfer complete and error CH10 */ 181 DMATCD11_IRQn = 15, /**< DMA transfer complete and error CH11 */ 182 DMATCD12_IRQn = 16, /**< DMA transfer complete and error CH12 */ 183 DMATCD13_IRQn = 17, /**< DMA transfer complete and error CH13 */ 184 DMATCD14_IRQn = 18, /**< DMA transfer complete and error CH14 */ 185 DMATCD15_IRQn = 19, /**< DMA transfer complete and error CH15 */ 186 DMATCD16_IRQn = 20, /**< DMA transfer complete and error CH16 */ 187 DMATCD17_IRQn = 21, /**< DMA transfer complete and error CH17 */ 188 DMATCD18_IRQn = 22, /**< DMA transfer complete and error CH18 */ 189 DMATCD19_IRQn = 23, /**< DMA transfer complete and error CH19 */ 190 DMATCD20_IRQn = 24, /**< DMA transfer complete and error CH20 */ 191 DMATCD21_IRQn = 25, /**< DMA transfer complete and error CH21 */ 192 DMATCD22_IRQn = 26, /**< DMA transfer complete and error CH22 */ 193 DMATCD23_IRQn = 27, /**< DMA transfer complete and error CH23 */ 194 DMATCD24_IRQn = 28, /**< DMA transfer complete and error CH24 */ 195 DMATCD25_IRQn = 29, /**< DMA transfer complete and error CH25 */ 196 DMATCD26_IRQn = 30, /**< DMA transfer complete and error CH26 */ 197 DMATCD27_IRQn = 31, /**< DMA transfer complete and error CH27 */ 198 DMATCD28_IRQn = 32, /**< DMA transfer complete and error CH28 */ 199 DMATCD29_IRQn = 33, /**< DMA transfer complete and error CH29 */ 200 DMATCD30_IRQn = 34, /**< DMA transfer complete and error CH30 */ 201 DMATCD31_IRQn = 35, /**< DMA transfer complete and error CH31 */ 202 ERM_0_IRQn = 36, /**< Single bit ECC error */ 203 ERM_1_IRQn = 37, /**< Multi bit ECC error */ 204 MCM_IRQn = 38, /**< Multi bit ECC error */ 205 STM0_IRQn = 39, /**< Single interrupt vector for all four channels */ 206 STM1_IRQn = 40, /**< Single interrupt vector for all four channels */ 207 SWT0_IRQn = 42, /**< Platform watchdog initial time-out */ 208 CTI0_IRQn = 45, /**< CTI Interrupt 0 */ 209 FLASH_0_IRQn = 48, /**< Program or erase operation is completed */ 210 FLASH_1_IRQn = 49, /**< Main watchdog timeout interrupt */ 211 FLASH_2_IRQn = 50, /**< Alternate watchdog timeout interrupt */ 212 RGM_IRQn = 51, /**< Interrupt request to the system */ 213 PMC_IRQn = 52, /**< One interrupt for all LVDs, One interrupt for all HVDs */ 214 SIUL_0_IRQn = 53, /**< External Interrupt Vector 0 */ 215 SIUL_1_IRQn = 54, /**< External Interrupt Vector 1 */ 216 SIUL_2_IRQn = 55, /**< External Interrupt Vector 2 */ 217 SIUL_3_IRQn = 56, /**< External Interrupt Vector 3 */ 218 EMIOS0_0_IRQn = 61, /**< Interrupt request 23,22,21,20 */ 219 EMIOS0_1_IRQn = 62, /**< Interrupt request 19,18,17,16 */ 220 EMIOS0_2_IRQn = 63, /**< Interrupt request 15,14,13,12 */ 221 EMIOS0_3_IRQn = 64, /**< Interrupt request 11,10,9,8 */ 222 EMIOS0_4_IRQn = 65, /**< Interrupt request 7,6,5,4 */ 223 EMIOS0_5_IRQn = 66, /**< Interrupt request 3,2,1,0 */ 224 EMIOS1_0_IRQn = 69, /**< Interrupt request 23,22,21,20 */ 225 EMIOS1_1_IRQn = 70, /**< Interrupt request 19,18,17,16 */ 226 EMIOS1_2_IRQn = 71, /**< Interrupt request 15,14,13,12 */ 227 EMIOS1_3_IRQn = 72, /**< Interrupt request 11,10,9,8 */ 228 EMIOS1_4_IRQn = 73, /**< Interrupt request 7,6,5,4 */ 229 EMIOS1_5_IRQn = 74, /**< Interrupt request 3,2,1,0 */ 230 EMIOS2_0_IRQn = 77, /**< Interrupt request 23,22,21,20 */ 231 EMIOS2_1_IRQn = 78, /**< Interrupt request 19,18,17,16 */ 232 EMIOS2_2_IRQn = 79, /**< Interrupt request 15,14,13,12 */ 233 EMIOS2_3_IRQn = 80, /**< Interrupt request 11,10,9,8 */ 234 EMIOS2_4_IRQn = 81, /**< Interrupt request 7,6,5,4 */ 235 EMIOS2_5_IRQn = 82, /**< Interrupt request 3,2,1,0 */ 236 WKPU_IRQn = 83, /**< Interrupts from pad group 0,1,2,3, Interrupts from pad group 0_64, Interrupts from pad group 1_64, Interrupts from pad group 2_64, Interrupts from pad group 3_64 */ 237 CMU0_IRQn = 84, /**< CMU0 interrupt */ 238 CMU1_IRQn = 85, /**< CMU1 interrupt */ 239 CMU2_IRQn = 86, /**< CMU2 interrupt */ 240 BCTU_IRQn = 87, /**< An interrupt is requested when a conversion is issued to the ADC, An interrupt is requested when new data is available from ADC0 conversion, An interrupt is requested when new data is available from ADC1 conversion, An interrupt is requested when new data is available from ADC2 conversion, An interrupt is requested when the last command of a list is issued to the ADC,An Interrupt output for FIFO1,An Interrupt output for FIFO2 */ 241 LCU0_IRQn = 92, /**< Interrupt 0, Interrupt 1 Interrupt 2 */ 242 LCU1_IRQn = 93, /**< Interrupt 0, Interrupt 1 Interrupt 2 */ 243 PIT0_IRQn = 96, /**< Interrupt for Channel0,Interrupt for Channel1,Interrupt for Channel2,Interrupt for Channel3,Interrupt for Channel4 */ 244 PIT1_IRQn = 97, /**< Interrupt for Channel0,Interrupt for Channel1,Interrupt for Channel2,Interrupt for Channel3 */ 245 PIT2_IRQn = 98, /**< Interrupt for Channel0,Interrupt for Channel1,Interrupt for Channel2,Interrupt for Channel3 */ 246 RTC_IRQn = 102, /**< RTCF or ROVRF interrupt to be serviced by the system controller, APIF interrupt to be serviced by the system controller */ 247 EMAC_0_IRQn = 105, /**< Common interrupt */ 248 EMAC_1_IRQn = 106, /**< Tx interrupt 0, Tx interrupt 1 */ 249 EMAC_2_IRQn = 107, /**< Rx interrupt 0, Rx interrupt 1 */ 250 EMAC_3_IRQn = 108, /**< Safety interrupt correctable, Safety interrupt un-correctable */ 251 FlexCAN0_0_IRQn = 109, /**< Interrupt indicating that the CAN bus went to Bus Off state */ 252 FlexCAN0_1_IRQn = 110, /**< Message Buffer Interrupt line 0-31,ORed Interrupt for Message Buffers */ 253 FlexCAN0_2_IRQn = 111, /**< Message Buffer Interrupt line 32-63 */ 254 FlexCAN0_3_IRQn = 112, /**< Message Buffer Interrupt line 64-95 */ 255 FlexCAN1_0_IRQn = 113, /**< Interrupt indicating that the CAN bus went to Bus Off state */ 256 FlexCAN1_1_IRQn = 114, /**< Message Buffer Interrupt line 0-31 */ 257 FlexCAN1_2_IRQn = 115, /**< Message Buffer Interrupt line 32-63 */ 258 FlexCAN2_0_IRQn = 116, /**< Interrupt indicating that the CAN bus went to Bus Off state */ 259 FlexCAN2_1_IRQn = 117, /**< Message Buffer Interrupt line 0-31 */ 260 FlexCAN2_2_IRQn = 118, /**< Message Buffer Interrupt line 32-63 */ 261 FlexCAN3_0_IRQn = 119, /**< Interrupt indicating that the CAN bus went to Bus Off state */ 262 FlexCAN3_1_IRQn = 120, /**< Message Buffer Interrupt line 0-31 */ 263 FlexCAN4_0_IRQn = 121, /**< Interrupt indicating that the CAN bus went to Bus Off state */ 264 FlexCAN4_1_IRQn = 122, /**< Message Buffer Interrupt line 0-31 */ 265 FlexCAN5_0_IRQn = 123, /**< Interrupt indicating that the CAN bus went to Bus Off state */ 266 FlexCAN5_1_IRQn = 124, /**< Message Buffer Interrupt line 0-31 */ 267 FLEXIO_IRQn = 139, /**< FlexIO Interrupt */ 268 LPUART0_IRQn = 141, /**< TX and RX interrupt */ 269 LPUART1_IRQn = 142, /**< TX and RX interrupt */ 270 LPUART2_IRQn = 143, /**< TX and RX interrupt */ 271 LPUART3_IRQn = 144, /**< TX and RX interrupt */ 272 LPUART4_IRQn = 145, /**< TX and RX interrupt */ 273 LPUART5_IRQn = 146, /**< TX and RX interrupt */ 274 LPUART6_IRQn = 147, /**< TX and RX interrupt */ 275 LPUART7_IRQn = 148, /**< TX and RX interrupt */ 276 LPUART8_IRQn = 149, /**< TX and RX interrupt */ 277 LPUART9_IRQn = 150, /**< TX and RX interrupt */ 278 LPUART10_IRQn = 151, /**< TX and RX interrupt */ 279 LPUART11_IRQn = 152, /**< TX and RX interrupt */ 280 LPUART12_IRQn = 153, /**< TX and RX interrupt */ 281 LPUART13_IRQn = 154, /**< TX and RX interrupt */ 282 LPUART14_IRQn = 155, /**< TX and RX interrupt */ 283 LPUART15_IRQn = 156, /**< TX and RX interrupt */ 284 LPI2C0_IRQn = 161, /**< LPI2C Master Interrupt, LPI2C Interrupt */ 285 LPI2C1_IRQn = 162, /**< LPI2C Master Interrupt, LPI2C Interrupt */ 286 LPSPI0_IRQn = 165, /**< LPSPI Interrupt */ 287 LPSPI1_IRQn = 166, /**< LPSPI Interrupt */ 288 LPSPI2_IRQn = 167, /**< LPSPI Interrupt */ 289 LPSPI3_IRQn = 168, /**< LPSPI Interrupt */ 290 LPSPI4_IRQn = 169, /**< LPSPI Interrupt */ 291 LPSPI5_IRQn = 170, /**< LPSPI Interrupt */ 292 QSPI_IRQn = 173, /**< TX Buffer Fill interrupt, Transfer Complete / Transaction Finished, RX Buffer Drain interrupt, Buffer Overflow / Underrun interrupt, Serial Flash Communication Error interrupt, All interrupts ORed output */ 293 SAI0_IRQn = 174, /**< RX interrupt,TX interrupt */ 294 SAI1_IRQn = 175, /**< RX interrupt,TX interrupt */ 295 JDC_IRQn = 178, /**< Indicates new data to be read from JIN_IPS register or can be written to JOUT_IPS register */ 296 ADC0_IRQn = 180, /**< End of conversion, Error interrupt, Watchdog interrupt */ 297 ADC1_IRQn = 181, /**< End of conversion, Error interrupt, Watchdog interrupt */ 298 ADC2_IRQn = 182, /**< End of conversion, Error interrupt, Watchdog interrupt */ 299 LPCMP0_IRQn = 183, /**< Async interrupt */ 300 LPCMP1_IRQn = 184, /**< Async interrupt */ 301 LPCMP2_IRQn = 185, /**< Async interrupt */ 302 FCCU_0_IRQn = 189, /**< Interrupt request(ALARM state) */ 303 FCCU_1_IRQn = 190, /**< Interrupt request(miscellaneous conditions) */ 304 STCU_LBIST_MBIST_IRQn = 191, /**< Interrupt request(miscellaneous conditions) */ 305 HSE_MU0_TX_IRQn = 192, /**< ORed TX interrupt to MU-0 */ 306 HSE_MU0_RX_IRQn = 193, /**< ORed RX interrupt to MU-0 */ 307 HSE_MU0_ORED_IRQn = 194, /**< ORed general purpose interrupt request to MU-0 */ 308 HSE_MU1_TX_IRQn = 195, /**< ORed TX interrupt to MU-1 */ 309 HSE_MU1_RX_IRQn = 196, /**< ORed RX interrupt to MU-1 */ 310 HSE_MU1_ORED_IRQn = 197, /**< ORed general purpose interrupt request to MU-1 */ 311 SoC_PLL_IRQn = 212 /**< PLL LOL interrupt */ 312 } IRQn_Type; 313 314 /*! 315 * @} 316 */ /* end of group Interrupt_vector_numbers */ 317 318 319 /* ---------------------------------------------------------------------------- 320 -- Cortex M7 Core Configuration 321 ---------------------------------------------------------------------------- */ 322 323 /*! 324 * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration 325 * @{ 326 */ 327 328 #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ 329 #define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */ 330 #define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */ 331 #define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */ 332 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ 333 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 334 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ 335 336 337 /*! 338 * @} 339 */ /* end of group Cortex_Core_Configuration */ 340 341 342 /* ---------------------------------------------------------------------------- 343 -- SDK Compatibility 344 ---------------------------------------------------------------------------- */ 345 346 /*! 347 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 348 * @{ 349 */ 350 351 /* No SDK compatibility issues. */ 352 353 /*! 354 * @} 355 */ /* end of group SDK_Compatibility_Symbols */ 356 357 358 #endif /* #if !defined(S32K344_COMMON_H_) */ 359 360
