1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_DMAMUX.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_DMAMUX 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_DMAMUX_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_DMAMUX_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- DMAMUX Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer 68 * @{ 69 */ 70 71 /** DMAMUX - Size of Registers Arrays */ 72 #define DMAMUX_CHCFG_COUNT 32u 73 74 /** DMAMUX - Register Layout Typedef */ 75 typedef struct { 76 __IO uint8_t CHCFG[DMAMUX_CHCFG_COUNT]; /**< Channel Configuration, array offset: 0x0, array step: 0x1, irregular array, not all indices are valid */ 77 } DMAMUX_Type, *DMAMUX_MemMapPtr; 78 79 /** Number of instances of the DMAMUX module. */ 80 #define DMAMUX_INSTANCE_COUNT (6u) 81 82 /* DMAMUX - Peripheral instance base addresses */ 83 /** Peripheral CE_DMAMUX base address */ 84 #define IP_CE_DMAMUX_BASE (0x448D8000u) 85 /** Peripheral CE_DMAMUX base pointer */ 86 #define IP_CE_DMAMUX ((DMAMUX_Type *)IP_CE_DMAMUX_BASE) 87 /** Peripheral DMAMUX_0A base address */ 88 #define IP_DMAMUX_0A_BASE (0x405A0000u) 89 /** Peripheral DMAMUX_0A base pointer */ 90 #define IP_DMAMUX_0A ((DMAMUX_Type *)IP_DMAMUX_0A_BASE) 91 /** Peripheral DMAMUX_0B base address */ 92 #define IP_DMAMUX_0B_BASE (0x405B0000u) 93 /** Peripheral DMAMUX_0B base pointer */ 94 #define IP_DMAMUX_0B ((DMAMUX_Type *)IP_DMAMUX_0B_BASE) 95 /** Peripheral DMAMUX_1 base address */ 96 #define IP_DMAMUX_1_BASE (0x40DA0000u) 97 /** Peripheral DMAMUX_1 base pointer */ 98 #define IP_DMAMUX_1 ((DMAMUX_Type *)IP_DMAMUX_1_BASE) 99 /** Peripheral DMAMUX_4 base address */ 100 #define IP_DMAMUX_4_BASE (0x425A0000u) 101 /** Peripheral DMAMUX_4 base pointer */ 102 #define IP_DMAMUX_4 ((DMAMUX_Type *)IP_DMAMUX_4_BASE) 103 /** Peripheral DMAMUX_5 base address */ 104 #define IP_DMAMUX_5_BASE (0x42DA0000u) 105 /** Peripheral DMAMUX_5 base pointer */ 106 #define IP_DMAMUX_5 ((DMAMUX_Type *)IP_DMAMUX_5_BASE) 107 /** Array initializer of DMAMUX peripheral base addresses */ 108 #define IP_DMAMUX_BASE_ADDRS { IP_CE_DMAMUX_BASE, IP_DMAMUX_0A_BASE, IP_DMAMUX_0B_BASE, IP_DMAMUX_1_BASE, IP_DMAMUX_4_BASE, IP_DMAMUX_5_BASE } 109 /** Array initializer of DMAMUX peripheral base pointers */ 110 #define IP_DMAMUX_BASE_PTRS { IP_CE_DMAMUX, IP_DMAMUX_0A, IP_DMAMUX_0B, IP_DMAMUX_1, IP_DMAMUX_4, IP_DMAMUX_5 } 111 112 /* ---------------------------------------------------------------------------- 113 -- DMAMUX Register Masks 114 ---------------------------------------------------------------------------- */ 115 116 /*! 117 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks 118 * @{ 119 */ 120 121 /*! @name CHCONF - Channel Configuration */ 122 /*! @{ */ 123 124 #define DMAMUX_CHCONF_SOURCE_MASK (0x3FU) 125 #define DMAMUX_CHCONF_SOURCE_SHIFT (0U) 126 #define DMAMUX_CHCONF_SOURCE_WIDTH (6U) 127 #define DMAMUX_CHCONF_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCONF_SOURCE_SHIFT)) & DMAMUX_CHCONF_SOURCE_MASK) 128 129 #define DMAMUX_CHCONF_TRIG_MASK (0x40U) 130 #define DMAMUX_CHCONF_TRIG_SHIFT (6U) 131 #define DMAMUX_CHCONF_TRIG_WIDTH (1U) 132 #define DMAMUX_CHCONF_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCONF_TRIG_SHIFT)) & DMAMUX_CHCONF_TRIG_MASK) 133 134 #define DMAMUX_CHCONF_ENBL_MASK (0x80U) 135 #define DMAMUX_CHCONF_ENBL_SHIFT (7U) 136 #define DMAMUX_CHCONF_ENBL_WIDTH (1U) 137 #define DMAMUX_CHCONF_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCONF_ENBL_SHIFT)) & DMAMUX_CHCONF_ENBL_MASK) 138 /*! @} */ 139 140 /*! 141 * @} 142 */ /* end of group DMAMUX_Register_Masks */ 143 144 /*! 145 * @} 146 */ /* end of group DMAMUX_Peripheral_Access_Layer */ 147 148 #endif /* #if !defined(S32Z2_DMAMUX_H_) */ 149
