1 /* 2 * Copyright 2020 Broadcom 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef DMA_PL330_H 8 #define DMA_PL330_H 9 10 #include <zephyr/drivers/dma.h> 11 12 #define DT_DRV_COMPAT arm_dma_pl330 13 /* 14 * Max burst length and max burst size for 32bit system with 15 * 128bit bus width for memory to memory data transfer 16 * 17 * Burst length is encoded in following format for pl330 18 * b0000 = 1 data transfer 19 * b0001 = 2 data transfers 20 * b0010 = 3 data transfers 21 * . 22 * . 23 * b1111 = 16 data transfers 24 * 25 * Burst size is encoded in following format for pl330 26 * b000 = 1 byte 27 * b001 = 2 bytes 28 * b010 = 4 bytes 29 * b011 = 8 bytes 30 * b100 = 16 bytes 31 * b101 = 32 bytes 32 * b110 = 64 bytes 33 * b111 = 128 bytes. 34 */ 35 #define MAX_BURST_LEN 0xf /* 16byte data */ 36 #define MAX_BURST_SIZE_LOG2 4 37 38 /* 39 * PL330 works only on 4GB boundary. 40 * PL330 has 32bit registers for source and destination addresses 41 */ 42 #define PL330_MAX_OFFSET 0x100000000 43 44 /* PL330 supports max 16MB dma based on AXI bus size */ 45 #define PL330_MAX_DMA_SIZE 0x1000000 46 47 /* Maximum possible values for PL330 ucode loop counters */ 48 #define PL330_LOOP_COUNTER0_MAX 0x100 49 #define PL330_LOOP_COUNTER1_MAX 0x100 50 51 #define MAX_DMA_CHANNELS DT_INST_PROP(0, dma_channels) 52 53 #define DMAC_PL330_CS0 0x100 54 #define DMAC_PL330_DBGSTATUS 0xd00 55 #define DMAC_PL330_DBGCMD 0xd04 56 #define DMAC_PL330_DBGINST0 0xd08 57 #define DMAC_PL330_DBGINST1 0xd0c 58 59 /* 60 * TIMEOUT value of 100000us is kept to cover all possible data 61 * transfer sizes, with lesser time out value(10us) DMA channel 62 * appears to be busy on FPGA/Emul environment. Ideally 100000us 63 * timeout value should never hit. 64 */ 65 #define DMA_TIMEOUT_US 100000 66 67 #define CH_STATUS_MASK 0xf 68 #define DATA_MASK 0xf 69 70 #define DMA_INTSR1_SHIFT 24 71 #define DMA_INTSR0_SHIFT 16 72 #define DMA_INTSR0 0xa0 73 #define DMA_SECURE_SHIFT 17 74 #define DMA_CH_SHIFT 8 75 76 #define CONTROL_OFFSET 0x4 77 #define HIGHER_32_ADDR_MASK 0x0f 78 #define DST_ADDR_SHIFT 0x4 79 80 #define MICROCODE_SIZE_MAX 0x400 81 #define TOTAL_MICROCODE_SIZE (MAX_DMA_CHANNELS * MICROCODE_SIZE_MAX) 82 #define GET_MAX_DMA_SIZE(byte_width, burst_len) \ 83 (PL330_LOOP_COUNTER0_MAX * PL330_LOOP_COUNTER1_MAX * \ 84 (byte_width) * ((burst_len) + 1)) 85 86 #define CC_SRCINC_SHIFT 0 87 #define CC_DSTINC_SHIFT 14 88 #define CC_SRCPRI_SHIFT 8 89 #define CC_DSTPRI_SHIFT 22 90 #define CC_DSTNS_SHIFT 23 91 #define CC_SRCBRSTLEN_SHIFT 4 92 #define CC_DSTBRSTLEN_SHIFT 18 93 #define CC_SRCBRSTSIZE_SHIFT 1 94 #define CC_DSTBRSTSIZE_SHIFT 15 95 #define CC_SRCCCTRL_SHIFT 11 96 #define CC_SRCCCTRL_MASK 0x7 97 #define CC_DSTCCTRL_SHIFT 25 98 #define CC_DRCCCTRL_MASK 0x7 99 #define CC_SWAP_SHIFT 28 100 #define SRC_PRI_NONSEC_VALUE 0x2 101 #define SRC_PRI_SEC_VALUE 0x0 102 103 #define OP_DMA_MOV 0xbc 104 #define OP_DMA_LOOP_COUNT1 0x22 105 #define OP_DMA_LOOP 0x20 106 #define OP_DMA_LD 0x4 107 #define OP_DMA_ST 0x8 108 #define OP_DMA_SEV 0x34 109 #define OP_DMA_END 0x00 110 #define OP_DMA_LP_BK_JMP1 0x38 111 #define OP_DMA_LP_BK_JMP2 0x3c 112 #define SZ_CMD_DMAMOV 0x6 113 114 enum dmamov_type { 115 /* Source Address Register */ 116 SAR = 0, 117 /* Channel Control Register */ 118 CCR, 119 /* Destination Address Register */ 120 DAR, 121 }; 122 123 /* Channel specific private data */ 124 struct dma_pl330_ch_internal { 125 uint64_t src_addr; 126 uint64_t dst_addr; 127 int src_burst_sz; 128 uint32_t src_burst_len; 129 int dst_burst_sz; 130 uint32_t dst_burst_len; 131 uint32_t trans_size; 132 uint32_t dst_id; 133 uint32_t src_id; 134 uint32_t perip_type; 135 uint32_t breq_only; 136 uint32_t src_cache_ctrl; 137 uint32_t dst_cache_ctrl; 138 uint32_t dst_inc; 139 uint32_t src_inc; 140 int nonsec_mode; 141 }; 142 143 struct dma_pl330_ch_config { 144 /* Channel configuration details */ 145 uint64_t src_addr; 146 enum dma_addr_adj src_addr_adj; 147 uint64_t dst_addr; 148 enum dma_addr_adj dst_addr_adj; 149 enum dma_channel_direction direction; 150 uint32_t trans_size; 151 void *user_data; 152 dma_callback_t dma_callback; 153 mem_addr_t dma_exec_addr; 154 struct k_mutex ch_mutex; 155 int channel_active; 156 157 /* Channel specific private data */ 158 struct dma_pl330_ch_internal internal; 159 }; 160 161 struct dma_pl330_config { 162 mem_addr_t mcode_base; 163 mem_addr_t reg_base; 164 #ifdef CONFIG_DMA_64BIT 165 mem_addr_t control_reg_base; 166 #endif 167 }; 168 169 struct dma_pl330_dev_data { 170 struct dma_pl330_ch_config channels[MAX_DMA_CHANNELS]; 171 }; 172 173 #endif 174
