1 /* 2 * Copyright 2023-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _S32Z270_GLUE_MCUX_H_ 8 #define _S32Z270_GLUE_MCUX_H_ 9 10 #include "S32Z270_device.h" 11 12 /* PIT - Peripheral instance base addresses */ 13 /** Peripheral PIT0 base address */ 14 #define PIT0_BASE IP_PIT_0_BASE 15 /** Peripheral PIT0 base pointer */ 16 #define PIT0 IP_PIT_0 17 /** Array initializer of PIT peripheral base addresses */ 18 #define PIT_BASE_ADDRS IP_PIT_BASE_ADDRS 19 /** Array initializer of PIT peripheral base pointers */ 20 #define PIT_BASE_PTRS IP_PIT_BASE_PTRS 21 /** Interrupt vectors for the PIT peripheral type */ 22 #define PIT_IRQS { RTU_RTUn_PIT0_IRQn } 23 24 /* I3C - Peripheral instance base addresses */ 25 /** Peripheral I3C0 base address */ 26 #define I3C0_BASE IP_I3C_0_BASE 27 /** Peripheral I3C0 base pointer */ 28 #define I3C0 IP_I3C_0 29 /** Peripheral I3C1 base address */ 30 #define I3C1_BASE IP_I3C_1_BASE 31 /** Peripheral I3C1 base pointer */ 32 #define I3C1 IP_I3C_1 33 /** Peripheral I3C2 base address */ 34 #define I3C2_BASE IP_I3C_2_BASE 35 /** Peripheral I3C1 base pointer */ 36 #define I3C2 IP_I3C_2 37 /** Array initializer of I3C peripheral base addresses */ 38 #define I3C_BASE_ADDRS IP_I3C_BASE_ADDRS 39 /** Array initializer of I3C peripheral base pointers */ 40 #define I3C_BASE_PTRS IP_I3C_BASE_PTRS 41 /** Interrupt vectors for the I3C peripheral type */ 42 #define I3C_IRQS { RTU_I3C0_IRQn, RTU_I3C1_IRQn, RTU_I3C2_IRQn } 43 44 /* 45 * These bit fields are not existed on this SoC, I3C slave request IBI will not be 46 * supported because I3C functionality is not stable in this SoC. Keep define these 47 * macros in order to build. 48 */ 49 #define I3C_IBIEXT2_EXT5(x) 0 50 #define I3C_IBIEXT2_EXT6(x) 0 51 #define I3C_IBIEXT2_EXT7(x) 0 52 53 /* SPI - Peripheral instance base addresses */ 54 /** Peripheral MSC_0_DSPI base address */ 55 #define SPI0_BASE IP_MSC_0_DSPI_BASE 56 /** Peripheral MSC_0_DSPI base pointer */ 57 #define SPI0 ((SPI_Type *)SPI0_BASE) 58 /** Array initializer of DSPI peripheral base addresses */ 59 #define SPI_BASE_ADDRS { SPI0_BASE } 60 /** Array initializer of DSPI peripheral base pointers */ 61 #define SPI_BASE_PTRS { SPI0 } 62 63 #define SPI_IRQS { RTU_MSC0_DSPI_IRQn } 64 65 /* CAN - Peripheral instance base addresses */ 66 /** Peripheral CAN_0 base address */ 67 #define CAN0_BASE IP_CE_CAN_0_BASE 68 /** Peripheral CAN_0 base pointer */ 69 #define CAN0 ((CAN_Type *)CAN0_BASE) 70 /** Peripheral CAN_1 base address */ 71 #define CAN1_BASE IP_CE_CAN_1_BASE 72 /** Peripheral CAN_1 base pointer */ 73 #define CAN1 ((CAN_Type *)CAN1_BASE) 74 /** Peripheral CAN_2 base address */ 75 #define CAN2_BASE IP_CE_CAN_2_BASE 76 /** Peripheral CAN_2 base pointer */ 77 #define CAN2 ((CAN_Type *)CAN2_BASE) 78 /** Peripheral CAN_3 base address */ 79 #define CAN3_BASE IP_CE_CAN_3_BASE 80 /** Peripheral CAN_3 base pointer */ 81 #define CAN3 ((CAN_Type *)CAN3_BASE) 82 /** Peripheral CAN_4 base address */ 83 #define CAN4_BASE IP_CE_CAN_4_BASE 84 /** Peripheral CAN_4 base pointer */ 85 #define CAN4 ((CAN_Type *)CAN4_BASE) 86 /** Peripheral CAN_5 base address */ 87 #define CAN5_BASE IP_CE_CAN_5_BASE 88 /** Peripheral CAN_5 base pointer */ 89 #define CAN5 ((CAN_Type *)CAN5_BASE) 90 /** Peripheral CAN_6 base address */ 91 #define CAN6_BASE IP_CE_CAN_6_BASE 92 /** Peripheral CAN_6 base pointer */ 93 #define CAN6 ((CAN_Type *)CAN6_BASE) 94 /** Peripheral CAN_7 base address */ 95 #define CAN7_BASE IP_CE_CAN_7_BASE 96 /** Peripheral CAN_7 base pointer */ 97 #define CAN7 ((CAN_Type *)CAN7_BASE) 98 /** Peripheral CAN_8 base address */ 99 #define CAN8_BASE IP_CE_CAN_8_BASE 100 /** Peripheral CAN_8 base pointer */ 101 #define CAN8 ((CAN_Type *)CAN8_BASE) 102 /** Peripheral CAN_9 base address */ 103 #define CAN9_BASE IP_CE_CAN_9_BASE 104 /** Peripheral CAN_9 base pointer */ 105 #define CAN9 ((CAN_Type *)CAN9_BASE) 106 /** Peripheral CAN_10 base address */ 107 #define CAN10_BASE IP_CE_CAN_10_BASE 108 /** Peripheral CAN_10 base pointer */ 109 #define CAN10 ((CAN_Type *)CAN10_BASE) 110 /** Peripheral CAN_11 base address */ 111 #define CAN11_BASE IP_CE_CAN_11_BASE 112 /** Peripheral CAN_11 base pointer */ 113 #define CAN11 ((CAN_Type *)CAN11_BASE) 114 /** Peripheral CAN_12 base address */ 115 #define CAN12_BASE IP_CE_CAN_12_BASE 116 /** Peripheral CAN_12 base pointer */ 117 #define CAN12 ((CAN_Type *)CAN12_BASE) 118 /** Peripheral CAN_13 base address */ 119 #define CAN13_BASE IP_CE_CAN_13_BASE 120 /** Peripheral CAN_13 base pointer */ 121 #define CAN13 ((CAN_Type *)CAN13_BASE) 122 /** Peripheral CAN_14 base address */ 123 #define CAN14_BASE IP_CE_CAN_14_BASE 124 /** Peripheral CAN_14 base pointer */ 125 #define CAN14 ((CAN_Type *)CAN14_BASE) 126 /** Peripheral CAN_15 base address */ 127 #define CAN15_BASE IP_CE_CAN_15_BASE 128 /** Peripheral CAN_15 base pointer */ 129 #define CAN15 ((CAN_Type *)CAN15_BASE) 130 /** Peripheral CAN_16 base address */ 131 #define CAN16_BASE IP_CE_CAN_16_BASE 132 /** Peripheral CAN_16 base pointer */ 133 #define CAN16 ((CAN_Type *)CAN16_BASE) 134 /** Peripheral CAN_17 base address */ 135 #define CAN17_BASE IP_CE_CAN_17_BASE 136 /** Peripheral CAN_17 base pointer */ 137 #define CAN17 ((CAN_Type *)CAN17_BASE) 138 /** Peripheral CAN_18 base address */ 139 #define CAN18_BASE IP_CE_CAN_18_BASE 140 /** Peripheral CAN_18 base pointer */ 141 #define CAN18 ((CAN_Type *)CAN18_BASE) 142 /** Peripheral CAN_19 base address */ 143 #define CAN19_BASE IP_CE_CAN_19_BASE 144 /** Peripheral CAN_19 base pointer */ 145 #define CAN19 ((CAN_Type *)CAN19_BASE) 146 /** Peripheral CAN_20 base address */ 147 #define CAN20_BASE IP_CE_CAN_20_BASE 148 /** Peripheral CAN_20 base pointer */ 149 #define CAN20 ((CAN_Type *)CAN20_BASE) 150 /** Peripheral CAN_21 base address */ 151 #define CAN21_BASE IP_CE_CAN_21_BASE 152 /** Peripheral CAN_21 base pointer */ 153 #define CAN21 ((CAN_Type *)CAN21_BASE) 154 /** Peripheral CAN_22 base address */ 155 #define CAN22_BASE IP_CE_CAN_22_BASE 156 /** Peripheral CAN_22 base pointer */ 157 #define CAN22 ((CAN_Type *)CAN22_BASE) 158 /** Peripheral CAN_23 base address */ 159 #define CAN23_BASE IP_CE_CAN_23_BASE 160 /** Peripheral CAN_19 base pointer */ 161 #define CAN23 ((CAN_Type *)CAN23_BASE) 162 /** Array initializer of CAN peripheral base addresses */ 163 #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE, CAN2_BASE, CAN3_BASE, CAN4_BASE, CAN5_BASE, \ 164 CAN6_BASE, CAN7_BASE, CAN8_BASE, CAN9_BASE, CAN10_BASE, CAN11_BASE, \ 165 CAN12_BASE, CAN13_BASE, CAN14_BASE, CAN15_BASE, CAN16_BASE, CAN17_BASE, \ 166 CAN18_BASE, CAN19_BASE, CAN20_BASE, CAN21_BASE,CAN22_BASE,CAN23_BASE } 167 /** Array initializer of CAN peripheral base pointers */ 168 #define CAN_BASE_PTRS { CAN0, CAN1, CAN2, CAN3, CAN4, CAN5, \ 169 CAN6, CAN7, CAN8, CAN9, CAN10, CAN11, \ 170 CAN12, CAN13, CAN14, CAN15, CAN16, CAN17, \ 171 CAN18, CAN19, CAN20, CAN21,CAN22,CAN23 } 172 173 /** Interrupt vectors for the CAN peripheral type */ 174 #define CAN_Rx_Warning_IRQS { RTU_CE_CAN0_INIT_OR_ERROR_IRQn, RTU_CE_CAN1_INIT_OR_ERROR_IRQn, RTU_CE_CAN2_INIT_OR_ERROR_IRQn, \ 175 RTU_CE_CAN3_INIT_OR_ERROR_IRQn, RTU_CE_CAN4_INIT_OR_ERROR_IRQn, RTU_CE_CAN5_INIT_OR_ERROR_IRQn, \ 176 RTU_CE_CAN6_INIT_OR_ERROR_IRQn, RTU_CE_CAN7_INIT_OR_ERROR_IRQn, RTU_CE_CAN8_INIT_OR_ERROR_IRQn, \ 177 RTU_CE_CAN9_INIT_OR_ERROR_IRQn, RTU_CE_CAN10_INIT_OR_ERROR_IRQn, RTU_CE_CAN11_INIT_OR_ERROR_IRQn, \ 178 RTU_CE_CAN12_INIT_OR_ERROR_IRQn, RTU_CE_CAN13_INIT_OR_ERROR_IRQn, RTU_CE_CAN14_INIT_OR_ERROR_IRQn, \ 179 RTU_CE_CAN15_INIT_OR_ERROR_IRQn, RTU_CE_CAN16_INIT_OR_ERROR_IRQn, RTU_CE_CAN17_INIT_OR_ERROR_IRQn, \ 180 RTU_CE_CAN18_INIT_OR_ERROR_IRQn, RTU_CE_CAN19_INIT_OR_ERROR_IRQn, RTU_CE_CAN20_INIT_OR_ERROR_IRQn, \ 181 RTU_CE_CAN21_INIT_OR_ERROR_IRQn, RTU_CE_CAN22_INIT_OR_ERROR_IRQn, RTU_CE_CAN23_INIT_OR_ERROR_IRQn } 182 #define CAN_Tx_Warning_IRQS { RTU_CE_CAN0_INIT_OR_ERROR_IRQn, RTU_CE_CAN1_INIT_OR_ERROR_IRQn, RTU_CE_CAN2_INIT_OR_ERROR_IRQn, \ 183 RTU_CE_CAN3_INIT_OR_ERROR_IRQn, RTU_CE_CAN4_INIT_OR_ERROR_IRQn, RTU_CE_CAN5_INIT_OR_ERROR_IRQn, \ 184 RTU_CE_CAN6_INIT_OR_ERROR_IRQn, RTU_CE_CAN7_INIT_OR_ERROR_IRQn, RTU_CE_CAN8_INIT_OR_ERROR_IRQn, \ 185 RTU_CE_CAN9_INIT_OR_ERROR_IRQn, RTU_CE_CAN10_INIT_OR_ERROR_IRQn, RTU_CE_CAN11_INIT_OR_ERROR_IRQn, \ 186 RTU_CE_CAN12_INIT_OR_ERROR_IRQn, RTU_CE_CAN13_INIT_OR_ERROR_IRQn, RTU_CE_CAN14_INIT_OR_ERROR_IRQn, \ 187 RTU_CE_CAN15_INIT_OR_ERROR_IRQn, RTU_CE_CAN16_INIT_OR_ERROR_IRQn, RTU_CE_CAN17_INIT_OR_ERROR_IRQn, \ 188 RTU_CE_CAN18_INIT_OR_ERROR_IRQn, RTU_CE_CAN19_INIT_OR_ERROR_IRQn, RTU_CE_CAN20_INIT_OR_ERROR_IRQn, \ 189 RTU_CE_CAN21_INIT_OR_ERROR_IRQn, RTU_CE_CAN22_INIT_OR_ERROR_IRQn, RTU_CE_CAN23_INIT_OR_ERROR_IRQn } 190 #define CAN_Wake_Up_IRQS { RTU_CE_CAN0_INIT_OR_ERROR_IRQn, RTU_CE_CAN1_INIT_OR_ERROR_IRQn, RTU_CE_CAN2_INIT_OR_ERROR_IRQn, \ 191 RTU_CE_CAN3_INIT_OR_ERROR_IRQn, RTU_CE_CAN4_INIT_OR_ERROR_IRQn, RTU_CE_CAN5_INIT_OR_ERROR_IRQn, \ 192 RTU_CE_CAN6_INIT_OR_ERROR_IRQn, RTU_CE_CAN7_INIT_OR_ERROR_IRQn, RTU_CE_CAN8_INIT_OR_ERROR_IRQn, \ 193 RTU_CE_CAN9_INIT_OR_ERROR_IRQn, RTU_CE_CAN10_INIT_OR_ERROR_IRQn, RTU_CE_CAN11_INIT_OR_ERROR_IRQn, \ 194 RTU_CE_CAN12_INIT_OR_ERROR_IRQn, RTU_CE_CAN13_INIT_OR_ERROR_IRQn, RTU_CE_CAN14_INIT_OR_ERROR_IRQn, \ 195 RTU_CE_CAN15_INIT_OR_ERROR_IRQn, RTU_CE_CAN16_INIT_OR_ERROR_IRQn, RTU_CE_CAN17_INIT_OR_ERROR_IRQn, \ 196 RTU_CE_CAN18_INIT_OR_ERROR_IRQn, RTU_CE_CAN19_INIT_OR_ERROR_IRQn, RTU_CE_CAN20_INIT_OR_ERROR_IRQn, \ 197 RTU_CE_CAN21_INIT_OR_ERROR_IRQn, RTU_CE_CAN22_INIT_OR_ERROR_IRQn, RTU_CE_CAN23_INIT_OR_ERROR_IRQn } 198 #define CAN_Error_IRQS { RTU_CE_CAN0_INIT_OR_ERROR_IRQn, RTU_CE_CAN1_INIT_OR_ERROR_IRQn, RTU_CE_CAN2_INIT_OR_ERROR_IRQn, \ 199 RTU_CE_CAN3_INIT_OR_ERROR_IRQn, RTU_CE_CAN4_INIT_OR_ERROR_IRQn, RTU_CE_CAN5_INIT_OR_ERROR_IRQn, \ 200 RTU_CE_CAN6_INIT_OR_ERROR_IRQn, RTU_CE_CAN7_INIT_OR_ERROR_IRQn, RTU_CE_CAN8_INIT_OR_ERROR_IRQn, \ 201 RTU_CE_CAN9_INIT_OR_ERROR_IRQn, RTU_CE_CAN10_INIT_OR_ERROR_IRQn, RTU_CE_CAN11_INIT_OR_ERROR_IRQn, \ 202 RTU_CE_CAN12_INIT_OR_ERROR_IRQn, RTU_CE_CAN13_INIT_OR_ERROR_IRQn, RTU_CE_CAN14_INIT_OR_ERROR_IRQn, \ 203 RTU_CE_CAN15_INIT_OR_ERROR_IRQn, RTU_CE_CAN16_INIT_OR_ERROR_IRQn, RTU_CE_CAN17_INIT_OR_ERROR_IRQn, \ 204 RTU_CE_CAN18_INIT_OR_ERROR_IRQn, RTU_CE_CAN19_INIT_OR_ERROR_IRQn, RTU_CE_CAN20_INIT_OR_ERROR_IRQn, \ 205 RTU_CE_CAN21_INIT_OR_ERROR_IRQn, RTU_CE_CAN22_INIT_OR_ERROR_IRQn, RTU_CE_CAN23_INIT_OR_ERROR_IRQn } 206 #define CAN_Bus_Off_IRQS { RTU_CE_CAN0_INIT_OR_ERROR_IRQn, RTU_CE_CAN1_INIT_OR_ERROR_IRQn, RTU_CE_CAN2_INIT_OR_ERROR_IRQn, \ 207 RTU_CE_CAN3_INIT_OR_ERROR_IRQn, RTU_CE_CAN4_INIT_OR_ERROR_IRQn, RTU_CE_CAN5_INIT_OR_ERROR_IRQn, \ 208 RTU_CE_CAN6_INIT_OR_ERROR_IRQn, RTU_CE_CAN7_INIT_OR_ERROR_IRQn, RTU_CE_CAN8_INIT_OR_ERROR_IRQn, \ 209 RTU_CE_CAN9_INIT_OR_ERROR_IRQn, RTU_CE_CAN10_INIT_OR_ERROR_IRQn, RTU_CE_CAN11_INIT_OR_ERROR_IRQn, \ 210 RTU_CE_CAN12_INIT_OR_ERROR_IRQn, RTU_CE_CAN13_INIT_OR_ERROR_IRQn, RTU_CE_CAN14_INIT_OR_ERROR_IRQn, \ 211 RTU_CE_CAN15_INIT_OR_ERROR_IRQn, RTU_CE_CAN16_INIT_OR_ERROR_IRQn, RTU_CE_CAN17_INIT_OR_ERROR_IRQn, \ 212 RTU_CE_CAN18_INIT_OR_ERROR_IRQn, RTU_CE_CAN19_INIT_OR_ERROR_IRQn, RTU_CE_CAN20_INIT_OR_ERROR_IRQn, \ 213 RTU_CE_CAN21_INIT_OR_ERROR_IRQn, RTU_CE_CAN22_INIT_OR_ERROR_IRQn, RTU_CE_CAN23_INIT_OR_ERROR_IRQn } 214 #define CAN_ORed_Message_buffer_0_31_IRQS { RTU_CE_CAN0_MB_31_0_IRQn, RTU_CE_CAN1_MB_31_0_IRQn, RTU_CE_CAN2_MB_31_0_IRQn, RTU_CE_CAN3_MB_31_0_IRQn, \ 215 RTU_CE_CAN4_MB_31_0_IRQn, RTU_CE_CAN5_MB_31_0_IRQn, RTU_CE_CAN6_MB_31_0_IRQn, RTU_CE_CAN7_MB_31_0_IRQn, \ 216 RTU_CE_CAN8_MB_31_0_IRQn, RTU_CE_CAN9_MB_31_0_IRQn, RTU_CE_CAN10_MB_31_0_IRQn, RTU_CE_CAN11_MB_31_0_IRQn, \ 217 RTU_CE_CAN12_MB_31_0_IRQn, RTU_CE_CAN13_MB_31_0_IRQn, RTU_CE_CAN14_MB_31_0_IRQn, RTU_CE_CAN15_MB_31_0_IRQn, \ 218 RTU_CE_CAN16_MB_31_0_IRQn, RTU_CE_CAN17_MB_31_0_IRQn, RTU_CE_CAN18_MB_31_0_IRQn, RTU_CE_CAN19_MB_31_0_IRQn, \ 219 RTU_CE_CAN20_MB_31_0_IRQn, RTU_CE_CAN21_MB_31_0_IRQn, RTU_CE_CAN22_MB_31_0_IRQn, RTU_CE_CAN23_MB_31_0_IRQn } 220 #define CAN_ORed_Message_buffer_32_63_IRQS { RTU_CE_CAN0_MB_63_32_IRQn, RTU_CE_CAN1_MB_63_32_IRQn, RTU_CE_CAN2_MB_63_32_IRQn, RTU_CE_CAN3_MB_63_32_IRQn, \ 221 RTU_CE_CAN4_MB_63_32_IRQn, RTU_CE_CAN5_MB_63_32_IRQn, RTU_CE_CAN6_MB_63_32_IRQn, RTU_CE_CAN7_MB_63_32_IRQn, \ 222 RTU_CE_CAN8_MB_63_32_IRQn, RTU_CE_CAN9_MB_63_32_IRQn, RTU_CE_CAN10_MB_63_32_IRQn, RTU_CE_CAN11_MB_63_32_IRQn, \ 223 RTU_CE_CAN12_MB_63_32_IRQn, RTU_CE_CAN13_MB_63_32_IRQn, RTU_CE_CAN14_MB_63_32_IRQn, RTU_CE_CAN15_MB_63_32_IRQn, \ 224 RTU_CE_CAN16_MB_63_32_IRQn, RTU_CE_CAN17_MB_63_32_IRQn, RTU_CE_CAN18_MB_63_32_IRQn, RTU_CE_CAN19_MB_63_32_IRQn, \ 225 RTU_CE_CAN20_MB_63_32_IRQn, RTU_CE_CAN21_MB_63_32_IRQn, RTU_CE_CAN22_MB_63_32_IRQn, RTU_CE_CAN23_MB_63_32_IRQn } 226 #define CAN_ORed_Message_buffer_64_95_IRQS { RTU_CE_CAN0_MB_95_64_IRQn, RTU_CE_CAN1_MB_95_64_IRQn, RTU_CE_CAN2_MB_95_64_IRQn, RTU_CE_CAN3_MB_95_64_IRQn, \ 227 RTU_CE_CAN4_MB_95_64_IRQn, RTU_CE_CAN5_MB_95_64_IRQn, RTU_CE_CAN6_MB_95_64_IRQn, RTU_CE_CAN7_MB_95_64_IRQn, \ 228 RTU_CE_CAN8_MB_95_64_IRQn, RTU_CE_CAN9_MB_95_64_IRQn, RTU_CE_CAN10_MB_95_64_IRQn, RTU_CE_CAN11_MB_95_64_IRQn, \ 229 RTU_CE_CAN12_MB_95_64_IRQn, RTU_CE_CAN13_MB_95_64_IRQn, RTU_CE_CAN14_MB_95_64_IRQn, RTU_CE_CAN15_MB_95_64_IRQn, \ 230 RTU_CE_CAN16_MB_95_64_IRQn, RTU_CE_CAN17_MB_95_64_IRQn, RTU_CE_CAN18_MB_95_64_IRQn, RTU_CE_CAN19_MB_95_64_IRQn, \ 231 RTU_CE_CAN20_MB_95_64_IRQn, RTU_CE_CAN21_MB_95_64_IRQn, RTU_CE_CAN22_MB_95_64_IRQn, RTU_CE_CAN23_MB_95_64_IRQn } 232 #define CAN_ORed_Message_buffer_96_127_IRQS { RTU_CE_CAN0_MB_127_96_IRQn, RTU_CE_CAN1_MB_127_96_IRQn, RTU_CE_CAN2_MB_127_96_IRQn, RTU_CE_CAN3_MB_127_96_IRQn, \ 233 RTU_CE_CAN4_MB_127_96_IRQn, RTU_CE_CAN5_MB_127_96_IRQn, RTU_CE_CAN6_MB_127_96_IRQn, RTU_CE_CAN7_MB_127_96_IRQn, \ 234 RTU_CE_CAN8_MB_127_96_IRQn, RTU_CE_CAN9_MB_127_96_IRQn, RTU_CE_CAN10_MB_127_96_IRQn, RTU_CE_CAN11_MB_127_96_IRQn, \ 235 RTU_CE_CAN12_MB_127_96_IRQn, RTU_CE_CAN13_MB_127_96_IRQn, RTU_CE_CAN14_MB_127_96_IRQn, RTU_CE_CAN15_MB_127_96_IRQn, \ 236 RTU_CE_CAN16_MB_127_96_IRQn, RTU_CE_CAN17_MB_127_96_IRQn, RTU_CE_CAN18_MB_127_96_IRQn, RTU_CE_CAN19_MB_127_96_IRQn, \ 237 RTU_CE_CAN20_MB_127_96_IRQn, RTU_CE_CAN21_MB_127_96_IRQn, RTU_CE_CAN22_MB_127_96_IRQn, RTU_CE_CAN23_MB_127_96_IRQn } 238 239 #define CAN_ORed_Message_buffer_IRQS CAN_ORed_Message_buffer_0_31_IRQS 240 241 /*! 242 * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer 243 * @{ 244 */ 245 246 /* LPI2C - Peripheral instance base addresses */ 247 /** Peripheral LPI2C1 base address */ 248 #define LPI2C1_BASE IP_LPI2C_1_BASE 249 /** Peripheral LPI2C1 base pointer */ 250 #define LPI2C1 IP_LPI2C_1 251 /** Peripheral LPI2C2 base address */ 252 #define LPI2C2_BASE IP_LPI2C_2_BASE 253 /** Peripheral LPI2C2 base pointer */ 254 #define LPI2C2 IP_LPI2C_2 255 /** Array initializer of LPI2C peripheral base addresses */ 256 #define LPI2C_BASE_ADDRS IP_LPI2C_BASE_ADDRS 257 /** Array initializer of LPI2C peripheral base pointers */ 258 #define LPI2C_BASE_PTRS IP_LPI2C_BASE_PTRS 259 /** Interrupt vectors for the LPI2C peripheral type */ 260 #define LPI2C_IRQS { RTU_LPI2C1_IRQn, RTU_LPI2C2_IRQn } 261 262 /* EDMA3 - Peripheral instance base addresses */ 263 264 /** Peripheral DMA0 base pointer */ 265 #define DMA0 ((DMA_Type *)IP_EDMA_0_MP_BASE) 266 /** Interrupt vectors for the DMA0 peripheral type */ 267 #define DMA0_IRQS { RTU_DMA0_0_IRQn, RTU_DMA0_1_IRQn, RTU_DMA0_2_IRQn, RTU_DMA0_3_IRQn, \ 268 RTU_DMA0_4_IRQn, RTU_DMA0_5_IRQn, RTU_DMA0_6_IRQn, RTU_DMA0_7_IRQn, \ 269 RTU_DMA0_8_IRQn, RTU_DMA0_9_IRQn, RTU_DMA0_10_IRQn, RTU_DMA0_11_IRQn, \ 270 RTU_DMA0_12_IRQn, RTU_DMA0_13_IRQn, RTU_DMA0_14_IRQn, RTU_DMA0_15_IRQn,\ 271 RTU_DMA0_16_IRQn, RTU_DMA0_17_IRQn, RTU_DMA0_18_IRQn, RTU_DMA0_19_IRQn,\ 272 RTU_DMA0_20_IRQn, RTU_DMA0_21_IRQn, RTU_DMA0_22_IRQn, RTU_DMA0_23_IRQn,\ 273 RTU_DMA0_24_IRQn, RTU_DMA0_25_IRQn, RTU_DMA0_26_IRQn, RTU_DMA0_27_IRQn,\ 274 RTU_DMA0_28_IRQn, RTU_DMA0_29_IRQn, RTU_DMA0_30_IRQn, RTU_DMA0_31_IRQn } 275 276 #define DMA0_ERROR_IRQS { RTU_DMA0_ERR_IRQn } 277 278 /** Peripheral DMA1 base pointer */ 279 #define DMA1 ((DMA_Type *)IP_EDMA_1_MP_BASE) 280 /** Interrupt vectors for the DMA1 peripheral type */ 281 #define DMA1_IRQS { RTU_DMA1_0_IRQn, RTU_DMA1_1_IRQn, RTU_DMA1_2_IRQn, RTU_DMA1_3_IRQn, \ 282 RTU_DMA1_4_IRQn, RTU_DMA1_5_IRQn, RTU_DMA1_6_IRQn, RTU_DMA1_7_IRQn, \ 283 RTU_DMA1_8_IRQn, RTU_DMA1_9_IRQn, RTU_DMA1_10_IRQn, RTU_DMA1_11_IRQn, \ 284 RTU_DMA1_12_IRQn, RTU_DMA1_13_IRQn, RTU_DMA1_14_IRQn, RTU_DMA1_15_IRQn } 285 286 #define DMA1_ERROR_IRQS { RTU_DMA1_ERR_IRQn } 287 288 /** Peripheral DMA4 base pointer */ 289 #define DMA4 ((DMA_Type *)IP_EDMA_4_MP_BASE) 290 /** Interrupt vectors for the DMA4 peripheral type */ 291 #define DMA4_IRQS { RTU_DMA4_0_IRQn, RTU_DMA4_1_IRQn, RTU_DMA4_2_IRQn, RTU_DMA4_3_IRQn, \ 292 RTU_DMA4_4_IRQn, RTU_DMA4_5_IRQn, RTU_DMA4_6_IRQn, RTU_DMA4_7_IRQn, \ 293 RTU_DMA4_8_IRQn, RTU_DMA4_9_IRQn, RTU_DMA4_10_IRQn, RTU_DMA4_11_IRQn, \ 294 RTU_DMA4_12_IRQn, RTU_DMA4_13_IRQn, RTU_DMA4_14_IRQn, RTU_DMA4_15_IRQn } 295 296 #define DMA4_ERROR_IRQS { RTU_DMA4_ERR_IRQn } 297 298 /** Peripheral DMA5 base pointer */ 299 #define DMA5 ((DMA_Type *)IP_EDMA_5_MP_BASE) 300 /** Interrupt vectors for the DMA5 peripheral type */ 301 #define DMA5_IRQS { RTU_DMA5_0_IRQn, RTU_DMA5_1_IRQn, RTU_DMA5_2_IRQn, RTU_DMA5_3_IRQn, \ 302 RTU_DMA5_4_IRQn, RTU_DMA5_5_IRQn, RTU_DMA5_6_IRQn, RTU_DMA5_7_IRQn, \ 303 RTU_DMA5_8_IRQn, RTU_DMA5_9_IRQn, RTU_DMA5_10_IRQn, RTU_DMA5_11_IRQn, \ 304 RTU_DMA5_12_IRQn, RTU_DMA5_13_IRQn, RTU_DMA5_14_IRQn, RTU_DMA5_15_IRQn } 305 306 #define DMA5_ERROR_IRQS { RTU_DMA5_ERR_IRQn } 307 308 /** Array initializer of DMA peripheral base pointers */ 309 #define DMA_BASE_PTRS { DMA0, DMA1, DMA4, DMA5 } 310 /** Interrupt vectors for the DMA peripheral type */ 311 #define DMA_IRQS { DMA0_IRQS, DMA1_IRQS, DMA4_IRQS, DMA5_IRQS } 312 #define DMA_ERROR_IRQS { DMA0_ERROR_IRQS, DMA1_ERROR_IRQS, DMA4_ERROR_IRQS, DMA5_ERROR_IRQS } 313 314 #endif /* _S32Z270_GLUE_MCUX_H_ */ 315
