1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_dma2d.h 4 * @author MCD Application Team 5 * @brief Header file of DMA2D HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef STM32L4xx_HAL_DMA2D_H 38 #define STM32L4xx_HAL_DMA2D_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 #if defined (DMA2D) 45 /* Includes ------------------------------------------------------------------*/ 46 #include "stm32l4xx_hal_def.h" 47 48 /** @addtogroup STM32L4xx_HAL_Driver 49 * @{ 50 */ 51 52 /** @addtogroup DMA2D DMA2D 53 * @brief DMA2D HAL module driver 54 * @{ 55 */ 56 57 /* Exported types ------------------------------------------------------------*/ 58 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types 59 * @{ 60 */ 61 #define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ 62 63 /** 64 * @brief DMA2D color Structure definition 65 */ 66 typedef struct 67 { 68 uint32_t Blue; /*!< Configures the blue value. 69 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ 70 71 uint32_t Green; /*!< Configures the green value. 72 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ 73 74 uint32_t Red; /*!< Configures the red value. 75 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ 76 } DMA2D_ColorTypeDef; 77 78 /** 79 * @brief DMA2D CLUT Structure definition 80 */ 81 typedef struct 82 { 83 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ 84 85 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. 86 This parameter can be one value of @ref DMA2D_CLUT_CM. */ 87 88 uint32_t Size; /*!< Configures the DMA2D CLUT size. 89 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ 90 } DMA2D_CLUTCfgTypeDef; 91 92 /** 93 * @brief DMA2D Init structure definition 94 */ 95 typedef struct 96 { 97 uint32_t Mode; /*!< Configures the DMA2D transfer mode. 98 This parameter can be one value of @ref DMA2D_Mode. */ 99 100 uint32_t ColorMode; /*!< Configures the color format of the output image. 101 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ 102 103 uint32_t OutputOffset; /*!< Specifies the Offset value. 104 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 105 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. 106 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 107 108 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) 109 for the output pixel format converter. 110 This parameter can be one value of @ref DMA2D_RB_Swap. */ 111 112 113 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) 114 uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). 115 This parameter can be one value of @ref DMA2D_Bytes_Swap. */ 116 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ 117 118 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) 119 uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. 120 This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ 121 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ 122 123 } DMA2D_InitTypeDef; 124 125 126 /** 127 * @brief DMA2D Layer structure definition 128 */ 129 typedef struct 130 { 131 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. 132 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 133 134 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. 135 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ 136 137 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. 138 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ 139 140 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. 141 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below. 142 @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between 143 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where 144 - InputAlpha[24:31] is the alpha value ALPHA[0:7] 145 - InputAlpha[16:23] is the red value RED[0:7] 146 - InputAlpha[8:15] is the green value GREEN[0:7] 147 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ 148 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. 149 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 150 151 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). 152 This parameter can be one value of @ref DMA2D_RB_Swap. */ 153 154 155 } DMA2D_LayerCfgTypeDef; 156 157 /** 158 * @brief HAL DMA2D State structures definition 159 */ 160 typedef enum 161 { 162 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ 163 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 164 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 165 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 166 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ 167 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ 168 }HAL_DMA2D_StateTypeDef; 169 170 /** 171 * @brief DMA2D handle Structure definition 172 */ 173 typedef struct __DMA2D_HandleTypeDef 174 { 175 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ 176 177 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ 178 179 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */ 180 181 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ 182 183 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 184 void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */ 185 186 void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */ 187 188 void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */ 189 190 void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */ 191 192 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ 193 194 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ 195 196 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ 197 198 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ 199 200 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ 201 } DMA2D_HandleTypeDef; 202 203 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 204 /** 205 * @brief HAL DMA2D Callback pointer definition 206 */ 207 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */ 208 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 209 /** 210 * @} 211 */ 212 213 /* Exported constants --------------------------------------------------------*/ 214 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants 215 * @{ 216 */ 217 218 /** @defgroup DMA2D_Error_Code DMA2D Error Code 219 * @{ 220 */ 221 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ 222 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ 223 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ 224 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ 225 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 226 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 227 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ 228 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ 229 230 /** 231 * @} 232 */ 233 234 /** @defgroup DMA2D_Mode DMA2D Mode 235 * @{ 236 */ 237 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 238 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 239 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 240 #define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ 241 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) 242 #define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ 243 #define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ 244 #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ 245 /** 246 * @} 247 */ 248 249 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 250 * @{ 251 */ 252 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ 253 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ 254 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ 255 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ 256 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ 257 /** 258 * @} 259 */ 260 261 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode 262 * @{ 263 */ 264 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ 265 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ 266 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ 267 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ 268 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ 269 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ 270 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ 271 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ 272 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ 273 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ 274 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ 275 /** 276 * @} 277 */ 278 279 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode 280 * @{ 281 */ 282 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 283 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ 284 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value 285 with original alpha channel value */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion 291 * @{ 292 */ 293 #define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 294 #define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */ 295 /** 296 * @} 297 */ 298 299 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap 300 * @{ 301 */ 302 #define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */ 303 #define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */ 304 /** 305 * @} 306 */ 307 308 309 310 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) 311 /** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode 312 * @{ 313 */ 314 #define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */ 315 #define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ 316 /** 317 * @} 318 */ 319 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ 320 321 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) 322 /** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap 323 * @{ 324 */ 325 #define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */ 326 #define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ 327 /** 328 * @} 329 */ 330 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ 331 332 333 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode 334 * @{ 335 */ 336 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ 337 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ 338 /** 339 * @} 340 */ 341 342 /** @defgroup DMA2D_Interrupts DMA2D Interrupts 343 * @{ 344 */ 345 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 346 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 347 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 348 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 349 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 350 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 351 /** 352 * @} 353 */ 354 355 /** @defgroup DMA2D_Flags DMA2D Flags 356 * @{ 357 */ 358 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 359 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 360 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 361 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 362 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 363 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 364 /** 365 * @} 366 */ 367 368 /** @defgroup DMA2D_Aliases DMA2D API Aliases 369 * @{ 370 */ 371 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */ 372 /** 373 * @} 374 */ 375 376 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 377 /** 378 * @brief HAL DMA2D common Callback ID enumeration definition 379 */ 380 typedef enum 381 { 382 HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ 383 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ 384 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ 385 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ 386 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ 387 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ 388 }HAL_DMA2D_CallbackIDTypeDef; 389 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 390 391 392 /** 393 * @} 394 */ 395 /* Exported macros ------------------------------------------------------------*/ 396 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros 397 * @{ 398 */ 399 400 /** @brief Reset DMA2D handle state 401 * @param __HANDLE__ specifies the DMA2D handle. 402 * @retval None 403 */ 404 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 405 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ 406 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ 407 (__HANDLE__)->MspInitCallback = NULL; \ 408 (__HANDLE__)->MspDeInitCallback = NULL; \ 409 }while(0) 410 #else 411 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) 412 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 413 414 415 /** 416 * @brief Enable the DMA2D. 417 * @param __HANDLE__ DMA2D handle 418 * @retval None. 419 */ 420 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) 421 422 423 /* Interrupt & Flag management */ 424 /** 425 * @brief Get the DMA2D pending flags. 426 * @param __HANDLE__ DMA2D handle 427 * @param __FLAG__ flag to check. 428 * This parameter can be any combination of the following values: 429 * @arg DMA2D_FLAG_CE: Configuration error flag 430 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 431 * @arg DMA2D_FLAG_CAE: CLUT access error flag 432 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 433 * @arg DMA2D_FLAG_TC: Transfer complete flag 434 * @arg DMA2D_FLAG_TE: Transfer error flag 435 * @retval The state of FLAG. 436 */ 437 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 438 439 /** 440 * @brief Clear the DMA2D pending flags. 441 * @param __HANDLE__ DMA2D handle 442 * @param __FLAG__ specifies the flag to clear. 443 * This parameter can be any combination of the following values: 444 * @arg DMA2D_FLAG_CE: Configuration error flag 445 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 446 * @arg DMA2D_FLAG_CAE: CLUT access error flag 447 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 448 * @arg DMA2D_FLAG_TC: Transfer complete flag 449 * @arg DMA2D_FLAG_TE: Transfer error flag 450 * @retval None 451 */ 452 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) 453 454 /** 455 * @brief Enable the specified DMA2D interrupts. 456 * @param __HANDLE__ DMA2D handle 457 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. 458 * This parameter can be any combination of the following values: 459 * @arg DMA2D_IT_CE: Configuration error interrupt mask 460 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 461 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 462 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 463 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 464 * @arg DMA2D_IT_TE: Transfer error interrupt mask 465 * @retval None 466 */ 467 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 468 469 /** 470 * @brief Disable the specified DMA2D interrupts. 471 * @param __HANDLE__ DMA2D handle 472 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. 473 * This parameter can be any combination of the following values: 474 * @arg DMA2D_IT_CE: Configuration error interrupt mask 475 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 476 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 477 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 478 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 479 * @arg DMA2D_IT_TE: Transfer error interrupt mask 480 * @retval None 481 */ 482 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 483 484 /** 485 * @brief Check whether the specified DMA2D interrupt source is enabled or not. 486 * @param __HANDLE__ DMA2D handle 487 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. 488 * This parameter can be one of the following values: 489 * @arg DMA2D_IT_CE: Configuration error interrupt mask 490 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 491 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 492 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 493 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 494 * @arg DMA2D_IT_TE: Transfer error interrupt mask 495 * @retval The state of INTERRUPT source. 496 */ 497 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 498 499 /** 500 * @} 501 */ 502 503 /* Exported functions --------------------------------------------------------*/ 504 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions 505 * @{ 506 */ 507 508 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions 509 * @{ 510 */ 511 512 /* Initialization and de-initialization functions *******************************/ 513 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 514 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); 515 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); 516 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); 517 /* Callbacks Register/UnRegister functions ***********************************/ 518 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 519 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback); 520 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); 521 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 522 523 /** 524 * @} 525 */ 526 527 528 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions 529 * @{ 530 */ 531 532 /* IO operation functions *******************************************************/ 533 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); 534 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); 535 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); 536 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); 537 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); 538 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); 539 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); 540 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 541 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 542 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 543 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 544 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 545 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 546 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); 547 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); 548 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); 549 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); 550 551 /** 552 * @} 553 */ 554 555 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions 556 * @{ 557 */ 558 559 /* Peripheral Control functions *************************************************/ 560 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 561 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 562 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); 563 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); 564 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); 565 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); 566 567 /** 568 * @} 569 */ 570 571 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions 572 * @{ 573 */ 574 575 /* Peripheral State functions ***************************************************/ 576 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); 577 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); 578 579 /** 580 * @} 581 */ 582 583 /** 584 * @} 585 */ 586 587 /* Private constants ---------------------------------------------------------*/ 588 589 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants 590 * @{ 591 */ 592 593 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 594 * @{ 595 */ 596 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ 597 /** 598 * @} 599 */ 600 601 /** @defgroup DMA2D_Color_Value DMA2D Color Value 602 * @{ 603 */ 604 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ 605 /** 606 * @} 607 */ 608 609 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers 610 * @{ 611 */ 612 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ 613 /** 614 * @} 615 */ 616 617 /** @defgroup DMA2D_Layers DMA2D Layers 618 * @{ 619 */ 620 #define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ 621 #define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ 622 /** 623 * @} 624 */ 625 626 /** @defgroup DMA2D_Offset DMA2D Offset 627 * @{ 628 */ 629 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ 630 /** 631 * @} 632 */ 633 634 /** @defgroup DMA2D_Size DMA2D Size 635 * @{ 636 */ 637 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ 638 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ 639 /** 640 * @} 641 */ 642 643 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size 644 * @{ 645 */ 646 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ 647 /** 648 * @} 649 */ 650 651 /** 652 * @} 653 */ 654 655 656 /* Private macros ------------------------------------------------------------*/ 657 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros 658 * @{ 659 */ 660 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER)) 661 662 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) 663 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 664 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ 665 ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) 666 #else 667 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 668 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) 669 #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ 670 671 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ 672 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ 673 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) 674 675 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) 676 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) 677 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) 678 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) 679 680 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ 681 ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ 682 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ 683 ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ 684 ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ 685 ((INPUT_CM) == DMA2D_INPUT_A4)) 686 687 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ 688 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ 689 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) 690 691 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ 692 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) 693 694 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ 695 ((RB_Swap) == DMA2D_RB_SWAP)) 696 697 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) 698 #define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ 699 ((LOM) == DMA2D_LOM_BYTES)) 700 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ 701 702 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) 703 #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ 704 ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) 705 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ 706 707 708 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) 709 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) 710 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) 711 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ 712 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ 713 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) 714 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ 715 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ 716 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 717 /** 718 * @} 719 */ 720 721 /** 722 * @} 723 */ 724 725 /** 726 * @} 727 */ 728 729 #endif /* DMA2D */ 730 731 #ifdef __cplusplus 732 } 733 #endif 734 735 #endif /* STM32L4xx_HAL_DMA2D_H */ 736 737 738 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 739
