1 // Copyright 2019 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 /** 22 * @brief Registers in DM9051 23 * 24 */ 25 #define DM9051_NCR (0x00) // Network Control Register 26 #define DM9051_NSR (0x01) // Network Status Register 27 #define DM9051_TCR (0x02) // Tx Control Register 28 #define DM9051_TSR1 (0x03) // Tx Status Register I 29 #define DM9051_TSR2 (0x04) // Tx Status Register II 30 #define DM9051_RCR (0x05) // Rx Control Register 31 #define DM9051_RSR (0x06) // Rx Status Register 32 #define DM9051_ROCR (0x07) // Receive Overflow Counter Register 33 #define DM9051_BPTR (0x08) // Back Pressure Threshold Register 34 #define DM9051_FCTR (0x09) // Flow Control Threshold Register 35 #define DM9051_FCR (0x0A) // Rx/Tx Flow Control Register 36 #define DM9051_EPCR (0x0B) // EEPROM & PHY Control Register 37 #define DM9051_EPAR (0x0C) // EEPROM & PHY Address Register 38 #define DM9051_EPDRL (0x0D) // EEPROM & PHY Data Register Low 39 #define DM9051_EPDRH (0x0E) // EEPROM & PHY Data Register High 40 #define DM9051_WCR (0x0F) // Wake Up Control Register 41 #define DM9051_PAR (0x10) // Physical Address Register 42 #define DM9051_MAR (0x16) // Multicast Address Hash Table Register 43 #define DM9051_GPCR (0x1E) // General Purpose Control Register 44 #define DM9051_GPR (0x1F) // General Purpose Register 45 #define DM9051_TRPAL (0x22) // Tx Memory Read Pointer Address Low Byte 46 #define DM9051_TRPAH (0x23) // Tx Memory Read Pointer Address High Byte 47 #define DM9051_RWPAL (0x24) // Rx Memory Read Pointer Address Low Byte 48 #define DM9051_RWPAH (0x25) // Rx Memory Read Pointer Address High Byte 49 #define DM9051_VIDL (0x28) // Vendor ID Low Byte 50 #define DM9051_VIDH (0x29) // Vendor ID High Byte 51 #define DM9051_PIDL (0x2A) // Product ID Low Byte 52 #define DM9051_PIDH (0x2B) // Product ID High Byte 53 #define DM9051_CHIPR (0x2C) // CHIP Revision 54 #define DM9051_TCR2 (0x2D) // Transmit Control Register 2 55 #define DM9051_ATCR (0x30) // Auto-Transmit Control Register 56 #define DM9051_TCSCR (0x31) // Transmit Check Sum Control Register 57 #define DM9051_RCSCSR (0x32) // Receive Check Sum Control Status Register 58 #define DM9051_SBCR (0x38) // SPI Bus Control Register 59 #define DM9051_INTCR (0x39) // INT Pin Control Register 60 #define DM9051_PPCSR (0x3D) // Pause Packet Control Status Register 61 #define DM9051_EEE_IN (0x3E) // IEEE 802.3az Enter Counter Register 62 #define DM9051_EEE_OUT (0x3F) // IEEE 802.3az Leave Counter Register 63 #define DM9051_ALNCR (0x4A) // SPI Byte Align Error Counter Register 64 #define DM9051_RLENCR (0x52) // Rx Packet Length Control Register 65 #define DM9051_BCASTCR (0x53) // RX Broadcast Control Register 66 #define DM9051_INTCKCR (0x54) // INT Pin Clock Output Control Register 67 #define DM9051_MPTRCR (0x55) // Memory Pointer Control Register 68 #define DM9051_MLEDCR (0x57) // More LED Control Register 69 #define DM9051_MEMSCR (0x59) // Memory Control Register 70 #define DM9051_TMEMR (0x5A) // Transmit Memory Size Register 71 #define DM9051_MBSR (0x5D) // Memory BIST Status Register 72 #define DM9051_MRCMDX (0x70) // Memory Data Pre-Fetch Read Command Without Address Increment Register 73 #define DM9051_MRCMDX1 (0x71) // Memory Read Command Without Pre-Fetch and Without Address Increment Register 74 #define DM9051_MRCMD (0x72) // Memory Data Read Command With Address Increment Register 75 #define DM9051_SDR_DLY (0x73) // SPI Data Read Delay Counter Register 76 #define DM9051_MRRL (0x74) // Memory Data Read Address Register Low Byte 77 #define DM9051_MRRH (0x75) // Memory Data Read Address Register High Byte 78 #define DM9051_MWCMDX (0x76) // Memory Data Write Command Without Address Increment Register 79 #define DM9051_MWCMD (0x78) // Memory Data Write Command With Address Increment Register 80 #define DM9051_MWRL (0x7A) // Memory Data Write Address Register Low Byte 81 #define DM9051_MWRH (0x7B) // Memory Data Write Address Register High Byte 82 #define DM9051_TXPLL (0x7C) // TX Packet Length Low Byte Register 83 #define DM9051_TXPLH (0x7D) // TX Packet Length High Byte Register 84 #define DM9051_ISR (0x7E) // Interrupt Status Register 85 #define DM9051_IMR (0x7F) // Interrupt Mask Register 86 87 /** 88 * @brief status and flag of DM9051 specific registers 89 * 90 */ 91 #define DM9051_SPI_RD (0) // Burst Read Command 92 #define DM9051_SPI_WR (1) // Burst Write Command 93 94 #define NCR_WAKEEN (1 << 6) // Enable Wakeup Function 95 #define NCR_FDX (1 << 3) // Duplex Mode of the Internal PHY 96 #define NCR_RST (1 << 0) // Software Reset and Auto-Clear after 10us 97 98 #define NSR_SPEED (1 << 7) // Speed of Internal PHY 99 #define NSR_LINKST (1 << 6) // Link Status of Internal PHY 100 #define NSR_WAKEST (1 << 5) // Wakeup Event Status 101 #define NSR_TX2END (1 << 3) // TX Packet Index II Complete Status 102 #define NSR_TX1END (1 << 2) // TX Packet Index I Complete Status 103 #define NSR_RXOV (1 << 1) // RX Memory Overflow Status 104 #define NSR_RXRDY (1 << 0) // RX Packet Ready 105 106 #define TCR_TXREQ (1 << 0) // TX Request. Auto-Clear after Sending Completely 107 108 #define RCR_WTDIS (1 << 6) // Watchdog Timer Disable 109 #define RCR_DIS_LONG (1 << 5) // Discard Long Packet 110 #define RCR_DIS_CRC (1 << 4) // Discard CRC Error Packet 111 #define RCR_ALL (1 << 3) // Receive All Multicast 112 #define RCR_RUNT (1 << 2) // Receive Runt Packet 113 #define RCR_PRMSC (1 << 1) // Promiscuous Mode 114 #define RCR_RXEN (1 << 0) // RX Enable 115 116 #define RSR_RF (1 << 7) // Runt Frame 117 #define RSR_MF (1 << 6) // Multicast Frame 118 #define RSR_LCS (1 << 5) // Late Collision Seen 119 #define RSR_RWTO (1 << 4) // Receive Watchdog Time-Out 120 #define RSR_PLE (1 << 3) // Physical Layer Error 121 #define RSR_AE (1 << 2) // Alignment Error 122 #define RSR_CE (1 << 1) // CRC Error 123 #define RSR_FOE (1 << 0) // RX Memory Overflow Error 124 125 #define FCR_FLOW_ENABLE (0x39) // Enable Flow Control 126 127 #define EPCR_REEP (1 << 5) // Reload EEPROM 128 #define EPCR_WEP (1 << 4) // Write EEPROM Enable 129 #define EPCR_EPOS (1 << 3) // EEPROM or PHY Operation Select 130 #define EPCR_ERPRR (1 << 2) // EEPROM Read or PHY Register Read Command 131 #define EPCR_ERPRW (1 << 1) // EEPROM Write or PHY Register Write Command 132 #define EPCR_ERRE (1 << 0) // EEPROM Access Status or PHY Access Status 133 134 #define TCR2_RLCP (1 << 6) // Retry Late Collision Packet 135 136 #define ATCR_AUTO_TX (1 << 7) // Auto-Transmit Control 137 138 #define TCSCR_UDPCSE (1 << 2) // UDP CheckSum Generation 139 #define TCSCR_TCPCSE (1 << 1) // TCP CheckSum Generation 140 #define TCSCR_IPCSE (1 << 0) // IPv4 CheckSum Generation 141 142 #define MPTRCR_RST_TX (1 << 1) // Reset TX Memory Pointer 143 #define MPTRCR_RST_RX (1 << 0) // Reset RX Memory Pointer 144 145 #define ISR_LNKCHGS (1 << 5) // Link Status Change 146 #define ISR_ROO (1 << 3) // Receive Overflow Counter Overflow 147 #define ISR_ROS (1 << 2) // Receive Overflow 148 #define ISR_PT (1 << 1) // Packet Transmitted 149 #define ISR_PR (1 << 0) // Packet Received 150 #define ISR_CLR_STATUS (ISR_LNKCHGS | ISR_ROO | ISR_ROS | ISR_PT | ISR_PR) 151 152 #define IMR_PAR (1 << 7) // Pointer Auto-Return Mode 153 #define IMR_LNKCHGI (1 << 5) // Enable Link Status Change Interrupt 154 #define IMR_ROOI (1 << 3) // Enable Receive Overflow Counter Overflow Interrupt 155 #define IMR_ROI (1 << 2) // Enable Receive Overflow Interrupt 156 #define IMR_PTI (1 << 1) // Enable Packet Transmitted Interrupt 157 #define IMR_PRI (1 << 0) // Enable Packet Received Interrupt 158 #define IMR_ALL (IMR_PAR | IMR_LNKCHGI | IMR_ROOI | IMR_ROI | IMR_PTI | IMR_PRI) 159 160 #ifdef __cplusplus 161 } 162 #endif 163
