1 /* 2 * Copyright (c) 2020 Mohamed ElShahawi. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_ESP32_CLOCK_H_ 8 #define ZEPHYR_DRIVERS_CLOCK_CONTROL_ESP32_CLOCK_H_ 9 10 #include <soc/efuse_reg.h> 11 12 /* 13 * Convenience macros for the above functions. 14 */ 15 #define I2C_WRITEREG_RTC(block, reg_add, indata) \ 16 esp32_rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata) 17 18 #define I2C_READREG_RTC(block, reg_add) \ 19 esp32_rom_i2c_readReg(block, block##_HOSTID, reg_add) 20 21 /* 22 * Get voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. 23 * 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) 24 */ 25 #define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV))) 26 #ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M 27 #define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT 28 #else 29 #define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10 30 #endif 31 #define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT 32 #define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 33 #define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 34 35 #define DELAY_PLL_DBIAS_RAISE 3 36 37 /** 38 * Register definitions for digital PLL (BBPLL) 39 * This file lists register fields of BBPLL, located on an internal configuration 40 * bus. 41 */ 42 #define I2C_BBPLL 0x66 43 #define I2C_BBPLL_HOSTID 4 44 #define I2C_BBPLL_IR_CAL_DELAY 0 45 #define I2C_BBPLL_IR_CAL_EXT_CAP 1 46 #define I2C_BBPLL_OC_LREF 2 47 #define I2C_BBPLL_OC_DIV_7_0 3 48 #define I2C_BBPLL_OC_ENB_FCAL 4 49 #define I2C_BBPLL_OC_DCUR 5 50 #define I2C_BBPLL_BBADC_DSMP 9 51 #define I2C_BBPLL_OC_ENB_VCON 10 52 #define I2C_BBPLL_ENDIV5 11 53 #define I2C_BBPLL_BBADC_CAL_7_0 12 54 55 /* BBPLL configuration values */ 56 #define BBPLL_ENDIV5_VAL_320M 0x43 57 #define BBPLL_BBADC_DSMP_VAL_320M 0x84 58 #define BBPLL_ENDIV5_VAL_480M 0xc3 59 #define BBPLL_BBADC_DSMP_VAL_480M 0x74 60 #define BBPLL_IR_CAL_DELAY_VAL 0x18 61 #define BBPLL_IR_CAL_EXT_CAP_VAL 0x20 62 #define BBPLL_OC_ENB_FCAL_VAL 0x9a 63 #define BBPLL_OC_ENB_VCON_VAL 0x00 64 #define BBPLL_BBADC_CAL_7_0_VAL 0x00 65 66 extern uint32_t esp32_rom_g_ticks_per_us_pro; 67 extern uint32_t esp32_rom_g_ticks_per_us_app; 68 extern void esp32_rom_ets_delay_us(uint32_t us); 69 70 #endif /* ZEPHYR_DRIVERS_CLOCK_CONTROL_ESP32_CLOCK_H_ */ 71
