1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_DFS.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_DFS 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_DFS_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_DFS_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- DFS Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup DFS_Peripheral_Access_Layer DFS Peripheral Access Layer 68 * @{ 69 */ 70 71 /** DFS - Size of Registers Arrays */ 72 #define DFS_DVPORT_COUNT 6u 73 74 /** DFS - Register Layout Typedef */ 75 typedef struct { 76 uint8_t RESERVED_0[12]; 77 __I uint32_t PORTSR; /**< Port Status Register, offset: 0xC */ 78 __IO uint32_t PORTLOLSR; /**< Port Loss of Lock Status, offset: 0x10 */ 79 __IO uint32_t PORTRESET; /**< Port Reset, offset: 0x14 */ 80 __IO uint32_t CTL; /**< Control, offset: 0x18 */ 81 __IO uint32_t DVPORT[DFS_DVPORT_COUNT]; /**< Divider for Port 0..Divider for Port 5, array offset: 0x1C, array step: 0x4 */ 82 } DFS_Type, *DFS_MemMapPtr; 83 84 /** Number of instances of the DFS module. */ 85 #define DFS_INSTANCE_COUNT (2u) 86 87 /* DFS - Peripheral instance base addresses */ 88 /** Peripheral CORE_DFS base address */ 89 #define IP_CORE_DFS_BASE (0x40260000u) 90 /** Peripheral CORE_DFS base pointer */ 91 #define IP_CORE_DFS ((DFS_Type *)IP_CORE_DFS_BASE) 92 /** Peripheral PERIPH_DFS base address */ 93 #define IP_PERIPH_DFS_BASE (0x40270000u) 94 /** Peripheral PERIPH_DFS base pointer */ 95 #define IP_PERIPH_DFS ((DFS_Type *)IP_PERIPH_DFS_BASE) 96 /** Array initializer of DFS peripheral base addresses */ 97 #define IP_DFS_BASE_ADDRS { IP_CORE_DFS_BASE, IP_PERIPH_DFS_BASE } 98 /** Array initializer of DFS peripheral base pointers */ 99 #define IP_DFS_BASE_PTRS { IP_CORE_DFS, IP_PERIPH_DFS } 100 101 /* ---------------------------------------------------------------------------- 102 -- DFS Register Masks 103 ---------------------------------------------------------------------------- */ 104 105 /*! 106 * @addtogroup DFS_Register_Masks DFS Register Masks 107 * @{ 108 */ 109 110 /*! @name PORTSR - Port Status Register */ 111 /*! @{ */ 112 113 #define DFS_PORTSR_PORTSTAT0_MASK (0x1U) 114 #define DFS_PORTSR_PORTSTAT0_SHIFT (0U) 115 #define DFS_PORTSR_PORTSTAT0_WIDTH (1U) 116 #define DFS_PORTSR_PORTSTAT0(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTSR_PORTSTAT0_SHIFT)) & DFS_PORTSR_PORTSTAT0_MASK) 117 118 #define DFS_PORTSR_PORTSTAT1_MASK (0x2U) 119 #define DFS_PORTSR_PORTSTAT1_SHIFT (1U) 120 #define DFS_PORTSR_PORTSTAT1_WIDTH (1U) 121 #define DFS_PORTSR_PORTSTAT1(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTSR_PORTSTAT1_SHIFT)) & DFS_PORTSR_PORTSTAT1_MASK) 122 123 #define DFS_PORTSR_PORTSTAT2_MASK (0x4U) 124 #define DFS_PORTSR_PORTSTAT2_SHIFT (2U) 125 #define DFS_PORTSR_PORTSTAT2_WIDTH (1U) 126 #define DFS_PORTSR_PORTSTAT2(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTSR_PORTSTAT2_SHIFT)) & DFS_PORTSR_PORTSTAT2_MASK) 127 128 #define DFS_PORTSR_PORTSTAT3_MASK (0x8U) 129 #define DFS_PORTSR_PORTSTAT3_SHIFT (3U) 130 #define DFS_PORTSR_PORTSTAT3_WIDTH (1U) 131 #define DFS_PORTSR_PORTSTAT3(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTSR_PORTSTAT3_SHIFT)) & DFS_PORTSR_PORTSTAT3_MASK) 132 133 #define DFS_PORTSR_PORTSTAT4_MASK (0x10U) 134 #define DFS_PORTSR_PORTSTAT4_SHIFT (4U) 135 #define DFS_PORTSR_PORTSTAT4_WIDTH (1U) 136 #define DFS_PORTSR_PORTSTAT4(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTSR_PORTSTAT4_SHIFT)) & DFS_PORTSR_PORTSTAT4_MASK) 137 138 #define DFS_PORTSR_PORTSTAT5_MASK (0x20U) 139 #define DFS_PORTSR_PORTSTAT5_SHIFT (5U) 140 #define DFS_PORTSR_PORTSTAT5_WIDTH (1U) 141 #define DFS_PORTSR_PORTSTAT5(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTSR_PORTSTAT5_SHIFT)) & DFS_PORTSR_PORTSTAT5_MASK) 142 /*! @} */ 143 144 /*! @name PORTLOLSR - Port Loss of Lock Status */ 145 /*! @{ */ 146 147 #define DFS_PORTLOLSR_LOLF0_MASK (0x1U) 148 #define DFS_PORTLOLSR_LOLF0_SHIFT (0U) 149 #define DFS_PORTLOLSR_LOLF0_WIDTH (1U) 150 #define DFS_PORTLOLSR_LOLF0(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTLOLSR_LOLF0_SHIFT)) & DFS_PORTLOLSR_LOLF0_MASK) 151 152 #define DFS_PORTLOLSR_LOLF1_MASK (0x2U) 153 #define DFS_PORTLOLSR_LOLF1_SHIFT (1U) 154 #define DFS_PORTLOLSR_LOLF1_WIDTH (1U) 155 #define DFS_PORTLOLSR_LOLF1(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTLOLSR_LOLF1_SHIFT)) & DFS_PORTLOLSR_LOLF1_MASK) 156 157 #define DFS_PORTLOLSR_LOLF2_MASK (0x4U) 158 #define DFS_PORTLOLSR_LOLF2_SHIFT (2U) 159 #define DFS_PORTLOLSR_LOLF2_WIDTH (1U) 160 #define DFS_PORTLOLSR_LOLF2(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTLOLSR_LOLF2_SHIFT)) & DFS_PORTLOLSR_LOLF2_MASK) 161 162 #define DFS_PORTLOLSR_LOLF3_MASK (0x8U) 163 #define DFS_PORTLOLSR_LOLF3_SHIFT (3U) 164 #define DFS_PORTLOLSR_LOLF3_WIDTH (1U) 165 #define DFS_PORTLOLSR_LOLF3(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTLOLSR_LOLF3_SHIFT)) & DFS_PORTLOLSR_LOLF3_MASK) 166 167 #define DFS_PORTLOLSR_LOLF4_MASK (0x10U) 168 #define DFS_PORTLOLSR_LOLF4_SHIFT (4U) 169 #define DFS_PORTLOLSR_LOLF4_WIDTH (1U) 170 #define DFS_PORTLOLSR_LOLF4(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTLOLSR_LOLF4_SHIFT)) & DFS_PORTLOLSR_LOLF4_MASK) 171 172 #define DFS_PORTLOLSR_LOLF5_MASK (0x20U) 173 #define DFS_PORTLOLSR_LOLF5_SHIFT (5U) 174 #define DFS_PORTLOLSR_LOLF5_WIDTH (1U) 175 #define DFS_PORTLOLSR_LOLF5(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTLOLSR_LOLF5_SHIFT)) & DFS_PORTLOLSR_LOLF5_MASK) 176 /*! @} */ 177 178 /*! @name PORTRESET - Port Reset */ 179 /*! @{ */ 180 181 #define DFS_PORTRESET_RESET0_MASK (0x1U) 182 #define DFS_PORTRESET_RESET0_SHIFT (0U) 183 #define DFS_PORTRESET_RESET0_WIDTH (1U) 184 #define DFS_PORTRESET_RESET0(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTRESET_RESET0_SHIFT)) & DFS_PORTRESET_RESET0_MASK) 185 186 #define DFS_PORTRESET_RESET1_MASK (0x2U) 187 #define DFS_PORTRESET_RESET1_SHIFT (1U) 188 #define DFS_PORTRESET_RESET1_WIDTH (1U) 189 #define DFS_PORTRESET_RESET1(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTRESET_RESET1_SHIFT)) & DFS_PORTRESET_RESET1_MASK) 190 191 #define DFS_PORTRESET_RESET2_MASK (0x4U) 192 #define DFS_PORTRESET_RESET2_SHIFT (2U) 193 #define DFS_PORTRESET_RESET2_WIDTH (1U) 194 #define DFS_PORTRESET_RESET2(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTRESET_RESET2_SHIFT)) & DFS_PORTRESET_RESET2_MASK) 195 196 #define DFS_PORTRESET_RESET3_MASK (0x8U) 197 #define DFS_PORTRESET_RESET3_SHIFT (3U) 198 #define DFS_PORTRESET_RESET3_WIDTH (1U) 199 #define DFS_PORTRESET_RESET3(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTRESET_RESET3_SHIFT)) & DFS_PORTRESET_RESET3_MASK) 200 201 #define DFS_PORTRESET_RESET4_MASK (0x10U) 202 #define DFS_PORTRESET_RESET4_SHIFT (4U) 203 #define DFS_PORTRESET_RESET4_WIDTH (1U) 204 #define DFS_PORTRESET_RESET4(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTRESET_RESET4_SHIFT)) & DFS_PORTRESET_RESET4_MASK) 205 206 #define DFS_PORTRESET_RESET5_MASK (0x20U) 207 #define DFS_PORTRESET_RESET5_SHIFT (5U) 208 #define DFS_PORTRESET_RESET5_WIDTH (1U) 209 #define DFS_PORTRESET_RESET5(x) (((uint32_t)(((uint32_t)(x)) << DFS_PORTRESET_RESET5_SHIFT)) & DFS_PORTRESET_RESET5_MASK) 210 /*! @} */ 211 212 /*! @name CTL - Control */ 213 /*! @{ */ 214 215 #define DFS_CTL_DFS_RESET_MASK (0x2U) 216 #define DFS_CTL_DFS_RESET_SHIFT (1U) 217 #define DFS_CTL_DFS_RESET_WIDTH (1U) 218 #define DFS_CTL_DFS_RESET(x) (((uint32_t)(((uint32_t)(x)) << DFS_CTL_DFS_RESET_SHIFT)) & DFS_CTL_DFS_RESET_MASK) 219 /*! @} */ 220 221 /*! @name DVPORT - Divider for Port 0..Divider for Port 5 */ 222 /*! @{ */ 223 224 #define DFS_DVPORT_MFN_MASK (0x3FU) 225 #define DFS_DVPORT_MFN_SHIFT (0U) 226 #define DFS_DVPORT_MFN_WIDTH (6U) 227 #define DFS_DVPORT_MFN(x) (((uint32_t)(((uint32_t)(x)) << DFS_DVPORT_MFN_SHIFT)) & DFS_DVPORT_MFN_MASK) 228 229 #define DFS_DVPORT_MFI_MASK (0xFF00U) 230 #define DFS_DVPORT_MFI_SHIFT (8U) 231 #define DFS_DVPORT_MFI_WIDTH (8U) 232 #define DFS_DVPORT_MFI(x) (((uint32_t)(((uint32_t)(x)) << DFS_DVPORT_MFI_SHIFT)) & DFS_DVPORT_MFI_MASK) 233 /*! @} */ 234 235 /*! 236 * @} 237 */ /* end of group DFS_Register_Masks */ 238 239 /*! 240 * @} 241 */ /* end of group DFS_Peripheral_Access_Layer */ 242 243 #endif /* #if !defined(S32Z2_DFS_H_) */ 244
