1 /* sensor_lsm9ds0_gyro.h - header file for LSM9DS0 gyroscope sensor driver */ 2 3 /* 4 * Copyright (c) 2016 Intel Corporation 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #ifndef ZEPHYR_DRIVERS_SENSOR_LSM9DS0_GYRO_LSM9DS0_GYRO_H_ 10 #define ZEPHYR_DRIVERS_SENSOR_LSM9DS0_GYRO_LSM9DS0_GYRO_H_ 11 12 #include <zephyr/types.h> 13 #include <zephyr/drivers/i2c.h> 14 #include <zephyr/drivers/gpio.h> 15 #include <zephyr/sys/util.h> 16 17 #define DEG2RAD 0.017453292519943295769236907684 18 19 #define LSM9DS0_GYRO_REG_WHO_AM_I_G 0x0F 20 #define LSM9DS0_GYRO_VAL_WHO_AM_I_G 0xD4 21 22 #define LSM9DS0_GYRO_REG_CTRL_REG1_G 0x20 23 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6)) 24 #define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_DR 6 25 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_BW (BIT(5) | BIT(4)) 26 #define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_BW 4 27 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_PD BIT(3) 28 #define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_PD 3 29 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_ZEN BIT(2) 30 #define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_ZEN 2 31 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_XEN BIT(1) 32 #define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_XEN 1 33 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_YEN BIT(0) 34 #define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_YEN 0 35 36 #define LSM9DS0_GYRO_REG_CTRL_REG2_G 0x21 37 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPM (BIT(5) | BIT(4)) 38 #define LSM9DS0_GYRO_SHIFT_CTRL_REG2_G_HPM 4 39 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPCF (BIT(3) | BIT(2) | BIT(1) | \ 40 BIT(0)) 41 42 #define LSM9DS0_GYRO_REG_CTRL_REG3_G 0x22 43 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I1_INT1 BIT(7) 44 #define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I1_INT1 7 45 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I1_BOOT BIT(6) 46 #define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I1_BOOT 6 47 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_H_L BIT(5) 48 #define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_H_L 5 49 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_PP_OD BIT(4) 50 #define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_PP_OD 4 51 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I2_DRDY BIT(3) 52 #define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I2_DRDY 3 53 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I2_WTM BIT(2) 54 #define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I2_WTM 2 55 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I2_OR BIT(1) 56 #define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I2_OR 1 57 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I2_E BIT(0) 58 #define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I2_E 0 59 60 #define LSM9DS0_GYRO_REG_CTRL_REG4_G 0x23 61 #define LSM9DS0_GYRO_MASK_CTRL_REG4_G_BDU BIT(7) 62 #define LSM9DS0_GYRO_SHIFT_CTRL_REG4_G_BDU 7 63 #define LSM9DS0_GYRO_MASK_CTRL_REG4_G_BLE BIT(6) 64 #define LSM9DS0_GYRO_SHIFT_CTRL_REG4_G_BLE 6 65 #define LSM9DS0_GYRO_MASK_CTRL_REG4_G_FS (BIT(5) | BIT(4)) 66 #define LSM9DS0_GYRO_SHIFT_CTRL_REG4_G_FS 4 67 #define LSM9DS0_GYRO_MASK_CTRL_REG4_G_ST (BIT(2) | BIT(1)) 68 #define LSM9DS0_GYRO_SHIFT_CTRL_REG4_G_ST 1 69 70 #define LSM9DS0_GYRO_REG_CTRL_REG5_G 0x24 71 #define LSM9DS0_GYRO_MASK_CTRL_REG5_G_BOOT BIT(7) 72 #define LSM9DS0_GYRO_SHIFT_CTRL_REG5_G_BOOT 7 73 #define LSM9DS0_GYRO_MASK_CTRL_REG5_G_FIFO_EN BIT(6) 74 #define LSM9DS0_GYRO_SHIFT_CTRL_REG5_G_FIFO_EN 6 75 #define LSM9DS0_GYRO_MASK_CTRL_REG5_G_HPEN BIT(4) 76 #define LSM9DS0_GYRO_SHIFT_CTRL_REG5_G_HPEN 4 77 #define LSM9DS0_GYRO_MASK_CTRL_REG5_G_INT1_SEL (BIT(3) | BIT(2)) 78 #define LSM9DS0_GYRO_SHIFT_CTRL_REG5_G_INT1_SEL 2 79 #define LSM9DS0_GYRO_MASK_CTRL_REG5_G_OUT_SEL (BIT(1) | BIT(0)) 80 #define LSM9DS0_GYRO_SHIFT_CTRL_REG5_G_OUT_SEL 0 81 82 #define LSM9DS0_GYRO_REG_DATACAPTURE_G 0x25 83 84 #define LSM9DS0_GYRO_REG_STATUS_REG_G 0x27 85 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_ZYXOR BIT(7) 86 #define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_ZYXOR 7 87 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_ZOR BIT(6) 88 #define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_ZOR 6 89 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_YOR BIT(5) 90 #define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_YOR 5 91 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_XOR BIT(4) 92 #define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_XOR 4 93 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_ZYXDA BIT(3) 94 #define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_ZYXDA 3 95 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_ZDA BIT(2) 96 #define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_ZDA 2 97 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_YDA BIT(1) 98 #define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_YDA 1 99 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_XDA BIT(0) 100 #define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_XDA 0 101 102 #define LSM9DS0_GYRO_REG_OUT_X_L_G 0x28 103 #define LSM9DS0_GYRO_REG_OUT_X_H_G 0x29 104 #define LSM9DS0_GYRO_REG_OUT_Y_L_G 0x2A 105 #define LSM9DS0_GYRO_REG_OUT_Y_H_G 0x2B 106 #define LSM9DS0_GYRO_REG_OUT_Z_L_G 0x2C 107 #define LSM9DS0_GYRO_REG_OUT_Z_H_G 0x2D 108 109 #define LSM9DS0_GYRO_REG_FIFO_CTRL_REG_G 0x2E 110 #define LSM9DS0_GYRO_MASK_FIFO_CTRL_REG_G_FM (BIT(7) | BIT(6) | BIT(5)) 111 #define LSM9DS0_GYRO_SHIFT_FIFO_CTRL_REG_G_FM 5 112 #define LSM9DS0_GYRO_MASK_FIFO_CTRL_REG_G_WTM (BIT(4) | BIT(3) | BIT(2) | \ 113 BIT(1) | BIT(0)) 114 #define LSM9DS0_GYRO_SHIFT_FIFO_CTRL_REG_G_WTM 0 115 116 #define LSM9DS0_GYRO_REG_FIFO_SRC_REG_G 0x2F 117 #define LSM9DS0_GYRO_MASK_FIFO_SRC_REG_G_WTM BIT(7) 118 #define LSM9DS0_GYRO_SHIFT_FIFO_SRC_REG_G_WTM 7 119 #define LSM9DS0_GYRO_MASK_FIFO_SRC_REG_G_OVRN BIT(6) 120 #define LSM9DS0_GYRO_SHIFT_FIFO_SRC_REG_G_OVRN 6 121 #define LSM9DS0_GYRO_MASK_FIFO_SRC_REG_G_EMPTY BIT(5) 122 #define LSM9DS0_GYRO_SHIFT_FIFO_SRC_REG_G_EMPTY 5 123 #define LSM9DS0_GYRO_MASK_FIFO_SRC_REG_G_FSS (BIT(4) | BIT(3) | BIT(2) | \ 124 BIT(1) | BIT(0)) 125 #define LSM9DS0_GYRO_SHIFT_FIFO_SRC_REG_G_FSS 0 126 127 #define LSM9DS0_GYRO_REG_INT1_CFG_G 0x30 128 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_ANDOR BIT(7) 129 #define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_ANDOR 7 130 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_LIR BIT(6) 131 #define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_LIR 6 132 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_ZHIE BIT(5) 133 #define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_ZHIE 5 134 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_ZLIE BIT(4) 135 #define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_ZLIE 4 136 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_YHIE BIT(3) 137 #define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_YHIE 3 138 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_YLIE BIT(2) 139 #define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_YLIE 2 140 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_XHIE BIT(1) 141 #define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_XHIE 1 142 #define LSM9DS0_GYRO_MASK_INT1_CFG_G_XLIE BIT(0) 143 #define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_XLIE 0 144 145 #define LSM9DS0_GYRO_REG_INT1_SRC_G 0x31 146 #define LSM9DS0_GYRO_MASK_INT1_SRC_G_IA BIT(6) 147 #define LSM9DS0_GYRO_SHIFT_INT1_SRC_G_IA 6 148 #define LSM9DS0_GYRO_MASK_INT1_SRC_G_ZH BIT(5) 149 #define LSM9DS0_GYRO_SHIFT_INT1_SRC_G_ZH 5 150 #define LSM9DS0_GYRO_MASK_INT1_SRC_G_ZL BIT(4) 151 #define LSM9DS0_GYRO_SHIFT_INT1_SRC_G_ZL 4 152 #define LSM9DS0_GYRO_MASK_INT1_SRC_G_YH BIT(3) 153 #define LSM9DS0_GYRO_SHIFT_INT1_SRC_G_YH 3 154 #define LSM9DS0_GYRO_MASK_INT1_SRC_G_YL BIT(2) 155 #define LSM9DS0_GYRO_SHIFT_INT1_SRC_G_YL 2 156 #define LSM9DS0_GYRO_MASK_INT1_SRC_G_XH BIT(1) 157 #define LSM9DS0_GYRO_SHIFT_INT1_SRC_G_XH 1 158 #define LSM9DS0_GYRO_MASK_INT1_SRC_G_XL BIT(0) 159 #define LSM9DS0_GYRO_SHIFT_INT1_SRC_G_XL 0 160 161 #define LSM9DS0_GYRO_REG_INT1_THS_XH_G 0x32 162 #define LSM9DS0_GYRO_MASK_INT1_THS_XH_G (BIT(6) | BIT(5) | BIT(4) | \ 163 BIT(3) | BIT(2) | BIT(1) | \ 164 BIT(0)) 165 166 #define LSM9DS0_GYRO_REG_INT1_THS_XL_G 0x33 167 168 #define LSM9DS0_GYRO_REG_INT1_THS_YH_G 0x34 169 #define LSM9DS0_GYRO_MASK_INT1_THS_YH_G (BIT(6) | BIT(5) | BIT(4) | \ 170 BIT(3) | BIT(2) | BIT(1) | \ 171 BIT(0)) 172 173 #define LSM9DS0_GYRO_REG_INT1_THS_YL_G 0x35 174 175 #define LSM9DS0_GYRO_REG_INT1_THS_ZH_G 0x36 176 #define LSM9DS0_GYRO_MASK_INT1_THS_ZH_G (BIT(6) | BIT(5) | BIT(4) | \ 177 BIT(3) | BIT(2) | BIT(1) | \ 178 BIT(0)) 179 180 #define LSM9DS0_GYRO_REG_INT1_THS_ZL_G 0x37 181 182 #define LSM9DS0_GYRO_REG_INT1_DURATION_G 0x38 183 #define LSM9DS0_GYRO_MASK_INT1_DURATION_G_WAIT BIT(7) 184 #define LSM9DS0_GYRO_SHIFT_INT1_DURATION_G_WAIT 7 185 #define LSM9DS0_GYRO_MASK_INT1_DURATION_G_D (BIT(6) | BIT(5) | BIT(4) | \ 186 BIT(3) | BIT(2) | BIT(1) | \ 187 BIT(0)) 188 #define LSM9DS0_GYRO_SHIFT_INT1_DURATION_G_D 0 189 190 #if defined(CONFIG_LSM9DS0_GYRO_FULLSCALE_245) 191 #define LSM9DS0_GYRO_DEFAULT_FULLSCALE 0 192 #elif defined(CONFIG_LSM9DS0_GYRO_FULLSCALE_500) 193 #define LSM9DS0_GYRO_DEFAULT_FULLSCALE 1 194 #elif defined(CONFIG_LSM9DS0_GYRO_FULLSCALE_2000) 195 #define LSM9DS0_GYRO_DEFAULT_FULLSCALE 2 196 #endif 197 198 #if defined(CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_95) 199 #define LSM9DS0_GYRO_DEFAULT_SAMPLING_RATE 0 200 #elif defined(CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_190) 201 #define LSM9DS0_GYRO_DEFAULT_SAMPLING_RATE 1 202 #elif defined(CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_380) 203 #define LSM9DS0_GYRO_DEFAULT_SAMPLING_RATE 2 204 #elif defined(CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_760) 205 #define LSM9DS0_GYRO_DEFAULT_SAMPLING_RATE 3 206 #endif 207 208 #if defined(CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_RUNTIME) || \ 209 defined(CONFIG_LSM9DS0_GYRO_FULLSCALE_RUNTIME) 210 #define LSM9DS0_GYRO_SET_ATTR 211 #endif 212 213 struct lsm9ds0_gyro_config { 214 struct i2c_dt_spec i2c; 215 216 #if CONFIG_LSM9DS0_GYRO_TRIGGER_DRDY 217 struct gpio_dt_spec int_gpio; 218 #endif 219 }; 220 221 struct lsm9ds0_gyro_data { 222 #if defined(CONFIG_LSM9DS0_GYRO_TRIGGERS) 223 struct k_sem sem; 224 #endif 225 226 #if defined(CONFIG_LSM9DS0_GYRO_TRIGGER_DRDY) 227 K_KERNEL_STACK_MEMBER(thread_stack, 228 CONFIG_LSM9DS0_GYRO_THREAD_STACK_SIZE); 229 struct k_thread thread; 230 const struct device *dev; 231 232 struct gpio_callback gpio_cb; 233 const struct sensor_trigger *trigger_drdy; 234 sensor_trigger_handler_t handler_drdy; 235 #endif 236 237 int sample_x, sample_y, sample_z; 238 #if defined(CONFIG_LSM9DS0_GYRO_FULLSCALE_RUNTIME) 239 uint8_t sample_fs; 240 uint8_t fs; 241 #endif 242 }; 243 244 #if defined(CONFIG_LSM9DS0_GYRO_TRIGGER_DRDY) 245 int lsm9ds0_gyro_trigger_set(const struct device *dev, 246 const struct sensor_trigger *trig, 247 sensor_trigger_handler_t handler); 248 249 int lsm9ds0_gyro_init_interrupt(const struct device *dev); 250 #endif 251 252 #endif /* ZEPHYR_DRIVERS_SENSOR_LSM9DS0_GYRO_LSM9DS0_GYRO_H_ */ 253
