1 /** @file mlan_decl.h 2 * 3 * @brief This file declares the generic data structures and APIs. 4 * 5 * Copyright 2008-2024 NXP 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 * 9 */ 10 11 /****************************************************** 12 Change log: 13 11/07/2008: initial version 14 ******************************************************/ 15 16 #ifndef _MLAN_DECL_H_ 17 #define _MLAN_DECL_H_ 18 19 #include "type_decls.h" 20 #include <osa.h> 21 #if CONFIG_WPA_SUPP 22 #include <ieee802_11_defs.h> 23 #endif 24 25 /** MLAN release version */ 26 #define MLAN_RELEASE_VERSION "310" 27 28 /** Constants below */ 29 30 #ifdef __GNUC__ 31 /** Structure packing begins */ 32 #define MLAN_PACK_START 33 /** Structure packeing end */ 34 #define MLAN_PACK_END __attribute__((packed)) 35 #else /* !__GNUC__ */ 36 #ifdef PRAGMA_PACK 37 /** Structure packing begins */ 38 #define MLAN_PACK_START 39 /** Structure packeing end */ 40 #define MLAN_PACK_END 41 #else /* !PRAGMA_PACK */ 42 /** Structure packing begins */ 43 #define MLAN_PACK_START __packed 44 /** Structure packing end */ 45 #define MLAN_PACK_END 46 #endif /* PRAGMA_PACK */ 47 #endif /* __GNUC__ */ 48 49 #ifndef INLINE 50 #ifdef __GNUC__ 51 /** inline directive */ 52 #define INLINE inline 53 #else 54 /** inline directive */ 55 #define INLINE __inline 56 #endif 57 #endif 58 59 /** MLAN TRUE */ 60 #define MTRUE (1) 61 /** MLAN FALSE */ 62 #define MFALSE (0) 63 64 /** Macros for Data Alignment : size */ 65 #define ALIGN_SZ(p, a) (((p) + ((a)-1U)) & ~((a)-1U)) 66 67 /** Macros for Data Alignment : address */ 68 #define ALIGN_ADDR(p, a) ((((t_ptr)(p)) + (((t_ptr)(a)) - 1U)) & ~(((t_ptr)(a)) - 1U)) 69 70 #ifndef MACSTR 71 /** MAC address security format */ 72 #define MACSTR "%02x:XX:XX:XX:%02x:%02x" 73 #endif 74 75 #ifndef MAC2STR 76 /** MAC address security print arguments */ 77 #define MAC2STR(a) (a)[0], (a)[4], (a)[5] 78 #endif 79 80 /** Return the byte offset of a field in the given structure */ 81 #define MLAN_FIELD_OFFSET(type, field) ((t_u32)(t_ptr) & (((type *)0)->field)) 82 /** Return aligned offset */ 83 #define OFFSET_ALIGN_ADDR(p, a) (t_u32)(ALIGN_ADDR(p, a) - (t_ptr)p) 84 85 /** Maximum BSS numbers */ 86 /* fixme: We have reduced this from 16 to 2. Ensure that this is Ok */ 87 #if UAP_SUPPORT 88 #define MLAN_MAX_BSS_NUM 2U 89 #else 90 #define MLAN_MAX_BSS_NUM 1U 91 #endif 92 93 /** NET IP alignment */ 94 #define MLAN_NET_IP_ALIGN 0 95 96 /** DMA alignment */ 97 #define DMA_ALIGNMENT 32U 98 /** max size of TxPD */ 99 #define MAX_TXPD_SIZE 32 100 101 /** Minimum data header length */ 102 #define MLAN_MIN_DATA_HEADER_LEN (DMA_ALIGNMENT + MAX_TXPD_SIZE) 103 104 /** rx data header length */ 105 #define MLAN_RX_HEADER_LEN MLAN_MIN_DATA_HEADER_LEN 106 107 /** This is current limit on Maximum Tx AMPDU allowed */ 108 #define MLAN_MAX_TX_BASTREAM_SUPPORTED 2U 109 /** This is current limit on Maximum Rx AMPDU allowed */ 110 #define MLAN_MAX_RX_BASTREAM_SUPPORTED 16 111 112 /** US country code */ 113 #define COUNTRY_CODE_US 0x10 114 115 #ifdef STA_SUPPORT 116 /** Default Win size attached during ADDBA request */ 117 #ifndef MLAN_STA_AMPDU_DEF_TXWINSIZE 118 #if defined(SD9177) && defined(COEX_APP_SUPPORT) 119 #define MLAN_STA_AMPDU_DEF_TXWINSIZE 32 120 #else 121 #define MLAN_STA_AMPDU_DEF_TXWINSIZE 64 122 #endif 123 #endif 124 125 /** Default Win size attached during ADDBA response */ 126 #ifndef MLAN_STA_AMPDU_DEF_RXWINSIZE 127 #if defined(SD9177) && !defined(COEX_APP_SUPPORT) 128 #define MLAN_STA_AMPDU_DEF_RXWINSIZE 64 129 #else 130 #define MLAN_STA_AMPDU_DEF_RXWINSIZE 32 131 #endif 132 #endif 133 #endif /* STA_SUPPORT */ 134 135 #if UAP_SUPPORT 136 /** Default Win size attached during ADDBA request */ 137 #ifndef MLAN_UAP_AMPDU_DEF_TXWINSIZE 138 #if defined(SD9177) && defined(COEX_APP_SUPPORT) 139 #define MLAN_UAP_AMPDU_DEF_TXWINSIZE 32 140 #else 141 #define MLAN_UAP_AMPDU_DEF_TXWINSIZE 64 142 #endif 143 #endif 144 145 /** Default Win size attached during ADDBA response */ 146 #ifndef MLAN_UAP_AMPDU_DEF_RXWINSIZE 147 #if defined(SD9177) && !defined(COEX_APP_SUPPORT) 148 #define MLAN_UAP_AMPDU_DEF_RXWINSIZE 64 149 #else 150 #define MLAN_UAP_AMPDU_DEF_RXWINSIZE 32 151 #endif 152 #endif 153 154 #endif /* UAP_SUPPORT */ 155 156 /** Block ack timeout value */ 157 #define MLAN_DEFAULT_BLOCK_ACK_TIMEOUT 0U 158 /** Maximum Tx Win size configured for ADDBA request [10 bits] */ 159 #define MLAN_AMPDU_MAX_TXWINSIZE 0x3ff 160 /** Maximum Rx Win size configured for ADDBA request [10 bits] */ 161 #define MLAN_AMPDU_MAX_RXWINSIZE 0x3ff 162 163 /** Rate index for HR/DSSS 0 */ 164 #define MLAN_RATE_INDEX_HRDSSS0 0 165 /** Rate index for HR/DSSS 3 */ 166 #define MLAN_RATE_INDEX_HRDSSS3 3 167 /** Rate index for OFDM 0 */ 168 #define MLAN_RATE_INDEX_OFDM0 4U 169 /** Rate index for OFDM 7 */ 170 #define MLAN_RATE_INDEX_OFDM7 11 171 /** Rate index for MCS 0 */ 172 #define MLAN_RATE_INDEX_MCS0 0U 173 /** Rate index for MCS 2 */ 174 #define MLAN_RATE_INDEX_MCS2 2U 175 /** Rate index for MCS 4 */ 176 #define MLAN_RATE_INDEX_MCS4 4U 177 /** Rate index for MCS 7 */ 178 #define MLAN_RATE_INDEX_MCS7 7U 179 /** Rate index for MCS 8 */ 180 #define MLAN_RATE_INDEX_MCS8 8U 181 /** Rate index for MCS 9 */ 182 #define MLAN_RATE_INDEX_MCS9 9U 183 #if CONFIG_11AX 184 /** Rate index for MCS11 */ 185 #define MLAN_RATE_INDEX_MCS11 11U 186 #endif 187 /** Rate index for MCS 32 */ 188 #define MLAN_RATE_INDEX_MCS32 32U 189 /** Rate index for MCS 127 */ 190 #define MLAN_RATE_INDEX_MCS127 127U 191 #if (CONFIG_11AC) || (CONFIG_11AX) 192 #define MLAN_RATE_NSS1 1 193 #define MLAN_RATE_NSS2 2 194 #endif 195 196 /** Rate bitmap for OFDM 0 */ 197 #define MLAN_RATE_BITMAP_OFDM0 16 198 /** Rate bitmap for OFDM 7 */ 199 #define MLAN_RATE_BITMAP_OFDM7 23 200 /** Rate bitmap for MCS 0 */ 201 #define MLAN_RATE_BITMAP_MCS0 32U 202 /** Rate bitmap for MCS 127 */ 203 #define MLAN_RATE_BITMAP_MCS127 159 204 #if CONFIG_11AC 205 #define MLAN_RATE_BITMAP_NSS1_MCS0 160 206 #define MLAN_RATE_BITMAP_NSS1_MCS9 169 207 #define MLAN_RATE_BITMAP_NSS2_MCS0 176 208 #define MLAN_RATE_BITMAP_NSS2_MCS9 185 209 #endif 210 211 /** MU beamformer */ 212 #define DEFALUT_11AC_CAP_BEAMFORMING_RESET_MASK (MBIT(19)) 213 #ifdef RW610 214 /** Short GI for 80MHz/TVHT_MODE_4C */ 215 #define DEFALUT_11AC_CAP_SHORTGI_80MHZ_RESET_MASK (MBIT(5)) 216 /** HE Phy Cap Info(40MHz in 2.4GHz band) */ 217 #define DEFAULT_11AX_CAP_40MHZIH2_4GHZBAND_RESET_MASK (MBIT(1)) 218 #endif 219 220 /** Size of rx data buffer */ 221 #define MLAN_RX_DATA_BUF_SIZE (4 * 1024) 222 /** Size of rx command buffer */ 223 #define MLAN_RX_CMD_BUF_SIZE (2 * 1024) 224 225 /** MLAN MAC Address Length */ 226 #define MLAN_MAC_ADDR_LENGTH (6U) 227 /** MLAN 802.11 MAC Address */ 228 typedef t_u8 mlan_802_11_mac_addr[MLAN_MAC_ADDR_LENGTH]; 229 230 /** MLAN Maximum SSID Length */ 231 #define MLAN_MAX_SSID_LENGTH (32U) 232 233 /** RTS/FRAG related defines */ 234 /** Minimum RTS value */ 235 #define MLAN_RTS_MIN_VALUE (0) 236 /** Maximum RTS value */ 237 #define MLAN_RTS_MAX_VALUE (2347) 238 /** Minimum FRAG value */ 239 #define MLAN_FRAG_MIN_VALUE (256) 240 /** Maximum FRAG value */ 241 #define MLAN_FRAG_MAX_VALUE (2346) 242 243 /** Minimum tx retry count */ 244 #define MLAN_TX_RETRY_MIN (0) 245 /** Maximum tx retry count */ 246 #define MLAN_TX_RETRY_MAX (14) 247 248 /** define SDIO block size for data Tx/Rx */ 249 /* We support up to 480-byte block size due to FW buffer limitation. */ 250 #define MLAN_SDIO_BLOCK_SIZE 256U 251 252 /** define SDIO block size for firmware download */ 253 #define MLAN_SDIO_BLOCK_SIZE_FW_DNLD MLAN_SDIO_BLOCK_SIZE 254 255 /** define allocated buffer size */ 256 #define ALLOC_BUF_SIZE (4 * 1024) 257 258 /** SDIO IO Port mask */ 259 #define MLAN_SDIO_IO_PORT_MASK 0xfffff 260 /** SDIO Block/Byte mode mask */ 261 #define MLAN_SDIO_BYTE_MODE_MASK 0x80000000U 262 263 /** Max retry number of IO write */ 264 #define MAX_READ_IOMEM_RETRY 2 265 266 /** IN parameter */ 267 #define IN 268 /** OUT parameter */ 269 #define OUT 270 271 /** BIT value */ 272 #define MBIT(x) (((t_u32)1) << (x)) 273 274 #define MRVL_PKT_TYPE_MGMT_FRAME 0xE5 275 276 /** Buffer flag for requeued packet */ 277 #define MLAN_BUF_FLAG_REQUEUED_PKT MBIT(0) 278 /** Buffer flag for transmit buf from moal */ 279 #define MLAN_BUF_FLAG_MOAL_TX_BUF MBIT(1) 280 /** Buffer flag for malloc mlan_buffer */ 281 #define MLAN_BUF_FLAG_MALLOC_BUF MBIT(2) 282 283 /** Buffer flag for bridge packet */ 284 #define MLAN_BUF_FLAG_BRIDGE_BUF MBIT(3) 285 286 /** Buffer flag for TX_STATUS */ 287 #define MLAN_BUF_FLAG_TX_STATUS MBIT(10) 288 289 #ifdef DEBUG_LEVEL1 290 /** Debug level bit definition */ 291 #define MMSG MBIT(0) 292 #define MFATAL MBIT(1) 293 #define MERROR MBIT(2) 294 #define MDATA MBIT(3) 295 #define MCMND MBIT(4) 296 #define MEVENT MBIT(5) 297 #define MINTR MBIT(6) 298 #define MIOCTL MBIT(7) 299 300 #define MDAT_D MBIT(16) 301 #define MCMD_D MBIT(17) 302 #define MEVT_D MBIT(18) 303 #define MFW_D MBIT(19) 304 #define MIF_D MBIT(20) 305 306 #define MENTRY MBIT(28) 307 #define MWARN MBIT(29) 308 #define MINFO MBIT(30) 309 #define MHEX_DUMP MBIT(31) 310 #endif /* DEBUG_LEVEL1 */ 311 312 /** Memory allocation type: DMA */ 313 #define MLAN_MEM_DMA MBIT(0U) 314 315 /** Default memory allocation flag */ 316 #define MLAN_MEM_DEF 0U 317 318 #if CONFIG_WIFI_IND_DNLD 319 /** driver initial the fw reset */ 320 #define FW_RELOAD_SDIO_INBAND_RESET 1 321 /** out band reset trigger reset, no interface re-emulation */ 322 #define FW_RELOAD_NO_EMULATION 2 323 /** out band reset with interface re-emulation */ 324 #define FW_RELOAD_WITH_EMULATION 3 325 /** sdio hw reset */ 326 #define FW_RELOAD_SDIO_HW_RESET 5 327 #endif 328 329 /** MrvlExtIEtypesHeader_t */ 330 typedef MLAN_PACK_START struct _MrvlExtIEtypesHeader 331 { 332 /** Header type */ 333 t_u16 type; 334 /** Header length */ 335 t_u16 len; 336 /** ext id */ 337 t_u8 ext_id; 338 } MLAN_PACK_END MrvlExtIEtypesHeader_t; 339 340 /** MrvlIEtypes_Data_t */ 341 typedef MLAN_PACK_START struct _MrvlExtIEtypes_Data_t 342 { 343 /** Header */ 344 MrvlExtIEtypesHeader_t header; 345 /** Data */ 346 t_u8 data[]; 347 } MLAN_PACK_END MrvlExtIEtypes_Data_t; 348 349 /** mlan_status */ 350 typedef enum _mlan_status 351 { 352 MLAN_STATUS_FAILURE = 0xffffffff, 353 MLAN_STATUS_SUCCESS = 0, 354 MLAN_STATUS_PENDING, 355 MLAN_STATUS_RESOURCE, 356 } mlan_status; 357 358 /** mlan_error_code */ 359 typedef enum _mlan_error_code 360 { 361 /** No error */ 362 MLAN_ERROR_NO_ERROR = 0, 363 /** Firmware/device errors below (MSB=0) */ 364 MLAN_ERROR_FW_NOT_READY = 0x00000001, 365 MLAN_ERROR_FW_BUSY, 366 MLAN_ERROR_FW_CMDRESP, 367 MLAN_ERROR_DATA_TX_FAIL, 368 MLAN_ERROR_DATA_RX_FAIL, 369 /** Driver errors below (MSB=1) */ 370 MLAN_ERROR_PKT_SIZE_INVALID = 0x80000001, 371 MLAN_ERROR_PKT_TIMEOUT, 372 MLAN_ERROR_PKT_INVALID, 373 MLAN_ERROR_CMD_INVALID, 374 MLAN_ERROR_CMD_TIMEOUT, 375 MLAN_ERROR_CMD_DNLD_FAIL, 376 MLAN_ERROR_CMD_CANCEL, 377 MLAN_ERROR_CMD_RESP_FAIL, 378 MLAN_ERROR_CMD_ASSOC_FAIL, 379 MLAN_ERROR_CMD_SCAN_FAIL, 380 MLAN_ERROR_IOCTL_INVALID, 381 MLAN_ERROR_IOCTL_FAIL, 382 MLAN_ERROR_EVENT_UNKNOWN, 383 MLAN_ERROR_INVALID_PARAMETER, 384 MLAN_ERROR_NO_MEM, 385 /** More to add */ 386 } mlan_error_code; 387 388 /** mlan_buf_type */ 389 typedef enum _mlan_buf_type 390 { 391 MLAN_BUF_TYPE_CMD = 1, 392 MLAN_BUF_TYPE_DATA, 393 MLAN_BUF_TYPE_EVENT, 394 MLAN_BUF_TYPE_RAW_DATA, 395 } mlan_buf_type; 396 397 /** MLAN BSS type */ 398 typedef enum _mlan_bss_type 399 { 400 MLAN_BSS_TYPE_STA = 0, 401 MLAN_BSS_TYPE_UAP = 1, 402 /* fixme: This macro will be enabled when 403 * mlan is completely integrated with wlan 404 */ 405 /* #ifdef WIFI_DIRECT_SUPPORT*/ 406 MLAN_BSS_TYPE_WIFIDIRECT = 2, 407 /*#endif*/ 408 MLAN_BSS_TYPE_ANY = 0xff, 409 } mlan_bss_type; 410 411 /** MLAN BSS role */ 412 typedef enum _mlan_bss_role 413 { 414 MLAN_BSS_ROLE_STA = 0, 415 MLAN_BSS_ROLE_UAP = 1, 416 MLAN_BSS_ROLE_ANY = 0xff, 417 } mlan_bss_role; 418 419 /** BSS role bit mask */ 420 #define BSS_ROLE_BIT_MASK MBIT(0) 421 422 /** Get BSS role */ 423 #define GET_BSS_ROLE(priv) ((unsigned)(priv)->bss_role & (BSS_ROLE_BIT_MASK)) 424 425 /** mlan_data_frame_type */ 426 typedef enum _mlan_data_frame_type 427 { 428 MLAN_DATA_FRAME_TYPE_ETH_II = 0, 429 MLAN_DATA_FRAME_TYPE_802_11, 430 } mlan_data_frame_type; 431 432 /** mlan_event_id */ 433 typedef enum _mlan_event_id 434 { 435 /* Event generated by firmware (MSB=0) */ 436 MLAN_EVENT_ID_FW_UNKNOWN = 0x00000001, 437 MLAN_EVENT_ID_FW_ADHOC_LINK_SENSED, 438 MLAN_EVENT_ID_FW_ADHOC_LINK_LOST, 439 MLAN_EVENT_ID_FW_DISCONNECTED, 440 MLAN_EVENT_ID_FW_MIC_ERR_UNI, 441 MLAN_EVENT_ID_FW_MIC_ERR_MUL, 442 MLAN_EVENT_ID_FW_BCN_RSSI_LOW, 443 MLAN_EVENT_ID_FW_BCN_RSSI_HIGH, 444 MLAN_EVENT_ID_FW_BCN_SNR_LOW, 445 MLAN_EVENT_ID_FW_BCN_SNR_HIGH, 446 MLAN_EVENT_ID_FW_MAX_FAIL, 447 MLAN_EVENT_ID_FW_DATA_RSSI_LOW, 448 MLAN_EVENT_ID_FW_DATA_RSSI_HIGH, 449 MLAN_EVENT_ID_FW_DATA_SNR_LOW, 450 MLAN_EVENT_ID_FW_DATA_SNR_HIGH, 451 MLAN_EVENT_ID_FW_LINK_QUALITY, 452 MLAN_EVENT_ID_FW_PORT_RELEASE, 453 MLAN_EVENT_ID_FW_PRE_BCN_LOST, 454 MLAN_EVENT_ID_FW_WMM_CONFIG_CHANGE, 455 MLAN_EVENT_ID_FW_HS_WAKEUP, 456 MLAN_EVENT_ID_FW_BG_SCAN, 457 MLAN_EVENT_ID_FW_WEP_ICV_ERR, 458 MLAN_EVENT_ID_FW_STOP_TX, 459 MLAN_EVENT_ID_FW_START_TX, 460 MLAN_EVENT_ID_FW_CHANNEL_SWITCH_ANN, 461 MLAN_EVENT_ID_FW_RADAR_DETECTED, 462 MLAN_EVENT_ID_FW_CHANNEL_REPORT_RDY, 463 MLAN_EVENT_ID_FW_BW_CHANGED, 464 #ifdef WIFI_DIRECT_SUPPORT 465 MLAN_EVENT_ID_FW_REMAIN_ON_CHAN_EXPIRED, 466 #endif 467 #if UAP_SUPPORT 468 MLAN_EVENT_ID_UAP_FW_BSS_START, 469 MLAN_EVENT_ID_UAP_FW_BSS_ACTIVE, 470 MLAN_EVENT_ID_UAP_FW_BSS_IDLE, 471 MLAN_EVENT_ID_UAP_FW_STA_CONNECT, 472 MLAN_EVENT_ID_UAP_FW_STA_DISCONNECT, 473 #endif 474 475 /* Event generated by MLAN driver (MSB=1) */ 476 MLAN_EVENT_ID_DRV_CONNECTED = 0x80000001, 477 MLAN_EVENT_ID_DRV_DEFER_HANDLING, 478 MLAN_EVENT_ID_DRV_HS_ACTIVATED, 479 MLAN_EVENT_ID_DRV_HS_DEACTIVATED, 480 MLAN_EVENT_ID_DRV_MGMT_FRAME, 481 MLAN_EVENT_ID_DRV_OBSS_SCAN_PARAM, 482 MLAN_EVENT_ID_DRV_PASSTHRU, 483 MLAN_EVENT_ID_DRV_SCAN_REPORT, 484 MLAN_EVENT_ID_DRV_MEAS_REPORT, 485 MLAN_EVENT_ID_DRV_ASSOC_FAILURE_REPORT, 486 MLAN_EVENT_ID_DRV_REPORT_STRING, 487 MLAN_EVENT_ID_DRV_DBG_DUMP, 488 } mlan_event_id; 489 490 /** Data Structures */ 491 /** mlan_image data structure */ 492 typedef struct _mlan_fw_image 493 { 494 /** Helper image buffer pointer */ 495 t_u8 *phelper_buf; 496 /** Helper image length */ 497 t_u32 helper_len; 498 /** Firmware image buffer pointer */ 499 t_u8 *pfw_buf; 500 /** Firmware image length */ 501 t_u32 fw_len; 502 #if CONFIG_WIFI_IND_DNLD 503 /** Firmware reload flag */ 504 t_u8 fw_reload; 505 #endif 506 } mlan_fw_image, *pmlan_fw_image; 507 508 /** Custom data structure */ 509 typedef struct _mlan_init_param 510 { 511 /** Cal data buffer pointer */ 512 t_u8 *pcal_data_buf; 513 /** Cal data length */ 514 t_u32 cal_data_len; 515 /** Other custom data */ 516 } mlan_init_param, *pmlan_init_param; 517 518 /** Channel usability flags */ 519 #define NXP_CHANNEL_NO_OFDM MBIT(9) 520 #define NXP_CHANNEL_NO_CCK MBIT(8) 521 #define NXP_CHANNEL_DISABLED MBIT(7) 522 /* BIT 5/6 resevered for FW */ 523 #define NXP_CHANNEL_NOHT160 MBIT(4) 524 #define NXP_CHANNEL_NOHT80 MBIT(3) 525 #define NXP_CHANNEL_NOHT40 MBIT(2) 526 #define NXP_CHANNEL_DFS MBIT(1) 527 #define NXP_CHANNEL_PASSIVE MBIT(0) 528 529 /** CFP dynamic (non-const) elements */ 530 typedef struct _cfp_dyn_t 531 { 532 /** extra flags to specify channel usability 533 * bit 9 : if set, channel is non-OFDM 534 * bit 8 : if set, channel is non-CCK 535 * bit 7 : if set, channel is disabled 536 * bit 5/6 resevered for FW 537 * bit 4 : if set, 160MHz on channel is disabled 538 * bit 3 : if set, 80MHz on channel is disabled 539 * bit 2 : if set, 40MHz on channel is disabled 540 * bit 1 : if set, channel is DFS channel 541 * bit 0 : if set, channel is passive 542 */ 543 t_u16 flags; 544 /** TRUE: Channel is blacklisted (do not use) */ 545 t_bool blacklist; 546 } cfp_dyn_t; 547 548 /** Chan-Freq-TxPower mapping table*/ 549 typedef struct _chan_freq_power_t 550 { 551 /** Channel Number */ 552 t_u16 channel; 553 /** Frequency of this Channel */ 554 t_u32 freq; 555 /** Max allowed Tx power level */ 556 t_u16 max_tx_power; 557 /** TRUE:radar detect required for BAND A or passive scan for BAND B/G; 558 * FALSE:radar detect not required for BAND A or active scan for BAND B/G*/ 559 t_bool passive_scan_or_radar_detect; 560 /** Elements associated to cfp that change at run-time */ 561 cfp_dyn_t dynamic; 562 } chan_freq_power_t; 563 564 /** mlan_event data structure */ 565 typedef struct _mlan_event 566 { 567 /** BSS index number for multiple BSS support */ 568 t_u32 bss_index; 569 /** Event ID */ 570 mlan_event_id event_id; 571 /** Event length */ 572 t_u32 event_len; 573 /** Event buffer */ 574 t_u8 event_buf[1]; 575 } mlan_event, *pmlan_event; 576 577 #if CONFIG_P2P 578 /** mlan_event data structure */ 579 typedef struct _mlan_event_p2p 580 { 581 /** Event length */ 582 t_u32 event_len; 583 /** Event buffer */ 584 t_u8 event_buf[0]; 585 } mlan_event_p2p, *pmlan_event_p2p; 586 #endif 587 588 #if CONFIG_EXT_SCAN_SUPPORT 589 /** mlan_event_scan_result data structure */ 590 typedef MLAN_PACK_START struct _mlan_event_scan_result 591 { 592 /** Event ID */ 593 t_u16 event_id; 594 /** BSS index number for multiple BSS support */ 595 t_u8 bss_index; 596 /** BSS type */ 597 t_u8 bss_type; 598 /** More event available or not */ 599 t_u8 more_event; 600 /** Reserved */ 601 t_u8 reserved[3]; 602 /** Size of the response buffer */ 603 t_u16 buf_size; 604 /** Number of BSS in scan response */ 605 t_u8 num_of_set; 606 } MLAN_PACK_END mlan_event_scan_result, *pmlan_event_scan_result; 607 #endif 608 609 /** mlan_buffer data structure */ 610 typedef struct _mlan_buffer 611 { 612 /** Pointer to previous mlan_buffer */ 613 // struct _mlan_buffer *pprev; 614 /** Pointer to next mlan_buffer */ 615 // struct _mlan_buffer *pnext; 616 /** Status code from firmware/driver */ 617 t_u32 status_code; 618 /** Flags for this buffer */ 619 t_u32 flags; 620 /** BSS index number for multiple BSS support */ 621 t_u32 bss_index; 622 /** Buffer descriptor, e.g. skb in Linux */ 623 t_void *pdesc; 624 /** Private member added for WMSDK. This is used to store the lwip pbuf 625 pointer */ 626 t_void *lwip_pbuf; 627 /** Pointer to buffer */ 628 t_u8 *pbuf; 629 /** Offset to data */ 630 t_u32 data_offset; 631 /** Data length */ 632 t_u32 data_len; 633 /** Buffer type: data, cmd, event etc. */ 634 mlan_buf_type buf_type; 635 636 /** Fields below are valid for data packet only */ 637 /** QoS priority */ 638 t_u32 priority; 639 /** Time stamp when packet is received (seconds) */ 640 // t_u32 in_ts_sec; 641 /** Time stamp when packet is received (micro seconds) */ 642 // t_u32 in_ts_usec; 643 /** Time stamp when packet is processed (seconds) */ 644 // t_u32 out_ts_sec; 645 /** Time stamp when packet is processed (micro seconds) */ 646 // t_u32 out_ts_usec; 647 648 /** Fields below are valid for MLAN module only */ 649 /** Pointer to parent mlan_buffer */ 650 // struct _mlan_buffer *pparent; 651 /** Use count for this buffer */ 652 t_u32 use_count; 653 } mlan_buffer, *pmlan_buffer; 654 655 /** mlan_bss_attr data structure */ 656 typedef struct _mlan_bss_attr 657 { 658 /** BSS type */ 659 mlan_bss_type bss_type; 660 /** Data frame type: Ethernet II, 802.11, etc. */ 661 t_u32 frame_type; 662 /** The BSS is active (non-0) or not (0). */ 663 t_u32 active; 664 /** BSS Priority */ 665 t_u32 bss_priority; 666 /** BSS number */ 667 t_u32 bss_num; 668 } mlan_bss_attr, *pmlan_bss_attr; 669 670 #ifdef PRAGMA_PACK 671 #pragma pack(push, 1) 672 #endif 673 674 /** Type enumeration for the command result */ 675 typedef MLAN_PACK_START enum _mlan_cmd_result_e { 676 MLAN_CMD_RESULT_SUCCESS = 0, 677 MLAN_CMD_RESULT_FAILURE = 1, 678 MLAN_CMD_RESULT_TIMEOUT = 2, 679 MLAN_CMD_RESULT_INVALID_DATA = 3 680 } MLAN_PACK_END mlan_cmd_result_e; 681 682 #define WMM_AC_BK 0 683 #define WMM_AC_BE 1 684 #define WMM_AC_VI 2 685 #define WMM_AC_VO 3 686 687 typedef t_u8 mlan_wmm_ac_e; 688 689 /** Type enumeration for the action field in the Queue Config command */ 690 typedef MLAN_PACK_START enum _mlan_wmm_queue_config_action_e { 691 MLAN_WMM_QUEUE_CONFIG_ACTION_GET = 0, 692 MLAN_WMM_QUEUE_CONFIG_ACTION_SET = 1, 693 MLAN_WMM_QUEUE_CONFIG_ACTION_DEFAULT = 2, 694 MLAN_WMM_QUEUE_CONFIG_ACTION_MAX 695 } MLAN_PACK_END mlan_wmm_queue_config_action_e; 696 697 /** Type enumeration for the action field in the queue stats command */ 698 typedef MLAN_PACK_START enum _mlan_wmm_queue_stats_action_e { 699 MLAN_WMM_STATS_ACTION_START = 0, 700 MLAN_WMM_STATS_ACTION_STOP = 1, 701 MLAN_WMM_STATS_ACTION_GET_CLR = 2, 702 MLAN_WMM_STATS_ACTION_SET_CFG = 3, /* Not currently used */ 703 MLAN_WMM_STATS_ACTION_GET_CFG = 4, /* Not currently used */ 704 MLAN_WMM_STATS_ACTION_MAX 705 } MLAN_PACK_END mlan_wmm_queue_stats_action_e; 706 707 /** 708 * @brief IOCTL structure for a Traffic stream status. 709 * 710 */ 711 typedef MLAN_PACK_START struct 712 { 713 /** TSID: Range: 0->7 */ 714 t_u8 tid; 715 /** TSID specified is valid */ 716 t_u8 valid; 717 /** AC TSID is active on */ 718 t_u8 access_category; 719 /** UP specified for the TSID */ 720 t_u8 user_priority; 721 /** Power save mode for TSID: 0 (legacy), 1 (UAPSD) */ 722 t_u8 psb; 723 /** Upstream(0), Downlink(1), Bidirectional(3) */ 724 t_u8 flow_dir; 725 /** Medium time granted for the TSID */ 726 t_u16 medium_time; 727 } MLAN_PACK_END wlan_ioctl_wmm_ts_status_t, 728 /** Type definition of mlan_ds_wmm_ts_status for MLAN_OID_WMM_CFG_TS_STATUS */ 729 mlan_ds_wmm_ts_status, *pmlan_ds_wmm_ts_status; 730 731 /** Max Ie length */ 732 #define MAX_IE_SIZE 256U 733 734 /** custom IE */ 735 typedef MLAN_PACK_START struct _custom_ie 736 { 737 /** IE Index */ 738 t_u16 ie_index; 739 /** Mgmt Subtype Mask */ 740 t_u16 mgmt_subtype_mask; 741 /** IE Length */ 742 t_u16 ie_length; 743 /** IE buffer */ 744 t_u8 ie_buffer[MAX_IE_SIZE]; 745 } MLAN_PACK_END custom_ie; 746 747 /** TLV buffer : custom IE */ 748 typedef MLAN_PACK_START struct _tlvbuf_custom_ie 749 { 750 /** Tag */ 751 t_u16 type; 752 /** Length */ 753 t_u16 length; 754 /** custom IE data */ 755 custom_ie ie_data[0]; 756 } MLAN_PACK_END tlvbuf_custom_ie; 757 758 /** Max IE index to FW */ 759 #define MAX_MGMT_IE_INDEX_TO_FW 4U 760 /** Max IE index per BSS */ 761 #define MAX_MGMT_IE_INDEX 16 762 763 /** custom IE info */ 764 typedef MLAN_PACK_START struct _custom_ie_info 765 { 766 /** size of buffer */ 767 t_u16 buf_size; 768 /** no of buffers of buf_size */ 769 t_u16 buf_count; 770 } MLAN_PACK_END custom_ie_info; 771 772 /** TLV buffer : Max Mgmt IE */ 773 typedef MLAN_PACK_START struct _tlvbuf_max_mgmt_ie 774 { 775 /** Type */ 776 t_u16 type; 777 /** Length */ 778 t_u16 len; 779 /** No of tuples */ 780 t_u16 count; 781 /** custom IE info tuples */ 782 custom_ie_info info[MAX_MGMT_IE_INDEX]; 783 } MLAN_PACK_END tlvbuf_max_mgmt_ie; 784 785 /** TLV buffer : custom IE */ 786 typedef MLAN_PACK_START struct _mlan_ds_misc_custom_ie 787 { 788 /** Type */ 789 t_u16 type; 790 /** Length */ 791 t_u16 len; 792 /** IE data */ 793 custom_ie ie_data_list[MAX_MGMT_IE_INDEX_TO_FW]; 794 /** Max mgmt IE TLV */ 795 tlvbuf_max_mgmt_ie max_mgmt_ie; 796 } MLAN_PACK_END mlan_ds_misc_custom_ie; 797 798 /** channel type */ 799 enum mlan_channel_type 800 { 801 CHAN_NO_HT, 802 CHAN_HT20, 803 CHAN_HT40MINUS, 804 CHAN_HT40PLUS, 805 CHAN_VHT80 806 }; 807 808 /** channel band */ 809 enum 810 { 811 BAND_2GHZ = 0, 812 BAND_5GHZ = 1, 813 BAND_6GHZ = 2, 814 BAND_4GHZ = 3, 815 }; 816 817 /** Band_Config_t */ 818 typedef MLAN_PACK_START struct _Band_Config_t 819 { 820 #ifdef BIG_ENDIAN_SUPPORT 821 /** Channel Selection Mode - (00)=manual, (01)=ACS, (02)=user*/ 822 t_u8 scanMode : 2; 823 /** Secondary Channel Offset - (00)=None, (01)=Above, (11)=Below */ 824 t_u8 chan2Offset : 2; 825 /** Channel Width - (00)=20MHz, (10)=40MHz, (11)=80MHz */ 826 t_u8 chanWidth : 2; 827 /** Band Info - (00)=2.4GHz, (01)=5GHz */ 828 t_u8 chanBand : 2; 829 #else 830 /** Band Info - (00)=2.4GHz, (01)=5GHz */ 831 t_u8 chanBand : 2; 832 /** Channel Width - (00)=20MHz, (10)=40MHz, (11)=80MHz */ 833 t_u8 chanWidth : 2; 834 /** Secondary Channel Offset - (00)=None, (01)=Above, (11)=Below */ 835 t_u8 chan2Offset : 2; 836 /** Channel Selection Mode - (00)=manual, (01)=ACS, (02)=Adoption mode*/ 837 t_u8 scanMode : 2; 838 #endif 839 } MLAN_PACK_END Band_Config_t; 840 841 /** channel_band_t */ 842 typedef MLAN_PACK_START struct _chan_band_info 843 { 844 /** Band Configuration */ 845 Band_Config_t bandcfg; 846 /** channel */ 847 t_u8 channel; 848 /** 11n flag */ 849 t_u8 is_11n_enabled; 850 /** center channel */ 851 t_u8 center_chan; 852 #if defined(ENABLE_802_11H) && defined(DFS_SUPPORT) 853 /** dfs channel flag */ 854 t_u8 is_dfs_chan; 855 #endif 856 } MLAN_PACK_END chan_band_info; 857 858 /** csi event data structure */ 859 #if CONFIG_CSI 860 typedef MLAN_PACK_START struct _csi_record_ds 861 { 862 /** Length in DWORDS, including header */ 863 t_u16 Len; 864 /** CSI signature. 0xABCD fixed */ 865 t_u16 CSI_Sign; 866 /** User defined HeaderID */ 867 t_u32 CSI_HeaderID; 868 /** Packet info field */ 869 t_u16 PKT_info; 870 /** Frame control field for the received packet*/ 871 t_u16 FCF; 872 /** Timestamp when packet received */ 873 t_u64 TSF; 874 /** Received Packet Destination MAC Address */ 875 t_u8 Dst_MAC[6]; 876 /** Received Packet Source MAC Address */ 877 t_u8 Src_MAC[6]; 878 /** RSSI for antenna A */ 879 t_u8 Rx_RSSI_A; 880 /** RSSI for antenna B */ 881 t_u8 Rx_RSSI_B; 882 /** Noise floor for antenna A */ 883 t_u8 Rx_NF_A; 884 /** Noise floor for antenna A */ 885 t_u8 Rx_NF_B; 886 /** Rx signal strength above noise floor */ 887 t_u8 Rx_SINR; 888 /** Channel */ 889 t_u8 channel; 890 /** user defined Chip ID */ 891 t_u16 chip_id; 892 /** Reserved */ 893 t_u32 rsvd; 894 /** CSI data length in DWORDs */ 895 t_u32 CSI_Data_Length; 896 /** Start of CSI data */ 897 t_u8 CSI_Data[0]; 898 /** At the end of CSI raw data, user defined TailID of 4 bytes*/ 899 } MLAN_PACK_END csi_record_ds, *pcsi_record_ds; 900 #endif 901 902 #ifdef PRAGMA_PACK 903 #pragma pack(pop) 904 #endif 905 906 /** mlan_callbacks data structure */ 907 typedef struct _mlan_callbacks 908 { 909 #if 0 910 /** moal_get_fw_data */ 911 mlan_status(*moal_get_fw_data) (IN t_void * pmoal_handle, 912 IN t_u32 offset, 913 IN t_u32 len, OUT t_u8 * pbuf); 914 /** moal_init_fw_complete */ 915 mlan_status(*moal_init_fw_complete) (IN t_void * pmoal_handle, 916 IN mlan_status status); 917 /** moal_shutdown_fw_complete */ 918 mlan_status(*moal_shutdown_fw_complete) (IN t_void * pmoal_handle, 919 IN mlan_status status); 920 /** moal_send_packet_complete */ 921 mlan_status(*moal_send_packet_complete) (IN t_void * pmoal_handle, 922 IN pmlan_buffer pmbuf, 923 IN mlan_status status); 924 /** moal_recv_complete */ 925 mlan_status(*moal_recv_complete) (IN t_void * pmoal_handle, 926 IN pmlan_buffer pmbuf, 927 IN t_u32 port, IN mlan_status status); 928 #endif /* 0 */ 929 /** moal_recv_packet */ 930 mlan_status (*moal_recv_packet)(IN t_void *pmoal_handle, IN pmlan_buffer pmbuf); 931 #if 0 932 /** moal_recv_event */ 933 mlan_status(*moal_recv_event) (IN t_void * pmoal_handle, 934 IN pmlan_event pmevent); 935 /** moal_ioctl_complete */ 936 mlan_status(*moal_ioctl_complete) (IN t_void * pmoal_handle, 937 IN pmlan_ioctl_req pioctl_req, 938 IN mlan_status status); 939 /** moal_alloc_mlan_buffer */ 940 mlan_status(*moal_alloc_mlan_buffer) (IN t_void * pmoal_handle, 941 IN t_u32 size, 942 OUT pmlan_buffer * pmbuf); 943 /** moal_free_mlan_buffer */ 944 mlan_status(*moal_free_mlan_buffer) (IN t_void * pmoal_handle, 945 IN pmlan_buffer pmbuf); 946 /** moal_write_reg */ 947 mlan_status(*moal_write_reg) (IN t_void * pmoal_handle, 948 IN t_u32 reg, IN t_u32 data); 949 /** moal_read_reg */ 950 mlan_status(*moal_read_reg) (IN t_void * pmoal_handle, 951 IN t_u32 reg, OUT t_u32 * data); 952 /** moal_write_data_sync */ 953 mlan_status(*moal_write_data_sync) (IN t_void * pmoal_handle, 954 IN pmlan_buffer pmbuf, 955 IN t_u32 port, IN t_u32 timeout); 956 /** moal_read_data_sync */ 957 mlan_status(*moal_read_data_sync) (IN t_void * pmoal_handle, 958 IN OUT pmlan_buffer pmbuf, 959 IN t_u32 port, IN t_u32 timeout); 960 #endif /* 0 */ 961 /** moal_malloc */ 962 mlan_status (*moal_malloc)(IN t_void *pmoal_handle, IN t_u32 size, IN t_u32 flag, OUT t_u8 **ppbuf); 963 /** moal_mfree */ 964 mlan_status (*moal_mfree)(IN t_void *pmoal_handle, IN t_u8 *pbuf); 965 #if 0 966 /** moal_memset */ 967 t_void *(*moal_memset) (IN t_void * pmoal_handle, 968 IN t_void * pmem, IN t_u8 byte, IN t_u32 num); 969 /** moal_memcpy */ 970 t_void *(*moal_memcpy) (IN t_void * pmoal_handle, 971 IN t_void * pdest, 972 IN const t_void * psrc, IN t_u32 num); 973 /** moal_memmove */ 974 t_void *(*moal_memmove) (IN t_void * pmoal_handle, 975 IN t_void * pdest, 976 IN const t_void * psrc, IN t_u32 num); 977 /** moal_memcmp */ 978 t_s32(*moal_memcmp) (IN t_void * pmoal_handle, 979 IN const t_void * pmem1, 980 IN const t_void * pmem2, IN t_u32 num); 981 /** moal_udelay */ 982 t_void(*moal_udelay) (IN t_void * pmoal_handle, IN t_u32 udelay); 983 /** moal_get_system_time */ 984 mlan_status(*moal_get_system_time) (IN t_void * pmoal_handle, 985 OUT t_u32 * psec, OUT t_u32 * pusec); 986 #endif /* 0 */ 987 988 /** moal_memcpy_ext */ 989 t_void *(*moal_memcpy_ext)(t_void *pmoal, t_void *pdest, const t_void *psrc, t_u32 num, t_u32 dest_size); 990 991 /** moal_init_timer*/ 992 mlan_status (*moal_init_timer)(IN t_void *pmoal_handle, 993 OUT t_void *ptimer, 994 IN t_void (*callback)(osa_timer_arg_t arg), 995 IN t_void *pcontext); 996 /** moal_free_timer */ 997 mlan_status (*moal_free_timer)(IN t_void *pmoal_handle, IN t_void *ptimer); 998 /** moal_start_timer*/ 999 mlan_status (*moal_start_timer)(IN t_void *pmoal_handle, IN t_void *ptimer, IN bool periodic, IN t_u32 msec); 1000 /** moal_reset_timer*/ 1001 mlan_status (*moal_reset_timer)(IN t_void *pmoal_handle, IN t_void *ptimer); 1002 /** moal_stop_timer*/ 1003 mlan_status (*moal_stop_timer)(IN t_void *pmoal_handle, IN t_void *ptimer); 1004 /** moal_init_lock */ 1005 mlan_status (*moal_init_lock)(IN t_void *pmoal_handle, OUT t_void *plock); 1006 /** moal_free_lock */ 1007 mlan_status (*moal_free_lock)(IN t_void *pmoal_handle, IN t_void *plock); 1008 /** moal_spin_lock */ 1009 mlan_status (*moal_spin_lock)(IN t_void *pmoal_handle, IN t_void *plock); 1010 /** moal_spin_unlock */ 1011 mlan_status (*moal_spin_unlock)(IN t_void *pmoal_handle, IN t_void *plock); 1012 #if CONFIG_WMM 1013 /** moal_init_semaphore */ 1014 mlan_status (*moal_init_semaphore)(IN t_void *pmoal_handle, IN const char *name, OUT t_void *plock); 1015 /** moal_free_semaphore */ 1016 mlan_status (*moal_free_semaphore)(IN t_void *pmoal_handle, IN t_void *plock); 1017 /** moal_semaphore_get */ 1018 mlan_status (*moal_semaphore_get)(IN t_void *pmoal_handle, IN t_void *plock); 1019 /** moal_semaphore_put */ 1020 mlan_status (*moal_semaphore_put)(IN t_void *pmoal_handle, IN t_void *plock); 1021 #endif 1022 #if 0 1023 /** moal_print */ 1024 t_void(*moal_print) (IN t_void * pmoal_handle, 1025 IN t_u32 level, IN t_s8 * pformat, IN ...); 1026 /** moal_print_netintf */ 1027 t_void(*moal_print_netintf) (IN t_void * pmoal_handle, 1028 IN t_u32 bss_index, IN t_u32 level); 1029 /** moal_assert */ 1030 t_void(*moal_assert) (IN t_void * pmoal_handle, IN t_u32 cond); 1031 #endif /* 0 */ 1032 } mlan_callbacks, *pmlan_callbacks; 1033 1034 /** Interrupt Mode SDIO */ 1035 #define INT_MODE_SDIO 0 1036 /** Interrupt Mode GPIO */ 1037 #define INT_MODE_GPIO 1 1038 1039 /** Parameter unchanged, use MLAN default setting */ 1040 #define MLAN_INIT_PARA_UNCHANGED 0 1041 /** Parameter enabled, override MLAN default setting */ 1042 #define MLAN_INIT_PARA_ENABLED 1 1043 /** Parameter disabled, override MLAN default setting */ 1044 #define MLAN_INIT_PARA_DISABLED 2U 1045 1046 /** mlan_device data structure */ 1047 typedef struct _mlan_device 1048 { 1049 /** BSS Attributes */ 1050 mlan_bss_attr bss_attr[MLAN_MAX_BSS_NUM]; 1051 /** Callbacks */ 1052 mlan_callbacks callbacks; 1053 } mlan_device, *pmlan_device; 1054 1055 /** MLAN API function prototype */ 1056 #define MLAN_API 1057 1058 /** Registration */ 1059 MLAN_API mlan_status mlan_register(IN pmlan_device pmdevice, OUT t_void **ppmlan_adapter); 1060 1061 /** Un-registration */ 1062 MLAN_API mlan_status mlan_unregister(IN t_void *pmlan_adapter); 1063 1064 /** Firmware Initialization */ 1065 MLAN_API mlan_status mlan_init_fw(IN t_void *pmlan_adapter); 1066 #endif /* !_MLAN_DECL_H_ */ 1067
