1 /*
2 * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef STM32MP2_DEF_H
8 #define STM32MP2_DEF_H
9
10 #include <common/tbbr/tbbr_img_def.h>
11 #ifndef __ASSEMBLER__
12 #include <drivers/st/bsec.h>
13 #endif
14 #include <drivers/st/stm32mp25_rcc.h>
15 #include <dt-bindings/clock/stm32mp25-clks.h>
16 #include <dt-bindings/clock/stm32mp25-clksrc.h>
17 #include <dt-bindings/reset/stm32mp25-resets.h>
18
19 #ifndef __ASSEMBLER__
20 #include <boot_api.h>
21 #include <stm32mp_common.h>
22 #include <stm32mp_dt.h>
23 #include <stm32mp_shared_resources.h>
24 #endif
25
26 /*******************************************************************************
27 * STM32MP2 memory map related constants
28 ******************************************************************************/
29 #define STM32MP_SYSRAM_BASE U(0x0E000000)
30 #define STM32MP_SYSRAM_SIZE U(0x00040000)
31
32 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
33 #define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE
34
35 /* DDR configuration */
36 #define STM32MP_DDR_BASE U(0x80000000)
37 #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */
38
39 /* DDR power initializations */
40 #ifndef __ASSEMBLER__
41 enum ddr_type {
42 STM32MP_DDR3,
43 STM32MP_DDR4,
44 STM32MP_LPDDR4
45 };
46 #endif
47
48 /* Section used inside TF binaries */
49 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
50 /* 512 Octets reserved for header */
51 #define STM32MP_HEADER_SIZE U(0x00000200)
52 #define STM32MP_HEADER_BASE (STM32MP_SEC_SYSRAM_BASE + \
53 STM32MP_PARAM_LOAD_SIZE)
54
55 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
56 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
57
58 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
59 STM32MP_PARAM_LOAD_SIZE + \
60 STM32MP_HEADER_SIZE)
61
62 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
63 (STM32MP_PARAM_LOAD_SIZE + \
64 STM32MP_HEADER_SIZE))
65
66 #define STM32MP_BL2_SIZE U(0x0002A000) /* 168 KB for BL2 */
67
68 #define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
69 STM32MP_SEC_SYSRAM_SIZE - \
70 STM32MP_BL2_SIZE)
71
72 /* BL2 and BL32/sp_min require 4 tables */
73 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
74
75 /*
76 * MAX_MMAP_REGIONS is usually:
77 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup
78 */
79 #define MAX_MMAP_REGIONS 6
80
81 /* DTB initialization value */
82 #define STM32MP_BL2_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
83
84 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
85 STM32MP_BL2_DTB_SIZE)
86
87 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000))
88 #define STM32MP_BL33_MAX_SIZE U(0x400000)
89
90 /*******************************************************************************
91 * STM32MP2 RCC
92 ******************************************************************************/
93 #define RCC_BASE U(0x44200000)
94
95 /*******************************************************************************
96 * STM32MP2 PWR
97 ******************************************************************************/
98 #define PWR_BASE U(0x44210000)
99
100 /*******************************************************************************
101 * STM32MP2 GPIO
102 ******************************************************************************/
103 #define GPIOA_BASE U(0x44240000)
104 #define GPIOB_BASE U(0x44250000)
105 #define GPIOC_BASE U(0x44260000)
106 #define GPIOD_BASE U(0x44270000)
107 #define GPIOE_BASE U(0x44280000)
108 #define GPIOF_BASE U(0x44290000)
109 #define GPIOG_BASE U(0x442A0000)
110 #define GPIOH_BASE U(0x442B0000)
111 #define GPIOI_BASE U(0x442C0000)
112 #define GPIOJ_BASE U(0x442D0000)
113 #define GPIOK_BASE U(0x442E0000)
114 #define GPIOZ_BASE U(0x46200000)
115 #define GPIO_BANK_OFFSET U(0x10000)
116
117 #define STM32MP_GPIOS_PIN_MAX_COUNT 16
118 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8
119
120 /*******************************************************************************
121 * STM32MP2 UART
122 ******************************************************************************/
123 #define USART1_BASE U(0x40330000)
124 #define USART2_BASE U(0x400E0000)
125 #define USART3_BASE U(0x400F0000)
126 #define UART4_BASE U(0x40100000)
127 #define UART5_BASE U(0x40110000)
128 #define USART6_BASE U(0x40220000)
129 #define UART7_BASE U(0x40370000)
130 #define UART8_BASE U(0x40380000)
131 #define UART9_BASE U(0x402C0000)
132 #define STM32MP_NB_OF_UART U(9)
133
134 /* For UART crash console */
135 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000
136 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */
137 #define STM32MP_DEBUG_USART_BASE USART2_BASE
138 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE
139 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR
140 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN
141 #define DEBUG_UART_TX_GPIO_PORT 4
142 #define DEBUG_UART_TX_GPIO_ALTERNATE 6
143 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR
144 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI
145 #define DEBUG_UART_TX_EN_REG RCC_USART2CFGR
146 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN
147 #define DEBUG_UART_RST_REG RCC_USART2CFGR
148 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST
149 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR
150 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR
151
152 /*******************************************************************************
153 * STM32MP2 SDMMC
154 ******************************************************************************/
155 #define STM32MP_SDMMC1_BASE U(0x48220000)
156 #define STM32MP_SDMMC2_BASE U(0x48230000)
157 #define STM32MP_SDMMC3_BASE U(0x48240000)
158
159 /*******************************************************************************
160 * STM32MP2 TAMP
161 ******************************************************************************/
162 #define PLAT_MAX_TAMP_INT U(5)
163 #define PLAT_MAX_TAMP_EXT U(3)
164 #define TAMP_BASE U(0x46010000)
165 #define TAMP_SMCR (TAMP_BASE + U(0x20))
166 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
167 #define TAMP_BKP_REG_CLK CK_BUS_RTC
168 #define TAMP_BKP_SEC_NUMBER U(10)
169 #define TAMP_COUNTR U(0x40)
170
171 #if !(defined(__LINKER__) || defined(__ASSEMBLER__))
tamp_bkpr(uint32_t idx)172 static inline uintptr_t tamp_bkpr(uint32_t idx)
173 {
174 return TAMP_BKP_REGISTER_BASE + (idx << 2);
175 }
176 #endif
177
178 /*******************************************************************************
179 * STM32MP2 DDRCTRL
180 ******************************************************************************/
181 #define DDRCTRL_BASE U(0x48040000)
182
183 /*******************************************************************************
184 * STM32MP2 DDRDBG
185 ******************************************************************************/
186 #define DDRDBG_BASE U(0x48050000)
187
188 /*******************************************************************************
189 * STM32MP2 DDRPHYC
190 ******************************************************************************/
191 #define DDRPHYC_BASE U(0x48C00000)
192
193 /*******************************************************************************
194 * Miscellaneous STM32MP1 peripherals base address
195 ******************************************************************************/
196 #define BSEC_BASE U(0x44000000)
197 #define DBGMCU_BASE U(0x4A010000)
198 #define HASH_BASE U(0x42010000)
199 #define RTC_BASE U(0x46000000)
200 #define STGEN_BASE U(0x48080000)
201 #define SYSCFG_BASE U(0x44230000)
202
203 /*******************************************************************************
204 * REGULATORS
205 ******************************************************************************/
206 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
207 #define PLAT_NB_RDEVS U(19)
208 /* 2 FIXED */
209 #define PLAT_NB_FIXED_REGUS U(2)
210 /* No GPIO regu */
211 #define PLAT_NB_GPIO_REGUS U(0)
212
213 /*******************************************************************************
214 * Device Tree defines
215 ******************************************************************************/
216 #define DT_BSEC_COMPAT "st,stm32mp25-bsec"
217 #define DT_DDR_COMPAT "st,stm32mp2-ddr"
218 #define DT_PWR_COMPAT "st,stm32mp25-pwr"
219 #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc"
220 #define DT_UART_COMPAT "st,stm32h7-uart"
221
222 #endif /* STM32MP2_DEF_H */
223
