1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2021 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32K344_DCM_GPR.h
10  * @version 1.9
11  * @date 2021-10-27
12  * @brief Peripheral Access Layer for S32K344_DCM_GPR
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32K344_DCM_GPR_H_)  /* Check if memory map has not been already included */
58 #define S32K344_DCM_GPR_H_
59 
60 #include "S32K344_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- DCM_GPR Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup DCM_GPR_Peripheral_Access_Layer DCM_GPR Peripheral Access Layer
68  * @{
69  */
70 
71 /** DCM_GPR - Register Layout Typedef */
72 typedef struct {
73   uint8_t RESERVED_0[512];
74   __IO uint32_t DCMROD1;                           /**< Read Only GPR On Destructive Reset Register, offset: 0x200 */
75   uint8_t RESERVED_1[4];
76   __IO uint32_t DCMROD3;                           /**< Read Only GPR On Destructive Reset Register, offset: 0x208 */
77   __IO uint32_t DCMROD4;                           /**< Read Only GPR On Destructive Reset Register, offset: 0x20C */
78   __IO uint32_t DCMROD5;                           /**< Read Only GPR On Destructive Reset Register, offset: 0x210 */
79   uint8_t RESERVED_2[236];
80   __IO uint32_t DCMROF1;                           /**< Read Only GPR On Functional Reset Register, offset: 0x300 */
81   __IO uint32_t DCMROF2;                           /**< Read Only GPR On Functional Reset Register, offset: 0x304 */
82   __IO uint32_t DCMROF3;                           /**< Read Only GPR On Functional Reset Register, offset: 0x308 */
83   __IO uint32_t DCMROF4;                           /**< Read Only GPR On Functional Reset Register, offset: 0x30C */
84   __IO uint32_t DCMROF5;                           /**< Read Only GPR On Functional Reset Register, offset: 0x310 */
85   __IO uint32_t DCMROF6;                           /**< Read Only GPR On Functional Reset Register, offset: 0x314 */
86   __IO uint32_t DCMROF7;                           /**< Read Only GPR On Functional Reset Register, offset: 0x318 */
87   __IO uint32_t DCMROF8;                           /**< Read Only GPR On Functional Reset Register, offset: 0x31C */
88   __IO uint32_t DCMROF9;                           /**< Read Only GPR On Functional Reset Register, offset: 0x320 */
89   __IO uint32_t DCMROF10;                          /**< Read Only GPR On Functional Reset Register, offset: 0x324 */
90   __IO uint32_t DCMROF11;                          /**< Read Only GPR On Functional Reset Register, offset: 0x328 */
91   __IO uint32_t DCMROF12;                          /**< Read Only GPR On Functional Reset Register, offset: 0x32C */
92   __IO uint32_t DCMROF13;                          /**< Read Only GPR On Functional Reset Register, offset: 0x330 */
93   __IO uint32_t DCMROF14;                          /**< Read Only GPR On Functional Reset Register, offset: 0x334 */
94   __IO uint32_t DCMROF15;                          /**< Read Only GPR On Functional Reset Register, offset: 0x338 */
95   __IO uint32_t DCMROF16;                          /**< Read Only GPR On Functional Reset Register, offset: 0x33C */
96   __IO uint32_t DCMROF17;                          /**< Read Only GPR On Functional Reset Register, offset: 0x340 */
97   uint8_t RESERVED_3[4];
98   __I  uint32_t DCMROF19;                          /**< Read Only GPR On Functional Reset Register, offset: 0x348 */
99   __I  uint32_t DCMROF20;                          /**< Read Only GPR On Functional Reset Register, offset: 0x34C */
100   __I  uint32_t DCMROF21;                          /**< Read Only GPR On Functional Reset Register, offset: 0x350 */
101   uint8_t RESERVED_4[172];
102   __IO uint32_t DCMRWP1;                           /**< Read Write GPR On Power On Reset Register, offset: 0x400 */
103   uint8_t RESERVED_5[4];
104   __IO uint32_t DCMRWP3;                           /**< Read Write GPR On Power On Reset Register, offset: 0x408 */
105   uint8_t RESERVED_6[248];
106   __IO uint32_t DCMRWD2;                           /**< Read Write GPR On Destructive Reset Register, offset: 0x504 */
107   __IO uint32_t DCMRWD3;                           /**< Read Write GPR On Destructive Reset Register, offset: 0x508 */
108   __IO uint32_t DCMRWD4;                           /**< Read Write GPR On Destructive Reset Register, offset: 0x50C */
109   __IO uint32_t DCMRWD5;                           /**< Read Write GPR On Destructive Reset Register, offset: 0x510 */
110   __IO uint32_t DCMRWD6;                           /**< Read Write GPR On Destructive Reset Register, offset: 0x514 */
111        uint32_t DCMRWD7;                           /**< Read Write GPR On Destructive Reset Register, offset: 0x518 */
112        uint32_t DCMRWD8;                           /**< Read Write GPR On Destructive Reset Register, offset: 0x51C */
113        uint32_t DCMRWD9;                           /**< Read Write GPR On Destructive Reset Register, offset: 0x520 */
114   uint8_t RESERVED_7[220];
115   __IO uint32_t DCMRWF1;                           /**< Read Write GPR On Functional Reset Register, offset: 0x600 */
116   __IO uint32_t DCMRWF2;                           /**< Read Write GPR On Functional Reset Register, offset: 0x604 */
117   uint8_t RESERVED_8[4];
118   __IO uint32_t DCMRWF4;                           /**< Read Write GPR On Functional Reset Register, offset: 0x60C */
119   __IO uint32_t DCMRWF5;                           /**< Read Write GPR On Functional Reset Register, offset: 0x610 */
120   uint8_t RESERVED_9[236];
121   __IO uint32_t DCMROPP1;                          /**< Read Only GPR On PMCPOR Reset, offset: 0x700 */
122   __IO uint32_t DCMROPP2;                          /**< Read Only GPR On PMCPOR Reset, offset: 0x704 */
123   __IO uint32_t DCMROPP3;                          /**< Read Only GPR On PMCPOR Reset, offset: 0x708 */
124   __IO uint32_t DCMROPP4;                          /**< Read Only GPR On PMCPOR Reset, offset: 0x70C */
125 } DCM_GPR_Type, *DCM_GPR_MemMapPtr;
126 
127 /** Number of instances of the DCM_GPR module. */
128 #define DCM_GPR_INSTANCE_COUNT                   (1u)
129 
130 /* DCM_GPR - Peripheral instance base addresses */
131 /** Peripheral DCM_GPR base address */
132 #define IP_DCM_GPR_BASE                          (0x402AC000u)
133 /** Peripheral DCM_GPR base pointer */
134 #define IP_DCM_GPR                               ((DCM_GPR_Type *)IP_DCM_GPR_BASE)
135 /** Array initializer of DCM_GPR peripheral base addresses */
136 #define IP_DCM_GPR_BASE_ADDRS                    { IP_DCM_GPR_BASE }
137 /** Array initializer of DCM_GPR peripheral base pointers */
138 #define IP_DCM_GPR_BASE_PTRS                     { IP_DCM_GPR }
139 
140 /* ----------------------------------------------------------------------------
141    -- DCM_GPR Register Masks
142    ---------------------------------------------------------------------------- */
143 
144 /*!
145  * @addtogroup DCM_GPR_Register_Masks DCM_GPR Register Masks
146  * @{
147  */
148 
149 /*! @name DCMROD1 - Read Only GPR On Destructive Reset Register */
150 /*! @{ */
151 
152 #define DCM_GPR_DCMROD1_PCU_ISO_STATUS_MASK      (0x1U)
153 #define DCM_GPR_DCMROD1_PCU_ISO_STATUS_SHIFT     (0U)
154 #define DCM_GPR_DCMROD1_PCU_ISO_STATUS_WIDTH     (1U)
155 #define DCM_GPR_DCMROD1_PCU_ISO_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD1_PCU_ISO_STATUS_SHIFT)) & DCM_GPR_DCMROD1_PCU_ISO_STATUS_MASK)
156 
157 #define DCM_GPR_DCMROD1_HSE_DCF_VIO_MASK         (0x2U)
158 #define DCM_GPR_DCMROD1_HSE_DCF_VIO_SHIFT        (1U)
159 #define DCM_GPR_DCMROD1_HSE_DCF_VIO_WIDTH        (1U)
160 #define DCM_GPR_DCMROD1_HSE_DCF_VIO(x)           (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD1_HSE_DCF_VIO_SHIFT)) & DCM_GPR_DCMROD1_HSE_DCF_VIO_MASK)
161 
162 #define DCM_GPR_DCMROD1_KEY_RESP_READY_MASK      (0x4U)
163 #define DCM_GPR_DCMROD1_KEY_RESP_READY_SHIFT     (2U)
164 #define DCM_GPR_DCMROD1_KEY_RESP_READY_WIDTH     (1U)
165 #define DCM_GPR_DCMROD1_KEY_RESP_READY(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD1_KEY_RESP_READY_SHIFT)) & DCM_GPR_DCMROD1_KEY_RESP_READY_MASK)
166 /*! @} */
167 
168 /*! @name DCMROD3 - Read Only GPR On Destructive Reset Register */
169 /*! @{ */
170 
171 #define DCM_GPR_DCMROD3_CM7_0_LOCKUP_MASK        (0x1U)
172 #define DCM_GPR_DCMROD3_CM7_0_LOCKUP_SHIFT       (0U)
173 #define DCM_GPR_DCMROD3_CM7_0_LOCKUP_WIDTH       (1U)
174 #define DCM_GPR_DCMROD3_CM7_0_LOCKUP(x)          (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_CM7_0_LOCKUP_SHIFT)) & DCM_GPR_DCMROD3_CM7_0_LOCKUP_MASK)
175 
176 #define DCM_GPR_DCMROD3_HSE_LOCKUP_MASK          (0x4U)
177 #define DCM_GPR_DCMROD3_HSE_LOCKUP_SHIFT         (2U)
178 #define DCM_GPR_DCMROD3_HSE_LOCKUP_WIDTH         (1U)
179 #define DCM_GPR_DCMROD3_HSE_LOCKUP(x)            (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_HSE_LOCKUP_SHIFT)) & DCM_GPR_DCMROD3_HSE_LOCKUP_MASK)
180 
181 #define DCM_GPR_DCMROD3_CM7_RCCU1_ALARM_MASK     (0x8U)
182 #define DCM_GPR_DCMROD3_CM7_RCCU1_ALARM_SHIFT    (3U)
183 #define DCM_GPR_DCMROD3_CM7_RCCU1_ALARM_WIDTH    (1U)
184 #define DCM_GPR_DCMROD3_CM7_RCCU1_ALARM(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_CM7_RCCU1_ALARM_SHIFT)) & DCM_GPR_DCMROD3_CM7_RCCU1_ALARM_MASK)
185 
186 #define DCM_GPR_DCMROD3_CM7_RCCU2_ALARM_MASK     (0x10U)
187 #define DCM_GPR_DCMROD3_CM7_RCCU2_ALARM_SHIFT    (4U)
188 #define DCM_GPR_DCMROD3_CM7_RCCU2_ALARM_WIDTH    (1U)
189 #define DCM_GPR_DCMROD3_CM7_RCCU2_ALARM(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_CM7_RCCU2_ALARM_SHIFT)) & DCM_GPR_DCMROD3_CM7_RCCU2_ALARM_MASK)
190 
191 #define DCM_GPR_DCMROD3_TCM_GSKT_ALARM_MASK      (0x20U)
192 #define DCM_GPR_DCMROD3_TCM_GSKT_ALARM_SHIFT     (5U)
193 #define DCM_GPR_DCMROD3_TCM_GSKT_ALARM_WIDTH     (1U)
194 #define DCM_GPR_DCMROD3_TCM_GSKT_ALARM(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_TCM_GSKT_ALARM_SHIFT)) & DCM_GPR_DCMROD3_TCM_GSKT_ALARM_MASK)
195 
196 #define DCM_GPR_DCMROD3_DMA_SYS_GSKT_ALARM_MASK  (0x40U)
197 #define DCM_GPR_DCMROD3_DMA_SYS_GSKT_ALARM_SHIFT (6U)
198 #define DCM_GPR_DCMROD3_DMA_SYS_GSKT_ALARM_WIDTH (1U)
199 #define DCM_GPR_DCMROD3_DMA_SYS_GSKT_ALARM(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_DMA_SYS_GSKT_ALARM_SHIFT)) & DCM_GPR_DCMROD3_DMA_SYS_GSKT_ALARM_MASK)
200 
201 #define DCM_GPR_DCMROD3_DMA_PERIPH_GSKT_ALARM_MASK (0x80U)
202 #define DCM_GPR_DCMROD3_DMA_PERIPH_GSKT_ALARM_SHIFT (7U)
203 #define DCM_GPR_DCMROD3_DMA_PERIPH_GSKT_ALARM_WIDTH (1U)
204 #define DCM_GPR_DCMROD3_DMA_PERIPH_GSKT_ALARM(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_DMA_PERIPH_GSKT_ALARM_SHIFT)) & DCM_GPR_DCMROD3_DMA_PERIPH_GSKT_ALARM_MASK)
205 
206 #define DCM_GPR_DCMROD3_SYS_AXBS_ALARM_MASK      (0x100U)
207 #define DCM_GPR_DCMROD3_SYS_AXBS_ALARM_SHIFT     (8U)
208 #define DCM_GPR_DCMROD3_SYS_AXBS_ALARM_WIDTH     (1U)
209 #define DCM_GPR_DCMROD3_SYS_AXBS_ALARM(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_SYS_AXBS_ALARM_SHIFT)) & DCM_GPR_DCMROD3_SYS_AXBS_ALARM_MASK)
210 
211 #define DCM_GPR_DCMROD3_DMA_AXBS_ALARM_MASK      (0x200U)
212 #define DCM_GPR_DCMROD3_DMA_AXBS_ALARM_SHIFT     (9U)
213 #define DCM_GPR_DCMROD3_DMA_AXBS_ALARM_WIDTH     (1U)
214 #define DCM_GPR_DCMROD3_DMA_AXBS_ALARM(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_DMA_AXBS_ALARM_SHIFT)) & DCM_GPR_DCMROD3_DMA_AXBS_ALARM_MASK)
215 
216 #define DCM_GPR_DCMROD3_HSE_GSKT_ALARM_MASK      (0x800U)
217 #define DCM_GPR_DCMROD3_HSE_GSKT_ALARM_SHIFT     (11U)
218 #define DCM_GPR_DCMROD3_HSE_GSKT_ALARM_WIDTH     (1U)
219 #define DCM_GPR_DCMROD3_HSE_GSKT_ALARM(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_HSE_GSKT_ALARM_SHIFT)) & DCM_GPR_DCMROD3_HSE_GSKT_ALARM_MASK)
220 
221 #define DCM_GPR_DCMROD3_QSPI_GSKT_ALARM_MASK     (0x1000U)
222 #define DCM_GPR_DCMROD3_QSPI_GSKT_ALARM_SHIFT    (12U)
223 #define DCM_GPR_DCMROD3_QSPI_GSKT_ALARM_WIDTH    (1U)
224 #define DCM_GPR_DCMROD3_QSPI_GSKT_ALARM(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_QSPI_GSKT_ALARM_SHIFT)) & DCM_GPR_DCMROD3_QSPI_GSKT_ALARM_MASK)
225 
226 #define DCM_GPR_DCMROD3_AIPS1_GSKT_ALARM_MASK    (0x2000U)
227 #define DCM_GPR_DCMROD3_AIPS1_GSKT_ALARM_SHIFT   (13U)
228 #define DCM_GPR_DCMROD3_AIPS1_GSKT_ALARM_WIDTH   (1U)
229 #define DCM_GPR_DCMROD3_AIPS1_GSKT_ALARM(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_AIPS1_GSKT_ALARM_SHIFT)) & DCM_GPR_DCMROD3_AIPS1_GSKT_ALARM_MASK)
230 
231 #define DCM_GPR_DCMROD3_AIPS2_GSKT_ALARM_MASK    (0x4000U)
232 #define DCM_GPR_DCMROD3_AIPS2_GSKT_ALARM_SHIFT   (14U)
233 #define DCM_GPR_DCMROD3_AIPS2_GSKT_ALARM_WIDTH   (1U)
234 #define DCM_GPR_DCMROD3_AIPS2_GSKT_ALARM(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_AIPS2_GSKT_ALARM_SHIFT)) & DCM_GPR_DCMROD3_AIPS2_GSKT_ALARM_MASK)
235 
236 #define DCM_GPR_DCMROD3_ADDR_EDC_ERR_MASK        (0x8000U)
237 #define DCM_GPR_DCMROD3_ADDR_EDC_ERR_SHIFT       (15U)
238 #define DCM_GPR_DCMROD3_ADDR_EDC_ERR_WIDTH       (1U)
239 #define DCM_GPR_DCMROD3_ADDR_EDC_ERR(x)          (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_ADDR_EDC_ERR_SHIFT)) & DCM_GPR_DCMROD3_ADDR_EDC_ERR_MASK)
240 
241 #define DCM_GPR_DCMROD3_DATA_EDC_ERR_MASK        (0x10000U)
242 #define DCM_GPR_DCMROD3_DATA_EDC_ERR_SHIFT       (16U)
243 #define DCM_GPR_DCMROD3_DATA_EDC_ERR_WIDTH       (1U)
244 #define DCM_GPR_DCMROD3_DATA_EDC_ERR(x)          (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_DATA_EDC_ERR_SHIFT)) & DCM_GPR_DCMROD3_DATA_EDC_ERR_MASK)
245 
246 #define DCM_GPR_DCMROD3_TCM_AXBS_ALARM_MASK      (0x20000U)
247 #define DCM_GPR_DCMROD3_TCM_AXBS_ALARM_SHIFT     (17U)
248 #define DCM_GPR_DCMROD3_TCM_AXBS_ALARM_WIDTH     (1U)
249 #define DCM_GPR_DCMROD3_TCM_AXBS_ALARM(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_TCM_AXBS_ALARM_SHIFT)) & DCM_GPR_DCMROD3_TCM_AXBS_ALARM_MASK)
250 
251 #define DCM_GPR_DCMROD3_EMAC_GSKT_ALARM_MASK     (0x40000U)
252 #define DCM_GPR_DCMROD3_EMAC_GSKT_ALARM_SHIFT    (18U)
253 #define DCM_GPR_DCMROD3_EMAC_GSKT_ALARM_WIDTH    (1U)
254 #define DCM_GPR_DCMROD3_EMAC_GSKT_ALARM(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_EMAC_GSKT_ALARM_SHIFT)) & DCM_GPR_DCMROD3_EMAC_GSKT_ALARM_MASK)
255 
256 #define DCM_GPR_DCMROD3_PERIPH_AXBS_ALARM_MASK   (0x80000U)
257 #define DCM_GPR_DCMROD3_PERIPH_AXBS_ALARM_SHIFT  (19U)
258 #define DCM_GPR_DCMROD3_PERIPH_AXBS_ALARM_WIDTH  (1U)
259 #define DCM_GPR_DCMROD3_PERIPH_AXBS_ALARM(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_PERIPH_AXBS_ALARM_SHIFT)) & DCM_GPR_DCMROD3_PERIPH_AXBS_ALARM_MASK)
260 
261 #define DCM_GPR_DCMROD3_LC_ERR_MASK              (0x400000U)
262 #define DCM_GPR_DCMROD3_LC_ERR_SHIFT             (22U)
263 #define DCM_GPR_DCMROD3_LC_ERR_WIDTH             (1U)
264 #define DCM_GPR_DCMROD3_LC_ERR(x)                (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_LC_ERR_SHIFT)) & DCM_GPR_DCMROD3_LC_ERR_MASK)
265 
266 #define DCM_GPR_DCMROD3_PRAM1_ECC_ERR_MASK       (0x1000000U)
267 #define DCM_GPR_DCMROD3_PRAM1_ECC_ERR_SHIFT      (24U)
268 #define DCM_GPR_DCMROD3_PRAM1_ECC_ERR_WIDTH      (1U)
269 #define DCM_GPR_DCMROD3_PRAM1_ECC_ERR(x)         (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_PRAM1_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD3_PRAM1_ECC_ERR_MASK)
270 
271 #define DCM_GPR_DCMROD3_PRAM0_ECC_ERR_MASK       (0x2000000U)
272 #define DCM_GPR_DCMROD3_PRAM0_ECC_ERR_SHIFT      (25U)
273 #define DCM_GPR_DCMROD3_PRAM0_ECC_ERR_WIDTH      (1U)
274 #define DCM_GPR_DCMROD3_PRAM0_ECC_ERR(x)         (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_PRAM0_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD3_PRAM0_ECC_ERR_MASK)
275 
276 #define DCM_GPR_DCMROD3_CM7_0_DCDATA_ECC_ERR_MASK (0x4000000U)
277 #define DCM_GPR_DCMROD3_CM7_0_DCDATA_ECC_ERR_SHIFT (26U)
278 #define DCM_GPR_DCMROD3_CM7_0_DCDATA_ECC_ERR_WIDTH (1U)
279 #define DCM_GPR_DCMROD3_CM7_0_DCDATA_ECC_ERR(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_CM7_0_DCDATA_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD3_CM7_0_DCDATA_ECC_ERR_MASK)
280 
281 #define DCM_GPR_DCMROD3_CM7_0_DCTAG_ECC_ERR_MASK (0x10000000U)
282 #define DCM_GPR_DCMROD3_CM7_0_DCTAG_ECC_ERR_SHIFT (28U)
283 #define DCM_GPR_DCMROD3_CM7_0_DCTAG_ECC_ERR_WIDTH (1U)
284 #define DCM_GPR_DCMROD3_CM7_0_DCTAG_ECC_ERR(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_CM7_0_DCTAG_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD3_CM7_0_DCTAG_ECC_ERR_MASK)
285 
286 #define DCM_GPR_DCMROD3_CM7_0_ICDATA_ECC_ERR_MASK (0x40000000U)
287 #define DCM_GPR_DCMROD3_CM7_0_ICDATA_ECC_ERR_SHIFT (30U)
288 #define DCM_GPR_DCMROD3_CM7_0_ICDATA_ECC_ERR_WIDTH (1U)
289 #define DCM_GPR_DCMROD3_CM7_0_ICDATA_ECC_ERR(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD3_CM7_0_ICDATA_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD3_CM7_0_ICDATA_ECC_ERR_MASK)
290 /*! @} */
291 
292 /*! @name DCMROD4 - Read Only GPR On Destructive Reset Register */
293 /*! @{ */
294 
295 #define DCM_GPR_DCMROD4_CM7_0_ICTAG_ECC_ERR_MASK (0x1U)
296 #define DCM_GPR_DCMROD4_CM7_0_ICTAG_ECC_ERR_SHIFT (0U)
297 #define DCM_GPR_DCMROD4_CM7_0_ICTAG_ECC_ERR_WIDTH (1U)
298 #define DCM_GPR_DCMROD4_CM7_0_ICTAG_ECC_ERR(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_CM7_0_ICTAG_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD4_CM7_0_ICTAG_ECC_ERR_MASK)
299 
300 #define DCM_GPR_DCMROD4_CM7_0_ITCM_ECC_ERR_MASK  (0x4U)
301 #define DCM_GPR_DCMROD4_CM7_0_ITCM_ECC_ERR_SHIFT (2U)
302 #define DCM_GPR_DCMROD4_CM7_0_ITCM_ECC_ERR_WIDTH (1U)
303 #define DCM_GPR_DCMROD4_CM7_0_ITCM_ECC_ERR(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_CM7_0_ITCM_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD4_CM7_0_ITCM_ECC_ERR_MASK)
304 
305 #define DCM_GPR_DCMROD4_CM7_0_DTCM0_ECC_ERR_MASK (0x8U)
306 #define DCM_GPR_DCMROD4_CM7_0_DTCM0_ECC_ERR_SHIFT (3U)
307 #define DCM_GPR_DCMROD4_CM7_0_DTCM0_ECC_ERR_WIDTH (1U)
308 #define DCM_GPR_DCMROD4_CM7_0_DTCM0_ECC_ERR(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_CM7_0_DTCM0_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD4_CM7_0_DTCM0_ECC_ERR_MASK)
309 
310 #define DCM_GPR_DCMROD4_CM7_0_DTCM1_ECC_ERR_MASK (0x10U)
311 #define DCM_GPR_DCMROD4_CM7_0_DTCM1_ECC_ERR_SHIFT (4U)
312 #define DCM_GPR_DCMROD4_CM7_0_DTCM1_ECC_ERR_WIDTH (1U)
313 #define DCM_GPR_DCMROD4_CM7_0_DTCM1_ECC_ERR(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_CM7_0_DTCM1_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD4_CM7_0_DTCM1_ECC_ERR_MASK)
314 
315 #define DCM_GPR_DCMROD4_CM7_1_ITCM_ECC_ERR_MASK  (0x20U)
316 #define DCM_GPR_DCMROD4_CM7_1_ITCM_ECC_ERR_SHIFT (5U)
317 #define DCM_GPR_DCMROD4_CM7_1_ITCM_ECC_ERR_WIDTH (1U)
318 #define DCM_GPR_DCMROD4_CM7_1_ITCM_ECC_ERR(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_CM7_1_ITCM_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD4_CM7_1_ITCM_ECC_ERR_MASK)
319 
320 #define DCM_GPR_DCMROD4_CM7_1_DTCM0_ECC_ERR_MASK (0x40U)
321 #define DCM_GPR_DCMROD4_CM7_1_DTCM0_ECC_ERR_SHIFT (6U)
322 #define DCM_GPR_DCMROD4_CM7_1_DTCM0_ECC_ERR_WIDTH (1U)
323 #define DCM_GPR_DCMROD4_CM7_1_DTCM0_ECC_ERR(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_CM7_1_DTCM0_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD4_CM7_1_DTCM0_ECC_ERR_MASK)
324 
325 #define DCM_GPR_DCMROD4_CM7_1_DTCM1_ECC_ERR_MASK (0x80U)
326 #define DCM_GPR_DCMROD4_CM7_1_DTCM1_ECC_ERR_SHIFT (7U)
327 #define DCM_GPR_DCMROD4_CM7_1_DTCM1_ECC_ERR_WIDTH (1U)
328 #define DCM_GPR_DCMROD4_CM7_1_DTCM1_ECC_ERR(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_CM7_1_DTCM1_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD4_CM7_1_DTCM1_ECC_ERR_MASK)
329 
330 #define DCM_GPR_DCMROD4_DMA_TCD_RAM_ECC_ERR_MASK (0x100U)
331 #define DCM_GPR_DCMROD4_DMA_TCD_RAM_ECC_ERR_SHIFT (8U)
332 #define DCM_GPR_DCMROD4_DMA_TCD_RAM_ECC_ERR_WIDTH (1U)
333 #define DCM_GPR_DCMROD4_DMA_TCD_RAM_ECC_ERR(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_DMA_TCD_RAM_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD4_DMA_TCD_RAM_ECC_ERR_MASK)
334 
335 #define DCM_GPR_DCMROD4_PRAM0_FCCU_ALARM_MASK    (0x200U)
336 #define DCM_GPR_DCMROD4_PRAM0_FCCU_ALARM_SHIFT   (9U)
337 #define DCM_GPR_DCMROD4_PRAM0_FCCU_ALARM_WIDTH   (1U)
338 #define DCM_GPR_DCMROD4_PRAM0_FCCU_ALARM(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_PRAM0_FCCU_ALARM_SHIFT)) & DCM_GPR_DCMROD4_PRAM0_FCCU_ALARM_MASK)
339 
340 #define DCM_GPR_DCMROD4_PRAM1_FCCU_ALARM_MASK    (0x400U)
341 #define DCM_GPR_DCMROD4_PRAM1_FCCU_ALARM_SHIFT   (10U)
342 #define DCM_GPR_DCMROD4_PRAM1_FCCU_ALARM_WIDTH   (1U)
343 #define DCM_GPR_DCMROD4_PRAM1_FCCU_ALARM(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_PRAM1_FCCU_ALARM_SHIFT)) & DCM_GPR_DCMROD4_PRAM1_FCCU_ALARM_MASK)
344 
345 #define DCM_GPR_DCMROD4_HSE_RAM_ECC_ERR_MASK     (0x800U)
346 #define DCM_GPR_DCMROD4_HSE_RAM_ECC_ERR_SHIFT    (11U)
347 #define DCM_GPR_DCMROD4_HSE_RAM_ECC_ERR_WIDTH    (1U)
348 #define DCM_GPR_DCMROD4_HSE_RAM_ECC_ERR(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_HSE_RAM_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD4_HSE_RAM_ECC_ERR_MASK)
349 
350 #define DCM_GPR_DCMROD4_PF0_CODE_ECC_ERR_MASK    (0x1000U)
351 #define DCM_GPR_DCMROD4_PF0_CODE_ECC_ERR_SHIFT   (12U)
352 #define DCM_GPR_DCMROD4_PF0_CODE_ECC_ERR_WIDTH   (1U)
353 #define DCM_GPR_DCMROD4_PF0_CODE_ECC_ERR(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_PF0_CODE_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD4_PF0_CODE_ECC_ERR_MASK)
354 
355 #define DCM_GPR_DCMROD4_PF0_DATA_ECC_ERR_MASK    (0x2000U)
356 #define DCM_GPR_DCMROD4_PF0_DATA_ECC_ERR_SHIFT   (13U)
357 #define DCM_GPR_DCMROD4_PF0_DATA_ECC_ERR_WIDTH   (1U)
358 #define DCM_GPR_DCMROD4_PF0_DATA_ECC_ERR(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_PF0_DATA_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD4_PF0_DATA_ECC_ERR_MASK)
359 
360 #define DCM_GPR_DCMROD4_PF1_CODE_ECC_ERR_MASK    (0x4000U)
361 #define DCM_GPR_DCMROD4_PF1_CODE_ECC_ERR_SHIFT   (14U)
362 #define DCM_GPR_DCMROD4_PF1_CODE_ECC_ERR_WIDTH   (1U)
363 #define DCM_GPR_DCMROD4_PF1_CODE_ECC_ERR(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_PF1_CODE_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD4_PF1_CODE_ECC_ERR_MASK)
364 
365 #define DCM_GPR_DCMROD4_PF1_DATA_ECC_ERR_MASK    (0x8000U)
366 #define DCM_GPR_DCMROD4_PF1_DATA_ECC_ERR_SHIFT   (15U)
367 #define DCM_GPR_DCMROD4_PF1_DATA_ECC_ERR_WIDTH   (1U)
368 #define DCM_GPR_DCMROD4_PF1_DATA_ECC_ERR(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_PF1_DATA_ECC_ERR_SHIFT)) & DCM_GPR_DCMROD4_PF1_DATA_ECC_ERR_MASK)
369 
370 #define DCM_GPR_DCMROD4_FLASH_EDC_ERR_MASK       (0x40000U)
371 #define DCM_GPR_DCMROD4_FLASH_EDC_ERR_SHIFT      (18U)
372 #define DCM_GPR_DCMROD4_FLASH_EDC_ERR_WIDTH      (1U)
373 #define DCM_GPR_DCMROD4_FLASH_EDC_ERR(x)         (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_FLASH_EDC_ERR_SHIFT)) & DCM_GPR_DCMROD4_FLASH_EDC_ERR_MASK)
374 
375 #define DCM_GPR_DCMROD4_FLASH_ADDR_ENC_ERR_MASK  (0x80000U)
376 #define DCM_GPR_DCMROD4_FLASH_ADDR_ENC_ERR_SHIFT (19U)
377 #define DCM_GPR_DCMROD4_FLASH_ADDR_ENC_ERR_WIDTH (1U)
378 #define DCM_GPR_DCMROD4_FLASH_ADDR_ENC_ERR(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_FLASH_ADDR_ENC_ERR_SHIFT)) & DCM_GPR_DCMROD4_FLASH_ADDR_ENC_ERR_MASK)
379 
380 #define DCM_GPR_DCMROD4_FLASH_REF_ERR_MASK       (0x100000U)
381 #define DCM_GPR_DCMROD4_FLASH_REF_ERR_SHIFT      (20U)
382 #define DCM_GPR_DCMROD4_FLASH_REF_ERR_WIDTH      (1U)
383 #define DCM_GPR_DCMROD4_FLASH_REF_ERR(x)         (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_FLASH_REF_ERR_SHIFT)) & DCM_GPR_DCMROD4_FLASH_REF_ERR_MASK)
384 
385 #define DCM_GPR_DCMROD4_FLASH_RST_ERR_MASK       (0x200000U)
386 #define DCM_GPR_DCMROD4_FLASH_RST_ERR_SHIFT      (21U)
387 #define DCM_GPR_DCMROD4_FLASH_RST_ERR_WIDTH      (1U)
388 #define DCM_GPR_DCMROD4_FLASH_RST_ERR(x)         (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_FLASH_RST_ERR_SHIFT)) & DCM_GPR_DCMROD4_FLASH_RST_ERR_MASK)
389 
390 #define DCM_GPR_DCMROD4_FLASH_SCAN_ERR_MASK      (0x400000U)
391 #define DCM_GPR_DCMROD4_FLASH_SCAN_ERR_SHIFT     (22U)
392 #define DCM_GPR_DCMROD4_FLASH_SCAN_ERR_WIDTH     (1U)
393 #define DCM_GPR_DCMROD4_FLASH_SCAN_ERR(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_FLASH_SCAN_ERR_SHIFT)) & DCM_GPR_DCMROD4_FLASH_SCAN_ERR_MASK)
394 
395 #define DCM_GPR_DCMROD4_FLASH_ACCESS_ERR_MASK    (0x1000000U)
396 #define DCM_GPR_DCMROD4_FLASH_ACCESS_ERR_SHIFT   (24U)
397 #define DCM_GPR_DCMROD4_FLASH_ACCESS_ERR_WIDTH   (1U)
398 #define DCM_GPR_DCMROD4_FLASH_ACCESS_ERR(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_FLASH_ACCESS_ERR_SHIFT)) & DCM_GPR_DCMROD4_FLASH_ACCESS_ERR_MASK)
399 
400 #define DCM_GPR_DCMROD4_VDD1P1_GNG_ERR_MASK      (0x4000000U)
401 #define DCM_GPR_DCMROD4_VDD1P1_GNG_ERR_SHIFT     (26U)
402 #define DCM_GPR_DCMROD4_VDD1P1_GNG_ERR_WIDTH     (1U)
403 #define DCM_GPR_DCMROD4_VDD1P1_GNG_ERR(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_VDD1P1_GNG_ERR_SHIFT)) & DCM_GPR_DCMROD4_VDD1P1_GNG_ERR_MASK)
404 
405 #define DCM_GPR_DCMROD4_VDD2P5_GNG_ERR_MASK      (0x8000000U)
406 #define DCM_GPR_DCMROD4_VDD2P5_GNG_ERR_SHIFT     (27U)
407 #define DCM_GPR_DCMROD4_VDD2P5_GNG_ERR_WIDTH     (1U)
408 #define DCM_GPR_DCMROD4_VDD2P5_GNG_ERR(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_VDD2P5_GNG_ERR_SHIFT)) & DCM_GPR_DCMROD4_VDD2P5_GNG_ERR_MASK)
409 
410 #define DCM_GPR_DCMROD4_TEST_ACTIVATION_0_ERR_MASK (0x20000000U)
411 #define DCM_GPR_DCMROD4_TEST_ACTIVATION_0_ERR_SHIFT (29U)
412 #define DCM_GPR_DCMROD4_TEST_ACTIVATION_0_ERR_WIDTH (1U)
413 #define DCM_GPR_DCMROD4_TEST_ACTIVATION_0_ERR(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_TEST_ACTIVATION_0_ERR_SHIFT)) & DCM_GPR_DCMROD4_TEST_ACTIVATION_0_ERR_MASK)
414 
415 #define DCM_GPR_DCMROD4_TEST_ACTIVATION_1_ERR_MASK (0x40000000U)
416 #define DCM_GPR_DCMROD4_TEST_ACTIVATION_1_ERR_SHIFT (30U)
417 #define DCM_GPR_DCMROD4_TEST_ACTIVATION_1_ERR_WIDTH (1U)
418 #define DCM_GPR_DCMROD4_TEST_ACTIVATION_1_ERR(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD4_TEST_ACTIVATION_1_ERR_SHIFT)) & DCM_GPR_DCMROD4_TEST_ACTIVATION_1_ERR_MASK)
419 /*! @} */
420 
421 /*! @name DCMROD5 - Read Only GPR On Destructive Reset Register */
422 /*! @{ */
423 
424 #define DCM_GPR_DCMROD5_INTM_0_ERR_MASK          (0x2U)
425 #define DCM_GPR_DCMROD5_INTM_0_ERR_SHIFT         (1U)
426 #define DCM_GPR_DCMROD5_INTM_0_ERR_WIDTH         (1U)
427 #define DCM_GPR_DCMROD5_INTM_0_ERR(x)            (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_INTM_0_ERR_SHIFT)) & DCM_GPR_DCMROD5_INTM_0_ERR_MASK)
428 
429 #define DCM_GPR_DCMROD5_INTM_1_ERR_MASK          (0x4U)
430 #define DCM_GPR_DCMROD5_INTM_1_ERR_SHIFT         (2U)
431 #define DCM_GPR_DCMROD5_INTM_1_ERR_WIDTH         (1U)
432 #define DCM_GPR_DCMROD5_INTM_1_ERR(x)            (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_INTM_1_ERR_SHIFT)) & DCM_GPR_DCMROD5_INTM_1_ERR_MASK)
433 
434 #define DCM_GPR_DCMROD5_INTM_2_ERR_MASK          (0x8U)
435 #define DCM_GPR_DCMROD5_INTM_2_ERR_SHIFT         (3U)
436 #define DCM_GPR_DCMROD5_INTM_2_ERR_WIDTH         (1U)
437 #define DCM_GPR_DCMROD5_INTM_2_ERR(x)            (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_INTM_2_ERR_SHIFT)) & DCM_GPR_DCMROD5_INTM_2_ERR_MASK)
438 
439 #define DCM_GPR_DCMROD5_INTM_3_ERR_MASK          (0x10U)
440 #define DCM_GPR_DCMROD5_INTM_3_ERR_SHIFT         (4U)
441 #define DCM_GPR_DCMROD5_INTM_3_ERR_WIDTH         (1U)
442 #define DCM_GPR_DCMROD5_INTM_3_ERR(x)            (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_INTM_3_ERR_SHIFT)) & DCM_GPR_DCMROD5_INTM_3_ERR_MASK)
443 
444 #define DCM_GPR_DCMROD5_SW_NCF_0_MASK            (0x20U)
445 #define DCM_GPR_DCMROD5_SW_NCF_0_SHIFT           (5U)
446 #define DCM_GPR_DCMROD5_SW_NCF_0_WIDTH           (1U)
447 #define DCM_GPR_DCMROD5_SW_NCF_0(x)              (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_SW_NCF_0_SHIFT)) & DCM_GPR_DCMROD5_SW_NCF_0_MASK)
448 
449 #define DCM_GPR_DCMROD5_SW_NCF_1_MASK            (0x40U)
450 #define DCM_GPR_DCMROD5_SW_NCF_1_SHIFT           (6U)
451 #define DCM_GPR_DCMROD5_SW_NCF_1_WIDTH           (1U)
452 #define DCM_GPR_DCMROD5_SW_NCF_1(x)              (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_SW_NCF_1_SHIFT)) & DCM_GPR_DCMROD5_SW_NCF_1_MASK)
453 
454 #define DCM_GPR_DCMROD5_SW_NCF_2_MASK            (0x80U)
455 #define DCM_GPR_DCMROD5_SW_NCF_2_SHIFT           (7U)
456 #define DCM_GPR_DCMROD5_SW_NCF_2_WIDTH           (1U)
457 #define DCM_GPR_DCMROD5_SW_NCF_2(x)              (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_SW_NCF_2_SHIFT)) & DCM_GPR_DCMROD5_SW_NCF_2_MASK)
458 
459 #define DCM_GPR_DCMROD5_SW_NCF_3_MASK            (0x100U)
460 #define DCM_GPR_DCMROD5_SW_NCF_3_SHIFT           (8U)
461 #define DCM_GPR_DCMROD5_SW_NCF_3_WIDTH           (1U)
462 #define DCM_GPR_DCMROD5_SW_NCF_3(x)              (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_SW_NCF_3_SHIFT)) & DCM_GPR_DCMROD5_SW_NCF_3_MASK)
463 
464 #define DCM_GPR_DCMROD5_STCU_NCF_MASK            (0x200U)
465 #define DCM_GPR_DCMROD5_STCU_NCF_SHIFT           (9U)
466 #define DCM_GPR_DCMROD5_STCU_NCF_WIDTH           (1U)
467 #define DCM_GPR_DCMROD5_STCU_NCF(x)              (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_STCU_NCF_SHIFT)) & DCM_GPR_DCMROD5_STCU_NCF_MASK)
468 
469 #define DCM_GPR_DCMROD5_MBIST_ACTIVATION_ERR_MASK (0x400U)
470 #define DCM_GPR_DCMROD5_MBIST_ACTIVATION_ERR_SHIFT (10U)
471 #define DCM_GPR_DCMROD5_MBIST_ACTIVATION_ERR_WIDTH (1U)
472 #define DCM_GPR_DCMROD5_MBIST_ACTIVATION_ERR(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_MBIST_ACTIVATION_ERR_SHIFT)) & DCM_GPR_DCMROD5_MBIST_ACTIVATION_ERR_MASK)
473 
474 #define DCM_GPR_DCMROD5_STCU_BIST_USER_CF_MASK   (0x800U)
475 #define DCM_GPR_DCMROD5_STCU_BIST_USER_CF_SHIFT  (11U)
476 #define DCM_GPR_DCMROD5_STCU_BIST_USER_CF_WIDTH  (1U)
477 #define DCM_GPR_DCMROD5_STCU_BIST_USER_CF(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_STCU_BIST_USER_CF_SHIFT)) & DCM_GPR_DCMROD5_STCU_BIST_USER_CF_MASK)
478 
479 #define DCM_GPR_DCMROD5_MTR_BUS_ERR_MASK         (0x1000U)
480 #define DCM_GPR_DCMROD5_MTR_BUS_ERR_SHIFT        (12U)
481 #define DCM_GPR_DCMROD5_MTR_BUS_ERR_WIDTH        (1U)
482 #define DCM_GPR_DCMROD5_MTR_BUS_ERR(x)           (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_MTR_BUS_ERR_SHIFT)) & DCM_GPR_DCMROD5_MTR_BUS_ERR_MASK)
483 
484 #define DCM_GPR_DCMROD5_DEBUG_ACTIVATION_ERR_MASK (0x2000U)
485 #define DCM_GPR_DCMROD5_DEBUG_ACTIVATION_ERR_SHIFT (13U)
486 #define DCM_GPR_DCMROD5_DEBUG_ACTIVATION_ERR_WIDTH (1U)
487 #define DCM_GPR_DCMROD5_DEBUG_ACTIVATION_ERR(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_DEBUG_ACTIVATION_ERR_SHIFT)) & DCM_GPR_DCMROD5_DEBUG_ACTIVATION_ERR_MASK)
488 
489 #define DCM_GPR_DCMROD5_TCM_RDATA_EDC_ERR_MASK   (0x4000U)
490 #define DCM_GPR_DCMROD5_TCM_RDATA_EDC_ERR_SHIFT  (14U)
491 #define DCM_GPR_DCMROD5_TCM_RDATA_EDC_ERR_WIDTH  (1U)
492 #define DCM_GPR_DCMROD5_TCM_RDATA_EDC_ERR(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_TCM_RDATA_EDC_ERR_SHIFT)) & DCM_GPR_DCMROD5_TCM_RDATA_EDC_ERR_MASK)
493 
494 #define DCM_GPR_DCMROD5_EMAC_RDATA_EDC_ERR_MASK  (0x8000U)
495 #define DCM_GPR_DCMROD5_EMAC_RDATA_EDC_ERR_SHIFT (15U)
496 #define DCM_GPR_DCMROD5_EMAC_RDATA_EDC_ERR_WIDTH (1U)
497 #define DCM_GPR_DCMROD5_EMAC_RDATA_EDC_ERR(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_EMAC_RDATA_EDC_ERR_SHIFT)) & DCM_GPR_DCMROD5_EMAC_RDATA_EDC_ERR_MASK)
498 
499 #define DCM_GPR_DCMROD5_DMA_RDATA_EDC_ERR_MASK   (0x20000U)
500 #define DCM_GPR_DCMROD5_DMA_RDATA_EDC_ERR_SHIFT  (17U)
501 #define DCM_GPR_DCMROD5_DMA_RDATA_EDC_ERR_WIDTH  (1U)
502 #define DCM_GPR_DCMROD5_DMA_RDATA_EDC_ERR(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_DMA_RDATA_EDC_ERR_SHIFT)) & DCM_GPR_DCMROD5_DMA_RDATA_EDC_ERR_MASK)
503 
504 #define DCM_GPR_DCMROD5_CM7_0_AHBP_RDATA_EDC_ERR_MASK (0x100000U)
505 #define DCM_GPR_DCMROD5_CM7_0_AHBP_RDATA_EDC_ERR_SHIFT (20U)
506 #define DCM_GPR_DCMROD5_CM7_0_AHBP_RDATA_EDC_ERR_WIDTH (1U)
507 #define DCM_GPR_DCMROD5_CM7_0_AHBP_RDATA_EDC_ERR(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_CM7_0_AHBP_RDATA_EDC_ERR_SHIFT)) & DCM_GPR_DCMROD5_CM7_0_AHBP_RDATA_EDC_ERR_MASK)
508 
509 #define DCM_GPR_DCMROD5_CM7_0_AHBM_RDATA_EDC_ERR_MASK (0x200000U)
510 #define DCM_GPR_DCMROD5_CM7_0_AHBM_RDATA_EDC_ERR_SHIFT (21U)
511 #define DCM_GPR_DCMROD5_CM7_0_AHBM_RDATA_EDC_ERR_WIDTH (1U)
512 #define DCM_GPR_DCMROD5_CM7_0_AHBM_RDATA_EDC_ERR(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_CM7_0_AHBM_RDATA_EDC_ERR_SHIFT)) & DCM_GPR_DCMROD5_CM7_0_AHBM_RDATA_EDC_ERR_MASK)
513 
514 #define DCM_GPR_DCMROD5_HSE_RDATA_EDC_ERR_MASK   (0x400000U)
515 #define DCM_GPR_DCMROD5_HSE_RDATA_EDC_ERR_SHIFT  (22U)
516 #define DCM_GPR_DCMROD5_HSE_RDATA_EDC_ERR_WIDTH  (1U)
517 #define DCM_GPR_DCMROD5_HSE_RDATA_EDC_ERR(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROD5_HSE_RDATA_EDC_ERR_SHIFT)) & DCM_GPR_DCMROD5_HSE_RDATA_EDC_ERR_MASK)
518 /*! @} */
519 
520 /*! @name DCMROF1 - Read Only GPR On Functional Reset Register */
521 /*! @{ */
522 
523 #define DCM_GPR_DCMROF1_EMAC_MDC_CHID_0_MASK     (0x1U)
524 #define DCM_GPR_DCMROF1_EMAC_MDC_CHID_0_SHIFT    (0U)
525 #define DCM_GPR_DCMROF1_EMAC_MDC_CHID_0_WIDTH    (1U)
526 #define DCM_GPR_DCMROF1_EMAC_MDC_CHID_0(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF1_EMAC_MDC_CHID_0_SHIFT)) & DCM_GPR_DCMROF1_EMAC_MDC_CHID_0_MASK)
527 
528 #define DCM_GPR_DCMROF1_EMAC_MDC_CHID_1_MASK     (0x2U)
529 #define DCM_GPR_DCMROF1_EMAC_MDC_CHID_1_SHIFT    (1U)
530 #define DCM_GPR_DCMROF1_EMAC_MDC_CHID_1_WIDTH    (1U)
531 #define DCM_GPR_DCMROF1_EMAC_MDC_CHID_1(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF1_EMAC_MDC_CHID_1_SHIFT)) & DCM_GPR_DCMROF1_EMAC_MDC_CHID_1_MASK)
532 /*! @} */
533 
534 /*! @name DCMROF2 - Read Only GPR On Functional Reset Register */
535 /*! @{ */
536 
537 #define DCM_GPR_DCMROF2_DCF_SDID0_MASK           (0xFFFFFFFFU)
538 #define DCM_GPR_DCMROF2_DCF_SDID0_SHIFT          (0U)
539 #define DCM_GPR_DCMROF2_DCF_SDID0_WIDTH          (32U)
540 #define DCM_GPR_DCMROF2_DCF_SDID0(x)             (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF2_DCF_SDID0_SHIFT)) & DCM_GPR_DCMROF2_DCF_SDID0_MASK)
541 /*! @} */
542 
543 /*! @name DCMROF3 - Read Only GPR On Functional Reset Register */
544 /*! @{ */
545 
546 #define DCM_GPR_DCMROF3_DCF_SDID1_MASK           (0xFFFFFFFFU)
547 #define DCM_GPR_DCMROF3_DCF_SDID1_SHIFT          (0U)
548 #define DCM_GPR_DCMROF3_DCF_SDID1_WIDTH          (32U)
549 #define DCM_GPR_DCMROF3_DCF_SDID1(x)             (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF3_DCF_SDID1_SHIFT)) & DCM_GPR_DCMROF3_DCF_SDID1_MASK)
550 /*! @} */
551 
552 /*! @name DCMROF4 - Read Only GPR On Functional Reset Register */
553 /*! @{ */
554 
555 #define DCM_GPR_DCMROF4_DCF_SDID2_MASK           (0xFFFFFFFFU)
556 #define DCM_GPR_DCMROF4_DCF_SDID2_SHIFT          (0U)
557 #define DCM_GPR_DCMROF4_DCF_SDID2_WIDTH          (32U)
558 #define DCM_GPR_DCMROF4_DCF_SDID2(x)             (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF4_DCF_SDID2_SHIFT)) & DCM_GPR_DCMROF4_DCF_SDID2_MASK)
559 /*! @} */
560 
561 /*! @name DCMROF5 - Read Only GPR On Functional Reset Register */
562 /*! @{ */
563 
564 #define DCM_GPR_DCMROF5_DCF_SDID3_MASK           (0xFFFFFFFFU)
565 #define DCM_GPR_DCMROF5_DCF_SDID3_SHIFT          (0U)
566 #define DCM_GPR_DCMROF5_DCF_SDID3_WIDTH          (32U)
567 #define DCM_GPR_DCMROF5_DCF_SDID3(x)             (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF5_DCF_SDID3_SHIFT)) & DCM_GPR_DCMROF5_DCF_SDID3_MASK)
568 /*! @} */
569 
570 /*! @name DCMROF6 - Read Only GPR On Functional Reset Register */
571 /*! @{ */
572 
573 #define DCM_GPR_DCMROF6_DCF_SDID4_MASK           (0xFFFFFFFFU)
574 #define DCM_GPR_DCMROF6_DCF_SDID4_SHIFT          (0U)
575 #define DCM_GPR_DCMROF6_DCF_SDID4_WIDTH          (32U)
576 #define DCM_GPR_DCMROF6_DCF_SDID4(x)             (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF6_DCF_SDID4_SHIFT)) & DCM_GPR_DCMROF6_DCF_SDID4_MASK)
577 /*! @} */
578 
579 /*! @name DCMROF7 - Read Only GPR On Functional Reset Register */
580 /*! @{ */
581 
582 #define DCM_GPR_DCMROF7_DCF_SDID5_MASK           (0xFFFFFFFFU)
583 #define DCM_GPR_DCMROF7_DCF_SDID5_SHIFT          (0U)
584 #define DCM_GPR_DCMROF7_DCF_SDID5_WIDTH          (32U)
585 #define DCM_GPR_DCMROF7_DCF_SDID5(x)             (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF7_DCF_SDID5_SHIFT)) & DCM_GPR_DCMROF7_DCF_SDID5_MASK)
586 /*! @} */
587 
588 /*! @name DCMROF8 - Read Only GPR On Functional Reset Register */
589 /*! @{ */
590 
591 #define DCM_GPR_DCMROF8_DCF_SDID6_MASK           (0xFFFFFFFFU)
592 #define DCM_GPR_DCMROF8_DCF_SDID6_SHIFT          (0U)
593 #define DCM_GPR_DCMROF8_DCF_SDID6_WIDTH          (32U)
594 #define DCM_GPR_DCMROF8_DCF_SDID6(x)             (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF8_DCF_SDID6_SHIFT)) & DCM_GPR_DCMROF8_DCF_SDID6_MASK)
595 /*! @} */
596 
597 /*! @name DCMROF9 - Read Only GPR On Functional Reset Register */
598 /*! @{ */
599 
600 #define DCM_GPR_DCMROF9_DCF_SDID7_MASK           (0xFFFFFFFFU)
601 #define DCM_GPR_DCMROF9_DCF_SDID7_SHIFT          (0U)
602 #define DCM_GPR_DCMROF9_DCF_SDID7_WIDTH          (32U)
603 #define DCM_GPR_DCMROF9_DCF_SDID7(x)             (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF9_DCF_SDID7_SHIFT)) & DCM_GPR_DCMROF9_DCF_SDID7_MASK)
604 /*! @} */
605 
606 /*! @name DCMROF10 - Read Only GPR On Functional Reset Register */
607 /*! @{ */
608 
609 #define DCM_GPR_DCMROF10_DCF_SDID8_MASK          (0xFFFFFFFFU)
610 #define DCM_GPR_DCMROF10_DCF_SDID8_SHIFT         (0U)
611 #define DCM_GPR_DCMROF10_DCF_SDID8_WIDTH         (32U)
612 #define DCM_GPR_DCMROF10_DCF_SDID8(x)            (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF10_DCF_SDID8_SHIFT)) & DCM_GPR_DCMROF10_DCF_SDID8_MASK)
613 /*! @} */
614 
615 /*! @name DCMROF11 - Read Only GPR On Functional Reset Register */
616 /*! @{ */
617 
618 #define DCM_GPR_DCMROF11_DCF_SDID9_MASK          (0xFFFFFFFFU)
619 #define DCM_GPR_DCMROF11_DCF_SDID9_SHIFT         (0U)
620 #define DCM_GPR_DCMROF11_DCF_SDID9_WIDTH         (32U)
621 #define DCM_GPR_DCMROF11_DCF_SDID9(x)            (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF11_DCF_SDID9_SHIFT)) & DCM_GPR_DCMROF11_DCF_SDID9_MASK)
622 /*! @} */
623 
624 /*! @name DCMROF12 - Read Only GPR On Functional Reset Register */
625 /*! @{ */
626 
627 #define DCM_GPR_DCMROF12_DCF_SDID10_MASK         (0xFFFFFFFFU)
628 #define DCM_GPR_DCMROF12_DCF_SDID10_SHIFT        (0U)
629 #define DCM_GPR_DCMROF12_DCF_SDID10_WIDTH        (32U)
630 #define DCM_GPR_DCMROF12_DCF_SDID10(x)           (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF12_DCF_SDID10_SHIFT)) & DCM_GPR_DCMROF12_DCF_SDID10_MASK)
631 /*! @} */
632 
633 /*! @name DCMROF13 - Read Only GPR On Functional Reset Register */
634 /*! @{ */
635 
636 #define DCM_GPR_DCMROF13_DCF_SDID11_MASK         (0xFFFFFFFFU)
637 #define DCM_GPR_DCMROF13_DCF_SDID11_SHIFT        (0U)
638 #define DCM_GPR_DCMROF13_DCF_SDID11_WIDTH        (32U)
639 #define DCM_GPR_DCMROF13_DCF_SDID11(x)           (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF13_DCF_SDID11_SHIFT)) & DCM_GPR_DCMROF13_DCF_SDID11_MASK)
640 /*! @} */
641 
642 /*! @name DCMROF14 - Read Only GPR On Functional Reset Register */
643 /*! @{ */
644 
645 #define DCM_GPR_DCMROF14_DCF_SDID12_MASK         (0xFFFFFFFFU)
646 #define DCM_GPR_DCMROF14_DCF_SDID12_SHIFT        (0U)
647 #define DCM_GPR_DCMROF14_DCF_SDID12_WIDTH        (32U)
648 #define DCM_GPR_DCMROF14_DCF_SDID12(x)           (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF14_DCF_SDID12_SHIFT)) & DCM_GPR_DCMROF14_DCF_SDID12_MASK)
649 /*! @} */
650 
651 /*! @name DCMROF15 - Read Only GPR On Functional Reset Register */
652 /*! @{ */
653 
654 #define DCM_GPR_DCMROF15_DCF_SDID13_MASK         (0xFFFFFFFFU)
655 #define DCM_GPR_DCMROF15_DCF_SDID13_SHIFT        (0U)
656 #define DCM_GPR_DCMROF15_DCF_SDID13_WIDTH        (32U)
657 #define DCM_GPR_DCMROF15_DCF_SDID13(x)           (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF15_DCF_SDID13_SHIFT)) & DCM_GPR_DCMROF15_DCF_SDID13_MASK)
658 /*! @} */
659 
660 /*! @name DCMROF16 - Read Only GPR On Functional Reset Register */
661 /*! @{ */
662 
663 #define DCM_GPR_DCMROF16_DCF_SDID14_MASK         (0xFFFFFFFFU)
664 #define DCM_GPR_DCMROF16_DCF_SDID14_SHIFT        (0U)
665 #define DCM_GPR_DCMROF16_DCF_SDID14_WIDTH        (32U)
666 #define DCM_GPR_DCMROF16_DCF_SDID14(x)           (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF16_DCF_SDID14_SHIFT)) & DCM_GPR_DCMROF16_DCF_SDID14_MASK)
667 /*! @} */
668 
669 /*! @name DCMROF17 - Read Only GPR On Functional Reset Register */
670 /*! @{ */
671 
672 #define DCM_GPR_DCMROF17_DCF_SDID15_MASK         (0xFFFFFFFFU)
673 #define DCM_GPR_DCMROF17_DCF_SDID15_SHIFT        (0U)
674 #define DCM_GPR_DCMROF17_DCF_SDID15_WIDTH        (32U)
675 #define DCM_GPR_DCMROF17_DCF_SDID15(x)           (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF17_DCF_SDID15_SHIFT)) & DCM_GPR_DCMROF17_DCF_SDID15_MASK)
676 /*! @} */
677 
678 /*! @name DCMROF19 - Read Only GPR On Functional Reset Register */
679 /*! @{ */
680 
681 #define DCM_GPR_DCMROF19_LOCKSTEP_EN_MASK        (0x20000000U)
682 #define DCM_GPR_DCMROF19_LOCKSTEP_EN_SHIFT       (29U)
683 #define DCM_GPR_DCMROF19_LOCKSTEP_EN_WIDTH       (1U)
684 #define DCM_GPR_DCMROF19_LOCKSTEP_EN(x)          (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF19_LOCKSTEP_EN_SHIFT)) & DCM_GPR_DCMROF19_LOCKSTEP_EN_MASK)
685 
686 #define DCM_GPR_DCMROF19_DCM_DONE_MASK           (0x40000000U)
687 #define DCM_GPR_DCMROF19_DCM_DONE_SHIFT          (30U)
688 #define DCM_GPR_DCMROF19_DCM_DONE_WIDTH          (1U)
689 #define DCM_GPR_DCMROF19_DCM_DONE(x)             (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF19_DCM_DONE_SHIFT)) & DCM_GPR_DCMROF19_DCM_DONE_MASK)
690 
691 #define DCM_GPR_DCMROF19_FCCU_EOUT_DEDICATED_MASK (0x80000000U)
692 #define DCM_GPR_DCMROF19_FCCU_EOUT_DEDICATED_SHIFT (31U)
693 #define DCM_GPR_DCMROF19_FCCU_EOUT_DEDICATED_WIDTH (1U)
694 #define DCM_GPR_DCMROF19_FCCU_EOUT_DEDICATED(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF19_FCCU_EOUT_DEDICATED_SHIFT)) & DCM_GPR_DCMROF19_FCCU_EOUT_DEDICATED_MASK)
695 /*! @} */
696 
697 /*! @name DCMROF20 - Read Only GPR On Functional Reset Register */
698 /*! @{ */
699 
700 #define DCM_GPR_DCMROF20_POR_WDG_EN_MASK         (0x1U)
701 #define DCM_GPR_DCMROF20_POR_WDG_EN_SHIFT        (0U)
702 #define DCM_GPR_DCMROF20_POR_WDG_EN_WIDTH        (1U)
703 #define DCM_GPR_DCMROF20_POR_WDG_EN(x)           (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF20_POR_WDG_EN_SHIFT)) & DCM_GPR_DCMROF20_POR_WDG_EN_MASK)
704 
705 #define DCM_GPR_DCMROF20_LMAUTO_DIS_MASK         (0x2U)
706 #define DCM_GPR_DCMROF20_LMAUTO_DIS_SHIFT        (1U)
707 #define DCM_GPR_DCMROF20_LMAUTO_DIS_WIDTH        (1U)
708 #define DCM_GPR_DCMROF20_LMAUTO_DIS(x)           (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF20_LMAUTO_DIS_SHIFT)) & DCM_GPR_DCMROF20_LMAUTO_DIS_MASK)
709 
710 #define DCM_GPR_DCMROF20_DMA_AXBS_IAHB_BYP_MASK  (0x8U)
711 #define DCM_GPR_DCMROF20_DMA_AXBS_IAHB_BYP_SHIFT (3U)
712 #define DCM_GPR_DCMROF20_DMA_AXBS_IAHB_BYP_WIDTH (1U)
713 #define DCM_GPR_DCMROF20_DMA_AXBS_IAHB_BYP(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF20_DMA_AXBS_IAHB_BYP_SHIFT)) & DCM_GPR_DCMROF20_DMA_AXBS_IAHB_BYP_MASK)
714 
715 #define DCM_GPR_DCMROF20_QSPI_IAHB_BYP_MASK      (0x20U)
716 #define DCM_GPR_DCMROF20_QSPI_IAHB_BYP_SHIFT     (5U)
717 #define DCM_GPR_DCMROF20_QSPI_IAHB_BYP_WIDTH     (1U)
718 #define DCM_GPR_DCMROF20_QSPI_IAHB_BYP(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF20_QSPI_IAHB_BYP_SHIFT)) & DCM_GPR_DCMROF20_QSPI_IAHB_BYP_MASK)
719 
720 #define DCM_GPR_DCMROF20_AIPS_IAHB_BYP_MASK      (0x40U)
721 #define DCM_GPR_DCMROF20_AIPS_IAHB_BYP_SHIFT     (6U)
722 #define DCM_GPR_DCMROF20_AIPS_IAHB_BYP_WIDTH     (1U)
723 #define DCM_GPR_DCMROF20_AIPS_IAHB_BYP(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF20_AIPS_IAHB_BYP_SHIFT)) & DCM_GPR_DCMROF20_AIPS_IAHB_BYP_MASK)
724 
725 #define DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_MASK   (0xFFFC0000U)
726 #define DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_SHIFT  (18U)
727 #define DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_WIDTH  (14U)
728 #define DCM_GPR_DCMROF20_DCF_DEST_RST_ESC(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_SHIFT)) & DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_MASK)
729 /*! @} */
730 
731 /*! @name DCMROF21 - Read Only GPR On Functional Reset Register */
732 /*! @{ */
733 
734 #define DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_MASK   (0x3FFFFU)
735 #define DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_SHIFT  (0U)
736 #define DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_WIDTH  (18U)
737 #define DCM_GPR_DCMROF21_DCF_DEST_RST_ESC(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_SHIFT)) & DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_MASK)
738 
739 #define DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_MASK (0x180000U)
740 #define DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_SHIFT (19U)
741 #define DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_WIDTH (2U)
742 #define DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_SHIFT)) & DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_MASK)
743 /*! @} */
744 
745 /*! @name DCMRWP1 - Read Write GPR On Power On Reset Register */
746 /*! @{ */
747 
748 #define DCM_GPR_DCMRWP1_CLKOUT_STANDBY_MASK      (0x8U)
749 #define DCM_GPR_DCMRWP1_CLKOUT_STANDBY_SHIFT     (3U)
750 #define DCM_GPR_DCMRWP1_CLKOUT_STANDBY_WIDTH     (1U)
751 #define DCM_GPR_DCMRWP1_CLKOUT_STANDBY(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWP1_CLKOUT_STANDBY_SHIFT)) & DCM_GPR_DCMRWP1_CLKOUT_STANDBY_MASK)
752 
753 #define DCM_GPR_DCMRWP1_STANBDY_PWDOG_DIS_MASK   (0x100U)
754 #define DCM_GPR_DCMRWP1_STANBDY_PWDOG_DIS_SHIFT  (8U)
755 #define DCM_GPR_DCMRWP1_STANBDY_PWDOG_DIS_WIDTH  (1U)
756 #define DCM_GPR_DCMRWP1_STANBDY_PWDOG_DIS(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWP1_STANBDY_PWDOG_DIS_SHIFT)) & DCM_GPR_DCMRWP1_STANBDY_PWDOG_DIS_MASK)
757 
758 #define DCM_GPR_DCMRWP1_POR_WDOG_TRIM_MASK       (0x600U)
759 #define DCM_GPR_DCMRWP1_POR_WDOG_TRIM_SHIFT      (9U)
760 #define DCM_GPR_DCMRWP1_POR_WDOG_TRIM_WIDTH      (2U)
761 #define DCM_GPR_DCMRWP1_POR_WDOG_TRIM(x)         (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWP1_POR_WDOG_TRIM_SHIFT)) & DCM_GPR_DCMRWP1_POR_WDOG_TRIM_MASK)
762 /*! @} */
763 
764 /*! @name DCMRWP3 - Read Write GPR On Power On Reset Register */
765 /*! @{ */
766 
767 #define DCM_GPR_DCMRWP3_DEST_RST9_AS_IPI_MASK    (0x200U)
768 #define DCM_GPR_DCMRWP3_DEST_RST9_AS_IPI_SHIFT   (9U)
769 #define DCM_GPR_DCMRWP3_DEST_RST9_AS_IPI_WIDTH   (1U)
770 #define DCM_GPR_DCMRWP3_DEST_RST9_AS_IPI(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWP3_DEST_RST9_AS_IPI_SHIFT)) & DCM_GPR_DCMRWP3_DEST_RST9_AS_IPI_MASK)
771 /*! @} */
772 
773 /*! @name DCMRWD2 - Read Write GPR On Destructive Reset Register */
774 /*! @{ */
775 
776 #define DCM_GPR_DCMRWD2_EOUT_STAT_DUR_STEST_MASK (0x80U)
777 #define DCM_GPR_DCMRWD2_EOUT_STAT_DUR_STEST_SHIFT (7U)
778 #define DCM_GPR_DCMRWD2_EOUT_STAT_DUR_STEST_WIDTH (1U)
779 #define DCM_GPR_DCMRWD2_EOUT_STAT_DUR_STEST(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD2_EOUT_STAT_DUR_STEST_SHIFT)) & DCM_GPR_DCMRWD2_EOUT_STAT_DUR_STEST_MASK)
780 /*! @} */
781 
782 /*! @name DCMRWD3 - Read Write GPR On Destructive Reset Register */
783 /*! @{ */
784 
785 #define DCM_GPR_DCMRWD3_CM7_0_LOCKUP_EN_MASK     (0x1U)
786 #define DCM_GPR_DCMRWD3_CM7_0_LOCKUP_EN_SHIFT    (0U)
787 #define DCM_GPR_DCMRWD3_CM7_0_LOCKUP_EN_WIDTH    (1U)
788 #define DCM_GPR_DCMRWD3_CM7_0_LOCKUP_EN(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_CM7_0_LOCKUP_EN_SHIFT)) & DCM_GPR_DCMRWD3_CM7_0_LOCKUP_EN_MASK)
789 
790 #define DCM_GPR_DCMRWD3_CM7_RCCU1_ALARM_EN_MASK  (0x8U)
791 #define DCM_GPR_DCMRWD3_CM7_RCCU1_ALARM_EN_SHIFT (3U)
792 #define DCM_GPR_DCMRWD3_CM7_RCCU1_ALARM_EN_WIDTH (1U)
793 #define DCM_GPR_DCMRWD3_CM7_RCCU1_ALARM_EN(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_CM7_RCCU1_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD3_CM7_RCCU1_ALARM_EN_MASK)
794 
795 #define DCM_GPR_DCMRWD3_CM7_RCCU2_ALARM_EN_MASK  (0x10U)
796 #define DCM_GPR_DCMRWD3_CM7_RCCU2_ALARM_EN_SHIFT (4U)
797 #define DCM_GPR_DCMRWD3_CM7_RCCU2_ALARM_EN_WIDTH (1U)
798 #define DCM_GPR_DCMRWD3_CM7_RCCU2_ALARM_EN(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_CM7_RCCU2_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD3_CM7_RCCU2_ALARM_EN_MASK)
799 
800 #define DCM_GPR_DCMRWD3_TCM_GSKT_ALARM_EN_MASK   (0x20U)
801 #define DCM_GPR_DCMRWD3_TCM_GSKT_ALARM_EN_SHIFT  (5U)
802 #define DCM_GPR_DCMRWD3_TCM_GSKT_ALARM_EN_WIDTH  (1U)
803 #define DCM_GPR_DCMRWD3_TCM_GSKT_ALARM_EN(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_TCM_GSKT_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD3_TCM_GSKT_ALARM_EN_MASK)
804 
805 #define DCM_GPR_DCMRWD3_DMA_SYS_GSKT_ALARM_EN_MASK (0x40U)
806 #define DCM_GPR_DCMRWD3_DMA_SYS_GSKT_ALARM_EN_SHIFT (6U)
807 #define DCM_GPR_DCMRWD3_DMA_SYS_GSKT_ALARM_EN_WIDTH (1U)
808 #define DCM_GPR_DCMRWD3_DMA_SYS_GSKT_ALARM_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_DMA_SYS_GSKT_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD3_DMA_SYS_GSKT_ALARM_EN_MASK)
809 
810 #define DCM_GPR_DCMRWD3_DMA_PERIPH_GSKT_ALARM_EN_MASK (0x80U)
811 #define DCM_GPR_DCMRWD3_DMA_PERIPH_GSKT_ALARM_EN_SHIFT (7U)
812 #define DCM_GPR_DCMRWD3_DMA_PERIPH_GSKT_ALARM_EN_WIDTH (1U)
813 #define DCM_GPR_DCMRWD3_DMA_PERIPH_GSKT_ALARM_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_DMA_PERIPH_GSKT_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD3_DMA_PERIPH_GSKT_ALARM_EN_MASK)
814 
815 #define DCM_GPR_DCMRWD3_SYS_AXBS_ALARM_EN_MASK   (0x100U)
816 #define DCM_GPR_DCMRWD3_SYS_AXBS_ALARM_EN_SHIFT  (8U)
817 #define DCM_GPR_DCMRWD3_SYS_AXBS_ALARM_EN_WIDTH  (1U)
818 #define DCM_GPR_DCMRWD3_SYS_AXBS_ALARM_EN(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_SYS_AXBS_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD3_SYS_AXBS_ALARM_EN_MASK)
819 
820 #define DCM_GPR_DCMRWD3_DMA_AXBS_ALARM_EN_MASK   (0x200U)
821 #define DCM_GPR_DCMRWD3_DMA_AXBS_ALARM_EN_SHIFT  (9U)
822 #define DCM_GPR_DCMRWD3_DMA_AXBS_ALARM_EN_WIDTH  (1U)
823 #define DCM_GPR_DCMRWD3_DMA_AXBS_ALARM_EN(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_DMA_AXBS_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD3_DMA_AXBS_ALARM_EN_MASK)
824 
825 #define DCM_GPR_DCMRWD3_HSE_GSKT_ALARM_EN_MASK   (0x800U)
826 #define DCM_GPR_DCMRWD3_HSE_GSKT_ALARM_EN_SHIFT  (11U)
827 #define DCM_GPR_DCMRWD3_HSE_GSKT_ALARM_EN_WIDTH  (1U)
828 #define DCM_GPR_DCMRWD3_HSE_GSKT_ALARM_EN(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_HSE_GSKT_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD3_HSE_GSKT_ALARM_EN_MASK)
829 
830 #define DCM_GPR_DCMRWD3_QSPI_GSKT_ALARM_EN_MASK  (0x1000U)
831 #define DCM_GPR_DCMRWD3_QSPI_GSKT_ALARM_EN_SHIFT (12U)
832 #define DCM_GPR_DCMRWD3_QSPI_GSKT_ALARM_EN_WIDTH (1U)
833 #define DCM_GPR_DCMRWD3_QSPI_GSKT_ALARM_EN(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_QSPI_GSKT_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD3_QSPI_GSKT_ALARM_EN_MASK)
834 
835 #define DCM_GPR_DCMRWD3_AIPS1_GSKT_ALARM_EN_MASK (0x2000U)
836 #define DCM_GPR_DCMRWD3_AIPS1_GSKT_ALARM_EN_SHIFT (13U)
837 #define DCM_GPR_DCMRWD3_AIPS1_GSKT_ALARM_EN_WIDTH (1U)
838 #define DCM_GPR_DCMRWD3_AIPS1_GSKT_ALARM_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_AIPS1_GSKT_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD3_AIPS1_GSKT_ALARM_EN_MASK)
839 
840 #define DCM_GPR_DCMRWD3_AIPS2_GSKT_ALARM_EN_MASK (0x4000U)
841 #define DCM_GPR_DCMRWD3_AIPS2_GSKT_ALARM_EN_SHIFT (14U)
842 #define DCM_GPR_DCMRWD3_AIPS2_GSKT_ALARM_EN_WIDTH (1U)
843 #define DCM_GPR_DCMRWD3_AIPS2_GSKT_ALARM_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_AIPS2_GSKT_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD3_AIPS2_GSKT_ALARM_EN_MASK)
844 
845 #define DCM_GPR_DCMRWD3_ADDR_EDC_ERR_EN_MASK     (0x8000U)
846 #define DCM_GPR_DCMRWD3_ADDR_EDC_ERR_EN_SHIFT    (15U)
847 #define DCM_GPR_DCMRWD3_ADDR_EDC_ERR_EN_WIDTH    (1U)
848 #define DCM_GPR_DCMRWD3_ADDR_EDC_ERR_EN(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_ADDR_EDC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD3_ADDR_EDC_ERR_EN_MASK)
849 
850 #define DCM_GPR_DCMRWD3_DATA_EDC_ERR_EN_MASK     (0x10000U)
851 #define DCM_GPR_DCMRWD3_DATA_EDC_ERR_EN_SHIFT    (16U)
852 #define DCM_GPR_DCMRWD3_DATA_EDC_ERR_EN_WIDTH    (1U)
853 #define DCM_GPR_DCMRWD3_DATA_EDC_ERR_EN(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_DATA_EDC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD3_DATA_EDC_ERR_EN_MASK)
854 
855 #define DCM_GPR_DCMRWD3_TCM_AXBS_ALARM_EN_MASK   (0x20000U)
856 #define DCM_GPR_DCMRWD3_TCM_AXBS_ALARM_EN_SHIFT  (17U)
857 #define DCM_GPR_DCMRWD3_TCM_AXBS_ALARM_EN_WIDTH  (1U)
858 #define DCM_GPR_DCMRWD3_TCM_AXBS_ALARM_EN(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_TCM_AXBS_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD3_TCM_AXBS_ALARM_EN_MASK)
859 
860 #define DCM_GPR_DCMRWD3_EMAC_GSKT_ALARM_EN_MASK  (0x40000U)
861 #define DCM_GPR_DCMRWD3_EMAC_GSKT_ALARM_EN_SHIFT (18U)
862 #define DCM_GPR_DCMRWD3_EMAC_GSKT_ALARM_EN_WIDTH (1U)
863 #define DCM_GPR_DCMRWD3_EMAC_GSKT_ALARM_EN(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_EMAC_GSKT_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD3_EMAC_GSKT_ALARM_EN_MASK)
864 
865 #define DCM_GPR_DCMRWD3_PERIPH_AXBS_ALARM_EN_MASK (0x80000U)
866 #define DCM_GPR_DCMRWD3_PERIPH_AXBS_ALARM_EN_SHIFT (19U)
867 #define DCM_GPR_DCMRWD3_PERIPH_AXBS_ALARM_EN_WIDTH (1U)
868 #define DCM_GPR_DCMRWD3_PERIPH_AXBS_ALARM_EN(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_PERIPH_AXBS_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD3_PERIPH_AXBS_ALARM_EN_MASK)
869 
870 #define DCM_GPR_DCMRWD3_LC_ERR_EN_MASK           (0x400000U)
871 #define DCM_GPR_DCMRWD3_LC_ERR_EN_SHIFT          (22U)
872 #define DCM_GPR_DCMRWD3_LC_ERR_EN_WIDTH          (1U)
873 #define DCM_GPR_DCMRWD3_LC_ERR_EN(x)             (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_LC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD3_LC_ERR_EN_MASK)
874 
875 #define DCM_GPR_DCMRWD3_PRAM1_ECC_ERR_EN_MASK    (0x1000000U)
876 #define DCM_GPR_DCMRWD3_PRAM1_ECC_ERR_EN_SHIFT   (24U)
877 #define DCM_GPR_DCMRWD3_PRAM1_ECC_ERR_EN_WIDTH   (1U)
878 #define DCM_GPR_DCMRWD3_PRAM1_ECC_ERR_EN(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_PRAM1_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD3_PRAM1_ECC_ERR_EN_MASK)
879 
880 #define DCM_GPR_DCMRWD3_PRAM0_ECC_ERR_EN_MASK    (0x2000000U)
881 #define DCM_GPR_DCMRWD3_PRAM0_ECC_ERR_EN_SHIFT   (25U)
882 #define DCM_GPR_DCMRWD3_PRAM0_ECC_ERR_EN_WIDTH   (1U)
883 #define DCM_GPR_DCMRWD3_PRAM0_ECC_ERR_EN(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_PRAM0_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD3_PRAM0_ECC_ERR_EN_MASK)
884 
885 #define DCM_GPR_DCMRWD3_CM7_0_DCDATA_ECC_ERR_EN_MASK (0x4000000U)
886 #define DCM_GPR_DCMRWD3_CM7_0_DCDATA_ECC_ERR_EN_SHIFT (26U)
887 #define DCM_GPR_DCMRWD3_CM7_0_DCDATA_ECC_ERR_EN_WIDTH (1U)
888 #define DCM_GPR_DCMRWD3_CM7_0_DCDATA_ECC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_CM7_0_DCDATA_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD3_CM7_0_DCDATA_ECC_ERR_EN_MASK)
889 
890 #define DCM_GPR_DCMRWD3_CM7_0_DCTAG_ECC_ERR_EN_MASK (0x10000000U)
891 #define DCM_GPR_DCMRWD3_CM7_0_DCTAG_ECC_ERR_EN_SHIFT (28U)
892 #define DCM_GPR_DCMRWD3_CM7_0_DCTAG_ECC_ERR_EN_WIDTH (1U)
893 #define DCM_GPR_DCMRWD3_CM7_0_DCTAG_ECC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_CM7_0_DCTAG_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD3_CM7_0_DCTAG_ECC_ERR_EN_MASK)
894 
895 #define DCM_GPR_DCMRWD3_CM7_0_ICDATA_ECC_ERR_EN_MASK (0x40000000U)
896 #define DCM_GPR_DCMRWD3_CM7_0_ICDATA_ECC_ERR_EN_SHIFT (30U)
897 #define DCM_GPR_DCMRWD3_CM7_0_ICDATA_ECC_ERR_EN_WIDTH (1U)
898 #define DCM_GPR_DCMRWD3_CM7_0_ICDATA_ECC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD3_CM7_0_ICDATA_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD3_CM7_0_ICDATA_ECC_ERR_EN_MASK)
899 /*! @} */
900 
901 /*! @name DCMRWD4 - Read Write GPR On Destructive Reset Register */
902 /*! @{ */
903 
904 #define DCM_GPR_DCMRWD4_CM7_0_ICTAG_ECC_ERR_EN_MASK (0x1U)
905 #define DCM_GPR_DCMRWD4_CM7_0_ICTAG_ECC_ERR_EN_SHIFT (0U)
906 #define DCM_GPR_DCMRWD4_CM7_0_ICTAG_ECC_ERR_EN_WIDTH (1U)
907 #define DCM_GPR_DCMRWD4_CM7_0_ICTAG_ECC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_CM7_0_ICTAG_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_CM7_0_ICTAG_ECC_ERR_EN_MASK)
908 
909 #define DCM_GPR_DCMRWD4_CM7_0_ITCM_ECC_ERR_EN_MASK (0x4U)
910 #define DCM_GPR_DCMRWD4_CM7_0_ITCM_ECC_ERR_EN_SHIFT (2U)
911 #define DCM_GPR_DCMRWD4_CM7_0_ITCM_ECC_ERR_EN_WIDTH (1U)
912 #define DCM_GPR_DCMRWD4_CM7_0_ITCM_ECC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_CM7_0_ITCM_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_CM7_0_ITCM_ECC_ERR_EN_MASK)
913 
914 #define DCM_GPR_DCMRWD4_CM7_0_DTCM0_ECC_ERR_EN_MASK (0x8U)
915 #define DCM_GPR_DCMRWD4_CM7_0_DTCM0_ECC_ERR_EN_SHIFT (3U)
916 #define DCM_GPR_DCMRWD4_CM7_0_DTCM0_ECC_ERR_EN_WIDTH (1U)
917 #define DCM_GPR_DCMRWD4_CM7_0_DTCM0_ECC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_CM7_0_DTCM0_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_CM7_0_DTCM0_ECC_ERR_EN_MASK)
918 
919 #define DCM_GPR_DCMRWD4_CM7_0_DTCM1_ECC_ERR_EN_MASK (0x10U)
920 #define DCM_GPR_DCMRWD4_CM7_0_DTCM1_ECC_ERR_EN_SHIFT (4U)
921 #define DCM_GPR_DCMRWD4_CM7_0_DTCM1_ECC_ERR_EN_WIDTH (1U)
922 #define DCM_GPR_DCMRWD4_CM7_0_DTCM1_ECC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_CM7_0_DTCM1_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_CM7_0_DTCM1_ECC_ERR_EN_MASK)
923 
924 #define DCM_GPR_DCMRWD4_CM7_1_ITCM_ECC_ERR_EN_MASK (0x20U)
925 #define DCM_GPR_DCMRWD4_CM7_1_ITCM_ECC_ERR_EN_SHIFT (5U)
926 #define DCM_GPR_DCMRWD4_CM7_1_ITCM_ECC_ERR_EN_WIDTH (1U)
927 #define DCM_GPR_DCMRWD4_CM7_1_ITCM_ECC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_CM7_1_ITCM_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_CM7_1_ITCM_ECC_ERR_EN_MASK)
928 
929 #define DCM_GPR_DCMRWD4_CM7_1_DTCM0_ECC_ERR_EN_MASK (0x40U)
930 #define DCM_GPR_DCMRWD4_CM7_1_DTCM0_ECC_ERR_EN_SHIFT (6U)
931 #define DCM_GPR_DCMRWD4_CM7_1_DTCM0_ECC_ERR_EN_WIDTH (1U)
932 #define DCM_GPR_DCMRWD4_CM7_1_DTCM0_ECC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_CM7_1_DTCM0_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_CM7_1_DTCM0_ECC_ERR_EN_MASK)
933 
934 #define DCM_GPR_DCMRWD4_CM7_1_DTCM1_ECC_ERR_EN_MASK (0x80U)
935 #define DCM_GPR_DCMRWD4_CM7_1_DTCM1_ECC_ERR_EN_SHIFT (7U)
936 #define DCM_GPR_DCMRWD4_CM7_1_DTCM1_ECC_ERR_EN_WIDTH (1U)
937 #define DCM_GPR_DCMRWD4_CM7_1_DTCM1_ECC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_CM7_1_DTCM1_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_CM7_1_DTCM1_ECC_ERR_EN_MASK)
938 
939 #define DCM_GPR_DCMRWD4_DMA_TCD_RAM_ECC_ERR_EN_MASK (0x100U)
940 #define DCM_GPR_DCMRWD4_DMA_TCD_RAM_ECC_ERR_EN_SHIFT (8U)
941 #define DCM_GPR_DCMRWD4_DMA_TCD_RAM_ECC_ERR_EN_WIDTH (1U)
942 #define DCM_GPR_DCMRWD4_DMA_TCD_RAM_ECC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_DMA_TCD_RAM_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_DMA_TCD_RAM_ECC_ERR_EN_MASK)
943 
944 #define DCM_GPR_DCMRWD4_PRAM0_FCCU_ALARM_EN_MASK (0x200U)
945 #define DCM_GPR_DCMRWD4_PRAM0_FCCU_ALARM_EN_SHIFT (9U)
946 #define DCM_GPR_DCMRWD4_PRAM0_FCCU_ALARM_EN_WIDTH (1U)
947 #define DCM_GPR_DCMRWD4_PRAM0_FCCU_ALARM_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_PRAM0_FCCU_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD4_PRAM0_FCCU_ALARM_EN_MASK)
948 
949 #define DCM_GPR_DCMRWD4_PRAM1_FCCU_ALARM_EN_MASK (0x400U)
950 #define DCM_GPR_DCMRWD4_PRAM1_FCCU_ALARM_EN_SHIFT (10U)
951 #define DCM_GPR_DCMRWD4_PRAM1_FCCU_ALARM_EN_WIDTH (1U)
952 #define DCM_GPR_DCMRWD4_PRAM1_FCCU_ALARM_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_PRAM1_FCCU_ALARM_EN_SHIFT)) & DCM_GPR_DCMRWD4_PRAM1_FCCU_ALARM_EN_MASK)
953 
954 #define DCM_GPR_DCMRWD4_HSE_RAM_ECC_ERR_EN_MASK  (0x800U)
955 #define DCM_GPR_DCMRWD4_HSE_RAM_ECC_ERR_EN_SHIFT (11U)
956 #define DCM_GPR_DCMRWD4_HSE_RAM_ECC_ERR_EN_WIDTH (1U)
957 #define DCM_GPR_DCMRWD4_HSE_RAM_ECC_ERR_EN(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_HSE_RAM_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_HSE_RAM_ECC_ERR_EN_MASK)
958 
959 #define DCM_GPR_DCMRWD4_PF0_CODE_ECC_ERR_EN_MASK (0x1000U)
960 #define DCM_GPR_DCMRWD4_PF0_CODE_ECC_ERR_EN_SHIFT (12U)
961 #define DCM_GPR_DCMRWD4_PF0_CODE_ECC_ERR_EN_WIDTH (1U)
962 #define DCM_GPR_DCMRWD4_PF0_CODE_ECC_ERR_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_PF0_CODE_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_PF0_CODE_ECC_ERR_EN_MASK)
963 
964 #define DCM_GPR_DCMRWD4_PF0_DATA_ECC_ERR_EN_MASK (0x2000U)
965 #define DCM_GPR_DCMRWD4_PF0_DATA_ECC_ERR_EN_SHIFT (13U)
966 #define DCM_GPR_DCMRWD4_PF0_DATA_ECC_ERR_EN_WIDTH (1U)
967 #define DCM_GPR_DCMRWD4_PF0_DATA_ECC_ERR_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_PF0_DATA_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_PF0_DATA_ECC_ERR_EN_MASK)
968 
969 #define DCM_GPR_DCMRWD4_PF1_CODE_ECC_ERR_EN_MASK (0x4000U)
970 #define DCM_GPR_DCMRWD4_PF1_CODE_ECC_ERR_EN_SHIFT (14U)
971 #define DCM_GPR_DCMRWD4_PF1_CODE_ECC_ERR_EN_WIDTH (1U)
972 #define DCM_GPR_DCMRWD4_PF1_CODE_ECC_ERR_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_PF1_CODE_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_PF1_CODE_ECC_ERR_EN_MASK)
973 
974 #define DCM_GPR_DCMRWD4_PF1_DATA_ECC_ERR_EN_MASK (0x8000U)
975 #define DCM_GPR_DCMRWD4_PF1_DATA_ECC_ERR_EN_SHIFT (15U)
976 #define DCM_GPR_DCMRWD4_PF1_DATA_ECC_ERR_EN_WIDTH (1U)
977 #define DCM_GPR_DCMRWD4_PF1_DATA_ECC_ERR_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_PF1_DATA_ECC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_PF1_DATA_ECC_ERR_EN_MASK)
978 
979 #define DCM_GPR_DCMRWD4_FLASH_EDC_ERR_EN_MASK    (0x40000U)
980 #define DCM_GPR_DCMRWD4_FLASH_EDC_ERR_EN_SHIFT   (18U)
981 #define DCM_GPR_DCMRWD4_FLASH_EDC_ERR_EN_WIDTH   (1U)
982 #define DCM_GPR_DCMRWD4_FLASH_EDC_ERR_EN(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_FLASH_EDC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_FLASH_EDC_ERR_EN_MASK)
983 
984 #define DCM_GPR_DCMRWD4_FLASH_ADDR_ENC_ERR_EN_MASK (0x80000U)
985 #define DCM_GPR_DCMRWD4_FLASH_ADDR_ENC_ERR_EN_SHIFT (19U)
986 #define DCM_GPR_DCMRWD4_FLASH_ADDR_ENC_ERR_EN_WIDTH (1U)
987 #define DCM_GPR_DCMRWD4_FLASH_ADDR_ENC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_FLASH_ADDR_ENC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_FLASH_ADDR_ENC_ERR_EN_MASK)
988 
989 #define DCM_GPR_DCMRWD4_FLASH_REF_ERR_EN_MASK    (0x100000U)
990 #define DCM_GPR_DCMRWD4_FLASH_REF_ERR_EN_SHIFT   (20U)
991 #define DCM_GPR_DCMRWD4_FLASH_REF_ERR_EN_WIDTH   (1U)
992 #define DCM_GPR_DCMRWD4_FLASH_REF_ERR_EN(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_FLASH_REF_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_FLASH_REF_ERR_EN_MASK)
993 
994 #define DCM_GPR_DCMRWD4_FLASH_RST_ERR_EN_MASK    (0x200000U)
995 #define DCM_GPR_DCMRWD4_FLASH_RST_ERR_EN_SHIFT   (21U)
996 #define DCM_GPR_DCMRWD4_FLASH_RST_ERR_EN_WIDTH   (1U)
997 #define DCM_GPR_DCMRWD4_FLASH_RST_ERR_EN(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_FLASH_RST_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_FLASH_RST_ERR_EN_MASK)
998 
999 #define DCM_GPR_DCMRWD4_FLASH_SCAN_ERR_EN_MASK   (0x400000U)
1000 #define DCM_GPR_DCMRWD4_FLASH_SCAN_ERR_EN_SHIFT  (22U)
1001 #define DCM_GPR_DCMRWD4_FLASH_SCAN_ERR_EN_WIDTH  (1U)
1002 #define DCM_GPR_DCMRWD4_FLASH_SCAN_ERR_EN(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_FLASH_SCAN_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_FLASH_SCAN_ERR_EN_MASK)
1003 
1004 #define DCM_GPR_DCMRWD4_FLASH_ACCESS_ERR_EN_MASK (0x1000000U)
1005 #define DCM_GPR_DCMRWD4_FLASH_ACCESS_ERR_EN_SHIFT (24U)
1006 #define DCM_GPR_DCMRWD4_FLASH_ACCESS_ERR_EN_WIDTH (1U)
1007 #define DCM_GPR_DCMRWD4_FLASH_ACCESS_ERR_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_FLASH_ACCESS_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_FLASH_ACCESS_ERR_EN_MASK)
1008 
1009 #define DCM_GPR_DCMRWD4_VDD1P1_GNG_ERR_EN_MASK   (0x4000000U)
1010 #define DCM_GPR_DCMRWD4_VDD1P1_GNG_ERR_EN_SHIFT  (26U)
1011 #define DCM_GPR_DCMRWD4_VDD1P1_GNG_ERR_EN_WIDTH  (1U)
1012 #define DCM_GPR_DCMRWD4_VDD1P1_GNG_ERR_EN(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_VDD1P1_GNG_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_VDD1P1_GNG_ERR_EN_MASK)
1013 
1014 #define DCM_GPR_DCMRWD4_VDD2P5_GNG_ERR_EN_MASK   (0x8000000U)
1015 #define DCM_GPR_DCMRWD4_VDD2P5_GNG_ERR_EN_SHIFT  (27U)
1016 #define DCM_GPR_DCMRWD4_VDD2P5_GNG_ERR_EN_WIDTH  (1U)
1017 #define DCM_GPR_DCMRWD4_VDD2P5_GNG_ERR_EN(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_VDD2P5_GNG_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_VDD2P5_GNG_ERR_EN_MASK)
1018 
1019 #define DCM_GPR_DCMRWD4_TEST_ACTIVATION_0_ERR_EN_MASK (0x20000000U)
1020 #define DCM_GPR_DCMRWD4_TEST_ACTIVATION_0_ERR_EN_SHIFT (29U)
1021 #define DCM_GPR_DCMRWD4_TEST_ACTIVATION_0_ERR_EN_WIDTH (1U)
1022 #define DCM_GPR_DCMRWD4_TEST_ACTIVATION_0_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_TEST_ACTIVATION_0_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_TEST_ACTIVATION_0_ERR_EN_MASK)
1023 
1024 #define DCM_GPR_DCMRWD4_TEST_ACTIVATION_1_ERR_EN_MASK (0x40000000U)
1025 #define DCM_GPR_DCMRWD4_TEST_ACTIVATION_1_ERR_EN_SHIFT (30U)
1026 #define DCM_GPR_DCMRWD4_TEST_ACTIVATION_1_ERR_EN_WIDTH (1U)
1027 #define DCM_GPR_DCMRWD4_TEST_ACTIVATION_1_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD4_TEST_ACTIVATION_1_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD4_TEST_ACTIVATION_1_ERR_EN_MASK)
1028 /*! @} */
1029 
1030 /*! @name DCMRWD5 - Read Write GPR On Destructive Reset Register */
1031 /*! @{ */
1032 
1033 #define DCM_GPR_DCMRWD5_INTM_0_ERR_EN_MASK       (0x2U)
1034 #define DCM_GPR_DCMRWD5_INTM_0_ERR_EN_SHIFT      (1U)
1035 #define DCM_GPR_DCMRWD5_INTM_0_ERR_EN_WIDTH      (1U)
1036 #define DCM_GPR_DCMRWD5_INTM_0_ERR_EN(x)         (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_INTM_0_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD5_INTM_0_ERR_EN_MASK)
1037 
1038 #define DCM_GPR_DCMRWD5_INTM_1_ERR_EN_MASK       (0x4U)
1039 #define DCM_GPR_DCMRWD5_INTM_1_ERR_EN_SHIFT      (2U)
1040 #define DCM_GPR_DCMRWD5_INTM_1_ERR_EN_WIDTH      (1U)
1041 #define DCM_GPR_DCMRWD5_INTM_1_ERR_EN(x)         (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_INTM_1_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD5_INTM_1_ERR_EN_MASK)
1042 
1043 #define DCM_GPR_DCMRWD5_INTM_2_ERR_EN_MASK       (0x8U)
1044 #define DCM_GPR_DCMRWD5_INTM_2_ERR_EN_SHIFT      (3U)
1045 #define DCM_GPR_DCMRWD5_INTM_2_ERR_EN_WIDTH      (1U)
1046 #define DCM_GPR_DCMRWD5_INTM_2_ERR_EN(x)         (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_INTM_2_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD5_INTM_2_ERR_EN_MASK)
1047 
1048 #define DCM_GPR_DCMRWD5_INTM_3_ERR_EN_MASK       (0x10U)
1049 #define DCM_GPR_DCMRWD5_INTM_3_ERR_EN_SHIFT      (4U)
1050 #define DCM_GPR_DCMRWD5_INTM_3_ERR_EN_WIDTH      (1U)
1051 #define DCM_GPR_DCMRWD5_INTM_3_ERR_EN(x)         (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_INTM_3_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD5_INTM_3_ERR_EN_MASK)
1052 
1053 #define DCM_GPR_DCMRWD5_SW_NCF_0_EN_MASK         (0x20U)
1054 #define DCM_GPR_DCMRWD5_SW_NCF_0_EN_SHIFT        (5U)
1055 #define DCM_GPR_DCMRWD5_SW_NCF_0_EN_WIDTH        (1U)
1056 #define DCM_GPR_DCMRWD5_SW_NCF_0_EN(x)           (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_SW_NCF_0_EN_SHIFT)) & DCM_GPR_DCMRWD5_SW_NCF_0_EN_MASK)
1057 
1058 #define DCM_GPR_DCMRWD5_SW_NCF_1_EN_MASK         (0x40U)
1059 #define DCM_GPR_DCMRWD5_SW_NCF_1_EN_SHIFT        (6U)
1060 #define DCM_GPR_DCMRWD5_SW_NCF_1_EN_WIDTH        (1U)
1061 #define DCM_GPR_DCMRWD5_SW_NCF_1_EN(x)           (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_SW_NCF_1_EN_SHIFT)) & DCM_GPR_DCMRWD5_SW_NCF_1_EN_MASK)
1062 
1063 #define DCM_GPR_DCMRWD5_SW_NCF_2_EN_MASK         (0x80U)
1064 #define DCM_GPR_DCMRWD5_SW_NCF_2_EN_SHIFT        (7U)
1065 #define DCM_GPR_DCMRWD5_SW_NCF_2_EN_WIDTH        (1U)
1066 #define DCM_GPR_DCMRWD5_SW_NCF_2_EN(x)           (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_SW_NCF_2_EN_SHIFT)) & DCM_GPR_DCMRWD5_SW_NCF_2_EN_MASK)
1067 
1068 #define DCM_GPR_DCMRWD5_SW_NCF_3_EN_MASK         (0x100U)
1069 #define DCM_GPR_DCMRWD5_SW_NCF_3_EN_SHIFT        (8U)
1070 #define DCM_GPR_DCMRWD5_SW_NCF_3_EN_WIDTH        (1U)
1071 #define DCM_GPR_DCMRWD5_SW_NCF_3_EN(x)           (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_SW_NCF_3_EN_SHIFT)) & DCM_GPR_DCMRWD5_SW_NCF_3_EN_MASK)
1072 
1073 #define DCM_GPR_DCMRWD5_STCU_NCF_EN_MASK         (0x200U)
1074 #define DCM_GPR_DCMRWD5_STCU_NCF_EN_SHIFT        (9U)
1075 #define DCM_GPR_DCMRWD5_STCU_NCF_EN_WIDTH        (1U)
1076 #define DCM_GPR_DCMRWD5_STCU_NCF_EN(x)           (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_STCU_NCF_EN_SHIFT)) & DCM_GPR_DCMRWD5_STCU_NCF_EN_MASK)
1077 
1078 #define DCM_GPR_DCMRWD5_MBIST_ACTIVATION_ERR_EN_MASK (0x400U)
1079 #define DCM_GPR_DCMRWD5_MBIST_ACTIVATION_ERR_EN_SHIFT (10U)
1080 #define DCM_GPR_DCMRWD5_MBIST_ACTIVATION_ERR_EN_WIDTH (1U)
1081 #define DCM_GPR_DCMRWD5_MBIST_ACTIVATION_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_MBIST_ACTIVATION_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD5_MBIST_ACTIVATION_ERR_EN_MASK)
1082 
1083 #define DCM_GPR_DCMRWD5_STCU_BIST_USER_CF_EN_MASK (0x800U)
1084 #define DCM_GPR_DCMRWD5_STCU_BIST_USER_CF_EN_SHIFT (11U)
1085 #define DCM_GPR_DCMRWD5_STCU_BIST_USER_CF_EN_WIDTH (1U)
1086 #define DCM_GPR_DCMRWD5_STCU_BIST_USER_CF_EN(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_STCU_BIST_USER_CF_EN_SHIFT)) & DCM_GPR_DCMRWD5_STCU_BIST_USER_CF_EN_MASK)
1087 
1088 #define DCM_GPR_DCMRWD5_MTR_BUS_ERR_EN_MASK      (0x1000U)
1089 #define DCM_GPR_DCMRWD5_MTR_BUS_ERR_EN_SHIFT     (12U)
1090 #define DCM_GPR_DCMRWD5_MTR_BUS_ERR_EN_WIDTH     (1U)
1091 #define DCM_GPR_DCMRWD5_MTR_BUS_ERR_EN(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_MTR_BUS_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD5_MTR_BUS_ERR_EN_MASK)
1092 
1093 #define DCM_GPR_DCMRWD5_DEBUG_ACTIVATION_ERR_EN_MASK (0x2000U)
1094 #define DCM_GPR_DCMRWD5_DEBUG_ACTIVATION_ERR_EN_SHIFT (13U)
1095 #define DCM_GPR_DCMRWD5_DEBUG_ACTIVATION_ERR_EN_WIDTH (1U)
1096 #define DCM_GPR_DCMRWD5_DEBUG_ACTIVATION_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_DEBUG_ACTIVATION_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD5_DEBUG_ACTIVATION_ERR_EN_MASK)
1097 
1098 #define DCM_GPR_DCMRWD5_TCM_RDATA_EDC_ERR_EN_MASK (0x4000U)
1099 #define DCM_GPR_DCMRWD5_TCM_RDATA_EDC_ERR_EN_SHIFT (14U)
1100 #define DCM_GPR_DCMRWD5_TCM_RDATA_EDC_ERR_EN_WIDTH (1U)
1101 #define DCM_GPR_DCMRWD5_TCM_RDATA_EDC_ERR_EN(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_TCM_RDATA_EDC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD5_TCM_RDATA_EDC_ERR_EN_MASK)
1102 
1103 #define DCM_GPR_DCMRWD5_EMAC_RDATA_EDC_ERR_EN_MASK (0x8000U)
1104 #define DCM_GPR_DCMRWD5_EMAC_RDATA_EDC_ERR_EN_SHIFT (15U)
1105 #define DCM_GPR_DCMRWD5_EMAC_RDATA_EDC_ERR_EN_WIDTH (1U)
1106 #define DCM_GPR_DCMRWD5_EMAC_RDATA_EDC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_EMAC_RDATA_EDC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD5_EMAC_RDATA_EDC_ERR_EN_MASK)
1107 
1108 #define DCM_GPR_DCMRWD5_DMA_RDATA_EDC_ERR_EN_MASK (0x20000U)
1109 #define DCM_GPR_DCMRWD5_DMA_RDATA_EDC_ERR_EN_SHIFT (17U)
1110 #define DCM_GPR_DCMRWD5_DMA_RDATA_EDC_ERR_EN_WIDTH (1U)
1111 #define DCM_GPR_DCMRWD5_DMA_RDATA_EDC_ERR_EN(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_DMA_RDATA_EDC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD5_DMA_RDATA_EDC_ERR_EN_MASK)
1112 
1113 #define DCM_GPR_DCMRWD5_CM7_0_AHBP_RDATA_EDC_ERR_EN_MASK (0x100000U)
1114 #define DCM_GPR_DCMRWD5_CM7_0_AHBP_RDATA_EDC_ERR_EN_SHIFT (20U)
1115 #define DCM_GPR_DCMRWD5_CM7_0_AHBP_RDATA_EDC_ERR_EN_WIDTH (1U)
1116 #define DCM_GPR_DCMRWD5_CM7_0_AHBP_RDATA_EDC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_CM7_0_AHBP_RDATA_EDC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD5_CM7_0_AHBP_RDATA_EDC_ERR_EN_MASK)
1117 
1118 #define DCM_GPR_DCMRWD5_CM7_0_AHBM_RDATA_EDC_ERR_EN_MASK (0x200000U)
1119 #define DCM_GPR_DCMRWD5_CM7_0_AHBM_RDATA_EDC_ERR_EN_SHIFT (21U)
1120 #define DCM_GPR_DCMRWD5_CM7_0_AHBM_RDATA_EDC_ERR_EN_WIDTH (1U)
1121 #define DCM_GPR_DCMRWD5_CM7_0_AHBM_RDATA_EDC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_CM7_0_AHBM_RDATA_EDC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD5_CM7_0_AHBM_RDATA_EDC_ERR_EN_MASK)
1122 
1123 #define DCM_GPR_DCMRWD5_HSE_RDATA_EDC_ERR_EN_MASK (0x400000U)
1124 #define DCM_GPR_DCMRWD5_HSE_RDATA_EDC_ERR_EN_SHIFT (22U)
1125 #define DCM_GPR_DCMRWD5_HSE_RDATA_EDC_ERR_EN_WIDTH (1U)
1126 #define DCM_GPR_DCMRWD5_HSE_RDATA_EDC_ERR_EN(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD5_HSE_RDATA_EDC_ERR_EN_SHIFT)) & DCM_GPR_DCMRWD5_HSE_RDATA_EDC_ERR_EN_MASK)
1127 /*! @} */
1128 
1129 /*! @name DCMRWD6 - Read Write GPR On Destructive Reset Register */
1130 /*! @{ */
1131 
1132 #define DCM_GPR_DCMRWD6_EDMA_DBG_DIS_CM7_0_MASK  (0x1U)
1133 #define DCM_GPR_DCMRWD6_EDMA_DBG_DIS_CM7_0_SHIFT (0U)
1134 #define DCM_GPR_DCMRWD6_EDMA_DBG_DIS_CM7_0_WIDTH (1U)
1135 #define DCM_GPR_DCMRWD6_EDMA_DBG_DIS_CM7_0(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_EDMA_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_EDMA_DBG_DIS_CM7_0_MASK)
1136 
1137 #define DCM_GPR_DCMRWD6_FCCU_DBG_DIS_CM7_0_MASK  (0x2U)
1138 #define DCM_GPR_DCMRWD6_FCCU_DBG_DIS_CM7_0_SHIFT (1U)
1139 #define DCM_GPR_DCMRWD6_FCCU_DBG_DIS_CM7_0_WIDTH (1U)
1140 #define DCM_GPR_DCMRWD6_FCCU_DBG_DIS_CM7_0(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_FCCU_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_FCCU_DBG_DIS_CM7_0_MASK)
1141 
1142 #define DCM_GPR_DCMRWD6_LCU0_DBG_DIS_CM7_0_MASK  (0x4U)
1143 #define DCM_GPR_DCMRWD6_LCU0_DBG_DIS_CM7_0_SHIFT (2U)
1144 #define DCM_GPR_DCMRWD6_LCU0_DBG_DIS_CM7_0_WIDTH (1U)
1145 #define DCM_GPR_DCMRWD6_LCU0_DBG_DIS_CM7_0(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_LCU0_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_LCU0_DBG_DIS_CM7_0_MASK)
1146 
1147 #define DCM_GPR_DCMRWD6_LCU1_DBG_DIS_CM7_0_MASK  (0x8U)
1148 #define DCM_GPR_DCMRWD6_LCU1_DBG_DIS_CM7_0_SHIFT (3U)
1149 #define DCM_GPR_DCMRWD6_LCU1_DBG_DIS_CM7_0_WIDTH (1U)
1150 #define DCM_GPR_DCMRWD6_LCU1_DBG_DIS_CM7_0(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_LCU1_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_LCU1_DBG_DIS_CM7_0_MASK)
1151 
1152 #define DCM_GPR_DCMRWD6_EMIOS0_DBG_DIS_CM7_0_MASK (0x10U)
1153 #define DCM_GPR_DCMRWD6_EMIOS0_DBG_DIS_CM7_0_SHIFT (4U)
1154 #define DCM_GPR_DCMRWD6_EMIOS0_DBG_DIS_CM7_0_WIDTH (1U)
1155 #define DCM_GPR_DCMRWD6_EMIOS0_DBG_DIS_CM7_0(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_EMIOS0_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_EMIOS0_DBG_DIS_CM7_0_MASK)
1156 
1157 #define DCM_GPR_DCMRWD6_EMIOS1_DBG_DIS_CM7_0_MASK (0x20U)
1158 #define DCM_GPR_DCMRWD6_EMIOS1_DBG_DIS_CM7_0_SHIFT (5U)
1159 #define DCM_GPR_DCMRWD6_EMIOS1_DBG_DIS_CM7_0_WIDTH (1U)
1160 #define DCM_GPR_DCMRWD6_EMIOS1_DBG_DIS_CM7_0(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_EMIOS1_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_EMIOS1_DBG_DIS_CM7_0_MASK)
1161 
1162 #define DCM_GPR_DCMRWD6_EMIOS2_DBG_DIS_CM7_0_MASK (0x40U)
1163 #define DCM_GPR_DCMRWD6_EMIOS2_DBG_DIS_CM7_0_SHIFT (6U)
1164 #define DCM_GPR_DCMRWD6_EMIOS2_DBG_DIS_CM7_0_WIDTH (1U)
1165 #define DCM_GPR_DCMRWD6_EMIOS2_DBG_DIS_CM7_0(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_EMIOS2_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_EMIOS2_DBG_DIS_CM7_0_MASK)
1166 
1167 #define DCM_GPR_DCMRWD6_RTC_DBG_DIS_CM7_0_MASK   (0x80U)
1168 #define DCM_GPR_DCMRWD6_RTC_DBG_DIS_CM7_0_SHIFT  (7U)
1169 #define DCM_GPR_DCMRWD6_RTC_DBG_DIS_CM7_0_WIDTH  (1U)
1170 #define DCM_GPR_DCMRWD6_RTC_DBG_DIS_CM7_0(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_RTC_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_RTC_DBG_DIS_CM7_0_MASK)
1171 
1172 #define DCM_GPR_DCMRWD6_SWT0_DBG_DIS_CM7_0_MASK  (0x100U)
1173 #define DCM_GPR_DCMRWD6_SWT0_DBG_DIS_CM7_0_SHIFT (8U)
1174 #define DCM_GPR_DCMRWD6_SWT0_DBG_DIS_CM7_0_WIDTH (1U)
1175 #define DCM_GPR_DCMRWD6_SWT0_DBG_DIS_CM7_0(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_SWT0_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_SWT0_DBG_DIS_CM7_0_MASK)
1176 
1177 #define DCM_GPR_DCMRWD6_SWT1_DBG_DIS_CM7_0_MASK  (0x200U)
1178 #define DCM_GPR_DCMRWD6_SWT1_DBG_DIS_CM7_0_SHIFT (9U)
1179 #define DCM_GPR_DCMRWD6_SWT1_DBG_DIS_CM7_0_WIDTH (1U)
1180 #define DCM_GPR_DCMRWD6_SWT1_DBG_DIS_CM7_0(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_SWT1_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_SWT1_DBG_DIS_CM7_0_MASK)
1181 
1182 #define DCM_GPR_DCMRWD6_STM0_DBG_DIS_CM7_0_MASK  (0x400U)
1183 #define DCM_GPR_DCMRWD6_STM0_DBG_DIS_CM7_0_SHIFT (10U)
1184 #define DCM_GPR_DCMRWD6_STM0_DBG_DIS_CM7_0_WIDTH (1U)
1185 #define DCM_GPR_DCMRWD6_STM0_DBG_DIS_CM7_0(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_STM0_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_STM0_DBG_DIS_CM7_0_MASK)
1186 
1187 #define DCM_GPR_DCMRWD6_STM1_DBG_DIS_CM7_0_MASK  (0x800U)
1188 #define DCM_GPR_DCMRWD6_STM1_DBG_DIS_CM7_0_SHIFT (11U)
1189 #define DCM_GPR_DCMRWD6_STM1_DBG_DIS_CM7_0_WIDTH (1U)
1190 #define DCM_GPR_DCMRWD6_STM1_DBG_DIS_CM7_0(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_STM1_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_STM1_DBG_DIS_CM7_0_MASK)
1191 
1192 #define DCM_GPR_DCMRWD6_PIT0_DBG_DIS_CM7_0_MASK  (0x1000U)
1193 #define DCM_GPR_DCMRWD6_PIT0_DBG_DIS_CM7_0_SHIFT (12U)
1194 #define DCM_GPR_DCMRWD6_PIT0_DBG_DIS_CM7_0_WIDTH (1U)
1195 #define DCM_GPR_DCMRWD6_PIT0_DBG_DIS_CM7_0(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_PIT0_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_PIT0_DBG_DIS_CM7_0_MASK)
1196 
1197 #define DCM_GPR_DCMRWD6_PIT1_DBG_DIS_CM7_0_MASK  (0x2000U)
1198 #define DCM_GPR_DCMRWD6_PIT1_DBG_DIS_CM7_0_SHIFT (13U)
1199 #define DCM_GPR_DCMRWD6_PIT1_DBG_DIS_CM7_0_WIDTH (1U)
1200 #define DCM_GPR_DCMRWD6_PIT1_DBG_DIS_CM7_0(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_PIT1_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_PIT1_DBG_DIS_CM7_0_MASK)
1201 
1202 #define DCM_GPR_DCMRWD6_PIT2_DBG_DIS_CM7_0_MASK  (0x4000U)
1203 #define DCM_GPR_DCMRWD6_PIT2_DBG_DIS_CM7_0_SHIFT (14U)
1204 #define DCM_GPR_DCMRWD6_PIT2_DBG_DIS_CM7_0_WIDTH (1U)
1205 #define DCM_GPR_DCMRWD6_PIT2_DBG_DIS_CM7_0(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_PIT2_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_PIT2_DBG_DIS_CM7_0_MASK)
1206 
1207 #define DCM_GPR_DCMRWD6_LPSPI0_DBG_DIS_CM7_0_MASK (0x8000U)
1208 #define DCM_GPR_DCMRWD6_LPSPI0_DBG_DIS_CM7_0_SHIFT (15U)
1209 #define DCM_GPR_DCMRWD6_LPSPI0_DBG_DIS_CM7_0_WIDTH (1U)
1210 #define DCM_GPR_DCMRWD6_LPSPI0_DBG_DIS_CM7_0(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_LPSPI0_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_LPSPI0_DBG_DIS_CM7_0_MASK)
1211 
1212 #define DCM_GPR_DCMRWD6_LPSPI1_DBG_DIS_CM7_0_MASK (0x10000U)
1213 #define DCM_GPR_DCMRWD6_LPSPI1_DBG_DIS_CM7_0_SHIFT (16U)
1214 #define DCM_GPR_DCMRWD6_LPSPI1_DBG_DIS_CM7_0_WIDTH (1U)
1215 #define DCM_GPR_DCMRWD6_LPSPI1_DBG_DIS_CM7_0(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_LPSPI1_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_LPSPI1_DBG_DIS_CM7_0_MASK)
1216 
1217 #define DCM_GPR_DCMRWD6_LPSPI2_DBG_DIS_CM7_0_MASK (0x20000U)
1218 #define DCM_GPR_DCMRWD6_LPSPI2_DBG_DIS_CM7_0_SHIFT (17U)
1219 #define DCM_GPR_DCMRWD6_LPSPI2_DBG_DIS_CM7_0_WIDTH (1U)
1220 #define DCM_GPR_DCMRWD6_LPSPI2_DBG_DIS_CM7_0(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_LPSPI2_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_LPSPI2_DBG_DIS_CM7_0_MASK)
1221 
1222 #define DCM_GPR_DCMRWD6_LPSPI3_DBG_DIS_CM7_0_MASK (0x40000U)
1223 #define DCM_GPR_DCMRWD6_LPSPI3_DBG_DIS_CM7_0_SHIFT (18U)
1224 #define DCM_GPR_DCMRWD6_LPSPI3_DBG_DIS_CM7_0_WIDTH (1U)
1225 #define DCM_GPR_DCMRWD6_LPSPI3_DBG_DIS_CM7_0(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_LPSPI3_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_LPSPI3_DBG_DIS_CM7_0_MASK)
1226 
1227 #define DCM_GPR_DCMRWD6_LPSPI4_DBG_DIS_CM7_0_MASK (0x80000U)
1228 #define DCM_GPR_DCMRWD6_LPSPI4_DBG_DIS_CM7_0_SHIFT (19U)
1229 #define DCM_GPR_DCMRWD6_LPSPI4_DBG_DIS_CM7_0_WIDTH (1U)
1230 #define DCM_GPR_DCMRWD6_LPSPI4_DBG_DIS_CM7_0(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_LPSPI4_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_LPSPI4_DBG_DIS_CM7_0_MASK)
1231 
1232 #define DCM_GPR_DCMRWD6_LPSPI5_DBG_DIS_CM7_0_MASK (0x100000U)
1233 #define DCM_GPR_DCMRWD6_LPSPI5_DBG_DIS_CM7_0_SHIFT (20U)
1234 #define DCM_GPR_DCMRWD6_LPSPI5_DBG_DIS_CM7_0_WIDTH (1U)
1235 #define DCM_GPR_DCMRWD6_LPSPI5_DBG_DIS_CM7_0(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_LPSPI5_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_LPSPI5_DBG_DIS_CM7_0_MASK)
1236 
1237 #define DCM_GPR_DCMRWD6_LPI2C0_DBG_DIS_CM7_0_MASK (0x200000U)
1238 #define DCM_GPR_DCMRWD6_LPI2C0_DBG_DIS_CM7_0_SHIFT (21U)
1239 #define DCM_GPR_DCMRWD6_LPI2C0_DBG_DIS_CM7_0_WIDTH (1U)
1240 #define DCM_GPR_DCMRWD6_LPI2C0_DBG_DIS_CM7_0(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_LPI2C0_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_LPI2C0_DBG_DIS_CM7_0_MASK)
1241 
1242 #define DCM_GPR_DCMRWD6_LPI2C1_DBG_DIS_CM7_0_MASK (0x400000U)
1243 #define DCM_GPR_DCMRWD6_LPI2C1_DBG_DIS_CM7_0_SHIFT (22U)
1244 #define DCM_GPR_DCMRWD6_LPI2C1_DBG_DIS_CM7_0_WIDTH (1U)
1245 #define DCM_GPR_DCMRWD6_LPI2C1_DBG_DIS_CM7_0(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_LPI2C1_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_LPI2C1_DBG_DIS_CM7_0_MASK)
1246 
1247 #define DCM_GPR_DCMRWD6_FLEXIO_DBG_DIS_CM7_0_MASK (0x800000U)
1248 #define DCM_GPR_DCMRWD6_FLEXIO_DBG_DIS_CM7_0_SHIFT (23U)
1249 #define DCM_GPR_DCMRWD6_FLEXIO_DBG_DIS_CM7_0_WIDTH (1U)
1250 #define DCM_GPR_DCMRWD6_FLEXIO_DBG_DIS_CM7_0(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_FLEXIO_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_FLEXIO_DBG_DIS_CM7_0_MASK)
1251 
1252 #define DCM_GPR_DCMRWD6_FLEXCAN0_DBG_DIS_CM7_0_MASK (0x1000000U)
1253 #define DCM_GPR_DCMRWD6_FLEXCAN0_DBG_DIS_CM7_0_SHIFT (24U)
1254 #define DCM_GPR_DCMRWD6_FLEXCAN0_DBG_DIS_CM7_0_WIDTH (1U)
1255 #define DCM_GPR_DCMRWD6_FLEXCAN0_DBG_DIS_CM7_0(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_FLEXCAN0_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_FLEXCAN0_DBG_DIS_CM7_0_MASK)
1256 
1257 #define DCM_GPR_DCMRWD6_FLEXCAN1_DBG_DIS_CM7_0_MASK (0x2000000U)
1258 #define DCM_GPR_DCMRWD6_FLEXCAN1_DBG_DIS_CM7_0_SHIFT (25U)
1259 #define DCM_GPR_DCMRWD6_FLEXCAN1_DBG_DIS_CM7_0_WIDTH (1U)
1260 #define DCM_GPR_DCMRWD6_FLEXCAN1_DBG_DIS_CM7_0(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_FLEXCAN1_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_FLEXCAN1_DBG_DIS_CM7_0_MASK)
1261 
1262 #define DCM_GPR_DCMRWD6_FLEXCAN2_DBG_DIS_CM7_0_MASK (0x4000000U)
1263 #define DCM_GPR_DCMRWD6_FLEXCAN2_DBG_DIS_CM7_0_SHIFT (26U)
1264 #define DCM_GPR_DCMRWD6_FLEXCAN2_DBG_DIS_CM7_0_WIDTH (1U)
1265 #define DCM_GPR_DCMRWD6_FLEXCAN2_DBG_DIS_CM7_0(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_FLEXCAN2_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_FLEXCAN2_DBG_DIS_CM7_0_MASK)
1266 
1267 #define DCM_GPR_DCMRWD6_FLEXCAN3_DBG_DIS_CM7_0_MASK (0x8000000U)
1268 #define DCM_GPR_DCMRWD6_FLEXCAN3_DBG_DIS_CM7_0_SHIFT (27U)
1269 #define DCM_GPR_DCMRWD6_FLEXCAN3_DBG_DIS_CM7_0_WIDTH (1U)
1270 #define DCM_GPR_DCMRWD6_FLEXCAN3_DBG_DIS_CM7_0(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_FLEXCAN3_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_FLEXCAN3_DBG_DIS_CM7_0_MASK)
1271 
1272 #define DCM_GPR_DCMRWD6_FLEXCAN4_DBG_DIS_CM7_0_MASK (0x10000000U)
1273 #define DCM_GPR_DCMRWD6_FLEXCAN4_DBG_DIS_CM7_0_SHIFT (28U)
1274 #define DCM_GPR_DCMRWD6_FLEXCAN4_DBG_DIS_CM7_0_WIDTH (1U)
1275 #define DCM_GPR_DCMRWD6_FLEXCAN4_DBG_DIS_CM7_0(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_FLEXCAN4_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_FLEXCAN4_DBG_DIS_CM7_0_MASK)
1276 
1277 #define DCM_GPR_DCMRWD6_FLEXCAN5_DBG_DIS_CM7_0_MASK (0x20000000U)
1278 #define DCM_GPR_DCMRWD6_FLEXCAN5_DBG_DIS_CM7_0_SHIFT (29U)
1279 #define DCM_GPR_DCMRWD6_FLEXCAN5_DBG_DIS_CM7_0_WIDTH (1U)
1280 #define DCM_GPR_DCMRWD6_FLEXCAN5_DBG_DIS_CM7_0(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_FLEXCAN5_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_FLEXCAN5_DBG_DIS_CM7_0_MASK)
1281 
1282 #define DCM_GPR_DCMRWD6_SAI0_DBG_DIS_CM7_0_MASK  (0x40000000U)
1283 #define DCM_GPR_DCMRWD6_SAI0_DBG_DIS_CM7_0_SHIFT (30U)
1284 #define DCM_GPR_DCMRWD6_SAI0_DBG_DIS_CM7_0_WIDTH (1U)
1285 #define DCM_GPR_DCMRWD6_SAI0_DBG_DIS_CM7_0(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_SAI0_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_SAI0_DBG_DIS_CM7_0_MASK)
1286 
1287 #define DCM_GPR_DCMRWD6_SAI1_DBG_DIS_CM7_0_MASK  (0x80000000U)
1288 #define DCM_GPR_DCMRWD6_SAI1_DBG_DIS_CM7_0_SHIFT (31U)
1289 #define DCM_GPR_DCMRWD6_SAI1_DBG_DIS_CM7_0_WIDTH (1U)
1290 #define DCM_GPR_DCMRWD6_SAI1_DBG_DIS_CM7_0(x)    (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWD6_SAI1_DBG_DIS_CM7_0_SHIFT)) & DCM_GPR_DCMRWD6_SAI1_DBG_DIS_CM7_0_MASK)
1291 /*! @} */
1292 
1293 /*! @name DCMRWF1 - Read Write GPR On Functional Reset Register */
1294 /*! @{ */
1295 
1296 #define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_SEL_MASK   (0x1U)
1297 #define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_SEL_SHIFT  (0U)
1298 #define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_SEL_WIDTH  (1U)
1299 #define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_SEL(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_CAN_TIMESTAMP_SEL_SHIFT)) & DCM_GPR_DCMRWF1_CAN_TIMESTAMP_SEL_MASK)
1300 
1301 #define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_EN_MASK    (0x2U)
1302 #define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_EN_SHIFT   (1U)
1303 #define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_EN_WIDTH   (1U)
1304 #define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_EN(x)      (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_CAN_TIMESTAMP_EN_SHIFT)) & DCM_GPR_DCMRWF1_CAN_TIMESTAMP_EN_MASK)
1305 
1306 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF0_MASK        (0x4U)
1307 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF0_SHIFT       (2U)
1308 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF0_WIDTH       (1U)
1309 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF0(x)          (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_FCCU_SW_NCF0_SHIFT)) & DCM_GPR_DCMRWF1_FCCU_SW_NCF0_MASK)
1310 
1311 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF1_MASK        (0x8U)
1312 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF1_SHIFT       (3U)
1313 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF1_WIDTH       (1U)
1314 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF1(x)          (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_FCCU_SW_NCF1_SHIFT)) & DCM_GPR_DCMRWF1_FCCU_SW_NCF1_MASK)
1315 
1316 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF2_MASK        (0x10U)
1317 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF2_SHIFT       (4U)
1318 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF2_WIDTH       (1U)
1319 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF2(x)          (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_FCCU_SW_NCF2_SHIFT)) & DCM_GPR_DCMRWF1_FCCU_SW_NCF2_MASK)
1320 
1321 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF3_MASK        (0x20U)
1322 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF3_SHIFT       (5U)
1323 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF3_WIDTH       (1U)
1324 #define DCM_GPR_DCMRWF1_FCCU_SW_NCF3(x)          (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_FCCU_SW_NCF3_SHIFT)) & DCM_GPR_DCMRWF1_FCCU_SW_NCF3_MASK)
1325 
1326 #define DCM_GPR_DCMRWF1_EMAC_CONF_SEL_MASK       (0xC0U)
1327 #define DCM_GPR_DCMRWF1_EMAC_CONF_SEL_SHIFT      (6U)
1328 #define DCM_GPR_DCMRWF1_EMAC_CONF_SEL_WIDTH      (2U)
1329 #define DCM_GPR_DCMRWF1_EMAC_CONF_SEL(x)         (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_EMAC_CONF_SEL_SHIFT)) & DCM_GPR_DCMRWF1_EMAC_CONF_SEL_MASK)
1330 
1331 #define DCM_GPR_DCMRWF1_VDD_HV_B_IO_CTRL_LATCH_MASK (0x8000U)
1332 #define DCM_GPR_DCMRWF1_VDD_HV_B_IO_CTRL_LATCH_SHIFT (15U)
1333 #define DCM_GPR_DCMRWF1_VDD_HV_B_IO_CTRL_LATCH_WIDTH (1U)
1334 #define DCM_GPR_DCMRWF1_VDD_HV_B_IO_CTRL_LATCH(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_VDD_HV_B_IO_CTRL_LATCH_SHIFT)) & DCM_GPR_DCMRWF1_VDD_HV_B_IO_CTRL_LATCH_MASK)
1335 
1336 #define DCM_GPR_DCMRWF1_STANDBY_IO_CONFIG_MASK   (0x10000U)
1337 #define DCM_GPR_DCMRWF1_STANDBY_IO_CONFIG_SHIFT  (16U)
1338 #define DCM_GPR_DCMRWF1_STANDBY_IO_CONFIG_WIDTH  (1U)
1339 #define DCM_GPR_DCMRWF1_STANDBY_IO_CONFIG(x)     (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_STANDBY_IO_CONFIG_SHIFT)) & DCM_GPR_DCMRWF1_STANDBY_IO_CONFIG_MASK)
1340 
1341 #define DCM_GPR_DCMRWF1_SUPPLY_MON_EN_MASK       (0x100000U)
1342 #define DCM_GPR_DCMRWF1_SUPPLY_MON_EN_SHIFT      (20U)
1343 #define DCM_GPR_DCMRWF1_SUPPLY_MON_EN_WIDTH      (1U)
1344 #define DCM_GPR_DCMRWF1_SUPPLY_MON_EN(x)         (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_SUPPLY_MON_EN_SHIFT)) & DCM_GPR_DCMRWF1_SUPPLY_MON_EN_MASK)
1345 
1346 #define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_MASK      (0xE00000U)
1347 #define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT     (21U)
1348 #define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_WIDTH     (3U)
1349 #define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT)) & DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_MASK)
1350 
1351 #define DCM_GPR_DCMRWF1_VSS_LV_ANMUX_EN_MASK     (0x1000000U)
1352 #define DCM_GPR_DCMRWF1_VSS_LV_ANMUX_EN_SHIFT    (24U)
1353 #define DCM_GPR_DCMRWF1_VSS_LV_ANMUX_EN_WIDTH    (1U)
1354 #define DCM_GPR_DCMRWF1_VSS_LV_ANMUX_EN(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_VSS_LV_ANMUX_EN_SHIFT)) & DCM_GPR_DCMRWF1_VSS_LV_ANMUX_EN_MASK)
1355 
1356 #define DCM_GPR_DCMRWF1_VDD_HV_A_VLT_DVDR_EN_MASK (0x2000000U)
1357 #define DCM_GPR_DCMRWF1_VDD_HV_A_VLT_DVDR_EN_SHIFT (25U)
1358 #define DCM_GPR_DCMRWF1_VDD_HV_A_VLT_DVDR_EN_WIDTH (1U)
1359 #define DCM_GPR_DCMRWF1_VDD_HV_A_VLT_DVDR_EN(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_VDD_HV_A_VLT_DVDR_EN_SHIFT)) & DCM_GPR_DCMRWF1_VDD_HV_A_VLT_DVDR_EN_MASK)
1360 
1361 #define DCM_GPR_DCMRWF1_VDD_HV_B_VLT_DVDR_EN_MASK (0x4000000U)
1362 #define DCM_GPR_DCMRWF1_VDD_HV_B_VLT_DVDR_EN_SHIFT (26U)
1363 #define DCM_GPR_DCMRWF1_VDD_HV_B_VLT_DVDR_EN_WIDTH (1U)
1364 #define DCM_GPR_DCMRWF1_VDD_HV_B_VLT_DVDR_EN(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_VDD_HV_B_VLT_DVDR_EN_SHIFT)) & DCM_GPR_DCMRWF1_VDD_HV_B_VLT_DVDR_EN_MASK)
1365 
1366 #define DCM_GPR_DCMRWF1_VDD_1_5_VLT_DVDR_EN_MASK (0x8000000U)
1367 #define DCM_GPR_DCMRWF1_VDD_1_5_VLT_DVDR_EN_SHIFT (27U)
1368 #define DCM_GPR_DCMRWF1_VDD_1_5_VLT_DVDR_EN_WIDTH (1U)
1369 #define DCM_GPR_DCMRWF1_VDD_1_5_VLT_DVDR_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_VDD_1_5_VLT_DVDR_EN_SHIFT)) & DCM_GPR_DCMRWF1_VDD_1_5_VLT_DVDR_EN_MASK)
1370 /*! @} */
1371 
1372 /*! @name DCMRWF2 - Read Write GPR On Functional Reset Register */
1373 /*! @{ */
1374 
1375 #define DCM_GPR_DCMRWF2_DCM_SCAN_BYP_STDBY_EXT_MASK (0x8U)
1376 #define DCM_GPR_DCMRWF2_DCM_SCAN_BYP_STDBY_EXT_SHIFT (3U)
1377 #define DCM_GPR_DCMRWF2_DCM_SCAN_BYP_STDBY_EXT_WIDTH (1U)
1378 #define DCM_GPR_DCMRWF2_DCM_SCAN_BYP_STDBY_EXT(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF2_DCM_SCAN_BYP_STDBY_EXT_SHIFT)) & DCM_GPR_DCMRWF2_DCM_SCAN_BYP_STDBY_EXT_MASK)
1379 
1380 #define DCM_GPR_DCMRWF2_FIRC_TRIM_BYP_STDBY_EXT_MASK (0x10U)
1381 #define DCM_GPR_DCMRWF2_FIRC_TRIM_BYP_STDBY_EXT_SHIFT (4U)
1382 #define DCM_GPR_DCMRWF2_FIRC_TRIM_BYP_STDBY_EXT_WIDTH (1U)
1383 #define DCM_GPR_DCMRWF2_FIRC_TRIM_BYP_STDBY_EXT(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF2_FIRC_TRIM_BYP_STDBY_EXT_SHIFT)) & DCM_GPR_DCMRWF2_FIRC_TRIM_BYP_STDBY_EXT_MASK)
1384 
1385 #define DCM_GPR_DCMRWF2_PMC_TRIM_RGM_DCF_BYP_STDBY_EXT_MASK (0x20U)
1386 #define DCM_GPR_DCMRWF2_PMC_TRIM_RGM_DCF_BYP_STDBY_EXT_SHIFT (5U)
1387 #define DCM_GPR_DCMRWF2_PMC_TRIM_RGM_DCF_BYP_STDBY_EXT_WIDTH (1U)
1388 #define DCM_GPR_DCMRWF2_PMC_TRIM_RGM_DCF_BYP_STDBY_EXT(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF2_PMC_TRIM_RGM_DCF_BYP_STDBY_EXT_SHIFT)) & DCM_GPR_DCMRWF2_PMC_TRIM_RGM_DCF_BYP_STDBY_EXT_MASK)
1389 
1390 #define DCM_GPR_DCMRWF2_SIRC_TRIM_BYP_STDBY_EXT_MASK (0x40U)
1391 #define DCM_GPR_DCMRWF2_SIRC_TRIM_BYP_STDBY_EXT_SHIFT (6U)
1392 #define DCM_GPR_DCMRWF2_SIRC_TRIM_BYP_STDBY_EXT_WIDTH (1U)
1393 #define DCM_GPR_DCMRWF2_SIRC_TRIM_BYP_STDBY_EXT(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF2_SIRC_TRIM_BYP_STDBY_EXT_SHIFT)) & DCM_GPR_DCMRWF2_SIRC_TRIM_BYP_STDBY_EXT_MASK)
1394 
1395 #define DCM_GPR_DCMRWF2_HSE_GSKT_BYPASS_MASK     (0x10000U)
1396 #define DCM_GPR_DCMRWF2_HSE_GSKT_BYPASS_SHIFT    (16U)
1397 #define DCM_GPR_DCMRWF2_HSE_GSKT_BYPASS_WIDTH    (1U)
1398 #define DCM_GPR_DCMRWF2_HSE_GSKT_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF2_HSE_GSKT_BYPASS_SHIFT)) & DCM_GPR_DCMRWF2_HSE_GSKT_BYPASS_MASK)
1399 /*! @} */
1400 
1401 /*! @name DCMRWF4 - Read Write GPR On Functional Reset Register */
1402 /*! @{ */
1403 
1404 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S8_MASK (0x2U)
1405 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S8_SHIFT (1U)
1406 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S8_WIDTH (1U)
1407 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S8(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S8_SHIFT)) & DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S8_MASK)
1408 
1409 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S9_MASK (0x4U)
1410 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S9_SHIFT (2U)
1411 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S9_WIDTH (1U)
1412 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S9(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S9_SHIFT)) & DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S9_MASK)
1413 
1414 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S14_MASK (0x8U)
1415 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S14_SHIFT (3U)
1416 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S14_WIDTH (1U)
1417 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S14(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S14_SHIFT)) & DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S14_MASK)
1418 
1419 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S15_MASK (0x10U)
1420 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S15_SHIFT (4U)
1421 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S15_WIDTH (1U)
1422 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S15(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S15_SHIFT)) & DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S15_MASK)
1423 
1424 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S22_MASK (0x20U)
1425 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S22_SHIFT (5U)
1426 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S22_WIDTH (1U)
1427 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S22(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S22_SHIFT)) & DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S22_MASK)
1428 
1429 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S23_MASK (0x40U)
1430 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S23_SHIFT (6U)
1431 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S23_WIDTH (1U)
1432 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S23(x)  (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S23_SHIFT)) & DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S23_MASK)
1433 
1434 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S8_MASK (0x200U)
1435 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S8_SHIFT (9U)
1436 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S8_WIDTH (1U)
1437 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S8(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S8_SHIFT)) & DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S8_MASK)
1438 
1439 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S9_MASK (0x400U)
1440 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S9_SHIFT (10U)
1441 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S9_WIDTH (1U)
1442 #define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S9(x)   (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S9_SHIFT)) & DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S9_MASK)
1443 
1444 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN0_BYP_MASK (0x2000U)
1445 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN0_BYP_SHIFT (13U)
1446 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN0_BYP_WIDTH (1U)
1447 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN0_BYP(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN0_BYP_SHIFT)) & DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN0_BYP_MASK)
1448 
1449 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN1_BYP_MASK (0x4000U)
1450 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN1_BYP_SHIFT (14U)
1451 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN1_BYP_WIDTH (1U)
1452 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN1_BYP(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN1_BYP_SHIFT)) & DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN1_BYP_MASK)
1453 
1454 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN2_BYP_MASK (0x8000U)
1455 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN2_BYP_SHIFT (15U)
1456 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN2_BYP_WIDTH (1U)
1457 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN2_BYP(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN2_BYP_SHIFT)) & DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN2_BYP_MASK)
1458 
1459 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN3_BYP_MASK (0x10000U)
1460 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN3_BYP_SHIFT (16U)
1461 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN3_BYP_WIDTH (1U)
1462 #define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN3_BYP(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN3_BYP_SHIFT)) & DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN3_BYP_MASK)
1463 
1464 #define DCM_GPR_DCMRWF4_CM7_0_CPUWAIT_MASK       (0x20000U)
1465 #define DCM_GPR_DCMRWF4_CM7_0_CPUWAIT_SHIFT      (17U)
1466 #define DCM_GPR_DCMRWF4_CM7_0_CPUWAIT_WIDTH      (1U)
1467 #define DCM_GPR_DCMRWF4_CM7_0_CPUWAIT(x)         (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF4_CM7_0_CPUWAIT_SHIFT)) & DCM_GPR_DCMRWF4_CM7_0_CPUWAIT_MASK)
1468 /*! @} */
1469 
1470 /*! @name DCMRWF5 - Read Write GPR On Functional Reset Register */
1471 /*! @{ */
1472 
1473 #define DCM_GPR_DCMRWF5_BOOT_MODE_MASK           (0x1U)
1474 #define DCM_GPR_DCMRWF5_BOOT_MODE_SHIFT          (0U)
1475 #define DCM_GPR_DCMRWF5_BOOT_MODE_WIDTH          (1U)
1476 #define DCM_GPR_DCMRWF5_BOOT_MODE(x)             (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF5_BOOT_MODE_SHIFT)) & DCM_GPR_DCMRWF5_BOOT_MODE_MASK)
1477 
1478 #define DCM_GPR_DCMRWF5_BOOT_ADDRESS_MASK        (0xFFFFFFFEU)
1479 #define DCM_GPR_DCMRWF5_BOOT_ADDRESS_SHIFT       (1U)
1480 #define DCM_GPR_DCMRWF5_BOOT_ADDRESS_WIDTH       (31U)
1481 #define DCM_GPR_DCMRWF5_BOOT_ADDRESS(x)          (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF5_BOOT_ADDRESS_SHIFT)) & DCM_GPR_DCMRWF5_BOOT_ADDRESS_MASK)
1482 /*! @} */
1483 
1484 /*! @name DCMROPP1 - Read Only GPR On PMCPOR Reset */
1485 /*! @{ */
1486 
1487 #define DCM_GPR_DCMROPP1_POR_WDG_STAT0_MASK      (0x1U)
1488 #define DCM_GPR_DCMROPP1_POR_WDG_STAT0_SHIFT     (0U)
1489 #define DCM_GPR_DCMROPP1_POR_WDG_STAT0_WIDTH     (1U)
1490 #define DCM_GPR_DCMROPP1_POR_WDG_STAT0(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP1_POR_WDG_STAT0_SHIFT)) & DCM_GPR_DCMROPP1_POR_WDG_STAT0_MASK)
1491 
1492 #define DCM_GPR_DCMROPP1_POR_WDG_STAT1_MASK      (0x2U)
1493 #define DCM_GPR_DCMROPP1_POR_WDG_STAT1_SHIFT     (1U)
1494 #define DCM_GPR_DCMROPP1_POR_WDG_STAT1_WIDTH     (1U)
1495 #define DCM_GPR_DCMROPP1_POR_WDG_STAT1(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP1_POR_WDG_STAT1_SHIFT)) & DCM_GPR_DCMROPP1_POR_WDG_STAT1_MASK)
1496 
1497 #define DCM_GPR_DCMROPP1_POR_WDG_STAT2_MASK      (0x4U)
1498 #define DCM_GPR_DCMROPP1_POR_WDG_STAT2_SHIFT     (2U)
1499 #define DCM_GPR_DCMROPP1_POR_WDG_STAT2_WIDTH     (1U)
1500 #define DCM_GPR_DCMROPP1_POR_WDG_STAT2(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP1_POR_WDG_STAT2_SHIFT)) & DCM_GPR_DCMROPP1_POR_WDG_STAT2_MASK)
1501 
1502 #define DCM_GPR_DCMROPP1_POR_WDG_STAT3_MASK      (0x8U)
1503 #define DCM_GPR_DCMROPP1_POR_WDG_STAT3_SHIFT     (3U)
1504 #define DCM_GPR_DCMROPP1_POR_WDG_STAT3_WIDTH     (1U)
1505 #define DCM_GPR_DCMROPP1_POR_WDG_STAT3(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP1_POR_WDG_STAT3_SHIFT)) & DCM_GPR_DCMROPP1_POR_WDG_STAT3_MASK)
1506 
1507 #define DCM_GPR_DCMROPP1_POR_WDG_STAT4_MASK      (0x10U)
1508 #define DCM_GPR_DCMROPP1_POR_WDG_STAT4_SHIFT     (4U)
1509 #define DCM_GPR_DCMROPP1_POR_WDG_STAT4_WIDTH     (1U)
1510 #define DCM_GPR_DCMROPP1_POR_WDG_STAT4(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP1_POR_WDG_STAT4_SHIFT)) & DCM_GPR_DCMROPP1_POR_WDG_STAT4_MASK)
1511 
1512 #define DCM_GPR_DCMROPP1_POR_WDG_STAT5_MASK      (0x20U)
1513 #define DCM_GPR_DCMROPP1_POR_WDG_STAT5_SHIFT     (5U)
1514 #define DCM_GPR_DCMROPP1_POR_WDG_STAT5_WIDTH     (1U)
1515 #define DCM_GPR_DCMROPP1_POR_WDG_STAT5(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP1_POR_WDG_STAT5_SHIFT)) & DCM_GPR_DCMROPP1_POR_WDG_STAT5_MASK)
1516 
1517 #define DCM_GPR_DCMROPP1_POR_WDG_STAT6_MASK      (0x40U)
1518 #define DCM_GPR_DCMROPP1_POR_WDG_STAT6_SHIFT     (6U)
1519 #define DCM_GPR_DCMROPP1_POR_WDG_STAT6_WIDTH     (1U)
1520 #define DCM_GPR_DCMROPP1_POR_WDG_STAT6(x)        (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP1_POR_WDG_STAT6_SHIFT)) & DCM_GPR_DCMROPP1_POR_WDG_STAT6_MASK)
1521 
1522 #define DCM_GPR_DCMROPP1_POR_WDG_STAT10_MASK     (0x400U)
1523 #define DCM_GPR_DCMROPP1_POR_WDG_STAT10_SHIFT    (10U)
1524 #define DCM_GPR_DCMROPP1_POR_WDG_STAT10_WIDTH    (1U)
1525 #define DCM_GPR_DCMROPP1_POR_WDG_STAT10(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP1_POR_WDG_STAT10_SHIFT)) & DCM_GPR_DCMROPP1_POR_WDG_STAT10_MASK)
1526 
1527 #define DCM_GPR_DCMROPP1_POR_WDG_STAT11_MASK     (0x800U)
1528 #define DCM_GPR_DCMROPP1_POR_WDG_STAT11_SHIFT    (11U)
1529 #define DCM_GPR_DCMROPP1_POR_WDG_STAT11_WIDTH    (1U)
1530 #define DCM_GPR_DCMROPP1_POR_WDG_STAT11(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP1_POR_WDG_STAT11_SHIFT)) & DCM_GPR_DCMROPP1_POR_WDG_STAT11_MASK)
1531 
1532 #define DCM_GPR_DCMROPP1_POR_WDG_STAT14_MASK     (0x4000U)
1533 #define DCM_GPR_DCMROPP1_POR_WDG_STAT14_SHIFT    (14U)
1534 #define DCM_GPR_DCMROPP1_POR_WDG_STAT14_WIDTH    (1U)
1535 #define DCM_GPR_DCMROPP1_POR_WDG_STAT14(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP1_POR_WDG_STAT14_SHIFT)) & DCM_GPR_DCMROPP1_POR_WDG_STAT14_MASK)
1536 
1537 #define DCM_GPR_DCMROPP1_POR_WDG_STAT17_MASK     (0x20000U)
1538 #define DCM_GPR_DCMROPP1_POR_WDG_STAT17_SHIFT    (17U)
1539 #define DCM_GPR_DCMROPP1_POR_WDG_STAT17_WIDTH    (1U)
1540 #define DCM_GPR_DCMROPP1_POR_WDG_STAT17(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP1_POR_WDG_STAT17_SHIFT)) & DCM_GPR_DCMROPP1_POR_WDG_STAT17_MASK)
1541 
1542 #define DCM_GPR_DCMROPP1_POR_WDG_STAT20_MASK     (0x100000U)
1543 #define DCM_GPR_DCMROPP1_POR_WDG_STAT20_SHIFT    (20U)
1544 #define DCM_GPR_DCMROPP1_POR_WDG_STAT20_WIDTH    (1U)
1545 #define DCM_GPR_DCMROPP1_POR_WDG_STAT20(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP1_POR_WDG_STAT20_SHIFT)) & DCM_GPR_DCMROPP1_POR_WDG_STAT20_MASK)
1546 
1547 #define DCM_GPR_DCMROPP1_POR_WDG_STAT29_MASK     (0x20000000U)
1548 #define DCM_GPR_DCMROPP1_POR_WDG_STAT29_SHIFT    (29U)
1549 #define DCM_GPR_DCMROPP1_POR_WDG_STAT29_WIDTH    (1U)
1550 #define DCM_GPR_DCMROPP1_POR_WDG_STAT29(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP1_POR_WDG_STAT29_SHIFT)) & DCM_GPR_DCMROPP1_POR_WDG_STAT29_MASK)
1551 
1552 #define DCM_GPR_DCMROPP1_POR_WDG_STAT30_MASK     (0x40000000U)
1553 #define DCM_GPR_DCMROPP1_POR_WDG_STAT30_SHIFT    (30U)
1554 #define DCM_GPR_DCMROPP1_POR_WDG_STAT30_WIDTH    (1U)
1555 #define DCM_GPR_DCMROPP1_POR_WDG_STAT30(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP1_POR_WDG_STAT30_SHIFT)) & DCM_GPR_DCMROPP1_POR_WDG_STAT30_MASK)
1556 
1557 #define DCM_GPR_DCMROPP1_POR_WDG_STAT31_MASK     (0x80000000U)
1558 #define DCM_GPR_DCMROPP1_POR_WDG_STAT31_SHIFT    (31U)
1559 #define DCM_GPR_DCMROPP1_POR_WDG_STAT31_WIDTH    (1U)
1560 #define DCM_GPR_DCMROPP1_POR_WDG_STAT31(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP1_POR_WDG_STAT31_SHIFT)) & DCM_GPR_DCMROPP1_POR_WDG_STAT31_MASK)
1561 /*! @} */
1562 
1563 /*! @name DCMROPP2 - Read Only GPR On PMCPOR Reset */
1564 /*! @{ */
1565 
1566 #define DCM_GPR_DCMROPP2_POR_WDG_STAT32_MASK     (0x1U)
1567 #define DCM_GPR_DCMROPP2_POR_WDG_STAT32_SHIFT    (0U)
1568 #define DCM_GPR_DCMROPP2_POR_WDG_STAT32_WIDTH    (1U)
1569 #define DCM_GPR_DCMROPP2_POR_WDG_STAT32(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT32_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT32_MASK)
1570 
1571 #define DCM_GPR_DCMROPP2_POR_WDG_STAT33_MASK     (0x2U)
1572 #define DCM_GPR_DCMROPP2_POR_WDG_STAT33_SHIFT    (1U)
1573 #define DCM_GPR_DCMROPP2_POR_WDG_STAT33_WIDTH    (1U)
1574 #define DCM_GPR_DCMROPP2_POR_WDG_STAT33(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT33_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT33_MASK)
1575 
1576 #define DCM_GPR_DCMROPP2_POR_WDG_STAT34_MASK     (0x4U)
1577 #define DCM_GPR_DCMROPP2_POR_WDG_STAT34_SHIFT    (2U)
1578 #define DCM_GPR_DCMROPP2_POR_WDG_STAT34_WIDTH    (1U)
1579 #define DCM_GPR_DCMROPP2_POR_WDG_STAT34(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT34_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT34_MASK)
1580 
1581 #define DCM_GPR_DCMROPP2_POR_WDG_STAT35_MASK     (0x8U)
1582 #define DCM_GPR_DCMROPP2_POR_WDG_STAT35_SHIFT    (3U)
1583 #define DCM_GPR_DCMROPP2_POR_WDG_STAT35_WIDTH    (1U)
1584 #define DCM_GPR_DCMROPP2_POR_WDG_STAT35(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT35_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT35_MASK)
1585 
1586 #define DCM_GPR_DCMROPP2_POR_WDG_STAT36_MASK     (0x10U)
1587 #define DCM_GPR_DCMROPP2_POR_WDG_STAT36_SHIFT    (4U)
1588 #define DCM_GPR_DCMROPP2_POR_WDG_STAT36_WIDTH    (1U)
1589 #define DCM_GPR_DCMROPP2_POR_WDG_STAT36(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT36_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT36_MASK)
1590 
1591 #define DCM_GPR_DCMROPP2_POR_WDG_STAT37_MASK     (0x20U)
1592 #define DCM_GPR_DCMROPP2_POR_WDG_STAT37_SHIFT    (5U)
1593 #define DCM_GPR_DCMROPP2_POR_WDG_STAT37_WIDTH    (1U)
1594 #define DCM_GPR_DCMROPP2_POR_WDG_STAT37(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT37_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT37_MASK)
1595 
1596 #define DCM_GPR_DCMROPP2_POR_WDG_STAT38_MASK     (0x40U)
1597 #define DCM_GPR_DCMROPP2_POR_WDG_STAT38_SHIFT    (6U)
1598 #define DCM_GPR_DCMROPP2_POR_WDG_STAT38_WIDTH    (1U)
1599 #define DCM_GPR_DCMROPP2_POR_WDG_STAT38(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT38_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT38_MASK)
1600 
1601 #define DCM_GPR_DCMROPP2_POR_WDG_STAT39_MASK     (0x80U)
1602 #define DCM_GPR_DCMROPP2_POR_WDG_STAT39_SHIFT    (7U)
1603 #define DCM_GPR_DCMROPP2_POR_WDG_STAT39_WIDTH    (1U)
1604 #define DCM_GPR_DCMROPP2_POR_WDG_STAT39(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT39_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT39_MASK)
1605 
1606 #define DCM_GPR_DCMROPP2_POR_WDG_STAT40_MASK     (0x100U)
1607 #define DCM_GPR_DCMROPP2_POR_WDG_STAT40_SHIFT    (8U)
1608 #define DCM_GPR_DCMROPP2_POR_WDG_STAT40_WIDTH    (1U)
1609 #define DCM_GPR_DCMROPP2_POR_WDG_STAT40(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT40_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT40_MASK)
1610 
1611 #define DCM_GPR_DCMROPP2_POR_WDG_STAT41_MASK     (0x200U)
1612 #define DCM_GPR_DCMROPP2_POR_WDG_STAT41_SHIFT    (9U)
1613 #define DCM_GPR_DCMROPP2_POR_WDG_STAT41_WIDTH    (1U)
1614 #define DCM_GPR_DCMROPP2_POR_WDG_STAT41(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT41_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT41_MASK)
1615 
1616 #define DCM_GPR_DCMROPP2_POR_WDG_STAT42_MASK     (0x400U)
1617 #define DCM_GPR_DCMROPP2_POR_WDG_STAT42_SHIFT    (10U)
1618 #define DCM_GPR_DCMROPP2_POR_WDG_STAT42_WIDTH    (1U)
1619 #define DCM_GPR_DCMROPP2_POR_WDG_STAT42(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT42_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT42_MASK)
1620 
1621 #define DCM_GPR_DCMROPP2_POR_WDG_STAT43_MASK     (0x800U)
1622 #define DCM_GPR_DCMROPP2_POR_WDG_STAT43_SHIFT    (11U)
1623 #define DCM_GPR_DCMROPP2_POR_WDG_STAT43_WIDTH    (1U)
1624 #define DCM_GPR_DCMROPP2_POR_WDG_STAT43(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT43_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT43_MASK)
1625 
1626 #define DCM_GPR_DCMROPP2_POR_WDG_STAT44_MASK     (0x1000U)
1627 #define DCM_GPR_DCMROPP2_POR_WDG_STAT44_SHIFT    (12U)
1628 #define DCM_GPR_DCMROPP2_POR_WDG_STAT44_WIDTH    (1U)
1629 #define DCM_GPR_DCMROPP2_POR_WDG_STAT44(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT44_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT44_MASK)
1630 
1631 #define DCM_GPR_DCMROPP2_POR_WDG_STAT45_MASK     (0x2000U)
1632 #define DCM_GPR_DCMROPP2_POR_WDG_STAT45_SHIFT    (13U)
1633 #define DCM_GPR_DCMROPP2_POR_WDG_STAT45_WIDTH    (1U)
1634 #define DCM_GPR_DCMROPP2_POR_WDG_STAT45(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT45_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT45_MASK)
1635 
1636 #define DCM_GPR_DCMROPP2_POR_WDG_STAT46_MASK     (0x4000U)
1637 #define DCM_GPR_DCMROPP2_POR_WDG_STAT46_SHIFT    (14U)
1638 #define DCM_GPR_DCMROPP2_POR_WDG_STAT46_WIDTH    (1U)
1639 #define DCM_GPR_DCMROPP2_POR_WDG_STAT46(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT46_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT46_MASK)
1640 
1641 #define DCM_GPR_DCMROPP2_POR_WDG_STAT47_MASK     (0x8000U)
1642 #define DCM_GPR_DCMROPP2_POR_WDG_STAT47_SHIFT    (15U)
1643 #define DCM_GPR_DCMROPP2_POR_WDG_STAT47_WIDTH    (1U)
1644 #define DCM_GPR_DCMROPP2_POR_WDG_STAT47(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT47_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT47_MASK)
1645 
1646 #define DCM_GPR_DCMROPP2_POR_WDG_STAT48_MASK     (0x10000U)
1647 #define DCM_GPR_DCMROPP2_POR_WDG_STAT48_SHIFT    (16U)
1648 #define DCM_GPR_DCMROPP2_POR_WDG_STAT48_WIDTH    (1U)
1649 #define DCM_GPR_DCMROPP2_POR_WDG_STAT48(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT48_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT48_MASK)
1650 
1651 #define DCM_GPR_DCMROPP2_POR_WDG_STAT49_MASK     (0x20000U)
1652 #define DCM_GPR_DCMROPP2_POR_WDG_STAT49_SHIFT    (17U)
1653 #define DCM_GPR_DCMROPP2_POR_WDG_STAT49_WIDTH    (1U)
1654 #define DCM_GPR_DCMROPP2_POR_WDG_STAT49(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT49_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT49_MASK)
1655 
1656 #define DCM_GPR_DCMROPP2_POR_WDG_STAT50_MASK     (0x40000U)
1657 #define DCM_GPR_DCMROPP2_POR_WDG_STAT50_SHIFT    (18U)
1658 #define DCM_GPR_DCMROPP2_POR_WDG_STAT50_WIDTH    (1U)
1659 #define DCM_GPR_DCMROPP2_POR_WDG_STAT50(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT50_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT50_MASK)
1660 
1661 #define DCM_GPR_DCMROPP2_POR_WDG_STAT51_MASK     (0x80000U)
1662 #define DCM_GPR_DCMROPP2_POR_WDG_STAT51_SHIFT    (19U)
1663 #define DCM_GPR_DCMROPP2_POR_WDG_STAT51_WIDTH    (1U)
1664 #define DCM_GPR_DCMROPP2_POR_WDG_STAT51(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT51_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT51_MASK)
1665 
1666 #define DCM_GPR_DCMROPP2_POR_WDG_STAT52_MASK     (0x100000U)
1667 #define DCM_GPR_DCMROPP2_POR_WDG_STAT52_SHIFT    (20U)
1668 #define DCM_GPR_DCMROPP2_POR_WDG_STAT52_WIDTH    (1U)
1669 #define DCM_GPR_DCMROPP2_POR_WDG_STAT52(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT52_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT52_MASK)
1670 
1671 #define DCM_GPR_DCMROPP2_POR_WDG_STAT53_MASK     (0x200000U)
1672 #define DCM_GPR_DCMROPP2_POR_WDG_STAT53_SHIFT    (21U)
1673 #define DCM_GPR_DCMROPP2_POR_WDG_STAT53_WIDTH    (1U)
1674 #define DCM_GPR_DCMROPP2_POR_WDG_STAT53(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT53_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT53_MASK)
1675 
1676 #define DCM_GPR_DCMROPP2_POR_WDG_STAT54_MASK     (0x400000U)
1677 #define DCM_GPR_DCMROPP2_POR_WDG_STAT54_SHIFT    (22U)
1678 #define DCM_GPR_DCMROPP2_POR_WDG_STAT54_WIDTH    (1U)
1679 #define DCM_GPR_DCMROPP2_POR_WDG_STAT54(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT54_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT54_MASK)
1680 
1681 #define DCM_GPR_DCMROPP2_POR_WDG_STAT55_MASK     (0x800000U)
1682 #define DCM_GPR_DCMROPP2_POR_WDG_STAT55_SHIFT    (23U)
1683 #define DCM_GPR_DCMROPP2_POR_WDG_STAT55_WIDTH    (1U)
1684 #define DCM_GPR_DCMROPP2_POR_WDG_STAT55(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT55_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT55_MASK)
1685 
1686 #define DCM_GPR_DCMROPP2_POR_WDG_STAT56_MASK     (0x1000000U)
1687 #define DCM_GPR_DCMROPP2_POR_WDG_STAT56_SHIFT    (24U)
1688 #define DCM_GPR_DCMROPP2_POR_WDG_STAT56_WIDTH    (1U)
1689 #define DCM_GPR_DCMROPP2_POR_WDG_STAT56(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT56_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT56_MASK)
1690 
1691 #define DCM_GPR_DCMROPP2_POR_WDG_STAT57_MASK     (0x2000000U)
1692 #define DCM_GPR_DCMROPP2_POR_WDG_STAT57_SHIFT    (25U)
1693 #define DCM_GPR_DCMROPP2_POR_WDG_STAT57_WIDTH    (1U)
1694 #define DCM_GPR_DCMROPP2_POR_WDG_STAT57(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT57_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT57_MASK)
1695 
1696 #define DCM_GPR_DCMROPP2_POR_WDG_STAT58_MASK     (0x4000000U)
1697 #define DCM_GPR_DCMROPP2_POR_WDG_STAT58_SHIFT    (26U)
1698 #define DCM_GPR_DCMROPP2_POR_WDG_STAT58_WIDTH    (1U)
1699 #define DCM_GPR_DCMROPP2_POR_WDG_STAT58(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT58_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT58_MASK)
1700 
1701 #define DCM_GPR_DCMROPP2_POR_WDG_STAT59_MASK     (0x8000000U)
1702 #define DCM_GPR_DCMROPP2_POR_WDG_STAT59_SHIFT    (27U)
1703 #define DCM_GPR_DCMROPP2_POR_WDG_STAT59_WIDTH    (1U)
1704 #define DCM_GPR_DCMROPP2_POR_WDG_STAT59(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT59_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT59_MASK)
1705 
1706 #define DCM_GPR_DCMROPP2_POR_WDG_STAT60_MASK     (0x10000000U)
1707 #define DCM_GPR_DCMROPP2_POR_WDG_STAT60_SHIFT    (28U)
1708 #define DCM_GPR_DCMROPP2_POR_WDG_STAT60_WIDTH    (1U)
1709 #define DCM_GPR_DCMROPP2_POR_WDG_STAT60(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT60_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT60_MASK)
1710 
1711 #define DCM_GPR_DCMROPP2_POR_WDG_STAT61_MASK     (0x20000000U)
1712 #define DCM_GPR_DCMROPP2_POR_WDG_STAT61_SHIFT    (29U)
1713 #define DCM_GPR_DCMROPP2_POR_WDG_STAT61_WIDTH    (1U)
1714 #define DCM_GPR_DCMROPP2_POR_WDG_STAT61(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT61_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT61_MASK)
1715 
1716 #define DCM_GPR_DCMROPP2_POR_WDG_STAT62_MASK     (0x40000000U)
1717 #define DCM_GPR_DCMROPP2_POR_WDG_STAT62_SHIFT    (30U)
1718 #define DCM_GPR_DCMROPP2_POR_WDG_STAT62_WIDTH    (1U)
1719 #define DCM_GPR_DCMROPP2_POR_WDG_STAT62(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT62_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT62_MASK)
1720 
1721 #define DCM_GPR_DCMROPP2_POR_WDG_STAT63_MASK     (0x80000000U)
1722 #define DCM_GPR_DCMROPP2_POR_WDG_STAT63_SHIFT    (31U)
1723 #define DCM_GPR_DCMROPP2_POR_WDG_STAT63_WIDTH    (1U)
1724 #define DCM_GPR_DCMROPP2_POR_WDG_STAT63(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP2_POR_WDG_STAT63_SHIFT)) & DCM_GPR_DCMROPP2_POR_WDG_STAT63_MASK)
1725 /*! @} */
1726 
1727 /*! @name DCMROPP3 - Read Only GPR On PMCPOR Reset */
1728 /*! @{ */
1729 
1730 #define DCM_GPR_DCMROPP3_POR_WDG_STAT64_MASK     (0x1U)
1731 #define DCM_GPR_DCMROPP3_POR_WDG_STAT64_SHIFT    (0U)
1732 #define DCM_GPR_DCMROPP3_POR_WDG_STAT64_WIDTH    (1U)
1733 #define DCM_GPR_DCMROPP3_POR_WDG_STAT64(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT64_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT64_MASK)
1734 
1735 #define DCM_GPR_DCMROPP3_POR_WDG_STAT65_MASK     (0x2U)
1736 #define DCM_GPR_DCMROPP3_POR_WDG_STAT65_SHIFT    (1U)
1737 #define DCM_GPR_DCMROPP3_POR_WDG_STAT65_WIDTH    (1U)
1738 #define DCM_GPR_DCMROPP3_POR_WDG_STAT65(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT65_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT65_MASK)
1739 
1740 #define DCM_GPR_DCMROPP3_POR_WDG_STAT66_MASK     (0x4U)
1741 #define DCM_GPR_DCMROPP3_POR_WDG_STAT66_SHIFT    (2U)
1742 #define DCM_GPR_DCMROPP3_POR_WDG_STAT66_WIDTH    (1U)
1743 #define DCM_GPR_DCMROPP3_POR_WDG_STAT66(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT66_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT66_MASK)
1744 
1745 #define DCM_GPR_DCMROPP3_POR_WDG_STAT67_MASK     (0x8U)
1746 #define DCM_GPR_DCMROPP3_POR_WDG_STAT67_SHIFT    (3U)
1747 #define DCM_GPR_DCMROPP3_POR_WDG_STAT67_WIDTH    (1U)
1748 #define DCM_GPR_DCMROPP3_POR_WDG_STAT67(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT67_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT67_MASK)
1749 
1750 #define DCM_GPR_DCMROPP3_POR_WDG_STAT68_MASK     (0x10U)
1751 #define DCM_GPR_DCMROPP3_POR_WDG_STAT68_SHIFT    (4U)
1752 #define DCM_GPR_DCMROPP3_POR_WDG_STAT68_WIDTH    (1U)
1753 #define DCM_GPR_DCMROPP3_POR_WDG_STAT68(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT68_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT68_MASK)
1754 
1755 #define DCM_GPR_DCMROPP3_POR_WDG_STAT69_MASK     (0x20U)
1756 #define DCM_GPR_DCMROPP3_POR_WDG_STAT69_SHIFT    (5U)
1757 #define DCM_GPR_DCMROPP3_POR_WDG_STAT69_WIDTH    (1U)
1758 #define DCM_GPR_DCMROPP3_POR_WDG_STAT69(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT69_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT69_MASK)
1759 
1760 #define DCM_GPR_DCMROPP3_POR_WDG_STAT70_MASK     (0x40U)
1761 #define DCM_GPR_DCMROPP3_POR_WDG_STAT70_SHIFT    (6U)
1762 #define DCM_GPR_DCMROPP3_POR_WDG_STAT70_WIDTH    (1U)
1763 #define DCM_GPR_DCMROPP3_POR_WDG_STAT70(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT70_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT70_MASK)
1764 
1765 #define DCM_GPR_DCMROPP3_POR_WDG_STAT71_MASK     (0x80U)
1766 #define DCM_GPR_DCMROPP3_POR_WDG_STAT71_SHIFT    (7U)
1767 #define DCM_GPR_DCMROPP3_POR_WDG_STAT71_WIDTH    (1U)
1768 #define DCM_GPR_DCMROPP3_POR_WDG_STAT71(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT71_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT71_MASK)
1769 
1770 #define DCM_GPR_DCMROPP3_POR_WDG_STAT72_MASK     (0x100U)
1771 #define DCM_GPR_DCMROPP3_POR_WDG_STAT72_SHIFT    (8U)
1772 #define DCM_GPR_DCMROPP3_POR_WDG_STAT72_WIDTH    (1U)
1773 #define DCM_GPR_DCMROPP3_POR_WDG_STAT72(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT72_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT72_MASK)
1774 
1775 #define DCM_GPR_DCMROPP3_POR_WDG_STAT73_MASK     (0x200U)
1776 #define DCM_GPR_DCMROPP3_POR_WDG_STAT73_SHIFT    (9U)
1777 #define DCM_GPR_DCMROPP3_POR_WDG_STAT73_WIDTH    (1U)
1778 #define DCM_GPR_DCMROPP3_POR_WDG_STAT73(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT73_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT73_MASK)
1779 
1780 #define DCM_GPR_DCMROPP3_POR_WDG_STAT74_MASK     (0x400U)
1781 #define DCM_GPR_DCMROPP3_POR_WDG_STAT74_SHIFT    (10U)
1782 #define DCM_GPR_DCMROPP3_POR_WDG_STAT74_WIDTH    (1U)
1783 #define DCM_GPR_DCMROPP3_POR_WDG_STAT74(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT74_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT74_MASK)
1784 
1785 #define DCM_GPR_DCMROPP3_POR_WDG_STAT75_MASK     (0x800U)
1786 #define DCM_GPR_DCMROPP3_POR_WDG_STAT75_SHIFT    (11U)
1787 #define DCM_GPR_DCMROPP3_POR_WDG_STAT75_WIDTH    (1U)
1788 #define DCM_GPR_DCMROPP3_POR_WDG_STAT75(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT75_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT75_MASK)
1789 
1790 #define DCM_GPR_DCMROPP3_POR_WDG_STAT76_MASK     (0x1000U)
1791 #define DCM_GPR_DCMROPP3_POR_WDG_STAT76_SHIFT    (12U)
1792 #define DCM_GPR_DCMROPP3_POR_WDG_STAT76_WIDTH    (1U)
1793 #define DCM_GPR_DCMROPP3_POR_WDG_STAT76(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT76_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT76_MASK)
1794 
1795 #define DCM_GPR_DCMROPP3_POR_WDG_STAT77_MASK     (0x2000U)
1796 #define DCM_GPR_DCMROPP3_POR_WDG_STAT77_SHIFT    (13U)
1797 #define DCM_GPR_DCMROPP3_POR_WDG_STAT77_WIDTH    (1U)
1798 #define DCM_GPR_DCMROPP3_POR_WDG_STAT77(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT77_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT77_MASK)
1799 
1800 #define DCM_GPR_DCMROPP3_POR_WDG_STAT78_MASK     (0x4000U)
1801 #define DCM_GPR_DCMROPP3_POR_WDG_STAT78_SHIFT    (14U)
1802 #define DCM_GPR_DCMROPP3_POR_WDG_STAT78_WIDTH    (1U)
1803 #define DCM_GPR_DCMROPP3_POR_WDG_STAT78(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT78_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT78_MASK)
1804 
1805 #define DCM_GPR_DCMROPP3_POR_WDG_STAT79_MASK     (0x8000U)
1806 #define DCM_GPR_DCMROPP3_POR_WDG_STAT79_SHIFT    (15U)
1807 #define DCM_GPR_DCMROPP3_POR_WDG_STAT79_WIDTH    (1U)
1808 #define DCM_GPR_DCMROPP3_POR_WDG_STAT79(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT79_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT79_MASK)
1809 
1810 #define DCM_GPR_DCMROPP3_POR_WDG_STAT80_MASK     (0x10000U)
1811 #define DCM_GPR_DCMROPP3_POR_WDG_STAT80_SHIFT    (16U)
1812 #define DCM_GPR_DCMROPP3_POR_WDG_STAT80_WIDTH    (1U)
1813 #define DCM_GPR_DCMROPP3_POR_WDG_STAT80(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT80_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT80_MASK)
1814 
1815 #define DCM_GPR_DCMROPP3_POR_WDG_STAT81_MASK     (0x20000U)
1816 #define DCM_GPR_DCMROPP3_POR_WDG_STAT81_SHIFT    (17U)
1817 #define DCM_GPR_DCMROPP3_POR_WDG_STAT81_WIDTH    (1U)
1818 #define DCM_GPR_DCMROPP3_POR_WDG_STAT81(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT81_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT81_MASK)
1819 
1820 #define DCM_GPR_DCMROPP3_POR_WDG_STAT82_MASK     (0x40000U)
1821 #define DCM_GPR_DCMROPP3_POR_WDG_STAT82_SHIFT    (18U)
1822 #define DCM_GPR_DCMROPP3_POR_WDG_STAT82_WIDTH    (1U)
1823 #define DCM_GPR_DCMROPP3_POR_WDG_STAT82(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT82_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT82_MASK)
1824 
1825 #define DCM_GPR_DCMROPP3_POR_WDG_STAT83_MASK     (0x80000U)
1826 #define DCM_GPR_DCMROPP3_POR_WDG_STAT83_SHIFT    (19U)
1827 #define DCM_GPR_DCMROPP3_POR_WDG_STAT83_WIDTH    (1U)
1828 #define DCM_GPR_DCMROPP3_POR_WDG_STAT83(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT83_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT83_MASK)
1829 
1830 #define DCM_GPR_DCMROPP3_POR_WDG_STAT84_MASK     (0x100000U)
1831 #define DCM_GPR_DCMROPP3_POR_WDG_STAT84_SHIFT    (20U)
1832 #define DCM_GPR_DCMROPP3_POR_WDG_STAT84_WIDTH    (1U)
1833 #define DCM_GPR_DCMROPP3_POR_WDG_STAT84(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT84_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT84_MASK)
1834 
1835 #define DCM_GPR_DCMROPP3_POR_WDG_STAT85_MASK     (0x200000U)
1836 #define DCM_GPR_DCMROPP3_POR_WDG_STAT85_SHIFT    (21U)
1837 #define DCM_GPR_DCMROPP3_POR_WDG_STAT85_WIDTH    (1U)
1838 #define DCM_GPR_DCMROPP3_POR_WDG_STAT85(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT85_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT85_MASK)
1839 
1840 #define DCM_GPR_DCMROPP3_POR_WDG_STAT86_MASK     (0x400000U)
1841 #define DCM_GPR_DCMROPP3_POR_WDG_STAT86_SHIFT    (22U)
1842 #define DCM_GPR_DCMROPP3_POR_WDG_STAT86_WIDTH    (1U)
1843 #define DCM_GPR_DCMROPP3_POR_WDG_STAT86(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT86_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT86_MASK)
1844 
1845 #define DCM_GPR_DCMROPP3_POR_WDG_STAT87_MASK     (0x800000U)
1846 #define DCM_GPR_DCMROPP3_POR_WDG_STAT87_SHIFT    (23U)
1847 #define DCM_GPR_DCMROPP3_POR_WDG_STAT87_WIDTH    (1U)
1848 #define DCM_GPR_DCMROPP3_POR_WDG_STAT87(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT87_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT87_MASK)
1849 
1850 #define DCM_GPR_DCMROPP3_POR_WDG_STAT88_MASK     (0x1000000U)
1851 #define DCM_GPR_DCMROPP3_POR_WDG_STAT88_SHIFT    (24U)
1852 #define DCM_GPR_DCMROPP3_POR_WDG_STAT88_WIDTH    (1U)
1853 #define DCM_GPR_DCMROPP3_POR_WDG_STAT88(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT88_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT88_MASK)
1854 
1855 #define DCM_GPR_DCMROPP3_POR_WDG_STAT89_MASK     (0x2000000U)
1856 #define DCM_GPR_DCMROPP3_POR_WDG_STAT89_SHIFT    (25U)
1857 #define DCM_GPR_DCMROPP3_POR_WDG_STAT89_WIDTH    (1U)
1858 #define DCM_GPR_DCMROPP3_POR_WDG_STAT89(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT89_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT89_MASK)
1859 
1860 #define DCM_GPR_DCMROPP3_POR_WDG_STAT90_MASK     (0x4000000U)
1861 #define DCM_GPR_DCMROPP3_POR_WDG_STAT90_SHIFT    (26U)
1862 #define DCM_GPR_DCMROPP3_POR_WDG_STAT90_WIDTH    (1U)
1863 #define DCM_GPR_DCMROPP3_POR_WDG_STAT90(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT90_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT90_MASK)
1864 
1865 #define DCM_GPR_DCMROPP3_POR_WDG_STAT91_MASK     (0x8000000U)
1866 #define DCM_GPR_DCMROPP3_POR_WDG_STAT91_SHIFT    (27U)
1867 #define DCM_GPR_DCMROPP3_POR_WDG_STAT91_WIDTH    (1U)
1868 #define DCM_GPR_DCMROPP3_POR_WDG_STAT91(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT91_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT91_MASK)
1869 
1870 #define DCM_GPR_DCMROPP3_POR_WDG_STAT92_MASK     (0x10000000U)
1871 #define DCM_GPR_DCMROPP3_POR_WDG_STAT92_SHIFT    (28U)
1872 #define DCM_GPR_DCMROPP3_POR_WDG_STAT92_WIDTH    (1U)
1873 #define DCM_GPR_DCMROPP3_POR_WDG_STAT92(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT92_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT92_MASK)
1874 
1875 #define DCM_GPR_DCMROPP3_POR_WDG_STAT93_MASK     (0x20000000U)
1876 #define DCM_GPR_DCMROPP3_POR_WDG_STAT93_SHIFT    (29U)
1877 #define DCM_GPR_DCMROPP3_POR_WDG_STAT93_WIDTH    (1U)
1878 #define DCM_GPR_DCMROPP3_POR_WDG_STAT93(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT93_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT93_MASK)
1879 
1880 #define DCM_GPR_DCMROPP3_POR_WDG_STAT94_MASK     (0x40000000U)
1881 #define DCM_GPR_DCMROPP3_POR_WDG_STAT94_SHIFT    (30U)
1882 #define DCM_GPR_DCMROPP3_POR_WDG_STAT94_WIDTH    (1U)
1883 #define DCM_GPR_DCMROPP3_POR_WDG_STAT94(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT94_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT94_MASK)
1884 
1885 #define DCM_GPR_DCMROPP3_POR_WDG_STAT95_MASK     (0x80000000U)
1886 #define DCM_GPR_DCMROPP3_POR_WDG_STAT95_SHIFT    (31U)
1887 #define DCM_GPR_DCMROPP3_POR_WDG_STAT95_WIDTH    (1U)
1888 #define DCM_GPR_DCMROPP3_POR_WDG_STAT95(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP3_POR_WDG_STAT95_SHIFT)) & DCM_GPR_DCMROPP3_POR_WDG_STAT95_MASK)
1889 /*! @} */
1890 
1891 /*! @name DCMROPP4 - Read Only GPR On PMCPOR Reset */
1892 /*! @{ */
1893 
1894 #define DCM_GPR_DCMROPP4_POR_WDG_STAT96_MASK     (0x1U)
1895 #define DCM_GPR_DCMROPP4_POR_WDG_STAT96_SHIFT    (0U)
1896 #define DCM_GPR_DCMROPP4_POR_WDG_STAT96_WIDTH    (1U)
1897 #define DCM_GPR_DCMROPP4_POR_WDG_STAT96(x)       (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMROPP4_POR_WDG_STAT96_SHIFT)) & DCM_GPR_DCMROPP4_POR_WDG_STAT96_MASK)
1898 /*! @} */
1899 
1900 /*!
1901  * @}
1902  */ /* end of group DCM_GPR_Register_Masks */
1903 
1904 /*!
1905  * @}
1906  */ /* end of group DCM_GPR_Peripheral_Access_Layer */
1907 
1908 #endif  /* #if !defined(S32K344_DCM_GPR_H_) */
1909