1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG24 DCDC register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG24_DCDC_H 31 #define EFR32MG24_DCDC_H 32 #define DCDC_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG24_DCDC DCDC 40 * @{ 41 * @brief EFR32MG24 DCDC Register Declaration. 42 *****************************************************************************/ 43 44 /** DCDC Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IPVERSION */ 47 __IOM uint32_t CTRL; /**< Control */ 48 __IOM uint32_t EM01CTRL0; /**< EM01 Control */ 49 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 50 __IOM uint32_t EM23CTRL0; /**< EM23 Control */ 51 uint32_t RESERVED1[3U]; /**< Reserved for future use */ 52 __IOM uint32_t PFMXCTRL; /**< PFMX Control Register */ 53 uint32_t RESERVED2[1U]; /**< Reserved for future use */ 54 __IOM uint32_t IF; /**< Interrupt Flags */ 55 __IOM uint32_t IEN; /**< Interrupt Enable */ 56 __IM uint32_t STATUS; /**< Status Register */ 57 __IM uint32_t SYNCBUSY; /**< Syncbusy Status Register */ 58 uint32_t RESERVED3[2U]; /**< Reserved for future use */ 59 __IOM uint32_t LOCK; /**< Lock Register */ 60 __IM uint32_t LOCKSTATUS; /**< Lock Status Register */ 61 uint32_t RESERVED4[2U]; /**< Reserved for future use */ 62 uint32_t RESERVED5[1U]; /**< Reserved for future use */ 63 uint32_t RESERVED6[7U]; /**< Reserved for future use */ 64 uint32_t RESERVED7[1U]; /**< Reserved for future use */ 65 uint32_t RESERVED8[7U]; /**< Reserved for future use */ 66 uint32_t RESERVED9[1U]; /**< Reserved for future use */ 67 uint32_t RESERVED10[987U]; /**< Reserved for future use */ 68 __IM uint32_t IPVERSION_SET; /**< IPVERSION */ 69 __IOM uint32_t CTRL_SET; /**< Control */ 70 __IOM uint32_t EM01CTRL0_SET; /**< EM01 Control */ 71 uint32_t RESERVED11[1U]; /**< Reserved for future use */ 72 __IOM uint32_t EM23CTRL0_SET; /**< EM23 Control */ 73 uint32_t RESERVED12[3U]; /**< Reserved for future use */ 74 __IOM uint32_t PFMXCTRL_SET; /**< PFMX Control Register */ 75 uint32_t RESERVED13[1U]; /**< Reserved for future use */ 76 __IOM uint32_t IF_SET; /**< Interrupt Flags */ 77 __IOM uint32_t IEN_SET; /**< Interrupt Enable */ 78 __IM uint32_t STATUS_SET; /**< Status Register */ 79 __IM uint32_t SYNCBUSY_SET; /**< Syncbusy Status Register */ 80 uint32_t RESERVED14[2U]; /**< Reserved for future use */ 81 __IOM uint32_t LOCK_SET; /**< Lock Register */ 82 __IM uint32_t LOCKSTATUS_SET; /**< Lock Status Register */ 83 uint32_t RESERVED15[2U]; /**< Reserved for future use */ 84 uint32_t RESERVED16[1U]; /**< Reserved for future use */ 85 uint32_t RESERVED17[7U]; /**< Reserved for future use */ 86 uint32_t RESERVED18[1U]; /**< Reserved for future use */ 87 uint32_t RESERVED19[7U]; /**< Reserved for future use */ 88 uint32_t RESERVED20[1U]; /**< Reserved for future use */ 89 uint32_t RESERVED21[987U]; /**< Reserved for future use */ 90 __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ 91 __IOM uint32_t CTRL_CLR; /**< Control */ 92 __IOM uint32_t EM01CTRL0_CLR; /**< EM01 Control */ 93 uint32_t RESERVED22[1U]; /**< Reserved for future use */ 94 __IOM uint32_t EM23CTRL0_CLR; /**< EM23 Control */ 95 uint32_t RESERVED23[3U]; /**< Reserved for future use */ 96 __IOM uint32_t PFMXCTRL_CLR; /**< PFMX Control Register */ 97 uint32_t RESERVED24[1U]; /**< Reserved for future use */ 98 __IOM uint32_t IF_CLR; /**< Interrupt Flags */ 99 __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ 100 __IM uint32_t STATUS_CLR; /**< Status Register */ 101 __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy Status Register */ 102 uint32_t RESERVED25[2U]; /**< Reserved for future use */ 103 __IOM uint32_t LOCK_CLR; /**< Lock Register */ 104 __IM uint32_t LOCKSTATUS_CLR; /**< Lock Status Register */ 105 uint32_t RESERVED26[2U]; /**< Reserved for future use */ 106 uint32_t RESERVED27[1U]; /**< Reserved for future use */ 107 uint32_t RESERVED28[7U]; /**< Reserved for future use */ 108 uint32_t RESERVED29[1U]; /**< Reserved for future use */ 109 uint32_t RESERVED30[7U]; /**< Reserved for future use */ 110 uint32_t RESERVED31[1U]; /**< Reserved for future use */ 111 uint32_t RESERVED32[987U]; /**< Reserved for future use */ 112 __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ 113 __IOM uint32_t CTRL_TGL; /**< Control */ 114 __IOM uint32_t EM01CTRL0_TGL; /**< EM01 Control */ 115 uint32_t RESERVED33[1U]; /**< Reserved for future use */ 116 __IOM uint32_t EM23CTRL0_TGL; /**< EM23 Control */ 117 uint32_t RESERVED34[3U]; /**< Reserved for future use */ 118 __IOM uint32_t PFMXCTRL_TGL; /**< PFMX Control Register */ 119 uint32_t RESERVED35[1U]; /**< Reserved for future use */ 120 __IOM uint32_t IF_TGL; /**< Interrupt Flags */ 121 __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ 122 __IM uint32_t STATUS_TGL; /**< Status Register */ 123 __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy Status Register */ 124 uint32_t RESERVED36[2U]; /**< Reserved for future use */ 125 __IOM uint32_t LOCK_TGL; /**< Lock Register */ 126 __IM uint32_t LOCKSTATUS_TGL; /**< Lock Status Register */ 127 uint32_t RESERVED37[2U]; /**< Reserved for future use */ 128 uint32_t RESERVED38[1U]; /**< Reserved for future use */ 129 uint32_t RESERVED39[7U]; /**< Reserved for future use */ 130 uint32_t RESERVED40[1U]; /**< Reserved for future use */ 131 uint32_t RESERVED41[7U]; /**< Reserved for future use */ 132 uint32_t RESERVED42[1U]; /**< Reserved for future use */ 133 } DCDC_TypeDef; 134 /** @} End of group EFR32MG24_DCDC */ 135 136 /**************************************************************************//** 137 * @addtogroup EFR32MG24_DCDC 138 * @{ 139 * @defgroup EFR32MG24_DCDC_BitFields DCDC Bit Fields 140 * @{ 141 *****************************************************************************/ 142 143 /* Bit fields for DCDC IPVERSION */ 144 #define _DCDC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for DCDC_IPVERSION */ 145 #define _DCDC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DCDC_IPVERSION */ 146 #define _DCDC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DCDC_IPVERSION */ 147 #define _DCDC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_IPVERSION */ 148 #define _DCDC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for DCDC_IPVERSION */ 149 #define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ 150 151 /* Bit fields for DCDC CTRL */ 152 #define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ 153 #define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ 154 #define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ 155 #define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ 156 #define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ 157 #define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ 158 #define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ 159 #define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ 160 #define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ 161 #define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ 162 #define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ 163 #define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ 164 #define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ 165 #define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ 166 #define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ 167 168 /* Bit fields for DCDC EM01CTRL0 */ 169 #define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ 170 #define _DCDC_EM01CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM01CTRL0 */ 171 #define _DCDC_EM01CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ 172 #define _DCDC_EM01CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ 173 #define _DCDC_EM01CTRL0_IPKVAL_DEFAULT 0x00000009UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ 174 #define _DCDC_EM01CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM01CTRL0 */ 175 #define _DCDC_EM01CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM01CTRL0 */ 176 #define _DCDC_EM01CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM01CTRL0 */ 177 #define _DCDC_EM01CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM01CTRL0 */ 178 #define _DCDC_EM01CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM01CTRL0 */ 179 #define _DCDC_EM01CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM01CTRL0 */ 180 #define _DCDC_EM01CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM01CTRL0 */ 181 #define DCDC_EM01CTRL0_IPKVAL_DEFAULT (_DCDC_EM01CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ 182 #define DCDC_EM01CTRL0_IPKVAL_Load36mA (_DCDC_EM01CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM01CTRL0 */ 183 #define DCDC_EM01CTRL0_IPKVAL_Load40mA (_DCDC_EM01CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM01CTRL0 */ 184 #define DCDC_EM01CTRL0_IPKVAL_Load44mA (_DCDC_EM01CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM01CTRL0 */ 185 #define DCDC_EM01CTRL0_IPKVAL_Load48mA (_DCDC_EM01CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM01CTRL0 */ 186 #define DCDC_EM01CTRL0_IPKVAL_Load52mA (_DCDC_EM01CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM01CTRL0 */ 187 #define DCDC_EM01CTRL0_IPKVAL_Load56mA (_DCDC_EM01CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM01CTRL0 */ 188 #define DCDC_EM01CTRL0_IPKVAL_Load60mA (_DCDC_EM01CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM01CTRL0 */ 189 #define _DCDC_EM01CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ 190 #define _DCDC_EM01CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ 191 #define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ 192 #define _DCDC_EM01CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM01CTRL0 */ 193 #define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM01CTRL0 */ 194 #define _DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM01CTRL0 */ 195 #define _DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM01CTRL0 */ 196 #define DCDC_EM01CTRL0_DRVSPEED_DEFAULT (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ 197 #define DCDC_EM01CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM01CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM01CTRL0 */ 198 #define DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM01CTRL0*/ 199 #define DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM01CTRL0*/ 200 #define DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM01CTRL0*/ 201 202 /* Bit fields for DCDC EM23CTRL0 */ 203 #define _DCDC_EM23CTRL0_RESETVALUE 0x00000103UL /**< Default value for DCDC_EM23CTRL0 */ 204 #define _DCDC_EM23CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM23CTRL0 */ 205 #define _DCDC_EM23CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ 206 #define _DCDC_EM23CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ 207 #define _DCDC_EM23CTRL0_IPKVAL_DEFAULT 0x00000003UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ 208 #define _DCDC_EM23CTRL0_IPKVAL_Load5mA 0x00000003UL /**< Mode Load5mA for DCDC_EM23CTRL0 */ 209 #define _DCDC_EM23CTRL0_IPKVAL_Load10mA 0x00000009UL /**< Mode Load10mA for DCDC_EM23CTRL0 */ 210 #define DCDC_EM23CTRL0_IPKVAL_DEFAULT (_DCDC_EM23CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ 211 #define DCDC_EM23CTRL0_IPKVAL_Load5mA (_DCDC_EM23CTRL0_IPKVAL_Load5mA << 0) /**< Shifted mode Load5mA for DCDC_EM23CTRL0 */ 212 #define DCDC_EM23CTRL0_IPKVAL_Load10mA (_DCDC_EM23CTRL0_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_EM23CTRL0 */ 213 #define _DCDC_EM23CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ 214 #define _DCDC_EM23CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ 215 #define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ 216 #define _DCDC_EM23CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM23CTRL0 */ 217 #define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM23CTRL0 */ 218 #define _DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM23CTRL0 */ 219 #define _DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM23CTRL0 */ 220 #define DCDC_EM23CTRL0_DRVSPEED_DEFAULT (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ 221 #define DCDC_EM23CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM23CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM23CTRL0 */ 222 #define DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM23CTRL0*/ 223 #define DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM23CTRL0*/ 224 #define DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM23CTRL0*/ 225 226 /* Bit fields for DCDC PFMXCTRL */ 227 #define _DCDC_PFMXCTRL_RESETVALUE 0x00000C0CUL /**< Default value for DCDC_PFMXCTRL */ 228 #define _DCDC_PFMXCTRL_MASK 0x00001F0FUL /**< Mask for DCDC_PFMXCTRL */ 229 #define _DCDC_PFMXCTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ 230 #define _DCDC_PFMXCTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ 231 #define _DCDC_PFMXCTRL_IPKVAL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_PFMXCTRL */ 232 #define _DCDC_PFMXCTRL_IPKVAL_LOAD50MA 0x00000003UL /**< Mode LOAD50MA for DCDC_PFMXCTRL */ 233 #define _DCDC_PFMXCTRL_IPKVAL_LOAD65MA 0x00000004UL /**< Mode LOAD65MA for DCDC_PFMXCTRL */ 234 #define _DCDC_PFMXCTRL_IPKVAL_LOAD73MA 0x00000005UL /**< Mode LOAD73MA for DCDC_PFMXCTRL */ 235 #define _DCDC_PFMXCTRL_IPKVAL_LOAD80MA 0x00000006UL /**< Mode LOAD80MA for DCDC_PFMXCTRL */ 236 #define _DCDC_PFMXCTRL_IPKVAL_LOAD86MA 0x00000007UL /**< Mode LOAD86MA for DCDC_PFMXCTRL */ 237 #define _DCDC_PFMXCTRL_IPKVAL_LOAD93MA 0x00000008UL /**< Mode LOAD93MA for DCDC_PFMXCTRL */ 238 #define _DCDC_PFMXCTRL_IPKVAL_LOAD100MA 0x00000009UL /**< Mode LOAD100MA for DCDC_PFMXCTRL */ 239 #define _DCDC_PFMXCTRL_IPKVAL_LOAD106MA 0x0000000AUL /**< Mode LOAD106MA for DCDC_PFMXCTRL */ 240 #define _DCDC_PFMXCTRL_IPKVAL_LOAD113MA 0x0000000BUL /**< Mode LOAD113MA for DCDC_PFMXCTRL */ 241 #define _DCDC_PFMXCTRL_IPKVAL_LOAD120MA 0x0000000CUL /**< Mode LOAD120MA for DCDC_PFMXCTRL */ 242 #define DCDC_PFMXCTRL_IPKVAL_DEFAULT (_DCDC_PFMXCTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */ 243 #define DCDC_PFMXCTRL_IPKVAL_LOAD50MA (_DCDC_PFMXCTRL_IPKVAL_LOAD50MA << 0) /**< Shifted mode LOAD50MA for DCDC_PFMXCTRL */ 244 #define DCDC_PFMXCTRL_IPKVAL_LOAD65MA (_DCDC_PFMXCTRL_IPKVAL_LOAD65MA << 0) /**< Shifted mode LOAD65MA for DCDC_PFMXCTRL */ 245 #define DCDC_PFMXCTRL_IPKVAL_LOAD73MA (_DCDC_PFMXCTRL_IPKVAL_LOAD73MA << 0) /**< Shifted mode LOAD73MA for DCDC_PFMXCTRL */ 246 #define DCDC_PFMXCTRL_IPKVAL_LOAD80MA (_DCDC_PFMXCTRL_IPKVAL_LOAD80MA << 0) /**< Shifted mode LOAD80MA for DCDC_PFMXCTRL */ 247 #define DCDC_PFMXCTRL_IPKVAL_LOAD86MA (_DCDC_PFMXCTRL_IPKVAL_LOAD86MA << 0) /**< Shifted mode LOAD86MA for DCDC_PFMXCTRL */ 248 #define DCDC_PFMXCTRL_IPKVAL_LOAD93MA (_DCDC_PFMXCTRL_IPKVAL_LOAD93MA << 0) /**< Shifted mode LOAD93MA for DCDC_PFMXCTRL */ 249 #define DCDC_PFMXCTRL_IPKVAL_LOAD100MA (_DCDC_PFMXCTRL_IPKVAL_LOAD100MA << 0) /**< Shifted mode LOAD100MA for DCDC_PFMXCTRL */ 250 #define DCDC_PFMXCTRL_IPKVAL_LOAD106MA (_DCDC_PFMXCTRL_IPKVAL_LOAD106MA << 0) /**< Shifted mode LOAD106MA for DCDC_PFMXCTRL */ 251 #define DCDC_PFMXCTRL_IPKVAL_LOAD113MA (_DCDC_PFMXCTRL_IPKVAL_LOAD113MA << 0) /**< Shifted mode LOAD113MA for DCDC_PFMXCTRL */ 252 #define DCDC_PFMXCTRL_IPKVAL_LOAD120MA (_DCDC_PFMXCTRL_IPKVAL_LOAD120MA << 0) /**< Shifted mode LOAD120MA for DCDC_PFMXCTRL */ 253 #define _DCDC_PFMXCTRL_IPKTMAXCTRL_SHIFT 8 /**< Shift value for DCDC_IPKTMAXCTRL */ 254 #define _DCDC_PFMXCTRL_IPKTMAXCTRL_MASK 0x1F00UL /**< Bit mask for DCDC_IPKTMAXCTRL */ 255 #define _DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_PFMXCTRL */ 256 #define DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT (_DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */ 257 258 /* Bit fields for DCDC IF */ 259 #define _DCDC_IF_RESETVALUE 0x00000000UL /**< Default value for DCDC_IF */ 260 #define _DCDC_IF_MASK 0x000003FFUL /**< Mask for DCDC_IF */ 261 #define DCDC_IF_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled */ 262 #define _DCDC_IF_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ 263 #define _DCDC_IF_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ 264 #define _DCDC_IF_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 265 #define DCDC_IF_BYPSW_DEFAULT (_DCDC_IF_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IF */ 266 #define DCDC_IF_WARM (0x1UL << 1) /**< DCDC Warmup Time Done */ 267 #define _DCDC_IF_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ 268 #define _DCDC_IF_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ 269 #define _DCDC_IF_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 270 #define DCDC_IF_WARM_DEFAULT (_DCDC_IF_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IF */ 271 #define DCDC_IF_RUNNING (0x1UL << 2) /**< DCDC Running */ 272 #define _DCDC_IF_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ 273 #define _DCDC_IF_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ 274 #define _DCDC_IF_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 275 #define DCDC_IF_RUNNING_DEFAULT (_DCDC_IF_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IF */ 276 #define DCDC_IF_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold */ 277 #define _DCDC_IF_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ 278 #define _DCDC_IF_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ 279 #define _DCDC_IF_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 280 #define DCDC_IF_VREGINLOW_DEFAULT (_DCDC_IF_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IF */ 281 #define DCDC_IF_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold */ 282 #define _DCDC_IF_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ 283 #define _DCDC_IF_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ 284 #define _DCDC_IF_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 285 #define DCDC_IF_VREGINHIGH_DEFAULT (_DCDC_IF_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IF */ 286 #define DCDC_IF_REGULATION (0x1UL << 5) /**< DCDC in regulation */ 287 #define _DCDC_IF_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ 288 #define _DCDC_IF_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ 289 #define _DCDC_IF_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 290 #define DCDC_IF_REGULATION_DEFAULT (_DCDC_IF_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IF */ 291 #define DCDC_IF_TMAX (0x1UL << 6) /**< Ton_max Timeout Reached */ 292 #define _DCDC_IF_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ 293 #define _DCDC_IF_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ 294 #define _DCDC_IF_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 295 #define DCDC_IF_TMAX_DEFAULT (_DCDC_IF_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IF */ 296 #define DCDC_IF_EM4ERR (0x1UL << 7) /**< EM4 Entry Request Error */ 297 #define _DCDC_IF_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ 298 #define _DCDC_IF_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ 299 #define _DCDC_IF_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 300 #define DCDC_IF_EM4ERR_DEFAULT (_DCDC_IF_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IF */ 301 #define DCDC_IF_PFMXMODE (0x1UL << 9) /**< Entered PFMX mode */ 302 #define _DCDC_IF_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ 303 #define _DCDC_IF_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ 304 #define _DCDC_IF_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 305 #define DCDC_IF_PFMXMODE_DEFAULT (_DCDC_IF_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IF */ 306 307 /* Bit fields for DCDC IEN */ 308 #define _DCDC_IEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_IEN */ 309 #define _DCDC_IEN_MASK 0x000003FFUL /**< Mask for DCDC_IEN */ 310 #define DCDC_IEN_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled Interrupt Enable */ 311 #define _DCDC_IEN_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ 312 #define _DCDC_IEN_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ 313 #define _DCDC_IEN_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 314 #define DCDC_IEN_BYPSW_DEFAULT (_DCDC_IEN_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IEN */ 315 #define DCDC_IEN_WARM (0x1UL << 1) /**< DCDC Warmup Time Done Interrupt Enable */ 316 #define _DCDC_IEN_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ 317 #define _DCDC_IEN_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ 318 #define _DCDC_IEN_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 319 #define DCDC_IEN_WARM_DEFAULT (_DCDC_IEN_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IEN */ 320 #define DCDC_IEN_RUNNING (0x1UL << 2) /**< DCDC Running Interrupt Enable */ 321 #define _DCDC_IEN_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ 322 #define _DCDC_IEN_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ 323 #define _DCDC_IEN_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 324 #define DCDC_IEN_RUNNING_DEFAULT (_DCDC_IEN_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IEN */ 325 #define DCDC_IEN_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold Interrupt Enable */ 326 #define _DCDC_IEN_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ 327 #define _DCDC_IEN_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ 328 #define _DCDC_IEN_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 329 #define DCDC_IEN_VREGINLOW_DEFAULT (_DCDC_IEN_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IEN */ 330 #define DCDC_IEN_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold Interrupt Enable */ 331 #define _DCDC_IEN_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ 332 #define _DCDC_IEN_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ 333 #define _DCDC_IEN_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 334 #define DCDC_IEN_VREGINHIGH_DEFAULT (_DCDC_IEN_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IEN */ 335 #define DCDC_IEN_REGULATION (0x1UL << 5) /**< DCDC in Regulation Interrupt Enable */ 336 #define _DCDC_IEN_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ 337 #define _DCDC_IEN_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ 338 #define _DCDC_IEN_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 339 #define DCDC_IEN_REGULATION_DEFAULT (_DCDC_IEN_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IEN */ 340 #define DCDC_IEN_TMAX (0x1UL << 6) /**< Ton_max Timeout Interrupt Enable */ 341 #define _DCDC_IEN_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ 342 #define _DCDC_IEN_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ 343 #define _DCDC_IEN_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 344 #define DCDC_IEN_TMAX_DEFAULT (_DCDC_IEN_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IEN */ 345 #define DCDC_IEN_EM4ERR (0x1UL << 7) /**< EM4 Entry Req Interrupt Enable */ 346 #define _DCDC_IEN_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ 347 #define _DCDC_IEN_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ 348 #define _DCDC_IEN_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 349 #define DCDC_IEN_EM4ERR_DEFAULT (_DCDC_IEN_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IEN */ 350 #define DCDC_IEN_PFMXMODE (0x1UL << 9) /**< PFMX Mode Interrupt Enable */ 351 #define _DCDC_IEN_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ 352 #define _DCDC_IEN_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ 353 #define _DCDC_IEN_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 354 #define DCDC_IEN_PFMXMODE_DEFAULT (_DCDC_IEN_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IEN */ 355 356 /* Bit fields for DCDC STATUS */ 357 #define _DCDC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_STATUS */ 358 #define _DCDC_STATUS_MASK 0x0000071FUL /**< Mask for DCDC_STATUS */ 359 #define DCDC_STATUS_BYPSW (0x1UL << 0) /**< Bypass Switch is currently enabled */ 360 #define _DCDC_STATUS_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ 361 #define _DCDC_STATUS_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ 362 #define _DCDC_STATUS_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 363 #define DCDC_STATUS_BYPSW_DEFAULT (_DCDC_STATUS_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_STATUS */ 364 #define DCDC_STATUS_WARM (0x1UL << 1) /**< DCDC Warmup Done */ 365 #define _DCDC_STATUS_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ 366 #define _DCDC_STATUS_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ 367 #define _DCDC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 368 #define DCDC_STATUS_WARM_DEFAULT (_DCDC_STATUS_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_STATUS */ 369 #define DCDC_STATUS_RUNNING (0x1UL << 2) /**< DCDC is running */ 370 #define _DCDC_STATUS_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ 371 #define _DCDC_STATUS_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ 372 #define _DCDC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 373 #define DCDC_STATUS_RUNNING_DEFAULT (_DCDC_STATUS_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_STATUS */ 374 #define DCDC_STATUS_VREGIN (0x1UL << 3) /**< VREGVDD comparator status */ 375 #define _DCDC_STATUS_VREGIN_SHIFT 3 /**< Shift value for DCDC_VREGIN */ 376 #define _DCDC_STATUS_VREGIN_MASK 0x8UL /**< Bit mask for DCDC_VREGIN */ 377 #define _DCDC_STATUS_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 378 #define DCDC_STATUS_VREGIN_DEFAULT (_DCDC_STATUS_VREGIN_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_STATUS */ 379 #define DCDC_STATUS_BYPCMPOUT (0x1UL << 4) /**< Bypass Comparator Output */ 380 #define _DCDC_STATUS_BYPCMPOUT_SHIFT 4 /**< Shift value for DCDC_BYPCMPOUT */ 381 #define _DCDC_STATUS_BYPCMPOUT_MASK 0x10UL /**< Bit mask for DCDC_BYPCMPOUT */ 382 #define _DCDC_STATUS_BYPCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 383 #define DCDC_STATUS_BYPCMPOUT_DEFAULT (_DCDC_STATUS_BYPCMPOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_STATUS */ 384 #define DCDC_STATUS_PFMXMODE (0x1UL << 9) /**< DCDC in PFMX mode */ 385 #define _DCDC_STATUS_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ 386 #define _DCDC_STATUS_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ 387 #define _DCDC_STATUS_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 388 #define DCDC_STATUS_PFMXMODE_DEFAULT (_DCDC_STATUS_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_STATUS */ 389 390 /* Bit fields for DCDC SYNCBUSY */ 391 #define _DCDC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for DCDC_SYNCBUSY */ 392 #define _DCDC_SYNCBUSY_MASK 0x000000FFUL /**< Mask for DCDC_SYNCBUSY */ 393 #define DCDC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Sync Busy Status */ 394 #define _DCDC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for DCDC_CTRL */ 395 #define _DCDC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for DCDC_CTRL */ 396 #define _DCDC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ 397 #define DCDC_SYNCBUSY_CTRL_DEFAULT (_DCDC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ 398 #define DCDC_SYNCBUSY_EM01CTRL0 (0x1UL << 1) /**< EM01CTRL0 Sync Busy Status */ 399 #define _DCDC_SYNCBUSY_EM01CTRL0_SHIFT 1 /**< Shift value for DCDC_EM01CTRL0 */ 400 #define _DCDC_SYNCBUSY_EM01CTRL0_MASK 0x2UL /**< Bit mask for DCDC_EM01CTRL0 */ 401 #define _DCDC_SYNCBUSY_EM01CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ 402 #define DCDC_SYNCBUSY_EM01CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL0_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ 403 #define DCDC_SYNCBUSY_EM01CTRL1 (0x1UL << 2) /**< EM01CTRL1 Sync Bust Status */ 404 #define _DCDC_SYNCBUSY_EM01CTRL1_SHIFT 2 /**< Shift value for DCDC_EM01CTRL1 */ 405 #define _DCDC_SYNCBUSY_EM01CTRL1_MASK 0x4UL /**< Bit mask for DCDC_EM01CTRL1 */ 406 #define _DCDC_SYNCBUSY_EM01CTRL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ 407 #define DCDC_SYNCBUSY_EM01CTRL1_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL1_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ 408 #define DCDC_SYNCBUSY_EM23CTRL0 (0x1UL << 3) /**< EM23CTRL0 Sync Busy Status */ 409 #define _DCDC_SYNCBUSY_EM23CTRL0_SHIFT 3 /**< Shift value for DCDC_EM23CTRL0 */ 410 #define _DCDC_SYNCBUSY_EM23CTRL0_MASK 0x8UL /**< Bit mask for DCDC_EM23CTRL0 */ 411 #define _DCDC_SYNCBUSY_EM23CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ 412 #define DCDC_SYNCBUSY_EM23CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM23CTRL0_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ 413 #define DCDC_SYNCBUSY_PFMXCTRL (0x1UL << 7) /**< PFMXCTRL Sync Busy Status */ 414 #define _DCDC_SYNCBUSY_PFMXCTRL_SHIFT 7 /**< Shift value for DCDC_PFMXCTRL */ 415 #define _DCDC_SYNCBUSY_PFMXCTRL_MASK 0x80UL /**< Bit mask for DCDC_PFMXCTRL */ 416 #define _DCDC_SYNCBUSY_PFMXCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ 417 #define DCDC_SYNCBUSY_PFMXCTRL_DEFAULT (_DCDC_SYNCBUSY_PFMXCTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ 418 419 /* Bit fields for DCDC LOCK */ 420 #define _DCDC_LOCK_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCK */ 421 #define _DCDC_LOCK_MASK 0x0000FFFFUL /**< Mask for DCDC_LOCK */ 422 #define _DCDC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DCDC_LOCKKEY */ 423 #define _DCDC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DCDC_LOCKKEY */ 424 #define _DCDC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCK */ 425 #define _DCDC_LOCK_LOCKKEY_UNLOCKKEY 0x0000ABCDUL /**< Mode UNLOCKKEY for DCDC_LOCK */ 426 #define DCDC_LOCK_LOCKKEY_DEFAULT (_DCDC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCK */ 427 #define DCDC_LOCK_LOCKKEY_UNLOCKKEY (_DCDC_LOCK_LOCKKEY_UNLOCKKEY << 0) /**< Shifted mode UNLOCKKEY for DCDC_LOCK */ 428 429 /* Bit fields for DCDC LOCKSTATUS */ 430 #define _DCDC_LOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCKSTATUS */ 431 #define _DCDC_LOCKSTATUS_MASK 0x00000001UL /**< Mask for DCDC_LOCKSTATUS */ 432 #define DCDC_LOCKSTATUS_LOCK (0x1UL << 0) /**< Lock Status */ 433 #define _DCDC_LOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for DCDC_LOCK */ 434 #define _DCDC_LOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for DCDC_LOCK */ 435 #define _DCDC_LOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCKSTATUS */ 436 #define _DCDC_LOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DCDC_LOCKSTATUS */ 437 #define _DCDC_LOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DCDC_LOCKSTATUS */ 438 #define DCDC_LOCKSTATUS_LOCK_DEFAULT (_DCDC_LOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCKSTATUS */ 439 #define DCDC_LOCKSTATUS_LOCK_UNLOCKED (_DCDC_LOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for DCDC_LOCKSTATUS */ 440 #define DCDC_LOCKSTATUS_LOCK_LOCKED (_DCDC_LOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for DCDC_LOCKSTATUS */ 441 442 /** @} End of group EFR32MG24_DCDC_BitFields */ 443 /** @} End of group EFR32MG24_DCDC */ 444 /** @} End of group Parts */ 445 446 #endif /* EFR32MG24_DCDC_H */ 447
