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Searched defs:DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm4.h26702 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) macro
DMIMXRT1165_cm7.h26705 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm7.h28712 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) macro
DMIMXRT1166_cm4.h28709 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm7.h27023 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) macro
DMIMXRT1175_cm4.h27020 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h27023 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h29024 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) macro
DMIMXRT1173_cm7.h29027 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm4.h29027 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) macro
DMIMXRT1176_cm7.h29030 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h29030 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) macro