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Searched defs:DCDC_REG3_MINPWR_DC_HALFCLK_MASK (Results 1 – 23 of 23) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h8202 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h8920 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h10500 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h10484 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h12768 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h11526 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h12311 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h13137 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h12770 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h13923 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h13997 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm4.h26676 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
DMIMXRT1165_cm7.h26679 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm7.h28686 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
DMIMXRT1166_cm4.h28683 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm7.h26997 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
DMIMXRT1175_cm4.h26994 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h26997 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h28998 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
DMIMXRT1173_cm7.h29001 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm4.h29001 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
DMIMXRT1176_cm7.h29004 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h29004 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) macro