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Searched defs:DCDC_REG1_VBG_TRIM_MASK (Results 1 – 23 of 23) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h8131 #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h8849 #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h10429 #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h10413 #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h12697 #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h11455 #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h12240 #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h13066 #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h12699 #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h13852 #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h13926 #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm4.h26515 #define DCDC_REG1_VBG_TRIM_MASK (0x7C0U) macro
DMIMXRT1165_cm7.h26518 #define DCDC_REG1_VBG_TRIM_MASK (0x7C0U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm7.h28525 #define DCDC_REG1_VBG_TRIM_MASK (0x7C0U) macro
DMIMXRT1166_cm4.h28522 #define DCDC_REG1_VBG_TRIM_MASK (0x7C0U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm7.h26836 #define DCDC_REG1_VBG_TRIM_MASK (0x7C0U) macro
DMIMXRT1175_cm4.h26833 #define DCDC_REG1_VBG_TRIM_MASK (0x7C0U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h26836 #define DCDC_REG1_VBG_TRIM_MASK (0x7C0U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h28837 #define DCDC_REG1_VBG_TRIM_MASK (0x7C0U) macro
DMIMXRT1173_cm7.h28840 #define DCDC_REG1_VBG_TRIM_MASK (0x7C0U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm4.h28840 #define DCDC_REG1_VBG_TRIM_MASK (0x7C0U) macro
DMIMXRT1176_cm7.h28843 #define DCDC_REG1_VBG_TRIM_MASK (0x7C0U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h28843 #define DCDC_REG1_VBG_TRIM_MASK (0x7C0U) macro