1 /*! 2 \file gd32e50x_dbg.h 3 \brief definitions for the DBG 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50x 6 \version 2020-08-26, V1.1.0, firmware for GD32E50x 7 \version 2021-03-23, V1.2.0, firmware for GD32E50x 8 */ 9 10 /* 11 Copyright (c) 2021, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32E50X_DBG_H 38 #define GD32E50X_DBG_H 39 40 #include "gd32e50x.h" 41 42 /* DBG definitions */ 43 #define DBG DBG_BASE /*!< DBG base address */ 44 45 /* registers definitions */ 46 #define DBG_ID REG32(DBG + 0x00000000U) /*!< DBG_ID code register */ 47 #define DBG_CTL REG32(DBG + 0x00000004U) /*!< DBG control register */ 48 49 /* bits definitions */ 50 /* DBG_ID */ 51 #define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code */ 52 53 /* DBG_CTL */ 54 #define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ 55 #define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ 56 #define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ 57 #ifdef GD32E50X_CL 58 #define DBG_CTL_CAN2_HOLD BIT(3) /*!< hold CAN2 receive register counter when core is halted */ 59 #endif /* GD32E50X_CL */ 60 #define DBG_CTL_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ 61 #define DBG_CTL_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ 62 #define DBG_CTL_FWDGT_HOLD BIT(8) /*!< hold FWDGT counter when core is halted */ 63 #define DBG_CTL_WWDGT_HOLD BIT(9) /*!< hold WWDGT counter when core is halted */ 64 #define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ 65 #define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ 66 #define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ 67 #define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */ 68 #define DBG_CTL_CAN0_HOLD BIT(14) /*!< hold CAN0 receive register counter when core is halted */ 69 #define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus timeout when core is halted */ 70 #define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus timeout when core is halted */ 71 #define DBG_CTL_TIMER7_HOLD BIT(17) /*!< hold TIMER7 counter when core is halted */ 72 #define DBG_CTL_TIMER4_HOLD BIT(18) /*!< hold TIMER4 counter when core is halted */ 73 #define DBG_CTL_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */ 74 #define DBG_CTL_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */ 75 #define DBG_CTL_CAN1_HOLD BIT(21) /*!< hold CAN1 receive register counter when core is halted */ 76 #define DBG_CTL_I2C2_HOLD BIT(22) /*!< hold I2C2 smbus timeout when core is halted */ 77 #if (defined(GD32E50X_HD) || defined(GD32E50X_XD) || defined(GD32E50X_CL)) 78 #define DBG_CTL_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */ 79 #define DBG_CTL_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */ 80 #define DBG_CTL_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ 81 #define DBG_CTL_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */ 82 #define DBG_CTL_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */ 83 #define DBG_CTL_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */ 84 #define DBG_CTL_SHRTIMER_HOLD BIT(31) /*!< hold SHRTIMER counter when core is halted */ 85 #endif /* GD32E50X_HD and GD32E50X_XD and GD32E50X_CL */ 86 87 /* constants definitions */ 88 #define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */ 89 #define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ 90 #define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */ 91 92 /* define the peripheral debug hold bit position and its register index offset */ 93 #define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) 94 #define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) 95 #define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 96 97 /* register index */ 98 #define DBG_IDX_CTL ((uint32_t)0x00000004U) 99 100 typedef enum 101 { 102 #ifdef GD32E50X_CL 103 DBG_CAN2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 3U), /*!< hold CAN2 receive register counter when core is halted */ 104 #endif /* GD32E50X_CL */ 105 DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 8U), /*!< hold FWDGT counter when core is halted */ 106 DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 9U), /*!< hold WWDGT counter when core is halted */ 107 DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 10U), /*!< hold TIMER0 counter when core is halted */ 108 DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 11U), /*!< hold TIMER1 counter when core is halted */ 109 DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 12U), /*!< hold TIMER2 counter when core is halted */ 110 DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 13U), /*!< hold TIMER3 counter when core is halted */ 111 DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 14U), /*!< hold CAN0 receive register counter when core is halted */ 112 DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 15U), /*!< hold I2C0 smbus timeout when core is halted */ 113 DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 16U), /*!< hold I2C1 smbus timeout when core is halted */ 114 DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 17U), /*!< hold TIMER7 counter when core is halted */ 115 DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 18U), /*!< hold TIMER4 counter when core is halted */ 116 DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 19U), /*!< hold TIMER5 counter when core is halted */ 117 DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 20U), /*!< hold TIMER6 counter when core is halted */ 118 DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 21U), /*!< hold CAN1 receive register counter when core is halted */ 119 DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 22U), /*!< hold I2C2 smbus timeout when core is halted */ 120 #if (defined(GD32E50X_HD) || defined(GD32E50X_XD) || defined(GD32E50X_CL)) 121 DBG_TIMER11_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 25U), /*!< hold TIMER11 counter when core is halted */ 122 DBG_TIMER12_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 26U), /*!< hold TIMER12 counter when core is halted */ 123 DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 27U), /*!< hold TIMER13 counter when core is halted */ 124 DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 28U), /*!< hold TIMER8 counter when core is halted */ 125 DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 29U), /*!< hold TIMER9 counter when core is halted */ 126 DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 30U), /*!< hold TIMER10 counter when core is halted */ 127 DBG_SHRTIMER_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 31U), /*!< hold SHRTIMER counter when core is halted */ 128 #endif /* GD32E50X_HD and GD32E50X_XD and GD32E50X_CL */ 129 }dbg_periph_enum; 130 131 #define CTL_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6)) 132 #define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */ 133 #define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ 134 #define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ 135 #define TRACE_MODE_SYNC_DATASIZE_4 CTL_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */ 136 137 /* function declarations */ 138 /* deinitialize the DBG */ 139 void dbg_deinit(void); 140 /* read DBG_ID code register */ 141 uint32_t dbg_id_get(void); 142 143 /* enable low power behavior when the MCU is in debug mode */ 144 void dbg_low_power_enable(uint32_t dbg_low_power); 145 /* disable low power behavior when the MCU is in debug mode */ 146 void dbg_low_power_disable(uint32_t dbg_low_power); 147 148 /* enable peripheral behavior when the MCU is in debug mode */ 149 void dbg_periph_enable(dbg_periph_enum dbg_periph); 150 /* disable peripheral behavior when the MCU is in debug mode */ 151 void dbg_periph_disable(dbg_periph_enum dbg_periph); 152 153 /* enable trace pin assignment */ 154 void dbg_trace_pin_enable(void); 155 /* disable trace pin assignment */ 156 void dbg_trace_pin_disable(void); 157 /* set trace pin mode */ 158 void dbg_trace_pin_mode_set(uint32_t trace_mode); 159 160 #endif /* GD32E50X_DBG_H */ 161
