1 /**
2   ******************************************************************************
3   * @file    stm32f334x8.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32F334x8 Devices Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
16   * All rights reserved.</center></h2>
17   *
18   * This software component is licensed by ST under BSD 3-Clause license,
19   * the "License"; You may not use this file except in compliance with the
20   * License. You may obtain a copy of the License at:
21   *                        opensource.org/licenses/BSD-3-Clause
22   *
23   ******************************************************************************
24   */
25 
26 /** @addtogroup CMSIS_Device
27   * @{
28   */
29 
30 /** @addtogroup stm32f334x8
31   * @{
32   */
33 
34 #ifndef __STM32F334x8_H
35 #define __STM32F334x8_H
36 
37 #ifdef __cplusplus
38  extern "C" {
39 #endif /* __cplusplus */
40 
41 /** @addtogroup Configuration_section_for_CMSIS
42   * @{
43   */
44 
45 /**
46  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
47  */
48 #define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
49 #define __MPU_PRESENT             0U       /*!< STM32F334x8 devices do not provide an MPU */
50 #define __NVIC_PRIO_BITS          4U       /*!< STM32F334x8 devices use 4 Bits for the Priority Levels */
51 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used */
52 #define __FPU_PRESENT             1U       /*!< STM32F334x8 devices provide an FPU */
53 
54 /**
55   * @}
56   */
57 
58 /** @addtogroup Peripheral_interrupt_number_definition
59   * @{
60   */
61 
62 /**
63  * @brief STM32F334x8 devices Interrupt Number Definition, according to the selected device
64  *        in @ref Library_configuration_section
65  */
66 typedef enum
67 {
68 /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
69   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
70   HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
71   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
72   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
73   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
74   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
75   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
76   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
77   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
78 /******  STM32 specific Interrupt Numbers **********************************************************************/
79   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
80   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
81   TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line 19          */
82   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line 20                     */
83   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
84   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
85   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
86   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
87   EXTI2_TSC_IRQn              = 8,      /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt         */
88   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
89   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
90   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 Interrupt                                          */
91   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 Interrupt                                          */
92   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 Interrupt                                          */
93   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 Interrupt                                          */
94   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 Interrupt                                          */
95   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 Interrupt                                          */
96   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 Interrupt                                          */
97   ADC1_2_IRQn                 = 18,     /*!< ADC1 & ADC2 Interrupts                                            */
98   CAN_TX_IRQn                 = 19,     /*!< CAN TX Interrupt                                                  */
99   CAN_RX0_IRQn                = 20,     /*!< CAN RX0 Interrupt                                                 */
100   CAN_RX1_IRQn                = 21,     /*!< CAN RX1 Interrupt                                                 */
101   CAN_SCE_IRQn                = 22,     /*!< CAN SCE Interrupt                                                 */
102   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
103   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                                   */
104   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                                  */
105   TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt                  */
106   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
107   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
108   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
109   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup)        */
110   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
111   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
112   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup)   */
113   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup)   */
114   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup)   */
115   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
116   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt                 */
117   TIM6_DAC1_IRQn              = 54,     /*!< TIM6 global and DAC1 underrun error Interrupts*/
118   TIM7_DAC2_IRQn              = 55,     /*!< TIM7 global and DAC2 channel1 underrun error Interrupt            */
119   COMP2_IRQn                  = 64,     /*!< COMP2 global Interrupt via EXTI Line22                            */
120   COMP4_6_IRQn                = 65,     /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32           */
121   HRTIM1_Master_IRQn          = 67,     /*!< HRTIM Master Timer global Interrupts                              */
122   HRTIM1_TIMA_IRQn            = 68,     /*!< HRTIM Timer A global Interrupt                                    */
123   HRTIM1_TIMB_IRQn            = 69,     /*!< HRTIM Timer B global Interrupt                                    */
124   HRTIM1_TIMC_IRQn            = 70,     /*!< HRTIM Timer C global Interrupt                                    */
125   HRTIM1_TIMD_IRQn            = 71,     /*!< HRTIM Timer D global Interrupt                                    */
126   HRTIM1_TIME_IRQn            = 72,     /*!< HRTIM Timer E global Interrupt                                    */
127   HRTIM1_FLT_IRQn             = 73,     /*!< HRTIM Fault global Interrupt                                      */
128   FPU_IRQn                    = 81,      /*!< Floating point Interrupt                                          */
129 } IRQn_Type;
130 
131 /**
132   * @}
133   */
134 
135 #include "core_cm4.h"            /* Cortex-M4 processor and core peripherals */
136 #include "system_stm32f3xx.h"    /* STM32F3xx System Header */
137 #include <stdint.h>
138 
139 /** @addtogroup Peripheral_registers_structures
140   * @{
141   */
142 
143 /**
144   * @brief Analog to Digital Converter
145   */
146 
147 typedef struct
148 {
149   __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                 Address offset: 0x00 */
150   __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                     Address offset: 0x04 */
151   __IO uint32_t CR;               /*!< ADC control register,                              Address offset: 0x08 */
152   __IO uint32_t CFGR;             /*!< ADC Configuration register,                        Address offset: 0x0C */
153   uint32_t      RESERVED0;        /*!< Reserved, 0x010                                                         */
154   __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                        Address offset: 0x14 */
155   __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                        Address offset: 0x18 */
156   uint32_t      RESERVED1;        /*!< Reserved, 0x01C                                                         */
157   __IO uint32_t TR1;              /*!< ADC watchdog threshold register 1,                 Address offset: 0x20 */
158   __IO uint32_t TR2;              /*!< ADC watchdog threshold register 2,                 Address offset: 0x24 */
159   __IO uint32_t TR3;              /*!< ADC watchdog threshold register 3,                 Address offset: 0x28 */
160   uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                         */
161   __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                   Address offset: 0x30 */
162   __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                   Address offset: 0x34 */
163   __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                   Address offset: 0x38 */
164   __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                   Address offset: 0x3C */
165   __IO uint32_t DR;               /*!< ADC regular data register,                         Address offset: 0x40 */
166   uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                         */
167   uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                         */
168   __IO uint32_t JSQR;             /*!< ADC injected sequence register,                    Address offset: 0x4C */
169   uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                 */
170   __IO uint32_t OFR1;             /*!< ADC offset register 1,                             Address offset: 0x60 */
171   __IO uint32_t OFR2;             /*!< ADC offset register 2,                             Address offset: 0x64 */
172   __IO uint32_t OFR3;             /*!< ADC offset register 3,                             Address offset: 0x68 */
173   __IO uint32_t OFR4;             /*!< ADC offset register 4,                             Address offset: 0x6C */
174   uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                 */
175   __IO uint32_t JDR1;             /*!< ADC injected data register 1,                      Address offset: 0x80 */
176   __IO uint32_t JDR2;             /*!< ADC injected data register 2,                      Address offset: 0x84 */
177   __IO uint32_t JDR3;             /*!< ADC injected data register 3,                      Address offset: 0x88 */
178   __IO uint32_t JDR4;             /*!< ADC injected data register 4,                      Address offset: 0x8C */
179   uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                 */
180   __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,     Address offset: 0xA0 */
181   __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,     Address offset: 0xA4 */
182   uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                         */
183   uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                         */
184   __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,         Address offset: 0xB0 */
185   __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                          Address offset: 0xB4 */
186 
187 } ADC_TypeDef;
188 
189 typedef struct
190 {
191   __IO uint32_t CSR;            /*!< ADC Common status register,                  Address offset: ADC1/3 base address + 0x300 */
192   uint32_t      RESERVED;       /*!< Reserved, ADC1/3 base address + 0x304                                                    */
193   __IO uint32_t CCR;            /*!< ADC common control register,                 Address offset: ADC1/3 base address + 0x308 */
194   __IO uint32_t CDR;            /*!< ADC common regular data register for dual
195                                      AND triple modes,                            Address offset: ADC1/3 base address + 0x30C */
196 } ADC_Common_TypeDef;
197 
198 /**
199   * @brief Controller Area Network TxMailBox
200   */
201 typedef struct
202 {
203   __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
204   __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
205   __IO uint32_t TDLR; /*!< CAN mailbox data low register */
206   __IO uint32_t TDHR; /*!< CAN mailbox data high register */
207 } CAN_TxMailBox_TypeDef;
208 
209 /**
210   * @brief Controller Area Network FIFOMailBox
211   */
212 typedef struct
213 {
214   __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
215   __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
216   __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
217   __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
218 } CAN_FIFOMailBox_TypeDef;
219 
220 /**
221   * @brief Controller Area Network FilterRegister
222   */
223 typedef struct
224 {
225   __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
226   __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
227 } CAN_FilterRegister_TypeDef;
228 
229 /**
230   * @brief Controller Area Network
231   */
232 typedef struct
233 {
234   __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
235   __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
236   __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
237   __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
238   __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
239   __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
240   __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
241   __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
242   uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
243   CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
244   CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
245   uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
246   __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
247   __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
248   uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
249   __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
250   uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
251   __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
252   uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
253   __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
254   uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
255   CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
256 } CAN_TypeDef;
257 
258 /**
259   * @brief Analog Comparators
260   */
261 typedef struct
262 {
263   __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
264 } COMP_TypeDef;
265 
266 typedef struct
267 {
268   __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
269 } COMP_Common_TypeDef;
270 
271 /**
272   * @brief CRC calculation unit
273   */
274 
275 typedef struct
276 {
277   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
278   __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
279   uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
280   uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
281   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
282   uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
283   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
284   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
285 } CRC_TypeDef;
286 
287 /**
288   * @brief Digital to Analog Converter
289   */
290 
291 typedef struct
292 {
293   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
294   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
295   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
296   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
297   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
298   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
299   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
300   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
301   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
302   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
303   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
304   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
305   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
306   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
307 } DAC_TypeDef;
308 
309 /**
310   * @brief Debug MCU
311   */
312 
313 typedef struct
314 {
315   __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
316   __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
317   __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
318   __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
319 }DBGMCU_TypeDef;
320 
321 /**
322   * @brief DMA Controller
323   */
324 
325 typedef struct
326 {
327   __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
328   __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
329   __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
330   __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
331 } DMA_Channel_TypeDef;
332 
333 typedef struct
334 {
335   __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
336   __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
337 } DMA_TypeDef;
338 
339 /**
340   * @brief External Interrupt/Event Controller
341   */
342 
343 typedef struct
344 {
345   __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
346   __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
347   __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
348   __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
349   __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
350   __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
351   uint32_t      RESERVED1;    /*!< Reserved, 0x18                                                                */
352   uint32_t      RESERVED2;    /*!< Reserved, 0x1C                                                                */
353   __IO uint32_t IMR2;         /*!< EXTI Interrupt mask register,                            Address offset: 0x20 */
354   __IO uint32_t EMR2;         /*!< EXTI Event mask register,                                Address offset: 0x24 */
355   __IO uint32_t RTSR2;        /*!< EXTI Rising trigger selection register,                  Address offset: 0x28 */
356   __IO uint32_t FTSR2;        /*!< EXTI Falling trigger selection register,                 Address offset: 0x2C */
357   __IO uint32_t SWIER2;       /*!< EXTI Software interrupt event register,                  Address offset: 0x30 */
358   __IO uint32_t PR2;          /*!< EXTI Pending register,                                   Address offset: 0x34 */
359 }EXTI_TypeDef;
360 
361 /**
362   * @brief FLASH Registers
363   */
364 
365 typedef struct
366 {
367   __IO uint32_t ACR;          /*!< FLASH access control register,              Address offset: 0x00 */
368   __IO uint32_t KEYR;         /*!< FLASH key register,                         Address offset: 0x04 */
369   __IO uint32_t OPTKEYR;      /*!< FLASH option key register,                  Address offset: 0x08 */
370   __IO uint32_t SR;           /*!< FLASH status register,                      Address offset: 0x0C */
371   __IO uint32_t CR;           /*!< FLASH control register,                     Address offset: 0x10 */
372   __IO uint32_t AR;           /*!< FLASH address register,                     Address offset: 0x14 */
373   uint32_t      RESERVED;     /*!< Reserved, 0x18                                                   */
374   __IO uint32_t OBR;          /*!< FLASH Option byte register,                 Address offset: 0x1C */
375   __IO uint32_t WRPR;         /*!< FLASH Write register,                       Address offset: 0x20 */
376 
377 } FLASH_TypeDef;
378 
379 /**
380   * @brief Option Bytes Registers
381   */
382 typedef struct
383 {
384   __IO uint16_t RDP;          /*!<FLASH option byte Read protection,             Address offset: 0x00 */
385   __IO uint16_t USER;         /*!<FLASH option byte user options,                Address offset: 0x02 */
386   __IO uint16_t Data0;        /*!<FLASH option byte Data0 options,               Address offset: 0x04 */
387   __IO uint16_t Data1;        /*!<FLASH option byte Data1 options,               Address offset: 0x06 */
388   __IO uint16_t WRP0;         /*!<FLASH option byte write protection 0,          Address offset: 0x08 */
389   __IO uint16_t WRP1;         /*!<FLASH option byte write protection 1,          Address offset: 0x0C */
390 } OB_TypeDef;
391 
392 /**
393   * @brief General Purpose I/O
394   */
395 
396 typedef struct
397 {
398   __IO uint32_t MODER;        /*!< GPIO port mode register,               Address offset: 0x00      */
399   __IO uint32_t OTYPER;       /*!< GPIO port output type register,        Address offset: 0x04      */
400   __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,       Address offset: 0x08      */
401   __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
402   __IO uint32_t IDR;          /*!< GPIO port input data register,         Address offset: 0x10      */
403   __IO uint32_t ODR;          /*!< GPIO port output data register,        Address offset: 0x14      */
404   __IO uint32_t BSRR;         /*!< GPIO port bit set/reset register,      Address offset: 0x1A */
405   __IO uint32_t LCKR;         /*!< GPIO port configuration lock register, Address offset: 0x1C      */
406   __IO uint32_t AFR[2];       /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
407   __IO uint32_t BRR;          /*!< GPIO bit reset register,               Address offset: 0x28 */
408 }GPIO_TypeDef;
409 
410 /**
411   * @brief Operational Amplifier (OPAMP)
412   */
413 
414 typedef struct
415 {
416   __IO uint32_t CSR;        /*!< OPAMP control and status register,            Address offset: 0x00 */
417 } OPAMP_TypeDef;
418 
419 /**
420   * @brief High resolution Timer (HRTIM)
421   */
422 /* HRTIM master registers definition */
423 typedef struct
424 {
425   __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */
426   __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */
427   __IO uint32_t MICR;           /*!< HRTIM Master Timer interupt clear register,              Address offset: 0x08 */
428   __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */
429   __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */
430   __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */
431   __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */
432   __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */
433   uint32_t      RESERVED0;     /*!< Reserved,                                                                0x20 */
434   __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */
435   __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */
436   __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */
437   uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */
438 }HRTIM_Master_TypeDef;
439 
440 /* HRTIM Timer A to E registers definition */
441 typedef struct
442 {
443   __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00  */
444   __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04  */
445   __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08  */
446   __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C  */
447   __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10  */
448   __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14  */
449   __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18  */
450   __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C  */
451   __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20  */
452   __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24  */
453   __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28  */
454   __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C  */
455   __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30  */
456   __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */
457   __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */
458   __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */
459   __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */
460   __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */
461   __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */
462   __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */
463   __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */
464   __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */
465   __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */
466   __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */
467   __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */
468   __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */
469   __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */
470   uint32_t      RESERVED0[5];  /*!< Reserved,                                                              0x6C..0x7C */
471 }HRTIM_Timerx_TypeDef;
472 
473 /* HRTIM common register definition */
474 typedef struct
475 {
476   __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */
477   __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */
478   __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */
479   __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */
480   __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */
481   __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */
482   __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
483   __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
484   __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
485   __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */
486   __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
487   __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
488   __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
489   __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */
490   __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */
491   __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */
492   __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */
493   __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */
494   __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */
495   __IO uint32_t DLLCR;      /*!< HRTIM DLL control register,                                 Address offset: 0x4C */
496   __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */
497   __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */
498   __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */
499   __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */
500   __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */
501   __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */
502   __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */
503   __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */
504   __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */
505 }HRTIM_Common_TypeDef;
506 
507 /* HRTIM  register definition */
508 typedef struct {
509   HRTIM_Master_TypeDef sMasterRegs;
510   HRTIM_Timerx_TypeDef sTimerxRegs[5];
511   uint32_t             RESERVED0[32];
512   HRTIM_Common_TypeDef sCommonRegs;
513 }HRTIM_TypeDef;
514 
515 /**
516   * @brief System configuration controller
517   */
518 
519 typedef struct
520 {
521   __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                      Address offset: 0x00 */
522   __IO uint32_t RCR;        /*!< SYSCFG CCM SRAM protection register,               Address offset: 0x04 */
523   __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
524   __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                      Address offset: 0x18 */
525   __IO uint32_t RESERVED0;   /*!< Reserved,                                                           0x1C */
526   __IO uint32_t RESERVED1;   /*!< Reserved,                                                          0x20 */
527   __IO uint32_t RESERVED2;   /*!< Reserved,                                                          0x24 */
528   __IO uint32_t RESERVED4;   /*!< Reserved,                                                          0x28 */
529   __IO uint32_t RESERVED5;  /*!< Reserved,                                                          0x2C */
530   __IO uint32_t RESERVED6;   /*!< Reserved,                                                          0x30 */
531   __IO uint32_t RESERVED7;  /*!< Reserved,                                                          0x34 */
532   __IO uint32_t RESERVED8;  /*!< Reserved,                                                          0x38 */
533   __IO uint32_t RESERVED9;   /*!< Reserved,                                                          0x3C */
534   __IO uint32_t RESERVED10;  /*!< Reserved,                                                          0x40 */
535   __IO uint32_t RESERVED11;  /*!< Reserved,                                                          0x44 */
536   __IO uint32_t RESERVED12;  /*!< Reserved,                                                          0x48 */
537   __IO uint32_t RESERVED13;  /*!< Reserved,                                                          0x4C */
538   __IO uint32_t CFGR3;      /*!< SYSCFG configuration register 3,                    Address offset: 0x50 */
539 } SYSCFG_TypeDef;
540 
541 /**
542   * @brief Inter-integrated Circuit Interface
543   */
544 
545 typedef struct
546 {
547   __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
548   __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
549   __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
550   __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
551   __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
552   __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
553   __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
554   __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
555   __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
556   __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
557   __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
558 }I2C_TypeDef;
559 
560 /**
561   * @brief Independent WATCHDOG
562   */
563 
564 typedef struct
565 {
566   __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
567   __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
568   __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
569   __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
570   __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
571 } IWDG_TypeDef;
572 
573 /**
574   * @brief Power Control
575   */
576 
577 typedef struct
578 {
579   __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
580   __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
581 } PWR_TypeDef;
582 
583 /**
584   * @brief Reset and Clock Control
585   */
586 typedef struct
587 {
588   __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
589   __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
590   __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
591   __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
592   __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
593   __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
594   __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
595   __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
596   __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */
597   __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
598   __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
599   __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
600   __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
601 } RCC_TypeDef;
602 
603 /**
604   * @brief Real-Time Clock
605   */
606 
607 typedef struct
608 {
609   __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */
610   __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */
611   __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */
612   __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */
613   __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */
614   __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                Address offset: 0x14 */
615   uint32_t RESERVED0;       /*!< Reserved, 0x18                                                                 */
616   __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */
617   __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                     Address offset: 0x20 */
618   __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */
619   __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */
620   __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */
621   __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */
622   __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */
623   __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
624   __IO uint32_t CALR;       /*!< RTC calibration register,                                 Address offset: 0x3C */
625   __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
626   __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
627   __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                          Address offset: 0x48 */
628   uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                 */
629   __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                    Address offset: 0x50 */
630   __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                    Address offset: 0x54 */
631   __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                    Address offset: 0x58 */
632   __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                    Address offset: 0x5C */
633   __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                    Address offset: 0x60 */
634 } RTC_TypeDef;
635 
636 
637 /**
638   * @brief Serial Peripheral Interface
639   */
640 
641 typedef struct
642 {
643   __IO uint32_t CR1;      /*!< SPI Control register 1,                              Address offset: 0x00 */
644   __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
645   __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
646   __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
647   __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
648   __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
649   __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
650 } SPI_TypeDef;
651 
652 /**
653   * @brief TIM
654   */
655 typedef struct
656 {
657   __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
658   __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
659   __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
660   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
661   __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
662   __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
663   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
664   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
665   __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
666   __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
667   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
668   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
669   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
670   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
671   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
672   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
673   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
674   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
675   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
676   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
677   __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
678   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
679   __IO uint32_t CCR5;        /*!< TIM capture/compare register5,       Address offset: 0x58 */
680   __IO uint32_t CCR6;        /*!< TIM capture/compare register 4,      Address offset: 0x5C */
681 } TIM_TypeDef;
682 
683 /**
684   * @brief Touch Sensing Controller (TSC)
685   */
686 typedef struct
687 {
688   __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
689   __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
690   __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
691   __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
692   __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
693   uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
694   __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
695   uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
696   __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
697   uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
698   __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
699   uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
700   __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
701   __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
702 } TSC_TypeDef;
703 
704 /**
705   * @brief Universal Synchronous Asynchronous Receiver Transmitter
706   */
707 
708 typedef struct
709 {
710   __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
711   __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
712   __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
713   __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
714   __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
715   __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
716   __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
717   __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
718   __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
719   __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
720   uint16_t  RESERVED1;  /*!< Reserved, 0x26                                                 */
721   __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
722   uint16_t  RESERVED2;  /*!< Reserved, 0x2A                                                 */
723 } USART_TypeDef;
724 
725 /**
726   * @brief Window WATCHDOG
727   */
728 typedef struct
729 {
730   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
731   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
732   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
733 } WWDG_TypeDef;
734 
735 /** @addtogroup Peripheral_memory_map
736   * @{
737   */
738 
739 #define FLASH_BASE            0x08000000UL /*!< FLASH base address in the alias region */
740 #define CCMDATARAM_BASE       0x10000000UL /*!< CCM(core coupled memory) data RAM base address in the alias region     */
741 #define SRAM_BASE             0x20000000UL /*!< SRAM base address in the alias region */
742 #define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region */
743 #define SRAM_BB_BASE          0x22000000UL /*!< SRAM base address in the bit-band region */
744 #define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region */
745 
746 
747 /*!< Peripheral memory map */
748 #define APB1PERIPH_BASE       PERIPH_BASE
749 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
750 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
751 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
752 #define AHB3PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
753 
754 /*!< APB1 peripherals */
755 #define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
756 #define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
757 #define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
758 #define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
759 #define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
760 #define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
761 #define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
762 #define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
763 #define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
764 #define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
765 #define CAN_BASE              (APB1PERIPH_BASE + 0x00006400UL)
766 #define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
767 #define DAC1_BASE             (APB1PERIPH_BASE + 0x00007400UL)
768 #define DAC2_BASE             (APB1PERIPH_BASE + 0x00009800UL)
769 #define DAC_BASE               DAC1_BASE
770 
771 /*!< APB2 peripherals */
772 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
773 #define COMP2_BASE            (APB2PERIPH_BASE + 0x00000020UL)
774 #define COMP4_BASE            (APB2PERIPH_BASE + 0x00000028UL)
775 #define COMP6_BASE            (APB2PERIPH_BASE + 0x00000030UL)
776 #define COMP_BASE             COMP2_BASE
777 #define OPAMP2_BASE           (APB2PERIPH_BASE + 0x0000003CUL)
778 #define OPAMP_BASE            OPAMP2_BASE
779 #define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
780 #define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00UL)
781 #define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
782 #define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
783 #define TIM15_BASE            (APB2PERIPH_BASE + 0x00004000UL)
784 #define TIM16_BASE            (APB2PERIPH_BASE + 0x00004400UL)
785 #define TIM17_BASE            (APB2PERIPH_BASE + 0x00004800UL)
786 #define HRTIM1_BASE           (APB2PERIPH_BASE + 0x00007400UL)
787 #define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)
788 #define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)
789 #define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)
790 #define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)
791 #define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)
792 #define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)
793 
794 /*!< AHB1 peripherals */
795 #define DMA1_BASE             (AHB1PERIPH_BASE + 0x00000000UL)
796 #define DMA1_Channel1_BASE    (AHB1PERIPH_BASE + 0x00000008UL)
797 #define DMA1_Channel2_BASE    (AHB1PERIPH_BASE + 0x0000001CUL)
798 #define DMA1_Channel3_BASE    (AHB1PERIPH_BASE + 0x00000030UL)
799 #define DMA1_Channel4_BASE    (AHB1PERIPH_BASE + 0x00000044UL)
800 #define DMA1_Channel5_BASE    (AHB1PERIPH_BASE + 0x00000058UL)
801 #define DMA1_Channel6_BASE    (AHB1PERIPH_BASE + 0x0000006CUL)
802 #define DMA1_Channel7_BASE    (AHB1PERIPH_BASE + 0x00000080UL)
803 #define RCC_BASE              (AHB1PERIPH_BASE + 0x00001000UL)
804 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */
805 #define OB_BASE               0x1FFFF800UL         /*!< Flash Option Bytes base address */
806 #define FLASHSIZE_BASE        0x1FFFF7CCUL         /*!< FLASH Size register base address */
807 #define UID_BASE              0x1FFFF7ACUL         /*!< Unique device ID register base address */
808 #define CRC_BASE              (AHB1PERIPH_BASE + 0x00003000UL)
809 #define TSC_BASE              (AHB1PERIPH_BASE + 0x00004000UL)
810 
811 /*!< AHB2 peripherals */
812 #define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000UL)
813 #define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400UL)
814 #define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800UL)
815 #define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00UL)
816 #define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400UL)
817 
818 /*!< AHB3 peripherals */
819 #define ADC1_BASE             (AHB3PERIPH_BASE + 0x00000000UL)
820 #define ADC2_BASE             (AHB3PERIPH_BASE + 0x00000100UL)
821 #define ADC1_2_COMMON_BASE    (AHB3PERIPH_BASE + 0x00000300UL)
822 
823 #define DBGMCU_BASE           0xE0042000UL /*!< Debug MCU registers base address */
824 /**
825   * @}
826   */
827 
828 /** @addtogroup Peripheral_declaration
829   * @{
830   */
831 #define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)
832 #define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
833 #define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
834 #define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
835 #define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
836 #define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
837 #define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
838 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
839 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
840 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
841 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
842 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
843 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
844 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
845 #define USART2              ((USART_TypeDef *) USART2_BASE)
846 #define USART3              ((USART_TypeDef *) USART3_BASE)
847 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
848 #define CAN                 ((CAN_TypeDef *) CAN_BASE)
849 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
850 #define DAC                 ((DAC_TypeDef *) DAC_BASE)
851 #define DAC1                ((DAC_TypeDef *) DAC1_BASE)
852 #define DAC2                ((DAC_TypeDef *) DAC2_BASE)
853 #define COMP2               ((COMP_TypeDef *) COMP2_BASE)
854 #define COMP4               ((COMP_TypeDef *) COMP4_BASE)
855 #define COMP6               ((COMP_TypeDef *) COMP6_BASE)
856 /* Legacy define */
857 #define COMP                ((COMP_TypeDef *) COMP_BASE)
858 #define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
859 #define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
860 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
861 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
862 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
863 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
864 #define USART1              ((USART_TypeDef *) USART1_BASE)
865 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
866 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
867 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
868 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
869 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
870 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
871 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
872 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
873 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
874 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
875 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
876 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
877 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
878 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
879 #define OB                  ((OB_TypeDef *) OB_BASE)
880 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
881 #define TSC                 ((TSC_TypeDef *) TSC_BASE)
882 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
883 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
884 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
885 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
886 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
887 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
888 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
889 #define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
890 /* Legacy defines */
891 #define ADC1_2_COMMON       ADC12_COMMON
892 
893 /**
894   * @}
895   */
896 
897 /** @addtogroup Exported_constants
898   * @{
899   */
900 
901   /** @addtogroup Hardware_Constant_Definition
902     * @{
903     */
904 #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */
905 
906   /**
907     * @}
908     */
909 
910   /** @addtogroup Peripheral_Registers_Bits_Definition
911   * @{
912   */
913 
914 /******************************************************************************/
915 /*                         Peripheral Registers_Bits_Definition               */
916 /******************************************************************************/
917 
918 /******************************************************************************/
919 /*                                                                            */
920 /*                        Analog to Digital Converter SAR (ADC)               */
921 /*                                                                            */
922 /******************************************************************************/
923 
924 #define ADC5_V1_1                                      /*!< ADC IP version */
925 
926 /*
927  * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
928  */
929 #define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
930 
931 /********************  Bit definition for ADC_ISR register  ********************/
932 #define ADC_ISR_ADRDY_Pos              (0U)
933 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)             /*!< 0x00000001 */
934 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
935 #define ADC_ISR_EOSMP_Pos              (1U)
936 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)             /*!< 0x00000002 */
937 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
938 #define ADC_ISR_EOC_Pos                (2U)
939 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)               /*!< 0x00000004 */
940 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
941 #define ADC_ISR_EOS_Pos                (3U)
942 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)               /*!< 0x00000008 */
943 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
944 #define ADC_ISR_OVR_Pos                (4U)
945 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)               /*!< 0x00000010 */
946 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
947 #define ADC_ISR_JEOC_Pos               (5U)
948 #define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)              /*!< 0x00000020 */
949 #define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
950 #define ADC_ISR_JEOS_Pos               (6U)
951 #define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)              /*!< 0x00000040 */
952 #define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
953 #define ADC_ISR_AWD1_Pos               (7U)
954 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)              /*!< 0x00000080 */
955 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
956 #define ADC_ISR_AWD2_Pos               (8U)
957 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)              /*!< 0x00000100 */
958 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
959 #define ADC_ISR_AWD3_Pos               (9U)
960 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)              /*!< 0x00000200 */
961 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
962 #define ADC_ISR_JQOVF_Pos              (10U)
963 #define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)             /*!< 0x00000400 */
964 #define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
965 
966 /* Legacy defines */
967 #define ADC_ISR_ADRD            (ADC_ISR_ADRDY)
968 
969 /********************  Bit definition for ADC_IER register  ********************/
970 #define ADC_IER_ADRDYIE_Pos            (0U)
971 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)           /*!< 0x00000001 */
972 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
973 #define ADC_IER_EOSMPIE_Pos            (1U)
974 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)           /*!< 0x00000002 */
975 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
976 #define ADC_IER_EOCIE_Pos              (2U)
977 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)             /*!< 0x00000004 */
978 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
979 #define ADC_IER_EOSIE_Pos              (3U)
980 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)             /*!< 0x00000008 */
981 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
982 #define ADC_IER_OVRIE_Pos              (4U)
983 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)             /*!< 0x00000010 */
984 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
985 #define ADC_IER_JEOCIE_Pos             (5U)
986 #define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)            /*!< 0x00000020 */
987 #define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
988 #define ADC_IER_JEOSIE_Pos             (6U)
989 #define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)            /*!< 0x00000040 */
990 #define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
991 #define ADC_IER_AWD1IE_Pos             (7U)
992 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)            /*!< 0x00000080 */
993 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
994 #define ADC_IER_AWD2IE_Pos             (8U)
995 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)            /*!< 0x00000100 */
996 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
997 #define ADC_IER_AWD3IE_Pos             (9U)
998 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)            /*!< 0x00000200 */
999 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
1000 #define ADC_IER_JQOVFIE_Pos            (10U)
1001 #define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)           /*!< 0x00000400 */
1002 #define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
1003 
1004 /* Legacy defines */
1005 #define ADC_IER_RDY             (ADC_IER_ADRDYIE)
1006 #define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)
1007 #define ADC_IER_EOC             (ADC_IER_EOCIE)
1008 #define ADC_IER_EOS             (ADC_IER_EOSIE)
1009 #define ADC_IER_OVR             (ADC_IER_OVRIE)
1010 #define ADC_IER_JEOC            (ADC_IER_JEOCIE)
1011 #define ADC_IER_JEOS            (ADC_IER_JEOSIE)
1012 #define ADC_IER_AWD1            (ADC_IER_AWD1IE)
1013 #define ADC_IER_AWD2            (ADC_IER_AWD2IE)
1014 #define ADC_IER_AWD3            (ADC_IER_AWD3IE)
1015 #define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)
1016 
1017 /********************  Bit definition for ADC_CR register  ********************/
1018 #define ADC_CR_ADEN_Pos                (0U)
1019 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)               /*!< 0x00000001 */
1020 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
1021 #define ADC_CR_ADDIS_Pos               (1U)
1022 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)              /*!< 0x00000002 */
1023 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
1024 #define ADC_CR_ADSTART_Pos             (2U)
1025 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)            /*!< 0x00000004 */
1026 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
1027 #define ADC_CR_JADSTART_Pos            (3U)
1028 #define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)           /*!< 0x00000008 */
1029 #define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
1030 #define ADC_CR_ADSTP_Pos               (4U)
1031 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)              /*!< 0x00000010 */
1032 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
1033 #define ADC_CR_JADSTP_Pos              (5U)
1034 #define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)             /*!< 0x00000020 */
1035 #define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
1036 #define ADC_CR_ADVREGEN_Pos            (28U)
1037 #define ADC_CR_ADVREGEN_Msk            (0x3UL << ADC_CR_ADVREGEN_Pos)           /*!< 0x30000000 */
1038 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
1039 #define ADC_CR_ADVREGEN_0              (0x1UL << ADC_CR_ADVREGEN_Pos)           /*!< 0x10000000 */
1040 #define ADC_CR_ADVREGEN_1              (0x2UL << ADC_CR_ADVREGEN_Pos)           /*!< 0x20000000 */
1041 #define ADC_CR_ADCALDIF_Pos            (30U)
1042 #define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)           /*!< 0x40000000 */
1043 #define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
1044 #define ADC_CR_ADCAL_Pos               (31U)
1045 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)              /*!< 0x80000000 */
1046 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1047 
1048 /********************  Bit definition for ADC_CFGR register  ******************/
1049 #define ADC_CFGR_DMAEN_Pos             (0U)
1050 #define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)            /*!< 0x00000001 */
1051 #define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA enable */
1052 #define ADC_CFGR_DMACFG_Pos            (1U)
1053 #define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)           /*!< 0x00000002 */
1054 #define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA configuration */
1055 
1056 #define ADC_CFGR_RES_Pos               (3U)
1057 #define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)              /*!< 0x00000018 */
1058 #define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
1059 #define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)              /*!< 0x00000008 */
1060 #define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)              /*!< 0x00000010 */
1061 
1062 #define ADC_CFGR_ALIGN_Pos             (5U)
1063 #define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)            /*!< 0x00000020 */
1064 #define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */
1065 
1066 #define ADC_CFGR_EXTSEL_Pos            (6U)
1067 #define ADC_CFGR_EXTSEL_Msk            (0xFUL << ADC_CFGR_EXTSEL_Pos)           /*!< 0x000003C0 */
1068 #define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
1069 #define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000040 */
1070 #define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000080 */
1071 #define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000100 */
1072 #define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000200 */
1073 
1074 #define ADC_CFGR_EXTEN_Pos             (10U)
1075 #define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000C00 */
1076 #define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
1077 #define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000400 */
1078 #define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000800 */
1079 
1080 #define ADC_CFGR_OVRMOD_Pos            (12U)
1081 #define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)           /*!< 0x00001000 */
1082 #define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
1083 #define ADC_CFGR_CONT_Pos              (13U)
1084 #define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)             /*!< 0x00002000 */
1085 #define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
1086 #define ADC_CFGR_AUTDLY_Pos            (14U)
1087 #define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)           /*!< 0x00004000 */
1088 #define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
1089 
1090 #define ADC_CFGR_DISCEN_Pos            (16U)
1091 #define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)           /*!< 0x00010000 */
1092 #define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
1093 
1094 #define ADC_CFGR_DISCNUM_Pos           (17U)
1095 #define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)          /*!< 0x000E0000 */
1096 #define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC Discontinuous mode channel count */
1097 #define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00020000 */
1098 #define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00040000 */
1099 #define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00080000 */
1100 
1101 #define ADC_CFGR_JDISCEN_Pos           (20U)
1102 #define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)          /*!< 0x00100000 */
1103 #define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC Discontinuous mode on injected channels */
1104 #define ADC_CFGR_JQM_Pos               (21U)
1105 #define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)              /*!< 0x00200000 */
1106 #define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
1107 #define ADC_CFGR_AWD1SGL_Pos           (22U)
1108 #define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)          /*!< 0x00400000 */
1109 #define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1110 #define ADC_CFGR_AWD1EN_Pos            (23U)
1111 #define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)           /*!< 0x00800000 */
1112 #define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1113 #define ADC_CFGR_JAWD1EN_Pos           (24U)
1114 #define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)          /*!< 0x01000000 */
1115 #define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1116 #define ADC_CFGR_JAUTO_Pos             (25U)
1117 #define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)            /*!< 0x02000000 */
1118 #define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
1119 
1120 #define ADC_CFGR_AWD1CH_Pos            (26U)
1121 #define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)          /*!< 0x7C000000 */
1122 #define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
1123 #define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)          /*!< 0x04000000 */
1124 #define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)          /*!< 0x08000000 */
1125 #define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)          /*!< 0x10000000 */
1126 #define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)          /*!< 0x20000000 */
1127 #define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)          /*!< 0x40000000 */
1128 
1129 /* Legacy defines */
1130 #define ADC_CFGR_AUTOFF_Pos            (15U)
1131 #define ADC_CFGR_AUTOFF_Msk            (0x1UL << ADC_CFGR_AUTOFF_Pos)           /*!< 0x00008000 */
1132 #define ADC_CFGR_AUTOFF                ADC_CFGR_AUTOFF_Msk                     /*!< ADC low power auto power off */
1133 
1134 /********************  Bit definition for ADC_SMPR1 register  *****************/
1135 #define ADC_SMPR1_SMP0_Pos             (0U)
1136 #define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000007 */
1137 #define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
1138 #define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000001 */
1139 #define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000002 */
1140 #define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000004 */
1141 
1142 #define ADC_SMPR1_SMP1_Pos             (3U)
1143 #define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000038 */
1144 #define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
1145 #define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000008 */
1146 #define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000010 */
1147 #define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000020 */
1148 
1149 #define ADC_SMPR1_SMP2_Pos             (6U)
1150 #define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)            /*!< 0x000001C0 */
1151 #define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
1152 #define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000040 */
1153 #define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000080 */
1154 #define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000100 */
1155 
1156 #define ADC_SMPR1_SMP3_Pos             (9U)
1157 #define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000E00 */
1158 #define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
1159 #define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000200 */
1160 #define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000400 */
1161 #define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000800 */
1162 
1163 #define ADC_SMPR1_SMP4_Pos             (12U)
1164 #define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)            /*!< 0x00007000 */
1165 #define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
1166 #define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)            /*!< 0x00001000 */
1167 #define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)            /*!< 0x00002000 */
1168 #define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)            /*!< 0x00004000 */
1169 
1170 #define ADC_SMPR1_SMP5_Pos             (15U)
1171 #define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)            /*!< 0x00038000 */
1172 #define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
1173 #define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)            /*!< 0x00008000 */
1174 #define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)            /*!< 0x00010000 */
1175 #define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)            /*!< 0x00020000 */
1176 
1177 #define ADC_SMPR1_SMP6_Pos             (18U)
1178 #define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)            /*!< 0x001C0000 */
1179 #define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
1180 #define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)            /*!< 0x00040000 */
1181 #define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)            /*!< 0x00080000 */
1182 #define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)            /*!< 0x00100000 */
1183 
1184 #define ADC_SMPR1_SMP7_Pos             (21U)
1185 #define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)            /*!< 0x00E00000 */
1186 #define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
1187 #define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)            /*!< 0x00200000 */
1188 #define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)            /*!< 0x00400000 */
1189 #define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)            /*!< 0x00800000 */
1190 
1191 #define ADC_SMPR1_SMP8_Pos             (24U)
1192 #define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)            /*!< 0x07000000 */
1193 #define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
1194 #define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)            /*!< 0x01000000 */
1195 #define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)            /*!< 0x02000000 */
1196 #define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)            /*!< 0x04000000 */
1197 
1198 #define ADC_SMPR1_SMP9_Pos             (27U)
1199 #define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)            /*!< 0x38000000 */
1200 #define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
1201 #define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)            /*!< 0x08000000 */
1202 #define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)            /*!< 0x10000000 */
1203 #define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)            /*!< 0x20000000 */
1204 
1205 /********************  Bit definition for ADC_SMPR2 register  *****************/
1206 #define ADC_SMPR2_SMP10_Pos            (0U)
1207 #define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000007 */
1208 #define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
1209 #define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000001 */
1210 #define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000002 */
1211 #define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000004 */
1212 
1213 #define ADC_SMPR2_SMP11_Pos            (3U)
1214 #define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000038 */
1215 #define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
1216 #define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000008 */
1217 #define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000010 */
1218 #define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000020 */
1219 
1220 #define ADC_SMPR2_SMP12_Pos            (6U)
1221 #define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)           /*!< 0x000001C0 */
1222 #define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
1223 #define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000040 */
1224 #define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000080 */
1225 #define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000100 */
1226 
1227 #define ADC_SMPR2_SMP13_Pos            (9U)
1228 #define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000E00 */
1229 #define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
1230 #define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000200 */
1231 #define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000400 */
1232 #define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000800 */
1233 
1234 #define ADC_SMPR2_SMP14_Pos            (12U)
1235 #define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)           /*!< 0x00007000 */
1236 #define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
1237 #define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)           /*!< 0x00001000 */
1238 #define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)           /*!< 0x00002000 */
1239 #define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)           /*!< 0x00004000 */
1240 
1241 #define ADC_SMPR2_SMP15_Pos            (15U)
1242 #define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)           /*!< 0x00038000 */
1243 #define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
1244 #define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)           /*!< 0x00008000 */
1245 #define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)           /*!< 0x00010000 */
1246 #define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)           /*!< 0x00020000 */
1247 
1248 #define ADC_SMPR2_SMP16_Pos            (18U)
1249 #define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)           /*!< 0x001C0000 */
1250 #define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
1251 #define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)           /*!< 0x00040000 */
1252 #define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)           /*!< 0x00080000 */
1253 #define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)           /*!< 0x00100000 */
1254 
1255 #define ADC_SMPR2_SMP17_Pos            (21U)
1256 #define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)           /*!< 0x00E00000 */
1257 #define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
1258 #define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)           /*!< 0x00200000 */
1259 #define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)           /*!< 0x00400000 */
1260 #define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)           /*!< 0x00800000 */
1261 
1262 #define ADC_SMPR2_SMP18_Pos            (24U)
1263 #define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)           /*!< 0x07000000 */
1264 #define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
1265 #define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)           /*!< 0x01000000 */
1266 #define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)           /*!< 0x02000000 */
1267 #define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)           /*!< 0x04000000 */
1268 
1269 /********************  Bit definition for ADC_TR1 register  *******************/
1270 #define ADC_TR1_LT1_Pos                (0U)
1271 #define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)             /*!< 0x00000FFF */
1272 #define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
1273 #define ADC_TR1_LT1_0                  (0x001UL << ADC_TR1_LT1_Pos)             /*!< 0x00000001 */
1274 #define ADC_TR1_LT1_1                  (0x002UL << ADC_TR1_LT1_Pos)             /*!< 0x00000002 */
1275 #define ADC_TR1_LT1_2                  (0x004UL << ADC_TR1_LT1_Pos)             /*!< 0x00000004 */
1276 #define ADC_TR1_LT1_3                  (0x008UL << ADC_TR1_LT1_Pos)             /*!< 0x00000008 */
1277 #define ADC_TR1_LT1_4                  (0x010UL << ADC_TR1_LT1_Pos)             /*!< 0x00000010 */
1278 #define ADC_TR1_LT1_5                  (0x020UL << ADC_TR1_LT1_Pos)             /*!< 0x00000020 */
1279 #define ADC_TR1_LT1_6                  (0x040UL << ADC_TR1_LT1_Pos)             /*!< 0x00000040 */
1280 #define ADC_TR1_LT1_7                  (0x080UL << ADC_TR1_LT1_Pos)             /*!< 0x00000080 */
1281 #define ADC_TR1_LT1_8                  (0x100UL << ADC_TR1_LT1_Pos)             /*!< 0x00000100 */
1282 #define ADC_TR1_LT1_9                  (0x200UL << ADC_TR1_LT1_Pos)             /*!< 0x00000200 */
1283 #define ADC_TR1_LT1_10                 (0x400UL << ADC_TR1_LT1_Pos)             /*!< 0x00000400 */
1284 #define ADC_TR1_LT1_11                 (0x800UL << ADC_TR1_LT1_Pos)             /*!< 0x00000800 */
1285 
1286 #define ADC_TR1_HT1_Pos                (16U)
1287 #define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)             /*!< 0x0FFF0000 */
1288 #define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
1289 #define ADC_TR1_HT1_0                  (0x001UL << ADC_TR1_HT1_Pos)             /*!< 0x00010000 */
1290 #define ADC_TR1_HT1_1                  (0x002UL << ADC_TR1_HT1_Pos)             /*!< 0x00020000 */
1291 #define ADC_TR1_HT1_2                  (0x004UL << ADC_TR1_HT1_Pos)             /*!< 0x00040000 */
1292 #define ADC_TR1_HT1_3                  (0x008UL << ADC_TR1_HT1_Pos)             /*!< 0x00080000 */
1293 #define ADC_TR1_HT1_4                  (0x010UL << ADC_TR1_HT1_Pos)             /*!< 0x00100000 */
1294 #define ADC_TR1_HT1_5                  (0x020UL << ADC_TR1_HT1_Pos)             /*!< 0x00200000 */
1295 #define ADC_TR1_HT1_6                  (0x040UL << ADC_TR1_HT1_Pos)             /*!< 0x00400000 */
1296 #define ADC_TR1_HT1_7                  (0x080UL << ADC_TR1_HT1_Pos)             /*!< 0x00800000 */
1297 #define ADC_TR1_HT1_8                  (0x100UL << ADC_TR1_HT1_Pos)             /*!< 0x01000000 */
1298 #define ADC_TR1_HT1_9                  (0x200UL << ADC_TR1_HT1_Pos)             /*!< 0x02000000 */
1299 #define ADC_TR1_HT1_10                 (0x400UL << ADC_TR1_HT1_Pos)             /*!< 0x04000000 */
1300 #define ADC_TR1_HT1_11                 (0x800UL << ADC_TR1_HT1_Pos)             /*!< 0x08000000 */
1301 
1302 /********************  Bit definition for ADC_TR2 register  *******************/
1303 #define ADC_TR2_LT2_Pos                (0U)
1304 #define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)              /*!< 0x000000FF */
1305 #define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
1306 #define ADC_TR2_LT2_0                  (0x01UL << ADC_TR2_LT2_Pos)              /*!< 0x00000001 */
1307 #define ADC_TR2_LT2_1                  (0x02UL << ADC_TR2_LT2_Pos)              /*!< 0x00000002 */
1308 #define ADC_TR2_LT2_2                  (0x04UL << ADC_TR2_LT2_Pos)              /*!< 0x00000004 */
1309 #define ADC_TR2_LT2_3                  (0x08UL << ADC_TR2_LT2_Pos)              /*!< 0x00000008 */
1310 #define ADC_TR2_LT2_4                  (0x10UL << ADC_TR2_LT2_Pos)              /*!< 0x00000010 */
1311 #define ADC_TR2_LT2_5                  (0x20UL << ADC_TR2_LT2_Pos)              /*!< 0x00000020 */
1312 #define ADC_TR2_LT2_6                  (0x40UL << ADC_TR2_LT2_Pos)              /*!< 0x00000040 */
1313 #define ADC_TR2_LT2_7                  (0x80UL << ADC_TR2_LT2_Pos)              /*!< 0x00000080 */
1314 
1315 #define ADC_TR2_HT2_Pos                (16U)
1316 #define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)              /*!< 0x00FF0000 */
1317 #define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
1318 #define ADC_TR2_HT2_0                  (0x01UL << ADC_TR2_HT2_Pos)              /*!< 0x00010000 */
1319 #define ADC_TR2_HT2_1                  (0x02UL << ADC_TR2_HT2_Pos)              /*!< 0x00020000 */
1320 #define ADC_TR2_HT2_2                  (0x04UL << ADC_TR2_HT2_Pos)              /*!< 0x00040000 */
1321 #define ADC_TR2_HT2_3                  (0x08UL << ADC_TR2_HT2_Pos)              /*!< 0x00080000 */
1322 #define ADC_TR2_HT2_4                  (0x10UL << ADC_TR2_HT2_Pos)              /*!< 0x00100000 */
1323 #define ADC_TR2_HT2_5                  (0x20UL << ADC_TR2_HT2_Pos)              /*!< 0x00200000 */
1324 #define ADC_TR2_HT2_6                  (0x40UL << ADC_TR2_HT2_Pos)              /*!< 0x00400000 */
1325 #define ADC_TR2_HT2_7                  (0x80UL << ADC_TR2_HT2_Pos)              /*!< 0x00800000 */
1326 
1327 /********************  Bit definition for ADC_TR3 register  *******************/
1328 #define ADC_TR3_LT3_Pos                (0U)
1329 #define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)              /*!< 0x000000FF */
1330 #define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
1331 #define ADC_TR3_LT3_0                  (0x01UL << ADC_TR3_LT3_Pos)              /*!< 0x00000001 */
1332 #define ADC_TR3_LT3_1                  (0x02UL << ADC_TR3_LT3_Pos)              /*!< 0x00000002 */
1333 #define ADC_TR3_LT3_2                  (0x04UL << ADC_TR3_LT3_Pos)              /*!< 0x00000004 */
1334 #define ADC_TR3_LT3_3                  (0x08UL << ADC_TR3_LT3_Pos)              /*!< 0x00000008 */
1335 #define ADC_TR3_LT3_4                  (0x10UL << ADC_TR3_LT3_Pos)              /*!< 0x00000010 */
1336 #define ADC_TR3_LT3_5                  (0x20UL << ADC_TR3_LT3_Pos)              /*!< 0x00000020 */
1337 #define ADC_TR3_LT3_6                  (0x40UL << ADC_TR3_LT3_Pos)              /*!< 0x00000040 */
1338 #define ADC_TR3_LT3_7                  (0x80UL << ADC_TR3_LT3_Pos)              /*!< 0x00000080 */
1339 
1340 #define ADC_TR3_HT3_Pos                (16U)
1341 #define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)              /*!< 0x00FF0000 */
1342 #define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
1343 #define ADC_TR3_HT3_0                  (0x01UL << ADC_TR3_HT3_Pos)              /*!< 0x00010000 */
1344 #define ADC_TR3_HT3_1                  (0x02UL << ADC_TR3_HT3_Pos)              /*!< 0x00020000 */
1345 #define ADC_TR3_HT3_2                  (0x04UL << ADC_TR3_HT3_Pos)              /*!< 0x00040000 */
1346 #define ADC_TR3_HT3_3                  (0x08UL << ADC_TR3_HT3_Pos)              /*!< 0x00080000 */
1347 #define ADC_TR3_HT3_4                  (0x10UL << ADC_TR3_HT3_Pos)              /*!< 0x00100000 */
1348 #define ADC_TR3_HT3_5                  (0x20UL << ADC_TR3_HT3_Pos)              /*!< 0x00200000 */
1349 #define ADC_TR3_HT3_6                  (0x40UL << ADC_TR3_HT3_Pos)              /*!< 0x00400000 */
1350 #define ADC_TR3_HT3_7                  (0x80UL << ADC_TR3_HT3_Pos)              /*!< 0x00800000 */
1351 
1352 /********************  Bit definition for ADC_SQR1 register  ******************/
1353 #define ADC_SQR1_L_Pos                 (0U)
1354 #define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)                /*!< 0x0000000F */
1355 #define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
1356 #define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)                /*!< 0x00000001 */
1357 #define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)                /*!< 0x00000002 */
1358 #define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)                /*!< 0x00000004 */
1359 #define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)                /*!< 0x00000008 */
1360 
1361 #define ADC_SQR1_SQ1_Pos               (6U)
1362 #define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)             /*!< 0x000007C0 */
1363 #define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
1364 #define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)             /*!< 0x00000040 */
1365 #define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)             /*!< 0x00000080 */
1366 #define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)             /*!< 0x00000100 */
1367 #define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)             /*!< 0x00000200 */
1368 #define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)             /*!< 0x00000400 */
1369 
1370 #define ADC_SQR1_SQ2_Pos               (12U)
1371 #define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)             /*!< 0x0001F000 */
1372 #define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
1373 #define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)             /*!< 0x00001000 */
1374 #define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)             /*!< 0x00002000 */
1375 #define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)             /*!< 0x00004000 */
1376 #define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)             /*!< 0x00008000 */
1377 #define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)             /*!< 0x00010000 */
1378 
1379 #define ADC_SQR1_SQ3_Pos               (18U)
1380 #define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)             /*!< 0x007C0000 */
1381 #define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
1382 #define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)             /*!< 0x00040000 */
1383 #define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)             /*!< 0x00080000 */
1384 #define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)             /*!< 0x00100000 */
1385 #define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)             /*!< 0x00200000 */
1386 #define ADC_SQR1_SQ3_4                 (0x10UL << ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
1387 
1388 #define ADC_SQR1_SQ4_Pos               (24U)
1389 #define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)             /*!< 0x1F000000 */
1390 #define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
1391 #define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)             /*!< 0x01000000 */
1392 #define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)             /*!< 0x02000000 */
1393 #define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)             /*!< 0x04000000 */
1394 #define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)             /*!< 0x08000000 */
1395 #define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)             /*!< 0x10000000 */
1396 
1397 /********************  Bit definition for ADC_SQR2 register  ******************/
1398 #define ADC_SQR2_SQ5_Pos               (0U)
1399 #define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)             /*!< 0x0000001F */
1400 #define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
1401 #define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)             /*!< 0x00000001 */
1402 #define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)             /*!< 0x00000002 */
1403 #define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)             /*!< 0x00000004 */
1404 #define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)             /*!< 0x00000008 */
1405 #define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)             /*!< 0x00000010 */
1406 
1407 #define ADC_SQR2_SQ6_Pos               (6U)
1408 #define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)             /*!< 0x000007C0 */
1409 #define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
1410 #define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)             /*!< 0x00000040 */
1411 #define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)             /*!< 0x00000080 */
1412 #define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)             /*!< 0x00000100 */
1413 #define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)             /*!< 0x00000200 */
1414 #define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)             /*!< 0x00000400 */
1415 
1416 #define ADC_SQR2_SQ7_Pos               (12U)
1417 #define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)             /*!< 0x0001F000 */
1418 #define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
1419 #define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)             /*!< 0x00001000 */
1420 #define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)             /*!< 0x00002000 */
1421 #define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)             /*!< 0x00004000 */
1422 #define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)             /*!< 0x00008000 */
1423 #define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)             /*!< 0x00010000 */
1424 
1425 #define ADC_SQR2_SQ8_Pos               (18U)
1426 #define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)             /*!< 0x007C0000 */
1427 #define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
1428 #define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)             /*!< 0x00040000 */
1429 #define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)             /*!< 0x00080000 */
1430 #define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)             /*!< 0x00100000 */
1431 #define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)             /*!< 0x00200000 */
1432 #define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)             /*!< 0x00400000 */
1433 
1434 #define ADC_SQR2_SQ9_Pos               (24U)
1435 #define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)             /*!< 0x1F000000 */
1436 #define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
1437 #define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)             /*!< 0x01000000 */
1438 #define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)             /*!< 0x02000000 */
1439 #define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)             /*!< 0x04000000 */
1440 #define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)             /*!< 0x08000000 */
1441 #define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)             /*!< 0x10000000 */
1442 
1443 /********************  Bit definition for ADC_SQR3 register  ******************/
1444 #define ADC_SQR3_SQ10_Pos              (0U)
1445 #define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)            /*!< 0x0000001F */
1446 #define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
1447 #define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)            /*!< 0x00000001 */
1448 #define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)            /*!< 0x00000002 */
1449 #define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)            /*!< 0x00000004 */
1450 #define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)            /*!< 0x00000008 */
1451 #define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)            /*!< 0x00000010 */
1452 
1453 #define ADC_SQR3_SQ11_Pos              (6U)
1454 #define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)            /*!< 0x000007C0 */
1455 #define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
1456 #define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)            /*!< 0x00000040 */
1457 #define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)            /*!< 0x00000080 */
1458 #define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)            /*!< 0x00000100 */
1459 #define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)            /*!< 0x00000200 */
1460 #define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)            /*!< 0x00000400 */
1461 
1462 #define ADC_SQR3_SQ12_Pos              (12U)
1463 #define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)            /*!< 0x0001F000 */
1464 #define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
1465 #define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)            /*!< 0x00001000 */
1466 #define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)            /*!< 0x00002000 */
1467 #define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)            /*!< 0x00004000 */
1468 #define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)            /*!< 0x00008000 */
1469 #define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)            /*!< 0x00010000 */
1470 
1471 #define ADC_SQR3_SQ13_Pos              (18U)
1472 #define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)            /*!< 0x007C0000 */
1473 #define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
1474 #define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)            /*!< 0x00040000 */
1475 #define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)            /*!< 0x00080000 */
1476 #define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)            /*!< 0x00100000 */
1477 #define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)            /*!< 0x00200000 */
1478 #define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)            /*!< 0x00400000 */
1479 
1480 #define ADC_SQR3_SQ14_Pos              (24U)
1481 #define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)            /*!< 0x1F000000 */
1482 #define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
1483 #define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)            /*!< 0x01000000 */
1484 #define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)            /*!< 0x02000000 */
1485 #define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)            /*!< 0x04000000 */
1486 #define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)            /*!< 0x08000000 */
1487 #define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)            /*!< 0x10000000 */
1488 
1489 /********************  Bit definition for ADC_SQR4 register  ******************/
1490 #define ADC_SQR4_SQ15_Pos              (0U)
1491 #define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)            /*!< 0x0000001F */
1492 #define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
1493 #define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)            /*!< 0x00000001 */
1494 #define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)            /*!< 0x00000002 */
1495 #define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)            /*!< 0x00000004 */
1496 #define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)            /*!< 0x00000008 */
1497 #define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)            /*!< 0x00000010 */
1498 
1499 #define ADC_SQR4_SQ16_Pos              (6U)
1500 #define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)            /*!< 0x000007C0 */
1501 #define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
1502 #define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)            /*!< 0x00000040 */
1503 #define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)            /*!< 0x00000080 */
1504 #define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)            /*!< 0x00000100 */
1505 #define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)            /*!< 0x00000200 */
1506 #define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)            /*!< 0x00000400 */
1507 
1508 /********************  Bit definition for ADC_DR register  ********************/
1509 #define ADC_DR_RDATA_Pos               (0U)
1510 #define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)           /*!< 0x0000FFFF */
1511 #define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
1512 #define ADC_DR_RDATA_0                 (0x0001UL << ADC_DR_RDATA_Pos)           /*!< 0x00000001 */
1513 #define ADC_DR_RDATA_1                 (0x0002UL << ADC_DR_RDATA_Pos)           /*!< 0x00000002 */
1514 #define ADC_DR_RDATA_2                 (0x0004UL << ADC_DR_RDATA_Pos)           /*!< 0x00000004 */
1515 #define ADC_DR_RDATA_3                 (0x0008UL << ADC_DR_RDATA_Pos)           /*!< 0x00000008 */
1516 #define ADC_DR_RDATA_4                 (0x0010UL << ADC_DR_RDATA_Pos)           /*!< 0x00000010 */
1517 #define ADC_DR_RDATA_5                 (0x0020UL << ADC_DR_RDATA_Pos)           /*!< 0x00000020 */
1518 #define ADC_DR_RDATA_6                 (0x0040UL << ADC_DR_RDATA_Pos)           /*!< 0x00000040 */
1519 #define ADC_DR_RDATA_7                 (0x0080UL << ADC_DR_RDATA_Pos)           /*!< 0x00000080 */
1520 #define ADC_DR_RDATA_8                 (0x0100UL << ADC_DR_RDATA_Pos)           /*!< 0x00000100 */
1521 #define ADC_DR_RDATA_9                 (0x0200UL << ADC_DR_RDATA_Pos)           /*!< 0x00000200 */
1522 #define ADC_DR_RDATA_10                (0x0400UL << ADC_DR_RDATA_Pos)           /*!< 0x00000400 */
1523 #define ADC_DR_RDATA_11                (0x0800UL << ADC_DR_RDATA_Pos)           /*!< 0x00000800 */
1524 #define ADC_DR_RDATA_12                (0x1000UL << ADC_DR_RDATA_Pos)           /*!< 0x00001000 */
1525 #define ADC_DR_RDATA_13                (0x2000UL << ADC_DR_RDATA_Pos)           /*!< 0x00002000 */
1526 #define ADC_DR_RDATA_14                (0x4000UL << ADC_DR_RDATA_Pos)           /*!< 0x00004000 */
1527 #define ADC_DR_RDATA_15                (0x8000UL << ADC_DR_RDATA_Pos)           /*!< 0x00008000 */
1528 
1529 /********************  Bit definition for ADC_JSQR register  ******************/
1530 #define ADC_JSQR_JL_Pos                (0U)
1531 #define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)               /*!< 0x00000003 */
1532 #define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
1533 #define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)               /*!< 0x00000001 */
1534 #define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)               /*!< 0x00000002 */
1535 
1536 #define ADC_JSQR_JEXTSEL_Pos           (2U)
1537 #define ADC_JSQR_JEXTSEL_Msk           (0xFUL << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x0000003C */
1538 #define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
1539 #define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000004 */
1540 #define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000008 */
1541 #define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000010 */
1542 #define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000020 */
1543 
1544 #define ADC_JSQR_JEXTEN_Pos            (6U)
1545 #define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)           /*!< 0x000000C0 */
1546 #define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
1547 #define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000040 */
1548 #define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000080 */
1549 
1550 #define ADC_JSQR_JSQ1_Pos              (8U)
1551 #define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001F00 */
1552 #define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
1553 #define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000100 */
1554 #define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000200 */
1555 #define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000400 */
1556 #define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000800 */
1557 #define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001000 */
1558 
1559 #define ADC_JSQR_JSQ2_Pos              (14U)
1560 #define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)            /*!< 0x0007C000 */
1561 #define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
1562 #define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)            /*!< 0x00004000 */
1563 #define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)            /*!< 0x00008000 */
1564 #define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)            /*!< 0x00010000 */
1565 #define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)            /*!< 0x00020000 */
1566 #define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)            /*!< 0x00040000 */
1567 
1568 #define ADC_JSQR_JSQ3_Pos              (20U)
1569 #define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)            /*!< 0x01F00000 */
1570 #define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
1571 #define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)            /*!< 0x00100000 */
1572 #define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)            /*!< 0x00200000 */
1573 #define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)            /*!< 0x00400000 */
1574 #define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)            /*!< 0x00800000 */
1575 #define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)            /*!< 0x01000000 */
1576 
1577 #define ADC_JSQR_JSQ4_Pos              (26U)
1578 #define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)            /*!< 0x7C000000 */
1579 #define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
1580 #define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)            /*!< 0x04000000 */
1581 #define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)            /*!< 0x08000000 */
1582 #define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)            /*!< 0x10000000 */
1583 #define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)            /*!< 0x20000000 */
1584 #define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)            /*!< 0x40000000 */
1585 
1586 
1587 /********************  Bit definition for ADC_OFR1 register  ******************/
1588 #define ADC_OFR1_OFFSET1_Pos           (0U)
1589 #define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000FFF */
1590 #define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
1591 #define ADC_OFR1_OFFSET1_0             (0x001UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000001 */
1592 #define ADC_OFR1_OFFSET1_1             (0x002UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000002 */
1593 #define ADC_OFR1_OFFSET1_2             (0x004UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000004 */
1594 #define ADC_OFR1_OFFSET1_3             (0x008UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000008 */
1595 #define ADC_OFR1_OFFSET1_4             (0x010UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000010 */
1596 #define ADC_OFR1_OFFSET1_5             (0x020UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000020 */
1597 #define ADC_OFR1_OFFSET1_6             (0x040UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000040 */
1598 #define ADC_OFR1_OFFSET1_7             (0x080UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000080 */
1599 #define ADC_OFR1_OFFSET1_8             (0x100UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000100 */
1600 #define ADC_OFR1_OFFSET1_9             (0x200UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000200 */
1601 #define ADC_OFR1_OFFSET1_10            (0x400UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000400 */
1602 #define ADC_OFR1_OFFSET1_11            (0x800UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000800 */
1603 
1604 #define ADC_OFR1_OFFSET1_CH_Pos        (26U)
1605 #define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x7C000000 */
1606 #define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
1607 #define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x04000000 */
1608 #define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x08000000 */
1609 #define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x10000000 */
1610 #define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x20000000 */
1611 #define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x40000000 */
1612 
1613 #define ADC_OFR1_OFFSET1_EN_Pos        (31U)
1614 #define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)       /*!< 0x80000000 */
1615 #define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
1616 
1617 /********************  Bit definition for ADC_OFR2 register  ******************/
1618 #define ADC_OFR2_OFFSET2_Pos           (0U)
1619 #define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000FFF */
1620 #define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
1621 #define ADC_OFR2_OFFSET2_0             (0x001UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000001 */
1622 #define ADC_OFR2_OFFSET2_1             (0x002UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000002 */
1623 #define ADC_OFR2_OFFSET2_2             (0x004UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000004 */
1624 #define ADC_OFR2_OFFSET2_3             (0x008UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000008 */
1625 #define ADC_OFR2_OFFSET2_4             (0x010UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000010 */
1626 #define ADC_OFR2_OFFSET2_5             (0x020UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000020 */
1627 #define ADC_OFR2_OFFSET2_6             (0x040UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000040 */
1628 #define ADC_OFR2_OFFSET2_7             (0x080UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000080 */
1629 #define ADC_OFR2_OFFSET2_8             (0x100UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000100 */
1630 #define ADC_OFR2_OFFSET2_9             (0x200UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000200 */
1631 #define ADC_OFR2_OFFSET2_10            (0x400UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000400 */
1632 #define ADC_OFR2_OFFSET2_11            (0x800UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000800 */
1633 
1634 #define ADC_OFR2_OFFSET2_CH_Pos        (26U)
1635 #define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x7C000000 */
1636 #define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
1637 #define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x04000000 */
1638 #define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x08000000 */
1639 #define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x10000000 */
1640 #define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x20000000 */
1641 #define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x40000000 */
1642 
1643 #define ADC_OFR2_OFFSET2_EN_Pos        (31U)
1644 #define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)       /*!< 0x80000000 */
1645 #define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
1646 
1647 /********************  Bit definition for ADC_OFR3 register  ******************/
1648 #define ADC_OFR3_OFFSET3_Pos           (0U)
1649 #define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000FFF */
1650 #define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
1651 #define ADC_OFR3_OFFSET3_0             (0x001UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000001 */
1652 #define ADC_OFR3_OFFSET3_1             (0x002UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000002 */
1653 #define ADC_OFR3_OFFSET3_2             (0x004UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000004 */
1654 #define ADC_OFR3_OFFSET3_3             (0x008UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000008 */
1655 #define ADC_OFR3_OFFSET3_4             (0x010UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000010 */
1656 #define ADC_OFR3_OFFSET3_5             (0x020UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000020 */
1657 #define ADC_OFR3_OFFSET3_6             (0x040UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000040 */
1658 #define ADC_OFR3_OFFSET3_7             (0x080UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000080 */
1659 #define ADC_OFR3_OFFSET3_8             (0x100UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000100 */
1660 #define ADC_OFR3_OFFSET3_9             (0x200UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000200 */
1661 #define ADC_OFR3_OFFSET3_10            (0x400UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000400 */
1662 #define ADC_OFR3_OFFSET3_11            (0x800UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000800 */
1663 
1664 #define ADC_OFR3_OFFSET3_CH_Pos        (26U)
1665 #define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x7C000000 */
1666 #define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
1667 #define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x04000000 */
1668 #define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x08000000 */
1669 #define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x10000000 */
1670 #define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x20000000 */
1671 #define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x40000000 */
1672 
1673 #define ADC_OFR3_OFFSET3_EN_Pos        (31U)
1674 #define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)       /*!< 0x80000000 */
1675 #define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
1676 
1677 /********************  Bit definition for ADC_OFR4 register  ******************/
1678 #define ADC_OFR4_OFFSET4_Pos           (0U)
1679 #define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000FFF */
1680 #define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
1681 #define ADC_OFR4_OFFSET4_0             (0x001UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000001 */
1682 #define ADC_OFR4_OFFSET4_1             (0x002UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000002 */
1683 #define ADC_OFR4_OFFSET4_2             (0x004UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000004 */
1684 #define ADC_OFR4_OFFSET4_3             (0x008UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000008 */
1685 #define ADC_OFR4_OFFSET4_4             (0x010UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000010 */
1686 #define ADC_OFR4_OFFSET4_5             (0x020UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000020 */
1687 #define ADC_OFR4_OFFSET4_6             (0x040UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000040 */
1688 #define ADC_OFR4_OFFSET4_7             (0x080UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000080 */
1689 #define ADC_OFR4_OFFSET4_8             (0x100UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000100 */
1690 #define ADC_OFR4_OFFSET4_9             (0x200UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000200 */
1691 #define ADC_OFR4_OFFSET4_10            (0x400UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000400 */
1692 #define ADC_OFR4_OFFSET4_11            (0x800UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000800 */
1693 
1694 #define ADC_OFR4_OFFSET4_CH_Pos        (26U)
1695 #define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x7C000000 */
1696 #define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
1697 #define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x04000000 */
1698 #define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x08000000 */
1699 #define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x10000000 */
1700 #define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x20000000 */
1701 #define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x40000000 */
1702 
1703 #define ADC_OFR4_OFFSET4_EN_Pos        (31U)
1704 #define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)       /*!< 0x80000000 */
1705 #define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
1706 
1707 /********************  Bit definition for ADC_JDR1 register  ******************/
1708 #define ADC_JDR1_JDATA_Pos             (0U)
1709 #define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)         /*!< 0x0000FFFF */
1710 #define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
1711 #define ADC_JDR1_JDATA_0               (0x0001UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000001 */
1712 #define ADC_JDR1_JDATA_1               (0x0002UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000002 */
1713 #define ADC_JDR1_JDATA_2               (0x0004UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000004 */
1714 #define ADC_JDR1_JDATA_3               (0x0008UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000008 */
1715 #define ADC_JDR1_JDATA_4               (0x0010UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000010 */
1716 #define ADC_JDR1_JDATA_5               (0x0020UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000020 */
1717 #define ADC_JDR1_JDATA_6               (0x0040UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000040 */
1718 #define ADC_JDR1_JDATA_7               (0x0080UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000080 */
1719 #define ADC_JDR1_JDATA_8               (0x0100UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000100 */
1720 #define ADC_JDR1_JDATA_9               (0x0200UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000200 */
1721 #define ADC_JDR1_JDATA_10              (0x0400UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000400 */
1722 #define ADC_JDR1_JDATA_11              (0x0800UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000800 */
1723 #define ADC_JDR1_JDATA_12              (0x1000UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00001000 */
1724 #define ADC_JDR1_JDATA_13              (0x2000UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00002000 */
1725 #define ADC_JDR1_JDATA_14              (0x4000UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00004000 */
1726 #define ADC_JDR1_JDATA_15              (0x8000UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00008000 */
1727 
1728 /********************  Bit definition for ADC_JDR2 register  ******************/
1729 #define ADC_JDR2_JDATA_Pos             (0U)
1730 #define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)         /*!< 0x0000FFFF */
1731 #define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
1732 #define ADC_JDR2_JDATA_0               (0x0001UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000001 */
1733 #define ADC_JDR2_JDATA_1               (0x0002UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000002 */
1734 #define ADC_JDR2_JDATA_2               (0x0004UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000004 */
1735 #define ADC_JDR2_JDATA_3               (0x0008UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000008 */
1736 #define ADC_JDR2_JDATA_4               (0x0010UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000010 */
1737 #define ADC_JDR2_JDATA_5               (0x0020UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000020 */
1738 #define ADC_JDR2_JDATA_6               (0x0040UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000040 */
1739 #define ADC_JDR2_JDATA_7               (0x0080UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000080 */
1740 #define ADC_JDR2_JDATA_8               (0x0100UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000100 */
1741 #define ADC_JDR2_JDATA_9               (0x0200UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000200 */
1742 #define ADC_JDR2_JDATA_10              (0x0400UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000400 */
1743 #define ADC_JDR2_JDATA_11              (0x0800UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000800 */
1744 #define ADC_JDR2_JDATA_12              (0x1000UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00001000 */
1745 #define ADC_JDR2_JDATA_13              (0x2000UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00002000 */
1746 #define ADC_JDR2_JDATA_14              (0x4000UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00004000 */
1747 #define ADC_JDR2_JDATA_15              (0x8000UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00008000 */
1748 
1749 /********************  Bit definition for ADC_JDR3 register  ******************/
1750 #define ADC_JDR3_JDATA_Pos             (0U)
1751 #define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)         /*!< 0x0000FFFF */
1752 #define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
1753 #define ADC_JDR3_JDATA_0               (0x0001UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000001 */
1754 #define ADC_JDR3_JDATA_1               (0x0002UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000002 */
1755 #define ADC_JDR3_JDATA_2               (0x0004UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000004 */
1756 #define ADC_JDR3_JDATA_3               (0x0008UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000008 */
1757 #define ADC_JDR3_JDATA_4               (0x0010UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000010 */
1758 #define ADC_JDR3_JDATA_5               (0x0020UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000020 */
1759 #define ADC_JDR3_JDATA_6               (0x0040UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000040 */
1760 #define ADC_JDR3_JDATA_7               (0x0080UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000080 */
1761 #define ADC_JDR3_JDATA_8               (0x0100UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000100 */
1762 #define ADC_JDR3_JDATA_9               (0x0200UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000200 */
1763 #define ADC_JDR3_JDATA_10              (0x0400UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000400 */
1764 #define ADC_JDR3_JDATA_11              (0x0800UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000800 */
1765 #define ADC_JDR3_JDATA_12              (0x1000UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00001000 */
1766 #define ADC_JDR3_JDATA_13              (0x2000UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00002000 */
1767 #define ADC_JDR3_JDATA_14              (0x4000UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00004000 */
1768 #define ADC_JDR3_JDATA_15              (0x8000UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00008000 */
1769 
1770 /********************  Bit definition for ADC_JDR4 register  ******************/
1771 #define ADC_JDR4_JDATA_Pos             (0U)
1772 #define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)         /*!< 0x0000FFFF */
1773 #define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
1774 #define ADC_JDR4_JDATA_0               (0x0001UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000001 */
1775 #define ADC_JDR4_JDATA_1               (0x0002UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000002 */
1776 #define ADC_JDR4_JDATA_2               (0x0004UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000004 */
1777 #define ADC_JDR4_JDATA_3               (0x0008UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000008 */
1778 #define ADC_JDR4_JDATA_4               (0x0010UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000010 */
1779 #define ADC_JDR4_JDATA_5               (0x0020UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000020 */
1780 #define ADC_JDR4_JDATA_6               (0x0040UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000040 */
1781 #define ADC_JDR4_JDATA_7               (0x0080UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000080 */
1782 #define ADC_JDR4_JDATA_8               (0x0100UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000100 */
1783 #define ADC_JDR4_JDATA_9               (0x0200UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000200 */
1784 #define ADC_JDR4_JDATA_10              (0x0400UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000400 */
1785 #define ADC_JDR4_JDATA_11              (0x0800UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000800 */
1786 #define ADC_JDR4_JDATA_12              (0x1000UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00001000 */
1787 #define ADC_JDR4_JDATA_13              (0x2000UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00002000 */
1788 #define ADC_JDR4_JDATA_14              (0x4000UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00004000 */
1789 #define ADC_JDR4_JDATA_15              (0x8000UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00008000 */
1790 
1791 /********************  Bit definition for ADC_AWD2CR register  ****************/
1792 #define ADC_AWD2CR_AWD2CH_Pos          (1U)
1793 #define ADC_AWD2CR_AWD2CH_Msk          (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x0003FFFF */
1794 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
1795 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000001 */
1796 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000002 */
1797 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000004 */
1798 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000008 */
1799 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000010 */
1800 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000020 */
1801 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000040 */
1802 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000080 */
1803 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000100 */
1804 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000200 */
1805 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000400 */
1806 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000800 */
1807 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00001000 */
1808 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00002000 */
1809 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00004000 */
1810 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00008000 */
1811 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00010000 */
1812 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00020000 */
1813 
1814 /********************  Bit definition for ADC_AWD3CR register  ****************/
1815 #define ADC_AWD3CR_AWD3CH_Pos          (1U)
1816 #define ADC_AWD3CR_AWD3CH_Msk          (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x0003FFFF */
1817 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
1818 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000001 */
1819 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000002 */
1820 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000004 */
1821 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000008 */
1822 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000010 */
1823 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000020 */
1824 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000040 */
1825 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000080 */
1826 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000100 */
1827 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000200 */
1828 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000400 */
1829 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000800 */
1830 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00001000 */
1831 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00002000 */
1832 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00004000 */
1833 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00008000 */
1834 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00010000 */
1835 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00020000 */
1836 
1837 /********************  Bit definition for ADC_DIFSEL register  ****************/
1838 #define ADC_DIFSEL_DIFSEL_Pos          (1U)
1839 #define ADC_DIFSEL_DIFSEL_Msk          (0x3FFFFUL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x0003FFFF */
1840 #define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
1841 #define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000001 */
1842 #define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000002 */
1843 #define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000004 */
1844 #define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000008 */
1845 #define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000010 */
1846 #define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000020 */
1847 #define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000040 */
1848 #define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000080 */
1849 #define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000100 */
1850 #define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000200 */
1851 #define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000400 */
1852 #define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000800 */
1853 #define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00001000 */
1854 #define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00002000 */
1855 #define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00004000 */
1856 #define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00008000 */
1857 #define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00010000 */
1858 #define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00020000 */
1859 
1860 /********************  Bit definition for ADC_CALFACT register  ***************/
1861 #define ADC_CALFACT_CALFACT_S_Pos      (0U)
1862 #define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x0000007F */
1863 #define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
1864 #define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000001 */
1865 #define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000002 */
1866 #define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000004 */
1867 #define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000008 */
1868 #define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000010 */
1869 #define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000020 */
1870 #define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000040 */
1871 
1872 #define ADC_CALFACT_CALFACT_D_Pos      (16U)
1873 #define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x007F0000 */
1874 #define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
1875 #define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00010000 */
1876 #define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00020000 */
1877 #define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00040000 */
1878 #define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00080000 */
1879 #define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00100000 */
1880 #define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00200000 */
1881 #define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00400000 */
1882 
1883 /*************************  ADC Common registers  *****************************/
1884 /***************  Bit definition for ADC12_COMMON_CSR register  ***************/
1885 #define ADC12_CSR_ADRDY_MST_Pos          (0U)
1886 #define ADC12_CSR_ADRDY_MST_Msk          (0x1UL << ADC12_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */
1887 #define ADC12_CSR_ADRDY_MST              ADC12_CSR_ADRDY_MST_Msk               /*!< Master ADC ready */
1888 #define ADC12_CSR_ADRDY_EOSMP_MST_Pos    (1U)
1889 #define ADC12_CSR_ADRDY_EOSMP_MST_Msk    (0x1UL << ADC12_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */
1890 #define ADC12_CSR_ADRDY_EOSMP_MST        ADC12_CSR_ADRDY_EOSMP_MST_Msk         /*!< End of sampling phase flag of the master ADC */
1891 #define ADC12_CSR_ADRDY_EOC_MST_Pos      (2U)
1892 #define ADC12_CSR_ADRDY_EOC_MST_Msk      (0x1UL << ADC12_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */
1893 #define ADC12_CSR_ADRDY_EOC_MST          ADC12_CSR_ADRDY_EOC_MST_Msk           /*!< End of regular conversion of the master ADC */
1894 #define ADC12_CSR_ADRDY_EOS_MST_Pos      (3U)
1895 #define ADC12_CSR_ADRDY_EOS_MST_Msk      (0x1UL << ADC12_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */
1896 #define ADC12_CSR_ADRDY_EOS_MST          ADC12_CSR_ADRDY_EOS_MST_Msk           /*!< End of regular sequence flag of the master ADC */
1897 #define ADC12_CSR_ADRDY_OVR_MST_Pos      (4U)
1898 #define ADC12_CSR_ADRDY_OVR_MST_Msk      (0x1UL << ADC12_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */
1899 #define ADC12_CSR_ADRDY_OVR_MST          ADC12_CSR_ADRDY_OVR_MST_Msk           /*!< Overrun flag of the master ADC */
1900 #define ADC12_CSR_ADRDY_JEOC_MST_Pos     (5U)
1901 #define ADC12_CSR_ADRDY_JEOC_MST_Msk     (0x1UL << ADC12_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */
1902 #define ADC12_CSR_ADRDY_JEOC_MST         ADC12_CSR_ADRDY_JEOC_MST_Msk          /*!< End of injected conversion of the master ADC */
1903 #define ADC12_CSR_ADRDY_JEOS_MST_Pos     (6U)
1904 #define ADC12_CSR_ADRDY_JEOS_MST_Msk     (0x1UL << ADC12_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */
1905 #define ADC12_CSR_ADRDY_JEOS_MST         ADC12_CSR_ADRDY_JEOS_MST_Msk          /*!< End of injected sequence flag of the master ADC */
1906 #define ADC12_CSR_AWD1_MST_Pos           (7U)
1907 #define ADC12_CSR_AWD1_MST_Msk           (0x1UL << ADC12_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */
1908 #define ADC12_CSR_AWD1_MST               ADC12_CSR_AWD1_MST_Msk                /*!< Analog watchdog 1 flag of the master ADC */
1909 #define ADC12_CSR_AWD2_MST_Pos           (8U)
1910 #define ADC12_CSR_AWD2_MST_Msk           (0x1UL << ADC12_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */
1911 #define ADC12_CSR_AWD2_MST               ADC12_CSR_AWD2_MST_Msk                /*!< Analog watchdog 2 flag of the master ADC */
1912 #define ADC12_CSR_AWD3_MST_Pos           (9U)
1913 #define ADC12_CSR_AWD3_MST_Msk           (0x1UL << ADC12_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */
1914 #define ADC12_CSR_AWD3_MST               ADC12_CSR_AWD3_MST_Msk                /*!< Analog watchdog 3 flag of the master ADC */
1915 #define ADC12_CSR_JQOVF_MST_Pos          (10U)
1916 #define ADC12_CSR_JQOVF_MST_Msk          (0x1UL << ADC12_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */
1917 #define ADC12_CSR_JQOVF_MST              ADC12_CSR_JQOVF_MST_Msk               /*!< Injected context queue overflow flag of the master ADC */
1918 #define ADC12_CSR_ADRDY_SLV_Pos          (16U)
1919 #define ADC12_CSR_ADRDY_SLV_Msk          (0x1UL << ADC12_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */
1920 #define ADC12_CSR_ADRDY_SLV              ADC12_CSR_ADRDY_SLV_Msk               /*!< Slave ADC ready */
1921 #define ADC12_CSR_ADRDY_EOSMP_SLV_Pos    (17U)
1922 #define ADC12_CSR_ADRDY_EOSMP_SLV_Msk    (0x1UL << ADC12_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */
1923 #define ADC12_CSR_ADRDY_EOSMP_SLV        ADC12_CSR_ADRDY_EOSMP_SLV_Msk         /*!< End of sampling phase flag of the slave ADC */
1924 #define ADC12_CSR_ADRDY_EOC_SLV_Pos      (18U)
1925 #define ADC12_CSR_ADRDY_EOC_SLV_Msk      (0x1UL << ADC12_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */
1926 #define ADC12_CSR_ADRDY_EOC_SLV          ADC12_CSR_ADRDY_EOC_SLV_Msk           /*!< End of regular conversion of the slave ADC */
1927 #define ADC12_CSR_ADRDY_EOS_SLV_Pos      (19U)
1928 #define ADC12_CSR_ADRDY_EOS_SLV_Msk      (0x1UL << ADC12_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
1929 #define ADC12_CSR_ADRDY_EOS_SLV          ADC12_CSR_ADRDY_EOS_SLV_Msk           /*!< End of regular sequence flag of the slave ADC */
1930 #define ADC12_CSR_ADRDY_OVR_SLV_Pos      (20U)
1931 #define ADC12_CSR_ADRDY_OVR_SLV_Msk      (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
1932 #define ADC12_CSR_ADRDY_OVR_SLV          ADC12_CSR_ADRDY_OVR_SLV_Msk           /*!< Overrun flag of the slave ADC */
1933 #define ADC12_CSR_ADRDY_JEOC_SLV_Pos     (21U)
1934 #define ADC12_CSR_ADRDY_JEOC_SLV_Msk     (0x1UL << ADC12_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
1935 #define ADC12_CSR_ADRDY_JEOC_SLV         ADC12_CSR_ADRDY_JEOC_SLV_Msk          /*!< End of injected conversion of the slave ADC */
1936 #define ADC12_CSR_ADRDY_JEOS_SLV_Pos     (22U)
1937 #define ADC12_CSR_ADRDY_JEOS_SLV_Msk     (0x1UL << ADC12_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */
1938 #define ADC12_CSR_ADRDY_JEOS_SLV         ADC12_CSR_ADRDY_JEOS_SLV_Msk          /*!< End of injected sequence flag of the slave ADC */
1939 #define ADC12_CSR_AWD1_SLV_Pos           (23U)
1940 #define ADC12_CSR_AWD1_SLV_Msk           (0x1UL << ADC12_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */
1941 #define ADC12_CSR_AWD1_SLV               ADC12_CSR_AWD1_SLV_Msk                /*!< Analog watchdog 1 flag of the slave ADC */
1942 #define ADC12_CSR_AWD2_SLV_Pos           (24U)
1943 #define ADC12_CSR_AWD2_SLV_Msk           (0x1UL << ADC12_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */
1944 #define ADC12_CSR_AWD2_SLV               ADC12_CSR_AWD2_SLV_Msk                /*!< Analog watchdog 2 flag of the slave ADC */
1945 #define ADC12_CSR_AWD3_SLV_Pos           (25U)
1946 #define ADC12_CSR_AWD3_SLV_Msk           (0x1UL << ADC12_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */
1947 #define ADC12_CSR_AWD3_SLV               ADC12_CSR_AWD3_SLV_Msk                /*!< Analog watchdog 3 flag of the slave ADC */
1948 #define ADC12_CSR_JQOVF_SLV_Pos          (26U)
1949 #define ADC12_CSR_JQOVF_SLV_Msk          (0x1UL << ADC12_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */
1950 #define ADC12_CSR_JQOVF_SLV              ADC12_CSR_JQOVF_SLV_Msk               /*!< Injected context queue overflow flag of the slave ADC */
1951 
1952 /***************  Bit definition for ADC34_COMMON_CSR register  ***************/
1953 #define ADC34_CSR_ADRDY_MST_Pos          (0U)
1954 #define ADC34_CSR_ADRDY_MST_Msk          (0x1UL << ADC34_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */
1955 #define ADC34_CSR_ADRDY_MST              ADC34_CSR_ADRDY_MST_Msk               /*!< Master ADC ready */
1956 #define ADC34_CSR_ADRDY_EOSMP_MST_Pos    (1U)
1957 #define ADC34_CSR_ADRDY_EOSMP_MST_Msk    (0x1UL << ADC34_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */
1958 #define ADC34_CSR_ADRDY_EOSMP_MST        ADC34_CSR_ADRDY_EOSMP_MST_Msk         /*!< End of sampling phase flag of the master ADC */
1959 #define ADC34_CSR_ADRDY_EOC_MST_Pos      (2U)
1960 #define ADC34_CSR_ADRDY_EOC_MST_Msk      (0x1UL << ADC34_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */
1961 #define ADC34_CSR_ADRDY_EOC_MST          ADC34_CSR_ADRDY_EOC_MST_Msk           /*!< End of regular conversion of the master ADC */
1962 #define ADC34_CSR_ADRDY_EOS_MST_Pos      (3U)
1963 #define ADC34_CSR_ADRDY_EOS_MST_Msk      (0x1UL << ADC34_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */
1964 #define ADC34_CSR_ADRDY_EOS_MST          ADC34_CSR_ADRDY_EOS_MST_Msk           /*!< End of regular sequence flag of the master ADC */
1965 #define ADC34_CSR_ADRDY_OVR_MST_Pos      (4U)
1966 #define ADC34_CSR_ADRDY_OVR_MST_Msk      (0x1UL << ADC34_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */
1967 #define ADC34_CSR_ADRDY_OVR_MST          ADC34_CSR_ADRDY_OVR_MST_Msk           /*!< Overrun flag of the master ADC */
1968 #define ADC34_CSR_ADRDY_JEOC_MST_Pos     (5U)
1969 #define ADC34_CSR_ADRDY_JEOC_MST_Msk     (0x1UL << ADC34_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */
1970 #define ADC34_CSR_ADRDY_JEOC_MST         ADC34_CSR_ADRDY_JEOC_MST_Msk          /*!< End of injected conversion of the master ADC */
1971 #define ADC34_CSR_ADRDY_JEOS_MST_Pos     (6U)
1972 #define ADC34_CSR_ADRDY_JEOS_MST_Msk     (0x1UL << ADC34_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */
1973 #define ADC34_CSR_ADRDY_JEOS_MST         ADC34_CSR_ADRDY_JEOS_MST_Msk          /*!< End of injected sequence flag of the master ADC */
1974 #define ADC34_CSR_AWD1_MST_Pos           (7U)
1975 #define ADC34_CSR_AWD1_MST_Msk           (0x1UL << ADC34_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */
1976 #define ADC34_CSR_AWD1_MST               ADC34_CSR_AWD1_MST_Msk                /*!< Analog watchdog 1 flag of the master ADC */
1977 #define ADC34_CSR_AWD2_MST_Pos           (8U)
1978 #define ADC34_CSR_AWD2_MST_Msk           (0x1UL << ADC34_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */
1979 #define ADC34_CSR_AWD2_MST               ADC34_CSR_AWD2_MST_Msk                /*!< Analog watchdog 2 flag of the master ADC */
1980 #define ADC34_CSR_AWD3_MST_Pos           (9U)
1981 #define ADC34_CSR_AWD3_MST_Msk           (0x1UL << ADC34_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */
1982 #define ADC34_CSR_AWD3_MST               ADC34_CSR_AWD3_MST_Msk                /*!< Analog watchdog 3 flag of the master ADC */
1983 #define ADC34_CSR_JQOVF_MST_Pos          (10U)
1984 #define ADC34_CSR_JQOVF_MST_Msk          (0x1UL << ADC34_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */
1985 #define ADC34_CSR_JQOVF_MST              ADC34_CSR_JQOVF_MST_Msk               /*!< Injected context queue overflow flag of the master ADC */
1986 #define ADC34_CSR_ADRDY_SLV_Pos          (16U)
1987 #define ADC34_CSR_ADRDY_SLV_Msk          (0x1UL << ADC34_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */
1988 #define ADC34_CSR_ADRDY_SLV              ADC34_CSR_ADRDY_SLV_Msk               /*!< Slave ADC ready */
1989 #define ADC34_CSR_ADRDY_EOSMP_SLV_Pos    (17U)
1990 #define ADC34_CSR_ADRDY_EOSMP_SLV_Msk    (0x1UL << ADC34_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */
1991 #define ADC34_CSR_ADRDY_EOSMP_SLV        ADC34_CSR_ADRDY_EOSMP_SLV_Msk         /*!< End of sampling phase flag of the slave ADC */
1992 #define ADC34_CSR_ADRDY_EOC_SLV_Pos      (18U)
1993 #define ADC34_CSR_ADRDY_EOC_SLV_Msk      (0x1UL << ADC34_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */
1994 #define ADC34_CSR_ADRDY_EOC_SLV          ADC34_CSR_ADRDY_EOC_SLV_Msk           /*!< End of regular conversion of the slave ADC */
1995 #define ADC34_CSR_ADRDY_EOS_SLV_Pos      (19U)
1996 #define ADC34_CSR_ADRDY_EOS_SLV_Msk      (0x1UL << ADC34_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
1997 #define ADC34_CSR_ADRDY_EOS_SLV          ADC34_CSR_ADRDY_EOS_SLV_Msk           /*!< End of regular sequence flag of the slave ADC */
1998 #define ADC12_CSR_ADRDY_OVR_SLV_Pos      (20U)
1999 #define ADC12_CSR_ADRDY_OVR_SLV_Msk      (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
2000 #define ADC12_CSR_ADRDY_OVR_SLV          ADC12_CSR_ADRDY_OVR_SLV_Msk           /*!< Overrun flag of the slave ADC */
2001 #define ADC34_CSR_ADRDY_JEOC_SLV_Pos     (21U)
2002 #define ADC34_CSR_ADRDY_JEOC_SLV_Msk     (0x1UL << ADC34_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
2003 #define ADC34_CSR_ADRDY_JEOC_SLV         ADC34_CSR_ADRDY_JEOC_SLV_Msk          /*!< End of injected conversion of the slave ADC */
2004 #define ADC34_CSR_ADRDY_JEOS_SLV_Pos     (22U)
2005 #define ADC34_CSR_ADRDY_JEOS_SLV_Msk     (0x1UL << ADC34_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */
2006 #define ADC34_CSR_ADRDY_JEOS_SLV         ADC34_CSR_ADRDY_JEOS_SLV_Msk          /*!< End of injected sequence flag of the slave ADC */
2007 #define ADC34_CSR_AWD1_SLV_Pos           (23U)
2008 #define ADC34_CSR_AWD1_SLV_Msk           (0x1UL << ADC34_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */
2009 #define ADC34_CSR_AWD1_SLV               ADC34_CSR_AWD1_SLV_Msk                /*!< Analog watchdog 1 flag of the slave ADC */
2010 #define ADC34_CSR_AWD2_SLV_Pos           (24U)
2011 #define ADC34_CSR_AWD2_SLV_Msk           (0x1UL << ADC34_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */
2012 #define ADC34_CSR_AWD2_SLV               ADC34_CSR_AWD2_SLV_Msk                /*!< Analog watchdog 2 flag of the slave ADC */
2013 #define ADC34_CSR_AWD3_SLV_Pos           (25U)
2014 #define ADC34_CSR_AWD3_SLV_Msk           (0x1UL << ADC34_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */
2015 #define ADC34_CSR_AWD3_SLV               ADC34_CSR_AWD3_SLV_Msk                /*!< Analog watchdog 3 flag of the slave ADC */
2016 #define ADC34_CSR_JQOVF_SLV_Pos          (26U)
2017 #define ADC34_CSR_JQOVF_SLV_Msk          (0x1UL << ADC34_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */
2018 #define ADC34_CSR_JQOVF_SLV              ADC34_CSR_JQOVF_SLV_Msk               /*!< Injected context queue overflow flag of the slave ADC */
2019 
2020 /***************  Bit definition for ADC12_COMMON_CCR register  ***************/
2021 #define ADC12_CCR_MULTI_Pos              (0U)
2022 #define ADC12_CCR_MULTI_Msk              (0x1FUL << ADC12_CCR_MULTI_Pos)        /*!< 0x0000001F */
2023 #define ADC12_CCR_MULTI                  ADC12_CCR_MULTI_Msk                   /*!< Multi ADC mode selection */
2024 #define ADC12_CCR_MULTI_0                (0x01UL << ADC12_CCR_MULTI_Pos)        /*!< 0x00000001 */
2025 #define ADC12_CCR_MULTI_1                (0x02UL << ADC12_CCR_MULTI_Pos)        /*!< 0x00000002 */
2026 #define ADC12_CCR_MULTI_2                (0x04UL << ADC12_CCR_MULTI_Pos)        /*!< 0x00000004 */
2027 #define ADC12_CCR_MULTI_3                (0x08UL << ADC12_CCR_MULTI_Pos)        /*!< 0x00000008 */
2028 #define ADC12_CCR_MULTI_4                (0x10UL << ADC12_CCR_MULTI_Pos)        /*!< 0x00000010 */
2029 #define ADC12_CCR_DELAY_Pos              (8U)
2030 #define ADC12_CCR_DELAY_Msk              (0xFUL << ADC12_CCR_DELAY_Pos)         /*!< 0x00000F00 */
2031 #define ADC12_CCR_DELAY                  ADC12_CCR_DELAY_Msk                   /*!< Delay between 2 sampling phases */
2032 #define ADC12_CCR_DELAY_0                (0x1UL << ADC12_CCR_DELAY_Pos)         /*!< 0x00000100 */
2033 #define ADC12_CCR_DELAY_1                (0x2UL << ADC12_CCR_DELAY_Pos)         /*!< 0x00000200 */
2034 #define ADC12_CCR_DELAY_2                (0x4UL << ADC12_CCR_DELAY_Pos)         /*!< 0x00000400 */
2035 #define ADC12_CCR_DELAY_3                (0x8UL << ADC12_CCR_DELAY_Pos)         /*!< 0x00000800 */
2036 #define ADC12_CCR_DMACFG_Pos             (13U)
2037 #define ADC12_CCR_DMACFG_Msk             (0x1UL << ADC12_CCR_DMACFG_Pos)        /*!< 0x00002000 */
2038 #define ADC12_CCR_DMACFG                 ADC12_CCR_DMACFG_Msk                  /*!< DMA configuration for multi-ADC mode */
2039 #define ADC12_CCR_MDMA_Pos               (14U)
2040 #define ADC12_CCR_MDMA_Msk               (0x3UL << ADC12_CCR_MDMA_Pos)          /*!< 0x0000C000 */
2041 #define ADC12_CCR_MDMA                   ADC12_CCR_MDMA_Msk                    /*!< DMA mode for multi-ADC mode */
2042 #define ADC12_CCR_MDMA_0                 (0x1UL << ADC12_CCR_MDMA_Pos)          /*!< 0x00004000 */
2043 #define ADC12_CCR_MDMA_1                 (0x2UL << ADC12_CCR_MDMA_Pos)          /*!< 0x00008000 */
2044 #define ADC12_CCR_CKMODE_Pos             (16U)
2045 #define ADC12_CCR_CKMODE_Msk             (0x3UL << ADC12_CCR_CKMODE_Pos)        /*!< 0x00030000 */
2046 #define ADC12_CCR_CKMODE                 ADC12_CCR_CKMODE_Msk                  /*!< ADC clock mode */
2047 #define ADC12_CCR_CKMODE_0               (0x1UL << ADC12_CCR_CKMODE_Pos)        /*!< 0x00010000 */
2048 #define ADC12_CCR_CKMODE_1               (0x2UL << ADC12_CCR_CKMODE_Pos)        /*!< 0x00020000 */
2049 #define ADC12_CCR_VREFEN_Pos             (22U)
2050 #define ADC12_CCR_VREFEN_Msk             (0x1UL << ADC12_CCR_VREFEN_Pos)        /*!< 0x00400000 */
2051 #define ADC12_CCR_VREFEN                 ADC12_CCR_VREFEN_Msk                  /*!< VREFINT enable */
2052 #define ADC12_CCR_TSEN_Pos               (23U)
2053 #define ADC12_CCR_TSEN_Msk               (0x1UL << ADC12_CCR_TSEN_Pos)          /*!< 0x00800000 */
2054 #define ADC12_CCR_TSEN                   ADC12_CCR_TSEN_Msk                    /*!< Temperature sensor enable */
2055 #define ADC12_CCR_VBATEN_Pos             (24U)
2056 #define ADC12_CCR_VBATEN_Msk             (0x1UL << ADC12_CCR_VBATEN_Pos)        /*!< 0x01000000 */
2057 #define ADC12_CCR_VBATEN                 ADC12_CCR_VBATEN_Msk                  /*!< VBAT enable */
2058 
2059 /***************  Bit definition for ADC12_COMMON_CDR register  ***************/
2060 #define ADC12_CDR_RDATA_MST_Pos          (0U)
2061 #define ADC12_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x0000FFFF */
2062 #define ADC12_CDR_RDATA_MST              ADC12_CDR_RDATA_MST_Msk               /*!< Regular Data of the master ADC */
2063 #define ADC12_CDR_RDATA_MST_0            (0x0001UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000001 */
2064 #define ADC12_CDR_RDATA_MST_1            (0x0002UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000002 */
2065 #define ADC12_CDR_RDATA_MST_2            (0x0004UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000004 */
2066 #define ADC12_CDR_RDATA_MST_3            (0x0008UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000008 */
2067 #define ADC12_CDR_RDATA_MST_4            (0x0010UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000010 */
2068 #define ADC12_CDR_RDATA_MST_5            (0x0020UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000020 */
2069 #define ADC12_CDR_RDATA_MST_6            (0x0040UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000040 */
2070 #define ADC12_CDR_RDATA_MST_7            (0x0080UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000080 */
2071 #define ADC12_CDR_RDATA_MST_8            (0x0100UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000100 */
2072 #define ADC12_CDR_RDATA_MST_9            (0x0200UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000200 */
2073 #define ADC12_CDR_RDATA_MST_10           (0x0400UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000400 */
2074 #define ADC12_CDR_RDATA_MST_11           (0x0800UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000800 */
2075 #define ADC12_CDR_RDATA_MST_12           (0x1000UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00001000 */
2076 #define ADC12_CDR_RDATA_MST_13           (0x2000UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00002000 */
2077 #define ADC12_CDR_RDATA_MST_14           (0x4000UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00004000 */
2078 #define ADC12_CDR_RDATA_MST_15           (0x8000UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00008000 */
2079 
2080 #define ADC12_CDR_RDATA_SLV_Pos          (16U)
2081 #define ADC12_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0xFFFF0000 */
2082 #define ADC12_CDR_RDATA_SLV              ADC12_CDR_RDATA_SLV_Msk               /*!< Regular Data of the master ADC */
2083 #define ADC12_CDR_RDATA_SLV_0            (0x0001UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00010000 */
2084 #define ADC12_CDR_RDATA_SLV_1            (0x0002UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00020000 */
2085 #define ADC12_CDR_RDATA_SLV_2            (0x0004UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00040000 */
2086 #define ADC12_CDR_RDATA_SLV_3            (0x0008UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00080000 */
2087 #define ADC12_CDR_RDATA_SLV_4            (0x0010UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00100000 */
2088 #define ADC12_CDR_RDATA_SLV_5            (0x0020UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00200000 */
2089 #define ADC12_CDR_RDATA_SLV_6            (0x0040UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00400000 */
2090 #define ADC12_CDR_RDATA_SLV_7            (0x0080UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00800000 */
2091 #define ADC12_CDR_RDATA_SLV_8            (0x0100UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x01000000 */
2092 #define ADC12_CDR_RDATA_SLV_9            (0x0200UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x02000000 */
2093 #define ADC12_CDR_RDATA_SLV_10           (0x0400UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x04000000 */
2094 #define ADC12_CDR_RDATA_SLV_11           (0x0800UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x08000000 */
2095 #define ADC12_CDR_RDATA_SLV_12           (0x1000UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x10000000 */
2096 #define ADC12_CDR_RDATA_SLV_13           (0x2000UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x20000000 */
2097 #define ADC12_CDR_RDATA_SLV_14           (0x4000UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x40000000 */
2098 #define ADC12_CDR_RDATA_SLV_15           (0x8000UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x80000000 */
2099 
2100 /********************  Bit definition for ADC_CSR register  *******************/
2101 #define ADC_CSR_ADRDY_MST_Pos          (0U)
2102 #define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)         /*!< 0x00000001 */
2103 #define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
2104 #define ADC_CSR_EOSMP_MST_Pos          (1U)
2105 #define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)         /*!< 0x00000002 */
2106 #define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
2107 #define ADC_CSR_EOC_MST_Pos            (2U)
2108 #define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)           /*!< 0x00000004 */
2109 #define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
2110 #define ADC_CSR_EOS_MST_Pos            (3U)
2111 #define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)           /*!< 0x00000008 */
2112 #define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
2113 #define ADC_CSR_OVR_MST_Pos            (4U)
2114 #define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)           /*!< 0x00000010 */
2115 #define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
2116 #define ADC_CSR_JEOC_MST_Pos           (5U)
2117 #define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)          /*!< 0x00000020 */
2118 #define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
2119 #define ADC_CSR_JEOS_MST_Pos           (6U)
2120 #define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)          /*!< 0x00000040 */
2121 #define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
2122 #define ADC_CSR_AWD1_MST_Pos           (7U)
2123 #define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)          /*!< 0x00000080 */
2124 #define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
2125 #define ADC_CSR_AWD2_MST_Pos           (8U)
2126 #define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)          /*!< 0x00000100 */
2127 #define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
2128 #define ADC_CSR_AWD3_MST_Pos           (9U)
2129 #define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)          /*!< 0x00000200 */
2130 #define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
2131 #define ADC_CSR_JQOVF_MST_Pos          (10U)
2132 #define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)         /*!< 0x00000400 */
2133 #define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
2134 
2135 #define ADC_CSR_ADRDY_SLV_Pos          (16U)
2136 #define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)         /*!< 0x00010000 */
2137 #define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
2138 #define ADC_CSR_EOSMP_SLV_Pos          (17U)
2139 #define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)         /*!< 0x00020000 */
2140 #define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
2141 #define ADC_CSR_EOC_SLV_Pos            (18U)
2142 #define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)           /*!< 0x00040000 */
2143 #define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
2144 #define ADC_CSR_EOS_SLV_Pos            (19U)
2145 #define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)           /*!< 0x00080000 */
2146 #define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
2147 #define ADC_CSR_OVR_SLV_Pos            (20U)
2148 #define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)           /*!< 0x00100000 */
2149 #define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
2150 #define ADC_CSR_JEOC_SLV_Pos           (21U)
2151 #define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)          /*!< 0x00200000 */
2152 #define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
2153 #define ADC_CSR_JEOS_SLV_Pos           (22U)
2154 #define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)          /*!< 0x00400000 */
2155 #define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
2156 #define ADC_CSR_AWD1_SLV_Pos           (23U)
2157 #define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)          /*!< 0x00800000 */
2158 #define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
2159 #define ADC_CSR_AWD2_SLV_Pos           (24U)
2160 #define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)          /*!< 0x01000000 */
2161 #define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
2162 #define ADC_CSR_AWD3_SLV_Pos           (25U)
2163 #define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)          /*!< 0x02000000 */
2164 #define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
2165 #define ADC_CSR_JQOVF_SLV_Pos          (26U)
2166 #define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)         /*!< 0x04000000 */
2167 #define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
2168 
2169 /* Legacy defines */
2170 #define ADC_CSR_ADRDY_EOSMP_MST   ADC_CSR_EOSMP_MST
2171 #define ADC_CSR_ADRDY_EOC_MST     ADC_CSR_EOC_MST
2172 #define ADC_CSR_ADRDY_EOS_MST     ADC_CSR_EOS_MST
2173 #define ADC_CSR_ADRDY_OVR_MST     ADC_CSR_OVR_MST
2174 #define ADC_CSR_ADRDY_JEOC_MST    ADC_CSR_JEOC_MST
2175 #define ADC_CSR_ADRDY_JEOS_MST    ADC_CSR_JEOS_MST
2176 
2177 #define ADC_CSR_ADRDY_EOSMP_SLV   ADC_CSR_EOSMP_SLV
2178 #define ADC_CSR_ADRDY_EOC_SLV     ADC_CSR_EOC_SLV
2179 #define ADC_CSR_ADRDY_EOS_SLV     ADC_CSR_EOS_SLV
2180 #define ADC_CSR_ADRDY_OVR_SLV     ADC_CSR_OVR_SLV
2181 #define ADC_CSR_ADRDY_JEOC_SLV    ADC_CSR_JEOC_SLV
2182 #define ADC_CSR_ADRDY_JEOS_SLV    ADC_CSR_JEOS_SLV
2183 
2184 /********************  Bit definition for ADC_CCR register  *******************/
2185 #define ADC_CCR_DUAL_Pos               (0U)
2186 #define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)             /*!< 0x0000001F */
2187 #define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
2188 #define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)             /*!< 0x00000001 */
2189 #define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)             /*!< 0x00000002 */
2190 #define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)             /*!< 0x00000004 */
2191 #define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)             /*!< 0x00000008 */
2192 #define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)             /*!< 0x00000010 */
2193 
2194 #define ADC_CCR_DELAY_Pos              (8U)
2195 #define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)             /*!< 0x00000F00 */
2196 #define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
2197 #define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)             /*!< 0x00000100 */
2198 #define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)             /*!< 0x00000200 */
2199 #define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)             /*!< 0x00000400 */
2200 #define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)             /*!< 0x00000800 */
2201 
2202 #define ADC_CCR_DMACFG_Pos             (13U)
2203 #define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)            /*!< 0x00002000 */
2204 #define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
2205 
2206 #define ADC_CCR_MDMA_Pos               (14U)
2207 #define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)              /*!< 0x0000C000 */
2208 #define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
2209 #define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)              /*!< 0x00004000 */
2210 #define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)              /*!< 0x00008000 */
2211 
2212 #define ADC_CCR_CKMODE_Pos             (16U)
2213 #define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)            /*!< 0x00030000 */
2214 #define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2215 #define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)            /*!< 0x00010000 */
2216 #define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)            /*!< 0x00020000 */
2217 
2218 #define ADC_CCR_VREFEN_Pos             (22U)
2219 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)            /*!< 0x00400000 */
2220 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
2221 #define ADC_CCR_TSEN_Pos               (23U)
2222 #define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)              /*!< 0x00800000 */
2223 #define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
2224 #define ADC_CCR_VBATEN_Pos             (24U)
2225 #define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)            /*!< 0x01000000 */
2226 #define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
2227 
2228 /* Legacy defines */
2229 #define ADC_CCR_MULTI           (ADC_CCR_DUAL)
2230 #define ADC_CCR_MULTI_0         (ADC_CCR_DUAL_0)
2231 #define ADC_CCR_MULTI_1         (ADC_CCR_DUAL_1)
2232 #define ADC_CCR_MULTI_2         (ADC_CCR_DUAL_2)
2233 #define ADC_CCR_MULTI_3         (ADC_CCR_DUAL_3)
2234 #define ADC_CCR_MULTI_4         (ADC_CCR_DUAL_4)
2235 
2236 /********************  Bit definition for ADC_CDR register  *******************/
2237 #define ADC_CDR_RDATA_MST_Pos          (0U)
2238 #define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x0000FFFF */
2239 #define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
2240 #define ADC_CDR_RDATA_MST_0            (0x0001UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000001 */
2241 #define ADC_CDR_RDATA_MST_1            (0x0002UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000002 */
2242 #define ADC_CDR_RDATA_MST_2            (0x0004UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000004 */
2243 #define ADC_CDR_RDATA_MST_3            (0x0008UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000008 */
2244 #define ADC_CDR_RDATA_MST_4            (0x0010UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000010 */
2245 #define ADC_CDR_RDATA_MST_5            (0x0020UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000020 */
2246 #define ADC_CDR_RDATA_MST_6            (0x0040UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000040 */
2247 #define ADC_CDR_RDATA_MST_7            (0x0080UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000080 */
2248 #define ADC_CDR_RDATA_MST_8            (0x0100UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000100 */
2249 #define ADC_CDR_RDATA_MST_9            (0x0200UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000200 */
2250 #define ADC_CDR_RDATA_MST_10           (0x0400UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000400 */
2251 #define ADC_CDR_RDATA_MST_11           (0x0800UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000800 */
2252 #define ADC_CDR_RDATA_MST_12           (0x1000UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00001000 */
2253 #define ADC_CDR_RDATA_MST_13           (0x2000UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00002000 */
2254 #define ADC_CDR_RDATA_MST_14           (0x4000UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00004000 */
2255 #define ADC_CDR_RDATA_MST_15           (0x8000UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00008000 */
2256 
2257 #define ADC_CDR_RDATA_SLV_Pos          (16U)
2258 #define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0xFFFF0000 */
2259 #define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
2260 #define ADC_CDR_RDATA_SLV_0            (0x0001UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00010000 */
2261 #define ADC_CDR_RDATA_SLV_1            (0x0002UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00020000 */
2262 #define ADC_CDR_RDATA_SLV_2            (0x0004UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00040000 */
2263 #define ADC_CDR_RDATA_SLV_3            (0x0008UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00080000 */
2264 #define ADC_CDR_RDATA_SLV_4            (0x0010UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00100000 */
2265 #define ADC_CDR_RDATA_SLV_5            (0x0020UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00200000 */
2266 #define ADC_CDR_RDATA_SLV_6            (0x0040UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00400000 */
2267 #define ADC_CDR_RDATA_SLV_7            (0x0080UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00800000 */
2268 #define ADC_CDR_RDATA_SLV_8            (0x0100UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x01000000 */
2269 #define ADC_CDR_RDATA_SLV_9            (0x0200UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x02000000 */
2270 #define ADC_CDR_RDATA_SLV_10           (0x0400UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x04000000 */
2271 #define ADC_CDR_RDATA_SLV_11           (0x0800UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x08000000 */
2272 #define ADC_CDR_RDATA_SLV_12           (0x1000UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x10000000 */
2273 #define ADC_CDR_RDATA_SLV_13           (0x2000UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x20000000 */
2274 #define ADC_CDR_RDATA_SLV_14           (0x4000UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x40000000 */
2275 #define ADC_CDR_RDATA_SLV_15           (0x8000UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x80000000 */
2276 
2277 /******************************************************************************/
2278 /*                                                                            */
2279 /*                      Analog Comparators (COMP)                             */
2280 /*                                                                            */
2281 /******************************************************************************/
2282 
2283 #define COMP_V1_3_0_0                                  /*!< Comparator IP version */
2284 
2285 /**********************  Bit definition for COMP2_CSR register  ***************/
2286 #define COMP2_CSR_COMP2EN_Pos            (0U)
2287 #define COMP2_CSR_COMP2EN_Msk            (0x1UL << COMP2_CSR_COMP2EN_Pos)       /*!< 0x00000001 */
2288 #define COMP2_CSR_COMP2EN                COMP2_CSR_COMP2EN_Msk                 /*!< COMP2 enable */
2289 #define COMP2_CSR_COMP2INSEL_Pos         (4U)
2290 #define COMP2_CSR_COMP2INSEL_Msk         (0x40007UL << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00400070 */
2291 #define COMP2_CSR_COMP2INSEL             COMP2_CSR_COMP2INSEL_Msk              /*!< COMP2 inverting input select */
2292 #define COMP2_CSR_COMP2INSEL_0           (0x00000010U)                         /*!< COMP2 inverting input select bit 0 */
2293 #define COMP2_CSR_COMP2INSEL_1           (0x00000020U)                         /*!< COMP2 inverting input select bit 1 */
2294 #define COMP2_CSR_COMP2INSEL_2           (0x00000040U)                         /*!< COMP2 inverting input select bit 2 */
2295 #define COMP2_CSR_COMP2INSEL_3           (0x00400000U)                         /*!< COMP2 inverting input select bit 3 */
2296 #define COMP2_CSR_COMP2OUTSEL_Pos        (10U)
2297 #define COMP2_CSR_COMP2OUTSEL_Msk        (0xFUL << COMP2_CSR_COMP2OUTSEL_Pos)   /*!< 0x00003C00 */
2298 #define COMP2_CSR_COMP2OUTSEL            COMP2_CSR_COMP2OUTSEL_Msk             /*!< COMP2 output select */
2299 #define COMP2_CSR_COMP2OUTSEL_0          (0x1UL << COMP2_CSR_COMP2OUTSEL_Pos)   /*!< 0x00000400 */
2300 #define COMP2_CSR_COMP2OUTSEL_1          (0x2UL << COMP2_CSR_COMP2OUTSEL_Pos)   /*!< 0x00000800 */
2301 #define COMP2_CSR_COMP2OUTSEL_2          (0x4UL << COMP2_CSR_COMP2OUTSEL_Pos)   /*!< 0x00001000 */
2302 #define COMP2_CSR_COMP2OUTSEL_3          (0x8UL << COMP2_CSR_COMP2OUTSEL_Pos)   /*!< 0x00002000 */
2303 #define COMP2_CSR_COMP2POL_Pos           (15U)
2304 #define COMP2_CSR_COMP2POL_Msk           (0x1UL << COMP2_CSR_COMP2POL_Pos)      /*!< 0x00008000 */
2305 #define COMP2_CSR_COMP2POL               COMP2_CSR_COMP2POL_Msk                /*!< COMP2 output polarity */
2306 #define COMP2_CSR_COMP2BLANKING_Pos      (18U)
2307 #define COMP2_CSR_COMP2BLANKING_Msk      (0x3UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x000C0000 */
2308 #define COMP2_CSR_COMP2BLANKING          COMP2_CSR_COMP2BLANKING_Msk           /*!< COMP2 blanking */
2309 #define COMP2_CSR_COMP2BLANKING_0        (0x1UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00040000 */
2310 #define COMP2_CSR_COMP2BLANKING_1        (0x2UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00080000 */
2311 #define COMP2_CSR_COMP2BLANKING_2        (0x4UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00100000 */
2312 #define COMP2_CSR_COMP2OUT_Pos           (30U)
2313 #define COMP2_CSR_COMP2OUT_Msk           (0x1UL << COMP2_CSR_COMP2OUT_Pos)      /*!< 0x40000000 */
2314 #define COMP2_CSR_COMP2OUT               COMP2_CSR_COMP2OUT_Msk                /*!< COMP2 output level */
2315 #define COMP2_CSR_COMP2LOCK_Pos          (31U)
2316 #define COMP2_CSR_COMP2LOCK_Msk          (0x1UL << COMP2_CSR_COMP2LOCK_Pos)     /*!< 0x80000000 */
2317 #define COMP2_CSR_COMP2LOCK              COMP2_CSR_COMP2LOCK_Msk               /*!< COMP2 lock */
2318 
2319 /**********************  Bit definition for COMP4_CSR register  ***************/
2320 #define COMP4_CSR_COMP4EN_Pos            (0U)
2321 #define COMP4_CSR_COMP4EN_Msk            (0x1UL << COMP4_CSR_COMP4EN_Pos)       /*!< 0x00000001 */
2322 #define COMP4_CSR_COMP4EN                COMP4_CSR_COMP4EN_Msk                 /*!< COMP4 enable */
2323 #define COMP4_CSR_COMP4INSEL_Pos         (4U)
2324 #define COMP4_CSR_COMP4INSEL_Msk         (0x40007UL << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00400070 */
2325 #define COMP4_CSR_COMP4INSEL             COMP4_CSR_COMP4INSEL_Msk              /*!< COMP4 inverting input select */
2326 #define COMP4_CSR_COMP4INSEL_0           (0x00000010U)                         /*!< COMP4 inverting input select bit 0 */
2327 #define COMP4_CSR_COMP4INSEL_1           (0x00000020U)                         /*!< COMP4 inverting input select bit 1 */
2328 #define COMP4_CSR_COMP4INSEL_2           (0x00000040U)                         /*!< COMP4 inverting input select bit 2 */
2329 #define COMP4_CSR_COMP4INSEL_3           (0x00400000U)                         /*!< COMP4 inverting input select bit 3 */
2330 #define COMP4_CSR_COMP4OUTSEL_Pos        (10U)
2331 #define COMP4_CSR_COMP4OUTSEL_Msk        (0xFUL << COMP4_CSR_COMP4OUTSEL_Pos)   /*!< 0x00003C00 */
2332 #define COMP4_CSR_COMP4OUTSEL            COMP4_CSR_COMP4OUTSEL_Msk             /*!< COMP4 output select */
2333 #define COMP4_CSR_COMP4OUTSEL_0          (0x1UL << COMP4_CSR_COMP4OUTSEL_Pos)   /*!< 0x00000400 */
2334 #define COMP4_CSR_COMP4OUTSEL_1          (0x2UL << COMP4_CSR_COMP4OUTSEL_Pos)   /*!< 0x00000800 */
2335 #define COMP4_CSR_COMP4OUTSEL_2          (0x4UL << COMP4_CSR_COMP4OUTSEL_Pos)   /*!< 0x00001000 */
2336 #define COMP4_CSR_COMP4OUTSEL_3          (0x8UL << COMP4_CSR_COMP4OUTSEL_Pos)   /*!< 0x00002000 */
2337 #define COMP4_CSR_COMP4POL_Pos           (15U)
2338 #define COMP4_CSR_COMP4POL_Msk           (0x1UL << COMP4_CSR_COMP4POL_Pos)      /*!< 0x00008000 */
2339 #define COMP4_CSR_COMP4POL               COMP4_CSR_COMP4POL_Msk                /*!< COMP4 output polarity */
2340 #define COMP4_CSR_COMP4BLANKING_Pos      (18U)
2341 #define COMP4_CSR_COMP4BLANKING_Msk      (0x3UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x000C0000 */
2342 #define COMP4_CSR_COMP4BLANKING          COMP4_CSR_COMP4BLANKING_Msk           /*!< COMP4 blanking */
2343 #define COMP4_CSR_COMP4BLANKING_0        (0x1UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00040000 */
2344 #define COMP4_CSR_COMP4BLANKING_1        (0x2UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00080000 */
2345 #define COMP4_CSR_COMP4BLANKING_2        (0x4UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00100000 */
2346 #define COMP4_CSR_COMP4OUT_Pos           (30U)
2347 #define COMP4_CSR_COMP4OUT_Msk           (0x1UL << COMP4_CSR_COMP4OUT_Pos)      /*!< 0x40000000 */
2348 #define COMP4_CSR_COMP4OUT               COMP4_CSR_COMP4OUT_Msk                /*!< COMP4 output level */
2349 #define COMP4_CSR_COMP4LOCK_Pos          (31U)
2350 #define COMP4_CSR_COMP4LOCK_Msk          (0x1UL << COMP4_CSR_COMP4LOCK_Pos)     /*!< 0x80000000 */
2351 #define COMP4_CSR_COMP4LOCK              COMP4_CSR_COMP4LOCK_Msk               /*!< COMP4 lock */
2352 
2353 /**********************  Bit definition for COMP6_CSR register  ***************/
2354 #define COMP6_CSR_COMP6EN_Pos            (0U)
2355 #define COMP6_CSR_COMP6EN_Msk            (0x1UL << COMP6_CSR_COMP6EN_Pos)       /*!< 0x00000001 */
2356 #define COMP6_CSR_COMP6EN                COMP6_CSR_COMP6EN_Msk                 /*!< COMP6 enable */
2357 #define COMP6_CSR_COMP6INSEL_Pos         (4U)
2358 #define COMP6_CSR_COMP6INSEL_Msk         (0x40007UL << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00400070 */
2359 #define COMP6_CSR_COMP6INSEL             COMP6_CSR_COMP6INSEL_Msk              /*!< COMP6 inverting input select */
2360 #define COMP6_CSR_COMP6INSEL_0           (0x00000010U)                         /*!< COMP6 inverting input select bit 0 */
2361 #define COMP6_CSR_COMP6INSEL_1           (0x00000020U)                         /*!< COMP6 inverting input select bit 1 */
2362 #define COMP6_CSR_COMP6INSEL_2           (0x00000040U)                         /*!< COMP6 inverting input select bit 2 */
2363 #define COMP6_CSR_COMP6INSEL_3           (0x00400000U)                         /*!< COMP6 inverting input select bit 3 */
2364 #define COMP6_CSR_COMP6OUTSEL_Pos        (10U)
2365 #define COMP6_CSR_COMP6OUTSEL_Msk        (0xFUL << COMP6_CSR_COMP6OUTSEL_Pos)   /*!< 0x00003C00 */
2366 #define COMP6_CSR_COMP6OUTSEL            COMP6_CSR_COMP6OUTSEL_Msk             /*!< COMP6 output select */
2367 #define COMP6_CSR_COMP6OUTSEL_0          (0x1UL << COMP6_CSR_COMP6OUTSEL_Pos)   /*!< 0x00000400 */
2368 #define COMP6_CSR_COMP6OUTSEL_1          (0x2UL << COMP6_CSR_COMP6OUTSEL_Pos)   /*!< 0x00000800 */
2369 #define COMP6_CSR_COMP6OUTSEL_2          (0x4UL << COMP6_CSR_COMP6OUTSEL_Pos)   /*!< 0x00001000 */
2370 #define COMP6_CSR_COMP6OUTSEL_3          (0x8UL << COMP6_CSR_COMP6OUTSEL_Pos)   /*!< 0x00002000 */
2371 #define COMP6_CSR_COMP6POL_Pos           (15U)
2372 #define COMP6_CSR_COMP6POL_Msk           (0x1UL << COMP6_CSR_COMP6POL_Pos)      /*!< 0x00008000 */
2373 #define COMP6_CSR_COMP6POL               COMP6_CSR_COMP6POL_Msk                /*!< COMP6 output polarity */
2374 #define COMP6_CSR_COMP6BLANKING_Pos      (18U)
2375 #define COMP6_CSR_COMP6BLANKING_Msk      (0x3UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x000C0000 */
2376 #define COMP6_CSR_COMP6BLANKING          COMP6_CSR_COMP6BLANKING_Msk           /*!< COMP6 blanking */
2377 #define COMP6_CSR_COMP6BLANKING_0        (0x1UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00040000 */
2378 #define COMP6_CSR_COMP6BLANKING_1        (0x2UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00080000 */
2379 #define COMP6_CSR_COMP6BLANKING_2        (0x4UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00100000 */
2380 #define COMP6_CSR_COMP6OUT_Pos           (30U)
2381 #define COMP6_CSR_COMP6OUT_Msk           (0x1UL << COMP6_CSR_COMP6OUT_Pos)      /*!< 0x40000000 */
2382 #define COMP6_CSR_COMP6OUT               COMP6_CSR_COMP6OUT_Msk                /*!< COMP6 output level */
2383 #define COMP6_CSR_COMP6LOCK_Pos          (31U)
2384 #define COMP6_CSR_COMP6LOCK_Msk          (0x1UL << COMP6_CSR_COMP6LOCK_Pos)     /*!< 0x80000000 */
2385 #define COMP6_CSR_COMP6LOCK              COMP6_CSR_COMP6LOCK_Msk               /*!< COMP6 lock */
2386 
2387 /**********************  Bit definition for COMP_CSR register  ****************/
2388 #define COMP_CSR_COMPxEN_Pos            (0U)
2389 #define COMP_CSR_COMPxEN_Msk            (0x1UL << COMP_CSR_COMPxEN_Pos)         /*!< 0x00000001 */
2390 #define COMP_CSR_COMPxEN                COMP_CSR_COMPxEN_Msk                   /*!< COMPx enable */
2391 #define COMP_CSR_COMPxINSEL_Pos         (4U)
2392 #define COMP_CSR_COMPxINSEL_Msk         (0x40007UL << COMP_CSR_COMPxINSEL_Pos)  /*!< 0x00400070 */
2393 #define COMP_CSR_COMPxINSEL             COMP_CSR_COMPxINSEL_Msk                /*!< COMPx inverting input select */
2394 #define COMP_CSR_COMPxINSEL_0           (0x00000010U)                          /*!< COMPx inverting input select bit 0 */
2395 #define COMP_CSR_COMPxINSEL_1           (0x00000020U)                          /*!< COMPx inverting input select bit 1 */
2396 #define COMP_CSR_COMPxINSEL_2           (0x00000040U)                          /*!< COMPx inverting input select bit 2 */
2397 #define COMP_CSR_COMPxINSEL_3           (0x00400000U)                          /*!< COMPx inverting input select bit 3 */
2398 #define COMP_CSR_COMPxOUTSEL_Pos        (10U)
2399 #define COMP_CSR_COMPxOUTSEL_Msk        (0xFUL << COMP_CSR_COMPxOUTSEL_Pos)     /*!< 0x00003C00 */
2400 #define COMP_CSR_COMPxOUTSEL            COMP_CSR_COMPxOUTSEL_Msk               /*!< COMPx output select */
2401 #define COMP_CSR_COMPxOUTSEL_0          (0x1UL << COMP_CSR_COMPxOUTSEL_Pos)     /*!< 0x00000400 */
2402 #define COMP_CSR_COMPxOUTSEL_1          (0x2UL << COMP_CSR_COMPxOUTSEL_Pos)     /*!< 0x00000800 */
2403 #define COMP_CSR_COMPxOUTSEL_2          (0x4UL << COMP_CSR_COMPxOUTSEL_Pos)     /*!< 0x00001000 */
2404 #define COMP_CSR_COMPxOUTSEL_3          (0x8UL << COMP_CSR_COMPxOUTSEL_Pos)     /*!< 0x00002000 */
2405 #define COMP_CSR_COMPxPOL_Pos           (15U)
2406 #define COMP_CSR_COMPxPOL_Msk           (0x1UL << COMP_CSR_COMPxPOL_Pos)        /*!< 0x00008000 */
2407 #define COMP_CSR_COMPxPOL               COMP_CSR_COMPxPOL_Msk                  /*!< COMPx output polarity */
2408 #define COMP_CSR_COMPxBLANKING_Pos      (18U)
2409 #define COMP_CSR_COMPxBLANKING_Msk      (0x3UL << COMP_CSR_COMPxBLANKING_Pos)   /*!< 0x000C0000 */
2410 #define COMP_CSR_COMPxBLANKING          COMP_CSR_COMPxBLANKING_Msk             /*!< COMPx blanking */
2411 #define COMP_CSR_COMPxBLANKING_0        (0x1UL << COMP_CSR_COMPxBLANKING_Pos)   /*!< 0x00040000 */
2412 #define COMP_CSR_COMPxBLANKING_1        (0x2UL << COMP_CSR_COMPxBLANKING_Pos)   /*!< 0x00080000 */
2413 #define COMP_CSR_COMPxBLANKING_2        (0x4UL << COMP_CSR_COMPxBLANKING_Pos)   /*!< 0x00100000 */
2414 #define COMP_CSR_COMPxOUT_Pos           (30U)
2415 #define COMP_CSR_COMPxOUT_Msk           (0x1UL << COMP_CSR_COMPxOUT_Pos)        /*!< 0x40000000 */
2416 #define COMP_CSR_COMPxOUT               COMP_CSR_COMPxOUT_Msk                  /*!< COMPx output level */
2417 #define COMP_CSR_COMPxLOCK_Pos          (31U)
2418 #define COMP_CSR_COMPxLOCK_Msk          (0x1UL << COMP_CSR_COMPxLOCK_Pos)       /*!< 0x80000000 */
2419 #define COMP_CSR_COMPxLOCK              COMP_CSR_COMPxLOCK_Msk                 /*!< COMPx lock */
2420 
2421 /******************************************************************************/
2422 /*                                                                            */
2423 /*                     Operational Amplifier (OPAMP)                          */
2424 /*                                                                            */
2425 /******************************************************************************/
2426 /*********************  Bit definition for OPAMP2_CSR register  ***************/
2427 #define OPAMP2_CSR_OPAMP2EN_Pos       (0U)
2428 #define OPAMP2_CSR_OPAMP2EN_Msk       (0x1UL << OPAMP2_CSR_OPAMP2EN_Pos)        /*!< 0x00000001 */
2429 #define OPAMP2_CSR_OPAMP2EN           OPAMP2_CSR_OPAMP2EN_Msk                  /*!< OPAMP2 enable */
2430 #define OPAMP2_CSR_FORCEVP_Pos        (1U)
2431 #define OPAMP2_CSR_FORCEVP_Msk        (0x1UL << OPAMP2_CSR_FORCEVP_Pos)         /*!< 0x00000002 */
2432 #define OPAMP2_CSR_FORCEVP            OPAMP2_CSR_FORCEVP_Msk                   /*!< Connect the internal references to the plus input of the OPAMPX */
2433 #define OPAMP2_CSR_VPSEL_Pos          (2U)
2434 #define OPAMP2_CSR_VPSEL_Msk          (0x3UL << OPAMP2_CSR_VPSEL_Pos)           /*!< 0x0000000C */
2435 #define OPAMP2_CSR_VPSEL              OPAMP2_CSR_VPSEL_Msk                     /*!< Non inverting input selection */
2436 #define OPAMP2_CSR_VPSEL_0            (0x1UL << OPAMP2_CSR_VPSEL_Pos)           /*!< 0x00000004 */
2437 #define OPAMP2_CSR_VPSEL_1            (0x2UL << OPAMP2_CSR_VPSEL_Pos)           /*!< 0x00000008 */
2438 #define OPAMP2_CSR_VMSEL_Pos          (5U)
2439 #define OPAMP2_CSR_VMSEL_Msk          (0x3UL << OPAMP2_CSR_VMSEL_Pos)           /*!< 0x00000060 */
2440 #define OPAMP2_CSR_VMSEL              OPAMP2_CSR_VMSEL_Msk                     /*!< Inverting input selection */
2441 #define OPAMP2_CSR_VMSEL_0            (0x1UL << OPAMP2_CSR_VMSEL_Pos)           /*!< 0x00000020 */
2442 #define OPAMP2_CSR_VMSEL_1            (0x2UL << OPAMP2_CSR_VMSEL_Pos)           /*!< 0x00000040 */
2443 #define OPAMP2_CSR_TCMEN_Pos          (7U)
2444 #define OPAMP2_CSR_TCMEN_Msk          (0x1UL << OPAMP2_CSR_TCMEN_Pos)           /*!< 0x00000080 */
2445 #define OPAMP2_CSR_TCMEN              OPAMP2_CSR_TCMEN_Msk                     /*!< Timer-Controlled Mux mode enable */
2446 #define OPAMP2_CSR_VMSSEL_Pos         (8U)
2447 #define OPAMP2_CSR_VMSSEL_Msk         (0x1UL << OPAMP2_CSR_VMSSEL_Pos)          /*!< 0x00000100 */
2448 #define OPAMP2_CSR_VMSSEL             OPAMP2_CSR_VMSSEL_Msk                    /*!< Inverting input secondary selection */
2449 #define OPAMP2_CSR_VPSSEL_Pos         (9U)
2450 #define OPAMP2_CSR_VPSSEL_Msk         (0x3UL << OPAMP2_CSR_VPSSEL_Pos)          /*!< 0x00000600 */
2451 #define OPAMP2_CSR_VPSSEL             OPAMP2_CSR_VPSSEL_Msk                    /*!< Non inverting input secondary selection */
2452 #define OPAMP2_CSR_VPSSEL_0           (0x1UL << OPAMP2_CSR_VPSSEL_Pos)          /*!< 0x00000200 */
2453 #define OPAMP2_CSR_VPSSEL_1           (0x2UL << OPAMP2_CSR_VPSSEL_Pos)          /*!< 0x00000400 */
2454 #define OPAMP2_CSR_CALON_Pos          (11U)
2455 #define OPAMP2_CSR_CALON_Msk          (0x1UL << OPAMP2_CSR_CALON_Pos)           /*!< 0x00000800 */
2456 #define OPAMP2_CSR_CALON              OPAMP2_CSR_CALON_Msk                     /*!< Calibration mode enable */
2457 #define OPAMP2_CSR_CALSEL_Pos         (12U)
2458 #define OPAMP2_CSR_CALSEL_Msk         (0x3UL << OPAMP2_CSR_CALSEL_Pos)          /*!< 0x00003000 */
2459 #define OPAMP2_CSR_CALSEL             OPAMP2_CSR_CALSEL_Msk                    /*!< Calibration selection */
2460 #define OPAMP2_CSR_CALSEL_0           (0x1UL << OPAMP2_CSR_CALSEL_Pos)          /*!< 0x00001000 */
2461 #define OPAMP2_CSR_CALSEL_1           (0x2UL << OPAMP2_CSR_CALSEL_Pos)          /*!< 0x00002000 */
2462 #define OPAMP2_CSR_PGGAIN_Pos         (14U)
2463 #define OPAMP2_CSR_PGGAIN_Msk         (0xFUL << OPAMP2_CSR_PGGAIN_Pos)          /*!< 0x0003C000 */
2464 #define OPAMP2_CSR_PGGAIN             OPAMP2_CSR_PGGAIN_Msk                    /*!< Gain in PGA mode */
2465 #define OPAMP2_CSR_PGGAIN_0           (0x1UL << OPAMP2_CSR_PGGAIN_Pos)          /*!< 0x00004000 */
2466 #define OPAMP2_CSR_PGGAIN_1           (0x2UL << OPAMP2_CSR_PGGAIN_Pos)          /*!< 0x00008000 */
2467 #define OPAMP2_CSR_PGGAIN_2           (0x4UL << OPAMP2_CSR_PGGAIN_Pos)          /*!< 0x00010000 */
2468 #define OPAMP2_CSR_PGGAIN_3           (0x8UL << OPAMP2_CSR_PGGAIN_Pos)          /*!< 0x00020000 */
2469 #define OPAMP2_CSR_USERTRIM_Pos       (18U)
2470 #define OPAMP2_CSR_USERTRIM_Msk       (0x1UL << OPAMP2_CSR_USERTRIM_Pos)        /*!< 0x00040000 */
2471 #define OPAMP2_CSR_USERTRIM           OPAMP2_CSR_USERTRIM_Msk                  /*!< User trimming enable */
2472 #define OPAMP2_CSR_TRIMOFFSETP_Pos    (19U)
2473 #define OPAMP2_CSR_TRIMOFFSETP_Msk    (0x1FUL << OPAMP2_CSR_TRIMOFFSETP_Pos)    /*!< 0x00F80000 */
2474 #define OPAMP2_CSR_TRIMOFFSETP        OPAMP2_CSR_TRIMOFFSETP_Msk               /*!< Offset trimming value (PMOS) */
2475 #define OPAMP2_CSR_TRIMOFFSETN_Pos    (24U)
2476 #define OPAMP2_CSR_TRIMOFFSETN_Msk    (0x1FUL << OPAMP2_CSR_TRIMOFFSETN_Pos)    /*!< 0x1F000000 */
2477 #define OPAMP2_CSR_TRIMOFFSETN        OPAMP2_CSR_TRIMOFFSETN_Msk               /*!< Offset trimming value (NMOS) */
2478 #define OPAMP2_CSR_TSTREF_Pos         (29U)
2479 #define OPAMP2_CSR_TSTREF_Msk         (0x1UL << OPAMP2_CSR_TSTREF_Pos)          /*!< 0x20000000 */
2480 #define OPAMP2_CSR_TSTREF             OPAMP2_CSR_TSTREF_Msk                    /*!< It enables the switch to put out the internal reference */
2481 #define OPAMP2_CSR_OUTCAL_Pos         (30U)
2482 #define OPAMP2_CSR_OUTCAL_Msk         (0x1UL << OPAMP2_CSR_OUTCAL_Pos)          /*!< 0x40000000 */
2483 #define OPAMP2_CSR_OUTCAL             OPAMP2_CSR_OUTCAL_Msk                    /*!< OPAMP ouput status flag */
2484 #define OPAMP2_CSR_LOCK_Pos           (31U)
2485 #define OPAMP2_CSR_LOCK_Msk           (0x1UL << OPAMP2_CSR_LOCK_Pos)            /*!< 0x80000000 */
2486 #define OPAMP2_CSR_LOCK               OPAMP2_CSR_LOCK_Msk                      /*!< OPAMP lock */
2487 
2488 /*********************  Bit definition for OPAMPx_CSR register  ***************/
2489 #define OPAMP_CSR_OPAMPxEN_Pos       (0U)
2490 #define OPAMP_CSR_OPAMPxEN_Msk       (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)          /*!< 0x00000001 */
2491 #define OPAMP_CSR_OPAMPxEN           OPAMP_CSR_OPAMPxEN_Msk                    /*!< OPAMP enable */
2492 #define OPAMP_CSR_FORCEVP_Pos        (1U)
2493 #define OPAMP_CSR_FORCEVP_Msk        (0x1UL << OPAMP_CSR_FORCEVP_Pos)           /*!< 0x00000002 */
2494 #define OPAMP_CSR_FORCEVP            OPAMP_CSR_FORCEVP_Msk                     /*!< Connect the internal references to the plus input of the OPAMPX */
2495 #define OPAMP_CSR_VPSEL_Pos          (2U)
2496 #define OPAMP_CSR_VPSEL_Msk          (0x3UL << OPAMP_CSR_VPSEL_Pos)             /*!< 0x0000000C */
2497 #define OPAMP_CSR_VPSEL              OPAMP_CSR_VPSEL_Msk                       /*!< Non inverting input selection */
2498 #define OPAMP_CSR_VPSEL_0            (0x1UL << OPAMP_CSR_VPSEL_Pos)             /*!< 0x00000004 */
2499 #define OPAMP_CSR_VPSEL_1            (0x2UL << OPAMP_CSR_VPSEL_Pos)             /*!< 0x00000008 */
2500 #define OPAMP_CSR_VMSEL_Pos          (5U)
2501 #define OPAMP_CSR_VMSEL_Msk          (0x3UL << OPAMP_CSR_VMSEL_Pos)             /*!< 0x00000060 */
2502 #define OPAMP_CSR_VMSEL              OPAMP_CSR_VMSEL_Msk                       /*!< Inverting input selection */
2503 #define OPAMP_CSR_VMSEL_0            (0x1UL << OPAMP_CSR_VMSEL_Pos)             /*!< 0x00000020 */
2504 #define OPAMP_CSR_VMSEL_1            (0x2UL << OPAMP_CSR_VMSEL_Pos)             /*!< 0x00000040 */
2505 #define OPAMP_CSR_TCMEN_Pos          (7U)
2506 #define OPAMP_CSR_TCMEN_Msk          (0x1UL << OPAMP_CSR_TCMEN_Pos)             /*!< 0x00000080 */
2507 #define OPAMP_CSR_TCMEN              OPAMP_CSR_TCMEN_Msk                       /*!< Timer-Controlled Mux mode enable */
2508 #define OPAMP_CSR_VMSSEL_Pos         (8U)
2509 #define OPAMP_CSR_VMSSEL_Msk         (0x1UL << OPAMP_CSR_VMSSEL_Pos)            /*!< 0x00000100 */
2510 #define OPAMP_CSR_VMSSEL             OPAMP_CSR_VMSSEL_Msk                      /*!< Inverting input secondary selection */
2511 #define OPAMP_CSR_VPSSEL_Pos         (9U)
2512 #define OPAMP_CSR_VPSSEL_Msk         (0x3UL << OPAMP_CSR_VPSSEL_Pos)            /*!< 0x00000600 */
2513 #define OPAMP_CSR_VPSSEL             OPAMP_CSR_VPSSEL_Msk                      /*!< Non inverting input secondary selection */
2514 #define OPAMP_CSR_VPSSEL_0           (0x1UL << OPAMP_CSR_VPSSEL_Pos)            /*!< 0x00000200 */
2515 #define OPAMP_CSR_VPSSEL_1           (0x2UL << OPAMP_CSR_VPSSEL_Pos)            /*!< 0x00000400 */
2516 #define OPAMP_CSR_CALON_Pos          (11U)
2517 #define OPAMP_CSR_CALON_Msk          (0x1UL << OPAMP_CSR_CALON_Pos)             /*!< 0x00000800 */
2518 #define OPAMP_CSR_CALON              OPAMP_CSR_CALON_Msk                       /*!< Calibration mode enable */
2519 #define OPAMP_CSR_CALSEL_Pos         (12U)
2520 #define OPAMP_CSR_CALSEL_Msk         (0x3UL << OPAMP_CSR_CALSEL_Pos)            /*!< 0x00003000 */
2521 #define OPAMP_CSR_CALSEL             OPAMP_CSR_CALSEL_Msk                      /*!< Calibration selection */
2522 #define OPAMP_CSR_CALSEL_0           (0x1UL << OPAMP_CSR_CALSEL_Pos)            /*!< 0x00001000 */
2523 #define OPAMP_CSR_CALSEL_1           (0x2UL << OPAMP_CSR_CALSEL_Pos)            /*!< 0x00002000 */
2524 #define OPAMP_CSR_PGGAIN_Pos         (14U)
2525 #define OPAMP_CSR_PGGAIN_Msk         (0xFUL << OPAMP_CSR_PGGAIN_Pos)            /*!< 0x0003C000 */
2526 #define OPAMP_CSR_PGGAIN             OPAMP_CSR_PGGAIN_Msk                      /*!< Gain in PGA mode */
2527 #define OPAMP_CSR_PGGAIN_0           (0x1UL << OPAMP_CSR_PGGAIN_Pos)            /*!< 0x00004000 */
2528 #define OPAMP_CSR_PGGAIN_1           (0x2UL << OPAMP_CSR_PGGAIN_Pos)            /*!< 0x00008000 */
2529 #define OPAMP_CSR_PGGAIN_2           (0x4UL << OPAMP_CSR_PGGAIN_Pos)            /*!< 0x00010000 */
2530 #define OPAMP_CSR_PGGAIN_3           (0x8UL << OPAMP_CSR_PGGAIN_Pos)            /*!< 0x00020000 */
2531 #define OPAMP_CSR_USERTRIM_Pos       (18U)
2532 #define OPAMP_CSR_USERTRIM_Msk       (0x1UL << OPAMP_CSR_USERTRIM_Pos)          /*!< 0x00040000 */
2533 #define OPAMP_CSR_USERTRIM           OPAMP_CSR_USERTRIM_Msk                    /*!< User trimming enable */
2534 #define OPAMP_CSR_TRIMOFFSETP_Pos    (19U)
2535 #define OPAMP_CSR_TRIMOFFSETP_Msk    (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos)      /*!< 0x00F80000 */
2536 #define OPAMP_CSR_TRIMOFFSETP        OPAMP_CSR_TRIMOFFSETP_Msk                 /*!< Offset trimming value (PMOS) */
2537 #define OPAMP_CSR_TRIMOFFSETN_Pos    (24U)
2538 #define OPAMP_CSR_TRIMOFFSETN_Msk    (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos)      /*!< 0x1F000000 */
2539 #define OPAMP_CSR_TRIMOFFSETN        OPAMP_CSR_TRIMOFFSETN_Msk                 /*!< Offset trimming value (NMOS) */
2540 #define OPAMP_CSR_TSTREF_Pos         (29U)
2541 #define OPAMP_CSR_TSTREF_Msk         (0x1UL << OPAMP_CSR_TSTREF_Pos)            /*!< 0x20000000 */
2542 #define OPAMP_CSR_TSTREF             OPAMP_CSR_TSTREF_Msk                      /*!< It enables the switch to put out the internal reference */
2543 #define OPAMP_CSR_OUTCAL_Pos         (30U)
2544 #define OPAMP_CSR_OUTCAL_Msk         (0x1UL << OPAMP_CSR_OUTCAL_Pos)            /*!< 0x40000000 */
2545 #define OPAMP_CSR_OUTCAL             OPAMP_CSR_OUTCAL_Msk                      /*!< OPAMP ouput status flag */
2546 #define OPAMP_CSR_LOCK_Pos           (31U)
2547 #define OPAMP_CSR_LOCK_Msk           (0x1UL << OPAMP_CSR_LOCK_Pos)              /*!< 0x80000000 */
2548 #define OPAMP_CSR_LOCK               OPAMP_CSR_LOCK_Msk                        /*!< OPAMP lock */
2549 
2550 /******************************************************************************/
2551 /*                                                                            */
2552 /*                   Controller Area Network (CAN )                           */
2553 /*                                                                            */
2554 /******************************************************************************/
2555 /*******************  Bit definition for CAN_MCR register  ********************/
2556 #define CAN_MCR_INRQ_Pos       (0U)
2557 #define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
2558 #define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
2559 #define CAN_MCR_SLEEP_Pos      (1U)
2560 #define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
2561 #define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
2562 #define CAN_MCR_TXFP_Pos       (2U)
2563 #define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
2564 #define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
2565 #define CAN_MCR_RFLM_Pos       (3U)
2566 #define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
2567 #define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
2568 #define CAN_MCR_NART_Pos       (4U)
2569 #define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
2570 #define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
2571 #define CAN_MCR_AWUM_Pos       (5U)
2572 #define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
2573 #define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
2574 #define CAN_MCR_ABOM_Pos       (6U)
2575 #define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
2576 #define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
2577 #define CAN_MCR_TTCM_Pos       (7U)
2578 #define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
2579 #define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
2580 #define CAN_MCR_RESET_Pos      (15U)
2581 #define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
2582 #define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
2583 
2584 /*******************  Bit definition for CAN_MSR register  ********************/
2585 #define CAN_MSR_INAK_Pos       (0U)
2586 #define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
2587 #define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
2588 #define CAN_MSR_SLAK_Pos       (1U)
2589 #define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
2590 #define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
2591 #define CAN_MSR_ERRI_Pos       (2U)
2592 #define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
2593 #define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
2594 #define CAN_MSR_WKUI_Pos       (3U)
2595 #define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
2596 #define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
2597 #define CAN_MSR_SLAKI_Pos      (4U)
2598 #define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
2599 #define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
2600 #define CAN_MSR_TXM_Pos        (8U)
2601 #define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
2602 #define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
2603 #define CAN_MSR_RXM_Pos        (9U)
2604 #define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
2605 #define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
2606 #define CAN_MSR_SAMP_Pos       (10U)
2607 #define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
2608 #define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
2609 #define CAN_MSR_RX_Pos         (11U)
2610 #define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
2611 #define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
2612 
2613 /*******************  Bit definition for CAN_TSR register  ********************/
2614 #define CAN_TSR_RQCP0_Pos      (0U)
2615 #define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
2616 #define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
2617 #define CAN_TSR_TXOK0_Pos      (1U)
2618 #define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
2619 #define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
2620 #define CAN_TSR_ALST0_Pos      (2U)
2621 #define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
2622 #define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
2623 #define CAN_TSR_TERR0_Pos      (3U)
2624 #define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
2625 #define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
2626 #define CAN_TSR_ABRQ0_Pos      (7U)
2627 #define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
2628 #define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
2629 #define CAN_TSR_RQCP1_Pos      (8U)
2630 #define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
2631 #define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
2632 #define CAN_TSR_TXOK1_Pos      (9U)
2633 #define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
2634 #define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
2635 #define CAN_TSR_ALST1_Pos      (10U)
2636 #define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
2637 #define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
2638 #define CAN_TSR_TERR1_Pos      (11U)
2639 #define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
2640 #define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
2641 #define CAN_TSR_ABRQ1_Pos      (15U)
2642 #define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
2643 #define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
2644 #define CAN_TSR_RQCP2_Pos      (16U)
2645 #define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
2646 #define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
2647 #define CAN_TSR_TXOK2_Pos      (17U)
2648 #define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
2649 #define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
2650 #define CAN_TSR_ALST2_Pos      (18U)
2651 #define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
2652 #define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
2653 #define CAN_TSR_TERR2_Pos      (19U)
2654 #define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
2655 #define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
2656 #define CAN_TSR_ABRQ2_Pos      (23U)
2657 #define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
2658 #define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
2659 #define CAN_TSR_CODE_Pos       (24U)
2660 #define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
2661 #define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
2662 
2663 #define CAN_TSR_TME_Pos        (26U)
2664 #define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
2665 #define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
2666 #define CAN_TSR_TME0_Pos       (26U)
2667 #define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
2668 #define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
2669 #define CAN_TSR_TME1_Pos       (27U)
2670 #define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
2671 #define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
2672 #define CAN_TSR_TME2_Pos       (28U)
2673 #define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
2674 #define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
2675 
2676 #define CAN_TSR_LOW_Pos        (29U)
2677 #define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
2678 #define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
2679 #define CAN_TSR_LOW0_Pos       (29U)
2680 #define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
2681 #define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
2682 #define CAN_TSR_LOW1_Pos       (30U)
2683 #define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
2684 #define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
2685 #define CAN_TSR_LOW2_Pos       (31U)
2686 #define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
2687 #define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
2688 
2689 /*******************  Bit definition for CAN_RF0R register  *******************/
2690 #define CAN_RF0R_FMP0_Pos      (0U)
2691 #define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
2692 #define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
2693 #define CAN_RF0R_FULL0_Pos     (3U)
2694 #define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
2695 #define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
2696 #define CAN_RF0R_FOVR0_Pos     (4U)
2697 #define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
2698 #define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
2699 #define CAN_RF0R_RFOM0_Pos     (5U)
2700 #define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
2701 #define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
2702 
2703 /*******************  Bit definition for CAN_RF1R register  *******************/
2704 #define CAN_RF1R_FMP1_Pos      (0U)
2705 #define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
2706 #define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
2707 #define CAN_RF1R_FULL1_Pos     (3U)
2708 #define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
2709 #define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
2710 #define CAN_RF1R_FOVR1_Pos     (4U)
2711 #define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
2712 #define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
2713 #define CAN_RF1R_RFOM1_Pos     (5U)
2714 #define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
2715 #define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
2716 
2717 /********************  Bit definition for CAN_IER register  *******************/
2718 #define CAN_IER_TMEIE_Pos      (0U)
2719 #define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
2720 #define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
2721 #define CAN_IER_FMPIE0_Pos     (1U)
2722 #define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
2723 #define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
2724 #define CAN_IER_FFIE0_Pos      (2U)
2725 #define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
2726 #define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
2727 #define CAN_IER_FOVIE0_Pos     (3U)
2728 #define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
2729 #define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
2730 #define CAN_IER_FMPIE1_Pos     (4U)
2731 #define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
2732 #define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
2733 #define CAN_IER_FFIE1_Pos      (5U)
2734 #define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
2735 #define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
2736 #define CAN_IER_FOVIE1_Pos     (6U)
2737 #define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
2738 #define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
2739 #define CAN_IER_EWGIE_Pos      (8U)
2740 #define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
2741 #define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
2742 #define CAN_IER_EPVIE_Pos      (9U)
2743 #define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
2744 #define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
2745 #define CAN_IER_BOFIE_Pos      (10U)
2746 #define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
2747 #define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
2748 #define CAN_IER_LECIE_Pos      (11U)
2749 #define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
2750 #define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
2751 #define CAN_IER_ERRIE_Pos      (15U)
2752 #define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
2753 #define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
2754 #define CAN_IER_WKUIE_Pos      (16U)
2755 #define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
2756 #define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
2757 #define CAN_IER_SLKIE_Pos      (17U)
2758 #define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
2759 #define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
2760 
2761 /********************  Bit definition for CAN_ESR register  *******************/
2762 #define CAN_ESR_EWGF_Pos       (0U)
2763 #define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
2764 #define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
2765 #define CAN_ESR_EPVF_Pos       (1U)
2766 #define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
2767 #define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
2768 #define CAN_ESR_BOFF_Pos       (2U)
2769 #define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
2770 #define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
2771 
2772 #define CAN_ESR_LEC_Pos        (4U)
2773 #define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
2774 #define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
2775 #define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
2776 #define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
2777 #define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
2778 
2779 #define CAN_ESR_TEC_Pos        (16U)
2780 #define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
2781 #define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
2782 #define CAN_ESR_REC_Pos        (24U)
2783 #define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
2784 #define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
2785 
2786 /*******************  Bit definition for CAN_BTR register  ********************/
2787 #define CAN_BTR_BRP_Pos        (0U)
2788 #define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
2789 #define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
2790 #define CAN_BTR_TS1_Pos        (16U)
2791 #define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
2792 #define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
2793 #define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
2794 #define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
2795 #define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
2796 #define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
2797 #define CAN_BTR_TS2_Pos        (20U)
2798 #define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
2799 #define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
2800 #define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
2801 #define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
2802 #define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
2803 #define CAN_BTR_SJW_Pos        (24U)
2804 #define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
2805 #define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
2806 #define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
2807 #define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
2808 #define CAN_BTR_LBKM_Pos       (30U)
2809 #define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
2810 #define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
2811 #define CAN_BTR_SILM_Pos       (31U)
2812 #define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
2813 #define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
2814 
2815 /*!<Mailbox registers */
2816 /******************  Bit definition for CAN_TI0R register  ********************/
2817 #define CAN_TI0R_TXRQ_Pos      (0U)
2818 #define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
2819 #define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2820 #define CAN_TI0R_RTR_Pos       (1U)
2821 #define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
2822 #define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
2823 #define CAN_TI0R_IDE_Pos       (2U)
2824 #define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
2825 #define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
2826 #define CAN_TI0R_EXID_Pos      (3U)
2827 #define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2828 #define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
2829 #define CAN_TI0R_STID_Pos      (21U)
2830 #define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
2831 #define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2832 
2833 /******************  Bit definition for CAN_TDT0R register  *******************/
2834 #define CAN_TDT0R_DLC_Pos      (0U)
2835 #define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
2836 #define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
2837 #define CAN_TDT0R_TGT_Pos      (8U)
2838 #define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
2839 #define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
2840 #define CAN_TDT0R_TIME_Pos     (16U)
2841 #define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
2842 #define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
2843 
2844 /******************  Bit definition for CAN_TDL0R register  *******************/
2845 #define CAN_TDL0R_DATA0_Pos    (0U)
2846 #define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
2847 #define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
2848 #define CAN_TDL0R_DATA1_Pos    (8U)
2849 #define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
2850 #define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
2851 #define CAN_TDL0R_DATA2_Pos    (16U)
2852 #define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
2853 #define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
2854 #define CAN_TDL0R_DATA3_Pos    (24U)
2855 #define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
2856 #define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
2857 
2858 /******************  Bit definition for CAN_TDH0R register  *******************/
2859 #define CAN_TDH0R_DATA4_Pos    (0U)
2860 #define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
2861 #define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
2862 #define CAN_TDH0R_DATA5_Pos    (8U)
2863 #define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
2864 #define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
2865 #define CAN_TDH0R_DATA6_Pos    (16U)
2866 #define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
2867 #define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
2868 #define CAN_TDH0R_DATA7_Pos    (24U)
2869 #define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
2870 #define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
2871 
2872 /*******************  Bit definition for CAN_TI1R register  *******************/
2873 #define CAN_TI1R_TXRQ_Pos      (0U)
2874 #define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
2875 #define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2876 #define CAN_TI1R_RTR_Pos       (1U)
2877 #define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
2878 #define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
2879 #define CAN_TI1R_IDE_Pos       (2U)
2880 #define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
2881 #define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
2882 #define CAN_TI1R_EXID_Pos      (3U)
2883 #define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
2884 #define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
2885 #define CAN_TI1R_STID_Pos      (21U)
2886 #define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
2887 #define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2888 
2889 /*******************  Bit definition for CAN_TDT1R register  ******************/
2890 #define CAN_TDT1R_DLC_Pos      (0U)
2891 #define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
2892 #define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
2893 #define CAN_TDT1R_TGT_Pos      (8U)
2894 #define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
2895 #define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
2896 #define CAN_TDT1R_TIME_Pos     (16U)
2897 #define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
2898 #define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
2899 
2900 /*******************  Bit definition for CAN_TDL1R register  ******************/
2901 #define CAN_TDL1R_DATA0_Pos    (0U)
2902 #define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
2903 #define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
2904 #define CAN_TDL1R_DATA1_Pos    (8U)
2905 #define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
2906 #define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
2907 #define CAN_TDL1R_DATA2_Pos    (16U)
2908 #define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
2909 #define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
2910 #define CAN_TDL1R_DATA3_Pos    (24U)
2911 #define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
2912 #define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
2913 
2914 /*******************  Bit definition for CAN_TDH1R register  ******************/
2915 #define CAN_TDH1R_DATA4_Pos    (0U)
2916 #define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
2917 #define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
2918 #define CAN_TDH1R_DATA5_Pos    (8U)
2919 #define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
2920 #define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
2921 #define CAN_TDH1R_DATA6_Pos    (16U)
2922 #define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
2923 #define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
2924 #define CAN_TDH1R_DATA7_Pos    (24U)
2925 #define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
2926 #define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
2927 
2928 /*******************  Bit definition for CAN_TI2R register  *******************/
2929 #define CAN_TI2R_TXRQ_Pos      (0U)
2930 #define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
2931 #define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2932 #define CAN_TI2R_RTR_Pos       (1U)
2933 #define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
2934 #define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
2935 #define CAN_TI2R_IDE_Pos       (2U)
2936 #define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
2937 #define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
2938 #define CAN_TI2R_EXID_Pos      (3U)
2939 #define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
2940 #define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
2941 #define CAN_TI2R_STID_Pos      (21U)
2942 #define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
2943 #define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2944 
2945 /*******************  Bit definition for CAN_TDT2R register  ******************/
2946 #define CAN_TDT2R_DLC_Pos      (0U)
2947 #define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
2948 #define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
2949 #define CAN_TDT2R_TGT_Pos      (8U)
2950 #define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
2951 #define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
2952 #define CAN_TDT2R_TIME_Pos     (16U)
2953 #define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
2954 #define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
2955 
2956 /*******************  Bit definition for CAN_TDL2R register  ******************/
2957 #define CAN_TDL2R_DATA0_Pos    (0U)
2958 #define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
2959 #define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
2960 #define CAN_TDL2R_DATA1_Pos    (8U)
2961 #define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
2962 #define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
2963 #define CAN_TDL2R_DATA2_Pos    (16U)
2964 #define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
2965 #define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
2966 #define CAN_TDL2R_DATA3_Pos    (24U)
2967 #define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
2968 #define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
2969 
2970 /*******************  Bit definition for CAN_TDH2R register  ******************/
2971 #define CAN_TDH2R_DATA4_Pos    (0U)
2972 #define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
2973 #define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
2974 #define CAN_TDH2R_DATA5_Pos    (8U)
2975 #define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
2976 #define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
2977 #define CAN_TDH2R_DATA6_Pos    (16U)
2978 #define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
2979 #define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
2980 #define CAN_TDH2R_DATA7_Pos    (24U)
2981 #define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
2982 #define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
2983 
2984 /*******************  Bit definition for CAN_RI0R register  *******************/
2985 #define CAN_RI0R_RTR_Pos       (1U)
2986 #define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
2987 #define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
2988 #define CAN_RI0R_IDE_Pos       (2U)
2989 #define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
2990 #define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
2991 #define CAN_RI0R_EXID_Pos      (3U)
2992 #define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2993 #define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
2994 #define CAN_RI0R_STID_Pos      (21U)
2995 #define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
2996 #define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2997 
2998 /*******************  Bit definition for CAN_RDT0R register  ******************/
2999 #define CAN_RDT0R_DLC_Pos      (0U)
3000 #define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
3001 #define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
3002 #define CAN_RDT0R_FMI_Pos      (8U)
3003 #define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
3004 #define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
3005 #define CAN_RDT0R_TIME_Pos     (16U)
3006 #define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
3007 #define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
3008 
3009 /*******************  Bit definition for CAN_RDL0R register  ******************/
3010 #define CAN_RDL0R_DATA0_Pos    (0U)
3011 #define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
3012 #define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
3013 #define CAN_RDL0R_DATA1_Pos    (8U)
3014 #define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
3015 #define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
3016 #define CAN_RDL0R_DATA2_Pos    (16U)
3017 #define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
3018 #define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
3019 #define CAN_RDL0R_DATA3_Pos    (24U)
3020 #define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
3021 #define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
3022 
3023 /*******************  Bit definition for CAN_RDH0R register  ******************/
3024 #define CAN_RDH0R_DATA4_Pos    (0U)
3025 #define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
3026 #define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
3027 #define CAN_RDH0R_DATA5_Pos    (8U)
3028 #define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
3029 #define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
3030 #define CAN_RDH0R_DATA6_Pos    (16U)
3031 #define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
3032 #define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
3033 #define CAN_RDH0R_DATA7_Pos    (24U)
3034 #define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
3035 #define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
3036 
3037 /*******************  Bit definition for CAN_RI1R register  *******************/
3038 #define CAN_RI1R_RTR_Pos       (1U)
3039 #define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
3040 #define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
3041 #define CAN_RI1R_IDE_Pos       (2U)
3042 #define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
3043 #define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
3044 #define CAN_RI1R_EXID_Pos      (3U)
3045 #define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
3046 #define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
3047 #define CAN_RI1R_STID_Pos      (21U)
3048 #define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
3049 #define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
3050 
3051 /*******************  Bit definition for CAN_RDT1R register  ******************/
3052 #define CAN_RDT1R_DLC_Pos      (0U)
3053 #define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
3054 #define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
3055 #define CAN_RDT1R_FMI_Pos      (8U)
3056 #define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
3057 #define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
3058 #define CAN_RDT1R_TIME_Pos     (16U)
3059 #define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
3060 #define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
3061 
3062 /*******************  Bit definition for CAN_RDL1R register  ******************/
3063 #define CAN_RDL1R_DATA0_Pos    (0U)
3064 #define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
3065 #define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
3066 #define CAN_RDL1R_DATA1_Pos    (8U)
3067 #define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
3068 #define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
3069 #define CAN_RDL1R_DATA2_Pos    (16U)
3070 #define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
3071 #define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
3072 #define CAN_RDL1R_DATA3_Pos    (24U)
3073 #define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
3074 #define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
3075 
3076 /*******************  Bit definition for CAN_RDH1R register  ******************/
3077 #define CAN_RDH1R_DATA4_Pos    (0U)
3078 #define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
3079 #define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
3080 #define CAN_RDH1R_DATA5_Pos    (8U)
3081 #define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
3082 #define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
3083 #define CAN_RDH1R_DATA6_Pos    (16U)
3084 #define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
3085 #define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
3086 #define CAN_RDH1R_DATA7_Pos    (24U)
3087 #define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
3088 #define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
3089 
3090 /*!<CAN filter registers */
3091 /*******************  Bit definition for CAN_FMR register  ********************/
3092 #define CAN_FMR_FINIT_Pos      (0U)
3093 #define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
3094 #define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
3095 
3096 /*******************  Bit definition for CAN_FM1R register  *******************/
3097 #define CAN_FM1R_FBM_Pos       (0U)
3098 #define CAN_FM1R_FBM_Msk       (0x3FFFUL << CAN_FM1R_FBM_Pos)                   /*!< 0x00003FFF */
3099 #define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
3100 #define CAN_FM1R_FBM0_Pos      (0U)
3101 #define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
3102 #define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
3103 #define CAN_FM1R_FBM1_Pos      (1U)
3104 #define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
3105 #define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
3106 #define CAN_FM1R_FBM2_Pos      (2U)
3107 #define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
3108 #define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
3109 #define CAN_FM1R_FBM3_Pos      (3U)
3110 #define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
3111 #define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
3112 #define CAN_FM1R_FBM4_Pos      (4U)
3113 #define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
3114 #define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
3115 #define CAN_FM1R_FBM5_Pos      (5U)
3116 #define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
3117 #define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
3118 #define CAN_FM1R_FBM6_Pos      (6U)
3119 #define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
3120 #define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
3121 #define CAN_FM1R_FBM7_Pos      (7U)
3122 #define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
3123 #define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
3124 #define CAN_FM1R_FBM8_Pos      (8U)
3125 #define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
3126 #define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
3127 #define CAN_FM1R_FBM9_Pos      (9U)
3128 #define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
3129 #define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
3130 #define CAN_FM1R_FBM10_Pos     (10U)
3131 #define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
3132 #define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
3133 #define CAN_FM1R_FBM11_Pos     (11U)
3134 #define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
3135 #define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
3136 #define CAN_FM1R_FBM12_Pos     (12U)
3137 #define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
3138 #define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
3139 #define CAN_FM1R_FBM13_Pos     (13U)
3140 #define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
3141 #define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
3142 
3143 /*******************  Bit definition for CAN_FS1R register  *******************/
3144 #define CAN_FS1R_FSC_Pos       (0U)
3145 #define CAN_FS1R_FSC_Msk       (0x3FFFUL << CAN_FS1R_FSC_Pos)                   /*!< 0x00003FFF */
3146 #define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
3147 #define CAN_FS1R_FSC0_Pos      (0U)
3148 #define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
3149 #define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
3150 #define CAN_FS1R_FSC1_Pos      (1U)
3151 #define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
3152 #define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
3153 #define CAN_FS1R_FSC2_Pos      (2U)
3154 #define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
3155 #define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
3156 #define CAN_FS1R_FSC3_Pos      (3U)
3157 #define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
3158 #define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
3159 #define CAN_FS1R_FSC4_Pos      (4U)
3160 #define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
3161 #define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
3162 #define CAN_FS1R_FSC5_Pos      (5U)
3163 #define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
3164 #define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
3165 #define CAN_FS1R_FSC6_Pos      (6U)
3166 #define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
3167 #define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
3168 #define CAN_FS1R_FSC7_Pos      (7U)
3169 #define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
3170 #define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
3171 #define CAN_FS1R_FSC8_Pos      (8U)
3172 #define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
3173 #define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
3174 #define CAN_FS1R_FSC9_Pos      (9U)
3175 #define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
3176 #define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
3177 #define CAN_FS1R_FSC10_Pos     (10U)
3178 #define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
3179 #define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
3180 #define CAN_FS1R_FSC11_Pos     (11U)
3181 #define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
3182 #define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
3183 #define CAN_FS1R_FSC12_Pos     (12U)
3184 #define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
3185 #define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
3186 #define CAN_FS1R_FSC13_Pos     (13U)
3187 #define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
3188 #define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
3189 
3190 /******************  Bit definition for CAN_FFA1R register  *******************/
3191 #define CAN_FFA1R_FFA_Pos      (0U)
3192 #define CAN_FFA1R_FFA_Msk      (0x3FFFUL << CAN_FFA1R_FFA_Pos)                  /*!< 0x00003FFF */
3193 #define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
3194 #define CAN_FFA1R_FFA0_Pos     (0U)
3195 #define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
3196 #define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */
3197 #define CAN_FFA1R_FFA1_Pos     (1U)
3198 #define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
3199 #define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */
3200 #define CAN_FFA1R_FFA2_Pos     (2U)
3201 #define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
3202 #define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */
3203 #define CAN_FFA1R_FFA3_Pos     (3U)
3204 #define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
3205 #define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */
3206 #define CAN_FFA1R_FFA4_Pos     (4U)
3207 #define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
3208 #define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */
3209 #define CAN_FFA1R_FFA5_Pos     (5U)
3210 #define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
3211 #define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */
3212 #define CAN_FFA1R_FFA6_Pos     (6U)
3213 #define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
3214 #define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */
3215 #define CAN_FFA1R_FFA7_Pos     (7U)
3216 #define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
3217 #define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */
3218 #define CAN_FFA1R_FFA8_Pos     (8U)
3219 #define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
3220 #define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */
3221 #define CAN_FFA1R_FFA9_Pos     (9U)
3222 #define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
3223 #define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */
3224 #define CAN_FFA1R_FFA10_Pos    (10U)
3225 #define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
3226 #define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */
3227 #define CAN_FFA1R_FFA11_Pos    (11U)
3228 #define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
3229 #define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */
3230 #define CAN_FFA1R_FFA12_Pos    (12U)
3231 #define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
3232 #define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */
3233 #define CAN_FFA1R_FFA13_Pos    (13U)
3234 #define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
3235 #define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */
3236 
3237 /*******************  Bit definition for CAN_FA1R register  *******************/
3238 #define CAN_FA1R_FACT_Pos      (0U)
3239 #define CAN_FA1R_FACT_Msk      (0x3FFFUL << CAN_FA1R_FACT_Pos)                  /*!< 0x00003FFF */
3240 #define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
3241 #define CAN_FA1R_FACT0_Pos     (0U)
3242 #define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
3243 #define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active */
3244 #define CAN_FA1R_FACT1_Pos     (1U)
3245 #define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
3246 #define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active */
3247 #define CAN_FA1R_FACT2_Pos     (2U)
3248 #define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
3249 #define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active */
3250 #define CAN_FA1R_FACT3_Pos     (3U)
3251 #define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
3252 #define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active */
3253 #define CAN_FA1R_FACT4_Pos     (4U)
3254 #define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
3255 #define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active */
3256 #define CAN_FA1R_FACT5_Pos     (5U)
3257 #define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
3258 #define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active */
3259 #define CAN_FA1R_FACT6_Pos     (6U)
3260 #define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
3261 #define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active */
3262 #define CAN_FA1R_FACT7_Pos     (7U)
3263 #define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
3264 #define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active */
3265 #define CAN_FA1R_FACT8_Pos     (8U)
3266 #define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
3267 #define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active */
3268 #define CAN_FA1R_FACT9_Pos     (9U)
3269 #define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
3270 #define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active */
3271 #define CAN_FA1R_FACT10_Pos    (10U)
3272 #define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
3273 #define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */
3274 #define CAN_FA1R_FACT11_Pos    (11U)
3275 #define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
3276 #define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */
3277 #define CAN_FA1R_FACT12_Pos    (12U)
3278 #define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
3279 #define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */
3280 #define CAN_FA1R_FACT13_Pos    (13U)
3281 #define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
3282 #define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */
3283 
3284 /*******************  Bit definition for CAN_F0R1 register  *******************/
3285 #define CAN_F0R1_FB0_Pos       (0U)
3286 #define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
3287 #define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
3288 #define CAN_F0R1_FB1_Pos       (1U)
3289 #define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
3290 #define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
3291 #define CAN_F0R1_FB2_Pos       (2U)
3292 #define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
3293 #define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
3294 #define CAN_F0R1_FB3_Pos       (3U)
3295 #define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
3296 #define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
3297 #define CAN_F0R1_FB4_Pos       (4U)
3298 #define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
3299 #define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
3300 #define CAN_F0R1_FB5_Pos       (5U)
3301 #define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
3302 #define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
3303 #define CAN_F0R1_FB6_Pos       (6U)
3304 #define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
3305 #define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
3306 #define CAN_F0R1_FB7_Pos       (7U)
3307 #define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
3308 #define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
3309 #define CAN_F0R1_FB8_Pos       (8U)
3310 #define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
3311 #define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
3312 #define CAN_F0R1_FB9_Pos       (9U)
3313 #define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
3314 #define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
3315 #define CAN_F0R1_FB10_Pos      (10U)
3316 #define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
3317 #define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
3318 #define CAN_F0R1_FB11_Pos      (11U)
3319 #define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
3320 #define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
3321 #define CAN_F0R1_FB12_Pos      (12U)
3322 #define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
3323 #define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
3324 #define CAN_F0R1_FB13_Pos      (13U)
3325 #define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
3326 #define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
3327 #define CAN_F0R1_FB14_Pos      (14U)
3328 #define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
3329 #define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
3330 #define CAN_F0R1_FB15_Pos      (15U)
3331 #define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
3332 #define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
3333 #define CAN_F0R1_FB16_Pos      (16U)
3334 #define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
3335 #define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
3336 #define CAN_F0R1_FB17_Pos      (17U)
3337 #define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
3338 #define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
3339 #define CAN_F0R1_FB18_Pos      (18U)
3340 #define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
3341 #define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
3342 #define CAN_F0R1_FB19_Pos      (19U)
3343 #define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
3344 #define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
3345 #define CAN_F0R1_FB20_Pos      (20U)
3346 #define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
3347 #define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
3348 #define CAN_F0R1_FB21_Pos      (21U)
3349 #define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
3350 #define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
3351 #define CAN_F0R1_FB22_Pos      (22U)
3352 #define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
3353 #define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
3354 #define CAN_F0R1_FB23_Pos      (23U)
3355 #define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
3356 #define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
3357 #define CAN_F0R1_FB24_Pos      (24U)
3358 #define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
3359 #define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
3360 #define CAN_F0R1_FB25_Pos      (25U)
3361 #define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
3362 #define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
3363 #define CAN_F0R1_FB26_Pos      (26U)
3364 #define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
3365 #define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
3366 #define CAN_F0R1_FB27_Pos      (27U)
3367 #define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
3368 #define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
3369 #define CAN_F0R1_FB28_Pos      (28U)
3370 #define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
3371 #define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
3372 #define CAN_F0R1_FB29_Pos      (29U)
3373 #define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
3374 #define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
3375 #define CAN_F0R1_FB30_Pos      (30U)
3376 #define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
3377 #define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
3378 #define CAN_F0R1_FB31_Pos      (31U)
3379 #define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
3380 #define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
3381 
3382 /*******************  Bit definition for CAN_F1R1 register  *******************/
3383 #define CAN_F1R1_FB0_Pos       (0U)
3384 #define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
3385 #define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
3386 #define CAN_F1R1_FB1_Pos       (1U)
3387 #define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
3388 #define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
3389 #define CAN_F1R1_FB2_Pos       (2U)
3390 #define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
3391 #define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
3392 #define CAN_F1R1_FB3_Pos       (3U)
3393 #define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
3394 #define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
3395 #define CAN_F1R1_FB4_Pos       (4U)
3396 #define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
3397 #define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
3398 #define CAN_F1R1_FB5_Pos       (5U)
3399 #define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
3400 #define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
3401 #define CAN_F1R1_FB6_Pos       (6U)
3402 #define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
3403 #define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
3404 #define CAN_F1R1_FB7_Pos       (7U)
3405 #define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
3406 #define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
3407 #define CAN_F1R1_FB8_Pos       (8U)
3408 #define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
3409 #define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
3410 #define CAN_F1R1_FB9_Pos       (9U)
3411 #define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
3412 #define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
3413 #define CAN_F1R1_FB10_Pos      (10U)
3414 #define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
3415 #define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
3416 #define CAN_F1R1_FB11_Pos      (11U)
3417 #define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
3418 #define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
3419 #define CAN_F1R1_FB12_Pos      (12U)
3420 #define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
3421 #define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
3422 #define CAN_F1R1_FB13_Pos      (13U)
3423 #define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
3424 #define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
3425 #define CAN_F1R1_FB14_Pos      (14U)
3426 #define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
3427 #define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
3428 #define CAN_F1R1_FB15_Pos      (15U)
3429 #define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
3430 #define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
3431 #define CAN_F1R1_FB16_Pos      (16U)
3432 #define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
3433 #define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
3434 #define CAN_F1R1_FB17_Pos      (17U)
3435 #define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
3436 #define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
3437 #define CAN_F1R1_FB18_Pos      (18U)
3438 #define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
3439 #define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
3440 #define CAN_F1R1_FB19_Pos      (19U)
3441 #define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
3442 #define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
3443 #define CAN_F1R1_FB20_Pos      (20U)
3444 #define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
3445 #define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
3446 #define CAN_F1R1_FB21_Pos      (21U)
3447 #define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
3448 #define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
3449 #define CAN_F1R1_FB22_Pos      (22U)
3450 #define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
3451 #define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
3452 #define CAN_F1R1_FB23_Pos      (23U)
3453 #define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
3454 #define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
3455 #define CAN_F1R1_FB24_Pos      (24U)
3456 #define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
3457 #define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
3458 #define CAN_F1R1_FB25_Pos      (25U)
3459 #define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
3460 #define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
3461 #define CAN_F1R1_FB26_Pos      (26U)
3462 #define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
3463 #define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
3464 #define CAN_F1R1_FB27_Pos      (27U)
3465 #define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
3466 #define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
3467 #define CAN_F1R1_FB28_Pos      (28U)
3468 #define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
3469 #define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
3470 #define CAN_F1R1_FB29_Pos      (29U)
3471 #define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
3472 #define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
3473 #define CAN_F1R1_FB30_Pos      (30U)
3474 #define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
3475 #define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
3476 #define CAN_F1R1_FB31_Pos      (31U)
3477 #define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
3478 #define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
3479 
3480 /*******************  Bit definition for CAN_F2R1 register  *******************/
3481 #define CAN_F2R1_FB0_Pos       (0U)
3482 #define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
3483 #define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
3484 #define CAN_F2R1_FB1_Pos       (1U)
3485 #define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
3486 #define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
3487 #define CAN_F2R1_FB2_Pos       (2U)
3488 #define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
3489 #define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
3490 #define CAN_F2R1_FB3_Pos       (3U)
3491 #define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
3492 #define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
3493 #define CAN_F2R1_FB4_Pos       (4U)
3494 #define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
3495 #define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
3496 #define CAN_F2R1_FB5_Pos       (5U)
3497 #define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
3498 #define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
3499 #define CAN_F2R1_FB6_Pos       (6U)
3500 #define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
3501 #define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
3502 #define CAN_F2R1_FB7_Pos       (7U)
3503 #define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
3504 #define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
3505 #define CAN_F2R1_FB8_Pos       (8U)
3506 #define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
3507 #define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
3508 #define CAN_F2R1_FB9_Pos       (9U)
3509 #define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
3510 #define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
3511 #define CAN_F2R1_FB10_Pos      (10U)
3512 #define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
3513 #define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
3514 #define CAN_F2R1_FB11_Pos      (11U)
3515 #define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
3516 #define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
3517 #define CAN_F2R1_FB12_Pos      (12U)
3518 #define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
3519 #define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
3520 #define CAN_F2R1_FB13_Pos      (13U)
3521 #define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
3522 #define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
3523 #define CAN_F2R1_FB14_Pos      (14U)
3524 #define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
3525 #define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
3526 #define CAN_F2R1_FB15_Pos      (15U)
3527 #define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
3528 #define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
3529 #define CAN_F2R1_FB16_Pos      (16U)
3530 #define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
3531 #define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
3532 #define CAN_F2R1_FB17_Pos      (17U)
3533 #define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
3534 #define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
3535 #define CAN_F2R1_FB18_Pos      (18U)
3536 #define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
3537 #define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
3538 #define CAN_F2R1_FB19_Pos      (19U)
3539 #define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
3540 #define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
3541 #define CAN_F2R1_FB20_Pos      (20U)
3542 #define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
3543 #define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
3544 #define CAN_F2R1_FB21_Pos      (21U)
3545 #define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
3546 #define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
3547 #define CAN_F2R1_FB22_Pos      (22U)
3548 #define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
3549 #define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
3550 #define CAN_F2R1_FB23_Pos      (23U)
3551 #define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
3552 #define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
3553 #define CAN_F2R1_FB24_Pos      (24U)
3554 #define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
3555 #define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
3556 #define CAN_F2R1_FB25_Pos      (25U)
3557 #define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
3558 #define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
3559 #define CAN_F2R1_FB26_Pos      (26U)
3560 #define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
3561 #define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
3562 #define CAN_F2R1_FB27_Pos      (27U)
3563 #define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
3564 #define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
3565 #define CAN_F2R1_FB28_Pos      (28U)
3566 #define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
3567 #define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
3568 #define CAN_F2R1_FB29_Pos      (29U)
3569 #define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
3570 #define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
3571 #define CAN_F2R1_FB30_Pos      (30U)
3572 #define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
3573 #define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
3574 #define CAN_F2R1_FB31_Pos      (31U)
3575 #define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
3576 #define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
3577 
3578 /*******************  Bit definition for CAN_F3R1 register  *******************/
3579 #define CAN_F3R1_FB0_Pos       (0U)
3580 #define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
3581 #define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
3582 #define CAN_F3R1_FB1_Pos       (1U)
3583 #define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
3584 #define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
3585 #define CAN_F3R1_FB2_Pos       (2U)
3586 #define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
3587 #define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
3588 #define CAN_F3R1_FB3_Pos       (3U)
3589 #define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
3590 #define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
3591 #define CAN_F3R1_FB4_Pos       (4U)
3592 #define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
3593 #define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
3594 #define CAN_F3R1_FB5_Pos       (5U)
3595 #define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
3596 #define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
3597 #define CAN_F3R1_FB6_Pos       (6U)
3598 #define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
3599 #define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
3600 #define CAN_F3R1_FB7_Pos       (7U)
3601 #define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
3602 #define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
3603 #define CAN_F3R1_FB8_Pos       (8U)
3604 #define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
3605 #define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
3606 #define CAN_F3R1_FB9_Pos       (9U)
3607 #define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
3608 #define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
3609 #define CAN_F3R1_FB10_Pos      (10U)
3610 #define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
3611 #define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
3612 #define CAN_F3R1_FB11_Pos      (11U)
3613 #define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
3614 #define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
3615 #define CAN_F3R1_FB12_Pos      (12U)
3616 #define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
3617 #define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
3618 #define CAN_F3R1_FB13_Pos      (13U)
3619 #define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
3620 #define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
3621 #define CAN_F3R1_FB14_Pos      (14U)
3622 #define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
3623 #define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
3624 #define CAN_F3R1_FB15_Pos      (15U)
3625 #define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
3626 #define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
3627 #define CAN_F3R1_FB16_Pos      (16U)
3628 #define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
3629 #define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
3630 #define CAN_F3R1_FB17_Pos      (17U)
3631 #define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
3632 #define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
3633 #define CAN_F3R1_FB18_Pos      (18U)
3634 #define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
3635 #define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
3636 #define CAN_F3R1_FB19_Pos      (19U)
3637 #define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
3638 #define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
3639 #define CAN_F3R1_FB20_Pos      (20U)
3640 #define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
3641 #define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
3642 #define CAN_F3R1_FB21_Pos      (21U)
3643 #define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
3644 #define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
3645 #define CAN_F3R1_FB22_Pos      (22U)
3646 #define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
3647 #define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
3648 #define CAN_F3R1_FB23_Pos      (23U)
3649 #define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
3650 #define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
3651 #define CAN_F3R1_FB24_Pos      (24U)
3652 #define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
3653 #define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
3654 #define CAN_F3R1_FB25_Pos      (25U)
3655 #define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
3656 #define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
3657 #define CAN_F3R1_FB26_Pos      (26U)
3658 #define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
3659 #define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
3660 #define CAN_F3R1_FB27_Pos      (27U)
3661 #define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
3662 #define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
3663 #define CAN_F3R1_FB28_Pos      (28U)
3664 #define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
3665 #define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
3666 #define CAN_F3R1_FB29_Pos      (29U)
3667 #define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
3668 #define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
3669 #define CAN_F3R1_FB30_Pos      (30U)
3670 #define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
3671 #define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
3672 #define CAN_F3R1_FB31_Pos      (31U)
3673 #define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
3674 #define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
3675 
3676 /*******************  Bit definition for CAN_F4R1 register  *******************/
3677 #define CAN_F4R1_FB0_Pos       (0U)
3678 #define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
3679 #define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
3680 #define CAN_F4R1_FB1_Pos       (1U)
3681 #define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
3682 #define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
3683 #define CAN_F4R1_FB2_Pos       (2U)
3684 #define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
3685 #define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
3686 #define CAN_F4R1_FB3_Pos       (3U)
3687 #define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
3688 #define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
3689 #define CAN_F4R1_FB4_Pos       (4U)
3690 #define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
3691 #define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
3692 #define CAN_F4R1_FB5_Pos       (5U)
3693 #define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
3694 #define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
3695 #define CAN_F4R1_FB6_Pos       (6U)
3696 #define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
3697 #define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
3698 #define CAN_F4R1_FB7_Pos       (7U)
3699 #define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
3700 #define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
3701 #define CAN_F4R1_FB8_Pos       (8U)
3702 #define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
3703 #define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
3704 #define CAN_F4R1_FB9_Pos       (9U)
3705 #define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
3706 #define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
3707 #define CAN_F4R1_FB10_Pos      (10U)
3708 #define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
3709 #define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
3710 #define CAN_F4R1_FB11_Pos      (11U)
3711 #define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
3712 #define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
3713 #define CAN_F4R1_FB12_Pos      (12U)
3714 #define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
3715 #define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
3716 #define CAN_F4R1_FB13_Pos      (13U)
3717 #define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
3718 #define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
3719 #define CAN_F4R1_FB14_Pos      (14U)
3720 #define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
3721 #define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
3722 #define CAN_F4R1_FB15_Pos      (15U)
3723 #define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
3724 #define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
3725 #define CAN_F4R1_FB16_Pos      (16U)
3726 #define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
3727 #define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
3728 #define CAN_F4R1_FB17_Pos      (17U)
3729 #define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
3730 #define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
3731 #define CAN_F4R1_FB18_Pos      (18U)
3732 #define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
3733 #define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
3734 #define CAN_F4R1_FB19_Pos      (19U)
3735 #define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
3736 #define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
3737 #define CAN_F4R1_FB20_Pos      (20U)
3738 #define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
3739 #define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
3740 #define CAN_F4R1_FB21_Pos      (21U)
3741 #define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
3742 #define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
3743 #define CAN_F4R1_FB22_Pos      (22U)
3744 #define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
3745 #define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
3746 #define CAN_F4R1_FB23_Pos      (23U)
3747 #define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
3748 #define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
3749 #define CAN_F4R1_FB24_Pos      (24U)
3750 #define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
3751 #define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
3752 #define CAN_F4R1_FB25_Pos      (25U)
3753 #define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
3754 #define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
3755 #define CAN_F4R1_FB26_Pos      (26U)
3756 #define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
3757 #define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
3758 #define CAN_F4R1_FB27_Pos      (27U)
3759 #define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
3760 #define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
3761 #define CAN_F4R1_FB28_Pos      (28U)
3762 #define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
3763 #define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
3764 #define CAN_F4R1_FB29_Pos      (29U)
3765 #define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
3766 #define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
3767 #define CAN_F4R1_FB30_Pos      (30U)
3768 #define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
3769 #define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
3770 #define CAN_F4R1_FB31_Pos      (31U)
3771 #define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
3772 #define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
3773 
3774 /*******************  Bit definition for CAN_F5R1 register  *******************/
3775 #define CAN_F5R1_FB0_Pos       (0U)
3776 #define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
3777 #define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
3778 #define CAN_F5R1_FB1_Pos       (1U)
3779 #define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
3780 #define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
3781 #define CAN_F5R1_FB2_Pos       (2U)
3782 #define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
3783 #define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
3784 #define CAN_F5R1_FB3_Pos       (3U)
3785 #define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
3786 #define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
3787 #define CAN_F5R1_FB4_Pos       (4U)
3788 #define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
3789 #define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
3790 #define CAN_F5R1_FB5_Pos       (5U)
3791 #define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
3792 #define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
3793 #define CAN_F5R1_FB6_Pos       (6U)
3794 #define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
3795 #define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
3796 #define CAN_F5R1_FB7_Pos       (7U)
3797 #define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
3798 #define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
3799 #define CAN_F5R1_FB8_Pos       (8U)
3800 #define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
3801 #define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
3802 #define CAN_F5R1_FB9_Pos       (9U)
3803 #define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
3804 #define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
3805 #define CAN_F5R1_FB10_Pos      (10U)
3806 #define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
3807 #define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
3808 #define CAN_F5R1_FB11_Pos      (11U)
3809 #define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
3810 #define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
3811 #define CAN_F5R1_FB12_Pos      (12U)
3812 #define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
3813 #define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
3814 #define CAN_F5R1_FB13_Pos      (13U)
3815 #define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
3816 #define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
3817 #define CAN_F5R1_FB14_Pos      (14U)
3818 #define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
3819 #define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
3820 #define CAN_F5R1_FB15_Pos      (15U)
3821 #define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
3822 #define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
3823 #define CAN_F5R1_FB16_Pos      (16U)
3824 #define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
3825 #define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
3826 #define CAN_F5R1_FB17_Pos      (17U)
3827 #define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
3828 #define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
3829 #define CAN_F5R1_FB18_Pos      (18U)
3830 #define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
3831 #define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
3832 #define CAN_F5R1_FB19_Pos      (19U)
3833 #define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
3834 #define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
3835 #define CAN_F5R1_FB20_Pos      (20U)
3836 #define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
3837 #define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
3838 #define CAN_F5R1_FB21_Pos      (21U)
3839 #define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
3840 #define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
3841 #define CAN_F5R1_FB22_Pos      (22U)
3842 #define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
3843 #define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
3844 #define CAN_F5R1_FB23_Pos      (23U)
3845 #define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
3846 #define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
3847 #define CAN_F5R1_FB24_Pos      (24U)
3848 #define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
3849 #define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
3850 #define CAN_F5R1_FB25_Pos      (25U)
3851 #define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
3852 #define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
3853 #define CAN_F5R1_FB26_Pos      (26U)
3854 #define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
3855 #define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
3856 #define CAN_F5R1_FB27_Pos      (27U)
3857 #define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
3858 #define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
3859 #define CAN_F5R1_FB28_Pos      (28U)
3860 #define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
3861 #define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
3862 #define CAN_F5R1_FB29_Pos      (29U)
3863 #define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
3864 #define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
3865 #define CAN_F5R1_FB30_Pos      (30U)
3866 #define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
3867 #define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
3868 #define CAN_F5R1_FB31_Pos      (31U)
3869 #define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
3870 #define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
3871 
3872 /*******************  Bit definition for CAN_F6R1 register  *******************/
3873 #define CAN_F6R1_FB0_Pos       (0U)
3874 #define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
3875 #define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
3876 #define CAN_F6R1_FB1_Pos       (1U)
3877 #define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
3878 #define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
3879 #define CAN_F6R1_FB2_Pos       (2U)
3880 #define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
3881 #define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
3882 #define CAN_F6R1_FB3_Pos       (3U)
3883 #define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
3884 #define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
3885 #define CAN_F6R1_FB4_Pos       (4U)
3886 #define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
3887 #define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
3888 #define CAN_F6R1_FB5_Pos       (5U)
3889 #define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
3890 #define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
3891 #define CAN_F6R1_FB6_Pos       (6U)
3892 #define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
3893 #define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
3894 #define CAN_F6R1_FB7_Pos       (7U)
3895 #define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
3896 #define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
3897 #define CAN_F6R1_FB8_Pos       (8U)
3898 #define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
3899 #define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
3900 #define CAN_F6R1_FB9_Pos       (9U)
3901 #define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
3902 #define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
3903 #define CAN_F6R1_FB10_Pos      (10U)
3904 #define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
3905 #define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
3906 #define CAN_F6R1_FB11_Pos      (11U)
3907 #define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
3908 #define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
3909 #define CAN_F6R1_FB12_Pos      (12U)
3910 #define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
3911 #define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
3912 #define CAN_F6R1_FB13_Pos      (13U)
3913 #define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
3914 #define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
3915 #define CAN_F6R1_FB14_Pos      (14U)
3916 #define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
3917 #define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
3918 #define CAN_F6R1_FB15_Pos      (15U)
3919 #define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
3920 #define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
3921 #define CAN_F6R1_FB16_Pos      (16U)
3922 #define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
3923 #define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
3924 #define CAN_F6R1_FB17_Pos      (17U)
3925 #define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
3926 #define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
3927 #define CAN_F6R1_FB18_Pos      (18U)
3928 #define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
3929 #define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
3930 #define CAN_F6R1_FB19_Pos      (19U)
3931 #define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
3932 #define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
3933 #define CAN_F6R1_FB20_Pos      (20U)
3934 #define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
3935 #define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
3936 #define CAN_F6R1_FB21_Pos      (21U)
3937 #define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
3938 #define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
3939 #define CAN_F6R1_FB22_Pos      (22U)
3940 #define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
3941 #define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
3942 #define CAN_F6R1_FB23_Pos      (23U)
3943 #define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
3944 #define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
3945 #define CAN_F6R1_FB24_Pos      (24U)
3946 #define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
3947 #define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
3948 #define CAN_F6R1_FB25_Pos      (25U)
3949 #define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
3950 #define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
3951 #define CAN_F6R1_FB26_Pos      (26U)
3952 #define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
3953 #define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
3954 #define CAN_F6R1_FB27_Pos      (27U)
3955 #define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
3956 #define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
3957 #define CAN_F6R1_FB28_Pos      (28U)
3958 #define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
3959 #define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
3960 #define CAN_F6R1_FB29_Pos      (29U)
3961 #define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
3962 #define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
3963 #define CAN_F6R1_FB30_Pos      (30U)
3964 #define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
3965 #define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
3966 #define CAN_F6R1_FB31_Pos      (31U)
3967 #define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
3968 #define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
3969 
3970 /*******************  Bit definition for CAN_F7R1 register  *******************/
3971 #define CAN_F7R1_FB0_Pos       (0U)
3972 #define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
3973 #define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
3974 #define CAN_F7R1_FB1_Pos       (1U)
3975 #define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
3976 #define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
3977 #define CAN_F7R1_FB2_Pos       (2U)
3978 #define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
3979 #define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
3980 #define CAN_F7R1_FB3_Pos       (3U)
3981 #define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
3982 #define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
3983 #define CAN_F7R1_FB4_Pos       (4U)
3984 #define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
3985 #define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
3986 #define CAN_F7R1_FB5_Pos       (5U)
3987 #define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
3988 #define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
3989 #define CAN_F7R1_FB6_Pos       (6U)
3990 #define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
3991 #define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
3992 #define CAN_F7R1_FB7_Pos       (7U)
3993 #define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
3994 #define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
3995 #define CAN_F7R1_FB8_Pos       (8U)
3996 #define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
3997 #define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
3998 #define CAN_F7R1_FB9_Pos       (9U)
3999 #define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
4000 #define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
4001 #define CAN_F7R1_FB10_Pos      (10U)
4002 #define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
4003 #define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
4004 #define CAN_F7R1_FB11_Pos      (11U)
4005 #define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
4006 #define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
4007 #define CAN_F7R1_FB12_Pos      (12U)
4008 #define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
4009 #define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
4010 #define CAN_F7R1_FB13_Pos      (13U)
4011 #define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
4012 #define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
4013 #define CAN_F7R1_FB14_Pos      (14U)
4014 #define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
4015 #define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
4016 #define CAN_F7R1_FB15_Pos      (15U)
4017 #define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
4018 #define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
4019 #define CAN_F7R1_FB16_Pos      (16U)
4020 #define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
4021 #define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
4022 #define CAN_F7R1_FB17_Pos      (17U)
4023 #define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
4024 #define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
4025 #define CAN_F7R1_FB18_Pos      (18U)
4026 #define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
4027 #define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
4028 #define CAN_F7R1_FB19_Pos      (19U)
4029 #define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
4030 #define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
4031 #define CAN_F7R1_FB20_Pos      (20U)
4032 #define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
4033 #define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
4034 #define CAN_F7R1_FB21_Pos      (21U)
4035 #define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
4036 #define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
4037 #define CAN_F7R1_FB22_Pos      (22U)
4038 #define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
4039 #define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
4040 #define CAN_F7R1_FB23_Pos      (23U)
4041 #define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
4042 #define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
4043 #define CAN_F7R1_FB24_Pos      (24U)
4044 #define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
4045 #define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
4046 #define CAN_F7R1_FB25_Pos      (25U)
4047 #define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
4048 #define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
4049 #define CAN_F7R1_FB26_Pos      (26U)
4050 #define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
4051 #define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
4052 #define CAN_F7R1_FB27_Pos      (27U)
4053 #define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
4054 #define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
4055 #define CAN_F7R1_FB28_Pos      (28U)
4056 #define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
4057 #define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
4058 #define CAN_F7R1_FB29_Pos      (29U)
4059 #define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
4060 #define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
4061 #define CAN_F7R1_FB30_Pos      (30U)
4062 #define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
4063 #define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
4064 #define CAN_F7R1_FB31_Pos      (31U)
4065 #define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
4066 #define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
4067 
4068 /*******************  Bit definition for CAN_F8R1 register  *******************/
4069 #define CAN_F8R1_FB0_Pos       (0U)
4070 #define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
4071 #define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
4072 #define CAN_F8R1_FB1_Pos       (1U)
4073 #define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
4074 #define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
4075 #define CAN_F8R1_FB2_Pos       (2U)
4076 #define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
4077 #define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
4078 #define CAN_F8R1_FB3_Pos       (3U)
4079 #define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
4080 #define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
4081 #define CAN_F8R1_FB4_Pos       (4U)
4082 #define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
4083 #define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
4084 #define CAN_F8R1_FB5_Pos       (5U)
4085 #define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
4086 #define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
4087 #define CAN_F8R1_FB6_Pos       (6U)
4088 #define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
4089 #define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
4090 #define CAN_F8R1_FB7_Pos       (7U)
4091 #define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
4092 #define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
4093 #define CAN_F8R1_FB8_Pos       (8U)
4094 #define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
4095 #define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
4096 #define CAN_F8R1_FB9_Pos       (9U)
4097 #define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
4098 #define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
4099 #define CAN_F8R1_FB10_Pos      (10U)
4100 #define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
4101 #define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
4102 #define CAN_F8R1_FB11_Pos      (11U)
4103 #define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
4104 #define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
4105 #define CAN_F8R1_FB12_Pos      (12U)
4106 #define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
4107 #define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
4108 #define CAN_F8R1_FB13_Pos      (13U)
4109 #define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
4110 #define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
4111 #define CAN_F8R1_FB14_Pos      (14U)
4112 #define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
4113 #define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
4114 #define CAN_F8R1_FB15_Pos      (15U)
4115 #define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
4116 #define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
4117 #define CAN_F8R1_FB16_Pos      (16U)
4118 #define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
4119 #define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
4120 #define CAN_F8R1_FB17_Pos      (17U)
4121 #define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
4122 #define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
4123 #define CAN_F8R1_FB18_Pos      (18U)
4124 #define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
4125 #define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
4126 #define CAN_F8R1_FB19_Pos      (19U)
4127 #define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
4128 #define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
4129 #define CAN_F8R1_FB20_Pos      (20U)
4130 #define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
4131 #define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
4132 #define CAN_F8R1_FB21_Pos      (21U)
4133 #define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
4134 #define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
4135 #define CAN_F8R1_FB22_Pos      (22U)
4136 #define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
4137 #define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
4138 #define CAN_F8R1_FB23_Pos      (23U)
4139 #define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
4140 #define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
4141 #define CAN_F8R1_FB24_Pos      (24U)
4142 #define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
4143 #define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
4144 #define CAN_F8R1_FB25_Pos      (25U)
4145 #define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
4146 #define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
4147 #define CAN_F8R1_FB26_Pos      (26U)
4148 #define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
4149 #define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
4150 #define CAN_F8R1_FB27_Pos      (27U)
4151 #define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
4152 #define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
4153 #define CAN_F8R1_FB28_Pos      (28U)
4154 #define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
4155 #define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
4156 #define CAN_F8R1_FB29_Pos      (29U)
4157 #define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
4158 #define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
4159 #define CAN_F8R1_FB30_Pos      (30U)
4160 #define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
4161 #define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
4162 #define CAN_F8R1_FB31_Pos      (31U)
4163 #define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
4164 #define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
4165 
4166 /*******************  Bit definition for CAN_F9R1 register  *******************/
4167 #define CAN_F9R1_FB0_Pos       (0U)
4168 #define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
4169 #define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
4170 #define CAN_F9R1_FB1_Pos       (1U)
4171 #define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
4172 #define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
4173 #define CAN_F9R1_FB2_Pos       (2U)
4174 #define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
4175 #define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
4176 #define CAN_F9R1_FB3_Pos       (3U)
4177 #define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
4178 #define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
4179 #define CAN_F9R1_FB4_Pos       (4U)
4180 #define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
4181 #define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
4182 #define CAN_F9R1_FB5_Pos       (5U)
4183 #define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
4184 #define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
4185 #define CAN_F9R1_FB6_Pos       (6U)
4186 #define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
4187 #define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
4188 #define CAN_F9R1_FB7_Pos       (7U)
4189 #define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
4190 #define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
4191 #define CAN_F9R1_FB8_Pos       (8U)
4192 #define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
4193 #define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
4194 #define CAN_F9R1_FB9_Pos       (9U)
4195 #define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
4196 #define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
4197 #define CAN_F9R1_FB10_Pos      (10U)
4198 #define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
4199 #define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
4200 #define CAN_F9R1_FB11_Pos      (11U)
4201 #define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
4202 #define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
4203 #define CAN_F9R1_FB12_Pos      (12U)
4204 #define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
4205 #define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
4206 #define CAN_F9R1_FB13_Pos      (13U)
4207 #define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
4208 #define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
4209 #define CAN_F9R1_FB14_Pos      (14U)
4210 #define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
4211 #define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
4212 #define CAN_F9R1_FB15_Pos      (15U)
4213 #define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
4214 #define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
4215 #define CAN_F9R1_FB16_Pos      (16U)
4216 #define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
4217 #define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
4218 #define CAN_F9R1_FB17_Pos      (17U)
4219 #define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
4220 #define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
4221 #define CAN_F9R1_FB18_Pos      (18U)
4222 #define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
4223 #define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
4224 #define CAN_F9R1_FB19_Pos      (19U)
4225 #define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
4226 #define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
4227 #define CAN_F9R1_FB20_Pos      (20U)
4228 #define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
4229 #define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
4230 #define CAN_F9R1_FB21_Pos      (21U)
4231 #define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
4232 #define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
4233 #define CAN_F9R1_FB22_Pos      (22U)
4234 #define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
4235 #define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
4236 #define CAN_F9R1_FB23_Pos      (23U)
4237 #define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
4238 #define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
4239 #define CAN_F9R1_FB24_Pos      (24U)
4240 #define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
4241 #define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
4242 #define CAN_F9R1_FB25_Pos      (25U)
4243 #define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
4244 #define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
4245 #define CAN_F9R1_FB26_Pos      (26U)
4246 #define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
4247 #define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
4248 #define CAN_F9R1_FB27_Pos      (27U)
4249 #define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
4250 #define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
4251 #define CAN_F9R1_FB28_Pos      (28U)
4252 #define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
4253 #define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
4254 #define CAN_F9R1_FB29_Pos      (29U)
4255 #define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
4256 #define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
4257 #define CAN_F9R1_FB30_Pos      (30U)
4258 #define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
4259 #define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
4260 #define CAN_F9R1_FB31_Pos      (31U)
4261 #define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
4262 #define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
4263 
4264 /*******************  Bit definition for CAN_F10R1 register  ******************/
4265 #define CAN_F10R1_FB0_Pos      (0U)
4266 #define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
4267 #define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
4268 #define CAN_F10R1_FB1_Pos      (1U)
4269 #define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
4270 #define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
4271 #define CAN_F10R1_FB2_Pos      (2U)
4272 #define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
4273 #define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
4274 #define CAN_F10R1_FB3_Pos      (3U)
4275 #define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
4276 #define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
4277 #define CAN_F10R1_FB4_Pos      (4U)
4278 #define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
4279 #define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
4280 #define CAN_F10R1_FB5_Pos      (5U)
4281 #define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
4282 #define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
4283 #define CAN_F10R1_FB6_Pos      (6U)
4284 #define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
4285 #define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
4286 #define CAN_F10R1_FB7_Pos      (7U)
4287 #define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
4288 #define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
4289 #define CAN_F10R1_FB8_Pos      (8U)
4290 #define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
4291 #define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
4292 #define CAN_F10R1_FB9_Pos      (9U)
4293 #define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
4294 #define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
4295 #define CAN_F10R1_FB10_Pos     (10U)
4296 #define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
4297 #define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
4298 #define CAN_F10R1_FB11_Pos     (11U)
4299 #define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
4300 #define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
4301 #define CAN_F10R1_FB12_Pos     (12U)
4302 #define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
4303 #define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
4304 #define CAN_F10R1_FB13_Pos     (13U)
4305 #define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
4306 #define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
4307 #define CAN_F10R1_FB14_Pos     (14U)
4308 #define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
4309 #define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
4310 #define CAN_F10R1_FB15_Pos     (15U)
4311 #define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
4312 #define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
4313 #define CAN_F10R1_FB16_Pos     (16U)
4314 #define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
4315 #define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
4316 #define CAN_F10R1_FB17_Pos     (17U)
4317 #define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
4318 #define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
4319 #define CAN_F10R1_FB18_Pos     (18U)
4320 #define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
4321 #define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
4322 #define CAN_F10R1_FB19_Pos     (19U)
4323 #define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
4324 #define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
4325 #define CAN_F10R1_FB20_Pos     (20U)
4326 #define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
4327 #define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
4328 #define CAN_F10R1_FB21_Pos     (21U)
4329 #define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
4330 #define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
4331 #define CAN_F10R1_FB22_Pos     (22U)
4332 #define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
4333 #define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
4334 #define CAN_F10R1_FB23_Pos     (23U)
4335 #define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
4336 #define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
4337 #define CAN_F10R1_FB24_Pos     (24U)
4338 #define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
4339 #define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
4340 #define CAN_F10R1_FB25_Pos     (25U)
4341 #define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
4342 #define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
4343 #define CAN_F10R1_FB26_Pos     (26U)
4344 #define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
4345 #define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
4346 #define CAN_F10R1_FB27_Pos     (27U)
4347 #define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
4348 #define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
4349 #define CAN_F10R1_FB28_Pos     (28U)
4350 #define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
4351 #define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
4352 #define CAN_F10R1_FB29_Pos     (29U)
4353 #define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
4354 #define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
4355 #define CAN_F10R1_FB30_Pos     (30U)
4356 #define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
4357 #define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
4358 #define CAN_F10R1_FB31_Pos     (31U)
4359 #define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
4360 #define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
4361 
4362 /*******************  Bit definition for CAN_F11R1 register  ******************/
4363 #define CAN_F11R1_FB0_Pos      (0U)
4364 #define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
4365 #define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
4366 #define CAN_F11R1_FB1_Pos      (1U)
4367 #define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
4368 #define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
4369 #define CAN_F11R1_FB2_Pos      (2U)
4370 #define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
4371 #define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
4372 #define CAN_F11R1_FB3_Pos      (3U)
4373 #define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
4374 #define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
4375 #define CAN_F11R1_FB4_Pos      (4U)
4376 #define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
4377 #define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
4378 #define CAN_F11R1_FB5_Pos      (5U)
4379 #define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
4380 #define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
4381 #define CAN_F11R1_FB6_Pos      (6U)
4382 #define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
4383 #define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
4384 #define CAN_F11R1_FB7_Pos      (7U)
4385 #define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
4386 #define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
4387 #define CAN_F11R1_FB8_Pos      (8U)
4388 #define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
4389 #define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
4390 #define CAN_F11R1_FB9_Pos      (9U)
4391 #define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
4392 #define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
4393 #define CAN_F11R1_FB10_Pos     (10U)
4394 #define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
4395 #define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
4396 #define CAN_F11R1_FB11_Pos     (11U)
4397 #define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
4398 #define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
4399 #define CAN_F11R1_FB12_Pos     (12U)
4400 #define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
4401 #define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
4402 #define CAN_F11R1_FB13_Pos     (13U)
4403 #define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
4404 #define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
4405 #define CAN_F11R1_FB14_Pos     (14U)
4406 #define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
4407 #define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
4408 #define CAN_F11R1_FB15_Pos     (15U)
4409 #define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
4410 #define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
4411 #define CAN_F11R1_FB16_Pos     (16U)
4412 #define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
4413 #define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
4414 #define CAN_F11R1_FB17_Pos     (17U)
4415 #define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
4416 #define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
4417 #define CAN_F11R1_FB18_Pos     (18U)
4418 #define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
4419 #define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
4420 #define CAN_F11R1_FB19_Pos     (19U)
4421 #define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
4422 #define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
4423 #define CAN_F11R1_FB20_Pos     (20U)
4424 #define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
4425 #define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
4426 #define CAN_F11R1_FB21_Pos     (21U)
4427 #define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
4428 #define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
4429 #define CAN_F11R1_FB22_Pos     (22U)
4430 #define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
4431 #define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
4432 #define CAN_F11R1_FB23_Pos     (23U)
4433 #define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
4434 #define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
4435 #define CAN_F11R1_FB24_Pos     (24U)
4436 #define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
4437 #define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
4438 #define CAN_F11R1_FB25_Pos     (25U)
4439 #define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
4440 #define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
4441 #define CAN_F11R1_FB26_Pos     (26U)
4442 #define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
4443 #define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
4444 #define CAN_F11R1_FB27_Pos     (27U)
4445 #define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
4446 #define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
4447 #define CAN_F11R1_FB28_Pos     (28U)
4448 #define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
4449 #define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
4450 #define CAN_F11R1_FB29_Pos     (29U)
4451 #define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
4452 #define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
4453 #define CAN_F11R1_FB30_Pos     (30U)
4454 #define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
4455 #define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
4456 #define CAN_F11R1_FB31_Pos     (31U)
4457 #define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
4458 #define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
4459 
4460 /*******************  Bit definition for CAN_F12R1 register  ******************/
4461 #define CAN_F12R1_FB0_Pos      (0U)
4462 #define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
4463 #define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
4464 #define CAN_F12R1_FB1_Pos      (1U)
4465 #define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
4466 #define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
4467 #define CAN_F12R1_FB2_Pos      (2U)
4468 #define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
4469 #define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
4470 #define CAN_F12R1_FB3_Pos      (3U)
4471 #define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
4472 #define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
4473 #define CAN_F12R1_FB4_Pos      (4U)
4474 #define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
4475 #define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
4476 #define CAN_F12R1_FB5_Pos      (5U)
4477 #define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
4478 #define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
4479 #define CAN_F12R1_FB6_Pos      (6U)
4480 #define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
4481 #define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
4482 #define CAN_F12R1_FB7_Pos      (7U)
4483 #define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
4484 #define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
4485 #define CAN_F12R1_FB8_Pos      (8U)
4486 #define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
4487 #define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
4488 #define CAN_F12R1_FB9_Pos      (9U)
4489 #define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
4490 #define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
4491 #define CAN_F12R1_FB10_Pos     (10U)
4492 #define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
4493 #define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
4494 #define CAN_F12R1_FB11_Pos     (11U)
4495 #define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
4496 #define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
4497 #define CAN_F12R1_FB12_Pos     (12U)
4498 #define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
4499 #define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
4500 #define CAN_F12R1_FB13_Pos     (13U)
4501 #define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
4502 #define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
4503 #define CAN_F12R1_FB14_Pos     (14U)
4504 #define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
4505 #define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
4506 #define CAN_F12R1_FB15_Pos     (15U)
4507 #define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
4508 #define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
4509 #define CAN_F12R1_FB16_Pos     (16U)
4510 #define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
4511 #define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
4512 #define CAN_F12R1_FB17_Pos     (17U)
4513 #define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
4514 #define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
4515 #define CAN_F12R1_FB18_Pos     (18U)
4516 #define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
4517 #define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
4518 #define CAN_F12R1_FB19_Pos     (19U)
4519 #define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
4520 #define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
4521 #define CAN_F12R1_FB20_Pos     (20U)
4522 #define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
4523 #define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
4524 #define CAN_F12R1_FB21_Pos     (21U)
4525 #define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
4526 #define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
4527 #define CAN_F12R1_FB22_Pos     (22U)
4528 #define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
4529 #define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
4530 #define CAN_F12R1_FB23_Pos     (23U)
4531 #define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
4532 #define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
4533 #define CAN_F12R1_FB24_Pos     (24U)
4534 #define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
4535 #define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
4536 #define CAN_F12R1_FB25_Pos     (25U)
4537 #define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
4538 #define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
4539 #define CAN_F12R1_FB26_Pos     (26U)
4540 #define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
4541 #define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
4542 #define CAN_F12R1_FB27_Pos     (27U)
4543 #define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
4544 #define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
4545 #define CAN_F12R1_FB28_Pos     (28U)
4546 #define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
4547 #define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
4548 #define CAN_F12R1_FB29_Pos     (29U)
4549 #define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
4550 #define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
4551 #define CAN_F12R1_FB30_Pos     (30U)
4552 #define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
4553 #define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
4554 #define CAN_F12R1_FB31_Pos     (31U)
4555 #define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
4556 #define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
4557 
4558 /*******************  Bit definition for CAN_F13R1 register  ******************/
4559 #define CAN_F13R1_FB0_Pos      (0U)
4560 #define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
4561 #define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
4562 #define CAN_F13R1_FB1_Pos      (1U)
4563 #define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
4564 #define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
4565 #define CAN_F13R1_FB2_Pos      (2U)
4566 #define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
4567 #define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
4568 #define CAN_F13R1_FB3_Pos      (3U)
4569 #define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
4570 #define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
4571 #define CAN_F13R1_FB4_Pos      (4U)
4572 #define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
4573 #define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
4574 #define CAN_F13R1_FB5_Pos      (5U)
4575 #define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
4576 #define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
4577 #define CAN_F13R1_FB6_Pos      (6U)
4578 #define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
4579 #define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
4580 #define CAN_F13R1_FB7_Pos      (7U)
4581 #define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
4582 #define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
4583 #define CAN_F13R1_FB8_Pos      (8U)
4584 #define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
4585 #define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
4586 #define CAN_F13R1_FB9_Pos      (9U)
4587 #define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
4588 #define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
4589 #define CAN_F13R1_FB10_Pos     (10U)
4590 #define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
4591 #define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
4592 #define CAN_F13R1_FB11_Pos     (11U)
4593 #define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
4594 #define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
4595 #define CAN_F13R1_FB12_Pos     (12U)
4596 #define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
4597 #define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
4598 #define CAN_F13R1_FB13_Pos     (13U)
4599 #define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
4600 #define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
4601 #define CAN_F13R1_FB14_Pos     (14U)
4602 #define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
4603 #define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
4604 #define CAN_F13R1_FB15_Pos     (15U)
4605 #define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
4606 #define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
4607 #define CAN_F13R1_FB16_Pos     (16U)
4608 #define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
4609 #define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
4610 #define CAN_F13R1_FB17_Pos     (17U)
4611 #define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
4612 #define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
4613 #define CAN_F13R1_FB18_Pos     (18U)
4614 #define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
4615 #define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
4616 #define CAN_F13R1_FB19_Pos     (19U)
4617 #define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
4618 #define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
4619 #define CAN_F13R1_FB20_Pos     (20U)
4620 #define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
4621 #define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
4622 #define CAN_F13R1_FB21_Pos     (21U)
4623 #define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
4624 #define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
4625 #define CAN_F13R1_FB22_Pos     (22U)
4626 #define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
4627 #define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
4628 #define CAN_F13R1_FB23_Pos     (23U)
4629 #define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
4630 #define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
4631 #define CAN_F13R1_FB24_Pos     (24U)
4632 #define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
4633 #define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
4634 #define CAN_F13R1_FB25_Pos     (25U)
4635 #define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
4636 #define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
4637 #define CAN_F13R1_FB26_Pos     (26U)
4638 #define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
4639 #define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
4640 #define CAN_F13R1_FB27_Pos     (27U)
4641 #define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
4642 #define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
4643 #define CAN_F13R1_FB28_Pos     (28U)
4644 #define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
4645 #define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
4646 #define CAN_F13R1_FB29_Pos     (29U)
4647 #define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
4648 #define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
4649 #define CAN_F13R1_FB30_Pos     (30U)
4650 #define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
4651 #define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
4652 #define CAN_F13R1_FB31_Pos     (31U)
4653 #define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
4654 #define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
4655 
4656 /*******************  Bit definition for CAN_F0R2 register  *******************/
4657 #define CAN_F0R2_FB0_Pos       (0U)
4658 #define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
4659 #define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
4660 #define CAN_F0R2_FB1_Pos       (1U)
4661 #define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
4662 #define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
4663 #define CAN_F0R2_FB2_Pos       (2U)
4664 #define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
4665 #define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
4666 #define CAN_F0R2_FB3_Pos       (3U)
4667 #define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
4668 #define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
4669 #define CAN_F0R2_FB4_Pos       (4U)
4670 #define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
4671 #define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
4672 #define CAN_F0R2_FB5_Pos       (5U)
4673 #define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
4674 #define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
4675 #define CAN_F0R2_FB6_Pos       (6U)
4676 #define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
4677 #define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
4678 #define CAN_F0R2_FB7_Pos       (7U)
4679 #define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
4680 #define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
4681 #define CAN_F0R2_FB8_Pos       (8U)
4682 #define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
4683 #define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
4684 #define CAN_F0R2_FB9_Pos       (9U)
4685 #define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
4686 #define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
4687 #define CAN_F0R2_FB10_Pos      (10U)
4688 #define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
4689 #define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
4690 #define CAN_F0R2_FB11_Pos      (11U)
4691 #define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
4692 #define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
4693 #define CAN_F0R2_FB12_Pos      (12U)
4694 #define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
4695 #define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
4696 #define CAN_F0R2_FB13_Pos      (13U)
4697 #define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
4698 #define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
4699 #define CAN_F0R2_FB14_Pos      (14U)
4700 #define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
4701 #define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
4702 #define CAN_F0R2_FB15_Pos      (15U)
4703 #define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
4704 #define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
4705 #define CAN_F0R2_FB16_Pos      (16U)
4706 #define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
4707 #define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
4708 #define CAN_F0R2_FB17_Pos      (17U)
4709 #define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
4710 #define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
4711 #define CAN_F0R2_FB18_Pos      (18U)
4712 #define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
4713 #define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
4714 #define CAN_F0R2_FB19_Pos      (19U)
4715 #define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
4716 #define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
4717 #define CAN_F0R2_FB20_Pos      (20U)
4718 #define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
4719 #define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
4720 #define CAN_F0R2_FB21_Pos      (21U)
4721 #define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
4722 #define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
4723 #define CAN_F0R2_FB22_Pos      (22U)
4724 #define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
4725 #define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
4726 #define CAN_F0R2_FB23_Pos      (23U)
4727 #define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
4728 #define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
4729 #define CAN_F0R2_FB24_Pos      (24U)
4730 #define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
4731 #define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
4732 #define CAN_F0R2_FB25_Pos      (25U)
4733 #define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
4734 #define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
4735 #define CAN_F0R2_FB26_Pos      (26U)
4736 #define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
4737 #define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
4738 #define CAN_F0R2_FB27_Pos      (27U)
4739 #define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
4740 #define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
4741 #define CAN_F0R2_FB28_Pos      (28U)
4742 #define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
4743 #define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
4744 #define CAN_F0R2_FB29_Pos      (29U)
4745 #define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
4746 #define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
4747 #define CAN_F0R2_FB30_Pos      (30U)
4748 #define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
4749 #define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
4750 #define CAN_F0R2_FB31_Pos      (31U)
4751 #define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
4752 #define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
4753 
4754 /*******************  Bit definition for CAN_F1R2 register  *******************/
4755 #define CAN_F1R2_FB0_Pos       (0U)
4756 #define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
4757 #define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
4758 #define CAN_F1R2_FB1_Pos       (1U)
4759 #define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
4760 #define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
4761 #define CAN_F1R2_FB2_Pos       (2U)
4762 #define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
4763 #define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
4764 #define CAN_F1R2_FB3_Pos       (3U)
4765 #define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
4766 #define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
4767 #define CAN_F1R2_FB4_Pos       (4U)
4768 #define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
4769 #define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
4770 #define CAN_F1R2_FB5_Pos       (5U)
4771 #define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
4772 #define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
4773 #define CAN_F1R2_FB6_Pos       (6U)
4774 #define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
4775 #define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
4776 #define CAN_F1R2_FB7_Pos       (7U)
4777 #define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
4778 #define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
4779 #define CAN_F1R2_FB8_Pos       (8U)
4780 #define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
4781 #define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
4782 #define CAN_F1R2_FB9_Pos       (9U)
4783 #define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
4784 #define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
4785 #define CAN_F1R2_FB10_Pos      (10U)
4786 #define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
4787 #define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
4788 #define CAN_F1R2_FB11_Pos      (11U)
4789 #define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
4790 #define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
4791 #define CAN_F1R2_FB12_Pos      (12U)
4792 #define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
4793 #define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
4794 #define CAN_F1R2_FB13_Pos      (13U)
4795 #define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
4796 #define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
4797 #define CAN_F1R2_FB14_Pos      (14U)
4798 #define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
4799 #define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
4800 #define CAN_F1R2_FB15_Pos      (15U)
4801 #define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
4802 #define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
4803 #define CAN_F1R2_FB16_Pos      (16U)
4804 #define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
4805 #define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
4806 #define CAN_F1R2_FB17_Pos      (17U)
4807 #define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
4808 #define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
4809 #define CAN_F1R2_FB18_Pos      (18U)
4810 #define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
4811 #define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
4812 #define CAN_F1R2_FB19_Pos      (19U)
4813 #define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
4814 #define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
4815 #define CAN_F1R2_FB20_Pos      (20U)
4816 #define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
4817 #define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
4818 #define CAN_F1R2_FB21_Pos      (21U)
4819 #define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
4820 #define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
4821 #define CAN_F1R2_FB22_Pos      (22U)
4822 #define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
4823 #define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
4824 #define CAN_F1R2_FB23_Pos      (23U)
4825 #define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
4826 #define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
4827 #define CAN_F1R2_FB24_Pos      (24U)
4828 #define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
4829 #define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
4830 #define CAN_F1R2_FB25_Pos      (25U)
4831 #define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
4832 #define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
4833 #define CAN_F1R2_FB26_Pos      (26U)
4834 #define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
4835 #define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
4836 #define CAN_F1R2_FB27_Pos      (27U)
4837 #define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
4838 #define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
4839 #define CAN_F1R2_FB28_Pos      (28U)
4840 #define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
4841 #define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
4842 #define CAN_F1R2_FB29_Pos      (29U)
4843 #define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
4844 #define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
4845 #define CAN_F1R2_FB30_Pos      (30U)
4846 #define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
4847 #define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
4848 #define CAN_F1R2_FB31_Pos      (31U)
4849 #define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
4850 #define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
4851 
4852 /*******************  Bit definition for CAN_F2R2 register  *******************/
4853 #define CAN_F2R2_FB0_Pos       (0U)
4854 #define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
4855 #define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
4856 #define CAN_F2R2_FB1_Pos       (1U)
4857 #define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
4858 #define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
4859 #define CAN_F2R2_FB2_Pos       (2U)
4860 #define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
4861 #define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
4862 #define CAN_F2R2_FB3_Pos       (3U)
4863 #define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
4864 #define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
4865 #define CAN_F2R2_FB4_Pos       (4U)
4866 #define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
4867 #define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
4868 #define CAN_F2R2_FB5_Pos       (5U)
4869 #define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
4870 #define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
4871 #define CAN_F2R2_FB6_Pos       (6U)
4872 #define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
4873 #define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
4874 #define CAN_F2R2_FB7_Pos       (7U)
4875 #define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
4876 #define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
4877 #define CAN_F2R2_FB8_Pos       (8U)
4878 #define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
4879 #define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
4880 #define CAN_F2R2_FB9_Pos       (9U)
4881 #define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
4882 #define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
4883 #define CAN_F2R2_FB10_Pos      (10U)
4884 #define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
4885 #define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
4886 #define CAN_F2R2_FB11_Pos      (11U)
4887 #define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
4888 #define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
4889 #define CAN_F2R2_FB12_Pos      (12U)
4890 #define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
4891 #define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
4892 #define CAN_F2R2_FB13_Pos      (13U)
4893 #define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
4894 #define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
4895 #define CAN_F2R2_FB14_Pos      (14U)
4896 #define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
4897 #define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
4898 #define CAN_F2R2_FB15_Pos      (15U)
4899 #define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
4900 #define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
4901 #define CAN_F2R2_FB16_Pos      (16U)
4902 #define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
4903 #define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
4904 #define CAN_F2R2_FB17_Pos      (17U)
4905 #define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
4906 #define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
4907 #define CAN_F2R2_FB18_Pos      (18U)
4908 #define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
4909 #define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
4910 #define CAN_F2R2_FB19_Pos      (19U)
4911 #define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
4912 #define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
4913 #define CAN_F2R2_FB20_Pos      (20U)
4914 #define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
4915 #define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
4916 #define CAN_F2R2_FB21_Pos      (21U)
4917 #define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
4918 #define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
4919 #define CAN_F2R2_FB22_Pos      (22U)
4920 #define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
4921 #define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
4922 #define CAN_F2R2_FB23_Pos      (23U)
4923 #define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
4924 #define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
4925 #define CAN_F2R2_FB24_Pos      (24U)
4926 #define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
4927 #define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
4928 #define CAN_F2R2_FB25_Pos      (25U)
4929 #define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
4930 #define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
4931 #define CAN_F2R2_FB26_Pos      (26U)
4932 #define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
4933 #define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
4934 #define CAN_F2R2_FB27_Pos      (27U)
4935 #define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
4936 #define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
4937 #define CAN_F2R2_FB28_Pos      (28U)
4938 #define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
4939 #define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
4940 #define CAN_F2R2_FB29_Pos      (29U)
4941 #define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
4942 #define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
4943 #define CAN_F2R2_FB30_Pos      (30U)
4944 #define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
4945 #define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
4946 #define CAN_F2R2_FB31_Pos      (31U)
4947 #define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
4948 #define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
4949 
4950 /*******************  Bit definition for CAN_F3R2 register  *******************/
4951 #define CAN_F3R2_FB0_Pos       (0U)
4952 #define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
4953 #define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
4954 #define CAN_F3R2_FB1_Pos       (1U)
4955 #define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
4956 #define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
4957 #define CAN_F3R2_FB2_Pos       (2U)
4958 #define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
4959 #define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
4960 #define CAN_F3R2_FB3_Pos       (3U)
4961 #define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
4962 #define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
4963 #define CAN_F3R2_FB4_Pos       (4U)
4964 #define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
4965 #define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
4966 #define CAN_F3R2_FB5_Pos       (5U)
4967 #define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
4968 #define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
4969 #define CAN_F3R2_FB6_Pos       (6U)
4970 #define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
4971 #define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
4972 #define CAN_F3R2_FB7_Pos       (7U)
4973 #define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
4974 #define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
4975 #define CAN_F3R2_FB8_Pos       (8U)
4976 #define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
4977 #define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
4978 #define CAN_F3R2_FB9_Pos       (9U)
4979 #define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
4980 #define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
4981 #define CAN_F3R2_FB10_Pos      (10U)
4982 #define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
4983 #define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
4984 #define CAN_F3R2_FB11_Pos      (11U)
4985 #define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
4986 #define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
4987 #define CAN_F3R2_FB12_Pos      (12U)
4988 #define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
4989 #define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
4990 #define CAN_F3R2_FB13_Pos      (13U)
4991 #define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
4992 #define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
4993 #define CAN_F3R2_FB14_Pos      (14U)
4994 #define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
4995 #define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
4996 #define CAN_F3R2_FB15_Pos      (15U)
4997 #define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
4998 #define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
4999 #define CAN_F3R2_FB16_Pos      (16U)
5000 #define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
5001 #define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
5002 #define CAN_F3R2_FB17_Pos      (17U)
5003 #define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
5004 #define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
5005 #define CAN_F3R2_FB18_Pos      (18U)
5006 #define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
5007 #define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
5008 #define CAN_F3R2_FB19_Pos      (19U)
5009 #define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
5010 #define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
5011 #define CAN_F3R2_FB20_Pos      (20U)
5012 #define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
5013 #define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
5014 #define CAN_F3R2_FB21_Pos      (21U)
5015 #define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
5016 #define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
5017 #define CAN_F3R2_FB22_Pos      (22U)
5018 #define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
5019 #define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
5020 #define CAN_F3R2_FB23_Pos      (23U)
5021 #define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
5022 #define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
5023 #define CAN_F3R2_FB24_Pos      (24U)
5024 #define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
5025 #define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
5026 #define CAN_F3R2_FB25_Pos      (25U)
5027 #define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
5028 #define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
5029 #define CAN_F3R2_FB26_Pos      (26U)
5030 #define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
5031 #define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
5032 #define CAN_F3R2_FB27_Pos      (27U)
5033 #define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
5034 #define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
5035 #define CAN_F3R2_FB28_Pos      (28U)
5036 #define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
5037 #define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
5038 #define CAN_F3R2_FB29_Pos      (29U)
5039 #define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
5040 #define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
5041 #define CAN_F3R2_FB30_Pos      (30U)
5042 #define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
5043 #define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
5044 #define CAN_F3R2_FB31_Pos      (31U)
5045 #define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
5046 #define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
5047 
5048 /*******************  Bit definition for CAN_F4R2 register  *******************/
5049 #define CAN_F4R2_FB0_Pos       (0U)
5050 #define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
5051 #define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
5052 #define CAN_F4R2_FB1_Pos       (1U)
5053 #define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
5054 #define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
5055 #define CAN_F4R2_FB2_Pos       (2U)
5056 #define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
5057 #define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
5058 #define CAN_F4R2_FB3_Pos       (3U)
5059 #define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
5060 #define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
5061 #define CAN_F4R2_FB4_Pos       (4U)
5062 #define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
5063 #define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
5064 #define CAN_F4R2_FB5_Pos       (5U)
5065 #define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
5066 #define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
5067 #define CAN_F4R2_FB6_Pos       (6U)
5068 #define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
5069 #define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
5070 #define CAN_F4R2_FB7_Pos       (7U)
5071 #define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
5072 #define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
5073 #define CAN_F4R2_FB8_Pos       (8U)
5074 #define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
5075 #define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
5076 #define CAN_F4R2_FB9_Pos       (9U)
5077 #define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
5078 #define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
5079 #define CAN_F4R2_FB10_Pos      (10U)
5080 #define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
5081 #define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
5082 #define CAN_F4R2_FB11_Pos      (11U)
5083 #define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
5084 #define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
5085 #define CAN_F4R2_FB12_Pos      (12U)
5086 #define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
5087 #define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
5088 #define CAN_F4R2_FB13_Pos      (13U)
5089 #define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
5090 #define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
5091 #define CAN_F4R2_FB14_Pos      (14U)
5092 #define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
5093 #define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
5094 #define CAN_F4R2_FB15_Pos      (15U)
5095 #define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
5096 #define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
5097 #define CAN_F4R2_FB16_Pos      (16U)
5098 #define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
5099 #define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
5100 #define CAN_F4R2_FB17_Pos      (17U)
5101 #define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
5102 #define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
5103 #define CAN_F4R2_FB18_Pos      (18U)
5104 #define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
5105 #define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
5106 #define CAN_F4R2_FB19_Pos      (19U)
5107 #define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
5108 #define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
5109 #define CAN_F4R2_FB20_Pos      (20U)
5110 #define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
5111 #define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
5112 #define CAN_F4R2_FB21_Pos      (21U)
5113 #define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
5114 #define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
5115 #define CAN_F4R2_FB22_Pos      (22U)
5116 #define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
5117 #define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
5118 #define CAN_F4R2_FB23_Pos      (23U)
5119 #define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
5120 #define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
5121 #define CAN_F4R2_FB24_Pos      (24U)
5122 #define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
5123 #define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
5124 #define CAN_F4R2_FB25_Pos      (25U)
5125 #define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
5126 #define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
5127 #define CAN_F4R2_FB26_Pos      (26U)
5128 #define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
5129 #define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
5130 #define CAN_F4R2_FB27_Pos      (27U)
5131 #define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
5132 #define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
5133 #define CAN_F4R2_FB28_Pos      (28U)
5134 #define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
5135 #define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
5136 #define CAN_F4R2_FB29_Pos      (29U)
5137 #define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
5138 #define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
5139 #define CAN_F4R2_FB30_Pos      (30U)
5140 #define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
5141 #define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
5142 #define CAN_F4R2_FB31_Pos      (31U)
5143 #define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
5144 #define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
5145 
5146 /*******************  Bit definition for CAN_F5R2 register  *******************/
5147 #define CAN_F5R2_FB0_Pos       (0U)
5148 #define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
5149 #define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
5150 #define CAN_F5R2_FB1_Pos       (1U)
5151 #define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
5152 #define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
5153 #define CAN_F5R2_FB2_Pos       (2U)
5154 #define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
5155 #define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
5156 #define CAN_F5R2_FB3_Pos       (3U)
5157 #define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
5158 #define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
5159 #define CAN_F5R2_FB4_Pos       (4U)
5160 #define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
5161 #define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
5162 #define CAN_F5R2_FB5_Pos       (5U)
5163 #define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
5164 #define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
5165 #define CAN_F5R2_FB6_Pos       (6U)
5166 #define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
5167 #define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
5168 #define CAN_F5R2_FB7_Pos       (7U)
5169 #define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
5170 #define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
5171 #define CAN_F5R2_FB8_Pos       (8U)
5172 #define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
5173 #define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
5174 #define CAN_F5R2_FB9_Pos       (9U)
5175 #define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
5176 #define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
5177 #define CAN_F5R2_FB10_Pos      (10U)
5178 #define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
5179 #define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
5180 #define CAN_F5R2_FB11_Pos      (11U)
5181 #define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
5182 #define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
5183 #define CAN_F5R2_FB12_Pos      (12U)
5184 #define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
5185 #define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
5186 #define CAN_F5R2_FB13_Pos      (13U)
5187 #define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
5188 #define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
5189 #define CAN_F5R2_FB14_Pos      (14U)
5190 #define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
5191 #define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
5192 #define CAN_F5R2_FB15_Pos      (15U)
5193 #define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
5194 #define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
5195 #define CAN_F5R2_FB16_Pos      (16U)
5196 #define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
5197 #define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
5198 #define CAN_F5R2_FB17_Pos      (17U)
5199 #define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
5200 #define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
5201 #define CAN_F5R2_FB18_Pos      (18U)
5202 #define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
5203 #define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
5204 #define CAN_F5R2_FB19_Pos      (19U)
5205 #define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
5206 #define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
5207 #define CAN_F5R2_FB20_Pos      (20U)
5208 #define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
5209 #define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
5210 #define CAN_F5R2_FB21_Pos      (21U)
5211 #define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
5212 #define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
5213 #define CAN_F5R2_FB22_Pos      (22U)
5214 #define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
5215 #define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
5216 #define CAN_F5R2_FB23_Pos      (23U)
5217 #define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
5218 #define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
5219 #define CAN_F5R2_FB24_Pos      (24U)
5220 #define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
5221 #define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
5222 #define CAN_F5R2_FB25_Pos      (25U)
5223 #define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
5224 #define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
5225 #define CAN_F5R2_FB26_Pos      (26U)
5226 #define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
5227 #define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
5228 #define CAN_F5R2_FB27_Pos      (27U)
5229 #define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
5230 #define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
5231 #define CAN_F5R2_FB28_Pos      (28U)
5232 #define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
5233 #define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
5234 #define CAN_F5R2_FB29_Pos      (29U)
5235 #define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
5236 #define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
5237 #define CAN_F5R2_FB30_Pos      (30U)
5238 #define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
5239 #define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
5240 #define CAN_F5R2_FB31_Pos      (31U)
5241 #define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
5242 #define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
5243 
5244 /*******************  Bit definition for CAN_F6R2 register  *******************/
5245 #define CAN_F6R2_FB0_Pos       (0U)
5246 #define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
5247 #define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
5248 #define CAN_F6R2_FB1_Pos       (1U)
5249 #define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
5250 #define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
5251 #define CAN_F6R2_FB2_Pos       (2U)
5252 #define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
5253 #define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
5254 #define CAN_F6R2_FB3_Pos       (3U)
5255 #define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
5256 #define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
5257 #define CAN_F6R2_FB4_Pos       (4U)
5258 #define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
5259 #define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
5260 #define CAN_F6R2_FB5_Pos       (5U)
5261 #define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
5262 #define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
5263 #define CAN_F6R2_FB6_Pos       (6U)
5264 #define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
5265 #define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
5266 #define CAN_F6R2_FB7_Pos       (7U)
5267 #define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
5268 #define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
5269 #define CAN_F6R2_FB8_Pos       (8U)
5270 #define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
5271 #define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
5272 #define CAN_F6R2_FB9_Pos       (9U)
5273 #define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
5274 #define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
5275 #define CAN_F6R2_FB10_Pos      (10U)
5276 #define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
5277 #define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
5278 #define CAN_F6R2_FB11_Pos      (11U)
5279 #define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
5280 #define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
5281 #define CAN_F6R2_FB12_Pos      (12U)
5282 #define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
5283 #define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
5284 #define CAN_F6R2_FB13_Pos      (13U)
5285 #define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
5286 #define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
5287 #define CAN_F6R2_FB14_Pos      (14U)
5288 #define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
5289 #define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
5290 #define CAN_F6R2_FB15_Pos      (15U)
5291 #define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
5292 #define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
5293 #define CAN_F6R2_FB16_Pos      (16U)
5294 #define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
5295 #define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
5296 #define CAN_F6R2_FB17_Pos      (17U)
5297 #define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
5298 #define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
5299 #define CAN_F6R2_FB18_Pos      (18U)
5300 #define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
5301 #define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
5302 #define CAN_F6R2_FB19_Pos      (19U)
5303 #define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
5304 #define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
5305 #define CAN_F6R2_FB20_Pos      (20U)
5306 #define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
5307 #define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
5308 #define CAN_F6R2_FB21_Pos      (21U)
5309 #define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
5310 #define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
5311 #define CAN_F6R2_FB22_Pos      (22U)
5312 #define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
5313 #define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
5314 #define CAN_F6R2_FB23_Pos      (23U)
5315 #define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
5316 #define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
5317 #define CAN_F6R2_FB24_Pos      (24U)
5318 #define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
5319 #define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
5320 #define CAN_F6R2_FB25_Pos      (25U)
5321 #define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
5322 #define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
5323 #define CAN_F6R2_FB26_Pos      (26U)
5324 #define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
5325 #define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
5326 #define CAN_F6R2_FB27_Pos      (27U)
5327 #define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
5328 #define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
5329 #define CAN_F6R2_FB28_Pos      (28U)
5330 #define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
5331 #define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
5332 #define CAN_F6R2_FB29_Pos      (29U)
5333 #define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
5334 #define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
5335 #define CAN_F6R2_FB30_Pos      (30U)
5336 #define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
5337 #define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
5338 #define CAN_F6R2_FB31_Pos      (31U)
5339 #define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
5340 #define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
5341 
5342 /*******************  Bit definition for CAN_F7R2 register  *******************/
5343 #define CAN_F7R2_FB0_Pos       (0U)
5344 #define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
5345 #define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
5346 #define CAN_F7R2_FB1_Pos       (1U)
5347 #define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
5348 #define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
5349 #define CAN_F7R2_FB2_Pos       (2U)
5350 #define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
5351 #define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
5352 #define CAN_F7R2_FB3_Pos       (3U)
5353 #define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
5354 #define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
5355 #define CAN_F7R2_FB4_Pos       (4U)
5356 #define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
5357 #define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
5358 #define CAN_F7R2_FB5_Pos       (5U)
5359 #define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
5360 #define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
5361 #define CAN_F7R2_FB6_Pos       (6U)
5362 #define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
5363 #define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
5364 #define CAN_F7R2_FB7_Pos       (7U)
5365 #define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
5366 #define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
5367 #define CAN_F7R2_FB8_Pos       (8U)
5368 #define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
5369 #define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
5370 #define CAN_F7R2_FB9_Pos       (9U)
5371 #define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
5372 #define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
5373 #define CAN_F7R2_FB10_Pos      (10U)
5374 #define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
5375 #define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
5376 #define CAN_F7R2_FB11_Pos      (11U)
5377 #define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
5378 #define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
5379 #define CAN_F7R2_FB12_Pos      (12U)
5380 #define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
5381 #define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
5382 #define CAN_F7R2_FB13_Pos      (13U)
5383 #define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
5384 #define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
5385 #define CAN_F7R2_FB14_Pos      (14U)
5386 #define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
5387 #define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
5388 #define CAN_F7R2_FB15_Pos      (15U)
5389 #define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
5390 #define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
5391 #define CAN_F7R2_FB16_Pos      (16U)
5392 #define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
5393 #define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
5394 #define CAN_F7R2_FB17_Pos      (17U)
5395 #define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
5396 #define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
5397 #define CAN_F7R2_FB18_Pos      (18U)
5398 #define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
5399 #define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
5400 #define CAN_F7R2_FB19_Pos      (19U)
5401 #define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
5402 #define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
5403 #define CAN_F7R2_FB20_Pos      (20U)
5404 #define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
5405 #define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
5406 #define CAN_F7R2_FB21_Pos      (21U)
5407 #define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
5408 #define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
5409 #define CAN_F7R2_FB22_Pos      (22U)
5410 #define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
5411 #define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
5412 #define CAN_F7R2_FB23_Pos      (23U)
5413 #define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
5414 #define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
5415 #define CAN_F7R2_FB24_Pos      (24U)
5416 #define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
5417 #define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
5418 #define CAN_F7R2_FB25_Pos      (25U)
5419 #define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
5420 #define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
5421 #define CAN_F7R2_FB26_Pos      (26U)
5422 #define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
5423 #define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
5424 #define CAN_F7R2_FB27_Pos      (27U)
5425 #define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
5426 #define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
5427 #define CAN_F7R2_FB28_Pos      (28U)
5428 #define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
5429 #define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
5430 #define CAN_F7R2_FB29_Pos      (29U)
5431 #define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
5432 #define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
5433 #define CAN_F7R2_FB30_Pos      (30U)
5434 #define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
5435 #define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
5436 #define CAN_F7R2_FB31_Pos      (31U)
5437 #define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
5438 #define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
5439 
5440 /*******************  Bit definition for CAN_F8R2 register  *******************/
5441 #define CAN_F8R2_FB0_Pos       (0U)
5442 #define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
5443 #define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
5444 #define CAN_F8R2_FB1_Pos       (1U)
5445 #define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
5446 #define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
5447 #define CAN_F8R2_FB2_Pos       (2U)
5448 #define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
5449 #define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
5450 #define CAN_F8R2_FB3_Pos       (3U)
5451 #define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
5452 #define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
5453 #define CAN_F8R2_FB4_Pos       (4U)
5454 #define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
5455 #define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
5456 #define CAN_F8R2_FB5_Pos       (5U)
5457 #define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
5458 #define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
5459 #define CAN_F8R2_FB6_Pos       (6U)
5460 #define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
5461 #define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
5462 #define CAN_F8R2_FB7_Pos       (7U)
5463 #define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
5464 #define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
5465 #define CAN_F8R2_FB8_Pos       (8U)
5466 #define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
5467 #define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
5468 #define CAN_F8R2_FB9_Pos       (9U)
5469 #define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
5470 #define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
5471 #define CAN_F8R2_FB10_Pos      (10U)
5472 #define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
5473 #define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
5474 #define CAN_F8R2_FB11_Pos      (11U)
5475 #define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
5476 #define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
5477 #define CAN_F8R2_FB12_Pos      (12U)
5478 #define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
5479 #define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
5480 #define CAN_F8R2_FB13_Pos      (13U)
5481 #define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
5482 #define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
5483 #define CAN_F8R2_FB14_Pos      (14U)
5484 #define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
5485 #define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
5486 #define CAN_F8R2_FB15_Pos      (15U)
5487 #define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
5488 #define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
5489 #define CAN_F8R2_FB16_Pos      (16U)
5490 #define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
5491 #define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
5492 #define CAN_F8R2_FB17_Pos      (17U)
5493 #define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
5494 #define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
5495 #define CAN_F8R2_FB18_Pos      (18U)
5496 #define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
5497 #define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
5498 #define CAN_F8R2_FB19_Pos      (19U)
5499 #define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
5500 #define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
5501 #define CAN_F8R2_FB20_Pos      (20U)
5502 #define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
5503 #define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
5504 #define CAN_F8R2_FB21_Pos      (21U)
5505 #define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
5506 #define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
5507 #define CAN_F8R2_FB22_Pos      (22U)
5508 #define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
5509 #define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
5510 #define CAN_F8R2_FB23_Pos      (23U)
5511 #define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
5512 #define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
5513 #define CAN_F8R2_FB24_Pos      (24U)
5514 #define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
5515 #define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
5516 #define CAN_F8R2_FB25_Pos      (25U)
5517 #define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
5518 #define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
5519 #define CAN_F8R2_FB26_Pos      (26U)
5520 #define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
5521 #define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
5522 #define CAN_F8R2_FB27_Pos      (27U)
5523 #define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
5524 #define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
5525 #define CAN_F8R2_FB28_Pos      (28U)
5526 #define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
5527 #define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
5528 #define CAN_F8R2_FB29_Pos      (29U)
5529 #define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
5530 #define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
5531 #define CAN_F8R2_FB30_Pos      (30U)
5532 #define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
5533 #define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
5534 #define CAN_F8R2_FB31_Pos      (31U)
5535 #define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
5536 #define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
5537 
5538 /*******************  Bit definition for CAN_F9R2 register  *******************/
5539 #define CAN_F9R2_FB0_Pos       (0U)
5540 #define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
5541 #define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
5542 #define CAN_F9R2_FB1_Pos       (1U)
5543 #define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
5544 #define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
5545 #define CAN_F9R2_FB2_Pos       (2U)
5546 #define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
5547 #define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
5548 #define CAN_F9R2_FB3_Pos       (3U)
5549 #define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
5550 #define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
5551 #define CAN_F9R2_FB4_Pos       (4U)
5552 #define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
5553 #define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
5554 #define CAN_F9R2_FB5_Pos       (5U)
5555 #define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
5556 #define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
5557 #define CAN_F9R2_FB6_Pos       (6U)
5558 #define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
5559 #define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
5560 #define CAN_F9R2_FB7_Pos       (7U)
5561 #define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
5562 #define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
5563 #define CAN_F9R2_FB8_Pos       (8U)
5564 #define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
5565 #define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
5566 #define CAN_F9R2_FB9_Pos       (9U)
5567 #define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
5568 #define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
5569 #define CAN_F9R2_FB10_Pos      (10U)
5570 #define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
5571 #define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
5572 #define CAN_F9R2_FB11_Pos      (11U)
5573 #define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
5574 #define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
5575 #define CAN_F9R2_FB12_Pos      (12U)
5576 #define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
5577 #define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
5578 #define CAN_F9R2_FB13_Pos      (13U)
5579 #define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
5580 #define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
5581 #define CAN_F9R2_FB14_Pos      (14U)
5582 #define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
5583 #define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
5584 #define CAN_F9R2_FB15_Pos      (15U)
5585 #define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
5586 #define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
5587 #define CAN_F9R2_FB16_Pos      (16U)
5588 #define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
5589 #define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
5590 #define CAN_F9R2_FB17_Pos      (17U)
5591 #define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
5592 #define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
5593 #define CAN_F9R2_FB18_Pos      (18U)
5594 #define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
5595 #define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
5596 #define CAN_F9R2_FB19_Pos      (19U)
5597 #define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
5598 #define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
5599 #define CAN_F9R2_FB20_Pos      (20U)
5600 #define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
5601 #define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
5602 #define CAN_F9R2_FB21_Pos      (21U)
5603 #define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
5604 #define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
5605 #define CAN_F9R2_FB22_Pos      (22U)
5606 #define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
5607 #define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
5608 #define CAN_F9R2_FB23_Pos      (23U)
5609 #define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
5610 #define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
5611 #define CAN_F9R2_FB24_Pos      (24U)
5612 #define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
5613 #define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
5614 #define CAN_F9R2_FB25_Pos      (25U)
5615 #define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
5616 #define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
5617 #define CAN_F9R2_FB26_Pos      (26U)
5618 #define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
5619 #define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
5620 #define CAN_F9R2_FB27_Pos      (27U)
5621 #define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
5622 #define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
5623 #define CAN_F9R2_FB28_Pos      (28U)
5624 #define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
5625 #define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
5626 #define CAN_F9R2_FB29_Pos      (29U)
5627 #define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
5628 #define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
5629 #define CAN_F9R2_FB30_Pos      (30U)
5630 #define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
5631 #define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
5632 #define CAN_F9R2_FB31_Pos      (31U)
5633 #define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
5634 #define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
5635 
5636 /*******************  Bit definition for CAN_F10R2 register  ******************/
5637 #define CAN_F10R2_FB0_Pos      (0U)
5638 #define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
5639 #define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
5640 #define CAN_F10R2_FB1_Pos      (1U)
5641 #define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
5642 #define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
5643 #define CAN_F10R2_FB2_Pos      (2U)
5644 #define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
5645 #define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
5646 #define CAN_F10R2_FB3_Pos      (3U)
5647 #define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
5648 #define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
5649 #define CAN_F10R2_FB4_Pos      (4U)
5650 #define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
5651 #define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
5652 #define CAN_F10R2_FB5_Pos      (5U)
5653 #define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
5654 #define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
5655 #define CAN_F10R2_FB6_Pos      (6U)
5656 #define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
5657 #define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
5658 #define CAN_F10R2_FB7_Pos      (7U)
5659 #define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
5660 #define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
5661 #define CAN_F10R2_FB8_Pos      (8U)
5662 #define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
5663 #define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
5664 #define CAN_F10R2_FB9_Pos      (9U)
5665 #define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
5666 #define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
5667 #define CAN_F10R2_FB10_Pos     (10U)
5668 #define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
5669 #define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
5670 #define CAN_F10R2_FB11_Pos     (11U)
5671 #define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
5672 #define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
5673 #define CAN_F10R2_FB12_Pos     (12U)
5674 #define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
5675 #define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
5676 #define CAN_F10R2_FB13_Pos     (13U)
5677 #define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
5678 #define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
5679 #define CAN_F10R2_FB14_Pos     (14U)
5680 #define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
5681 #define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
5682 #define CAN_F10R2_FB15_Pos     (15U)
5683 #define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
5684 #define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
5685 #define CAN_F10R2_FB16_Pos     (16U)
5686 #define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
5687 #define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
5688 #define CAN_F10R2_FB17_Pos     (17U)
5689 #define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
5690 #define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
5691 #define CAN_F10R2_FB18_Pos     (18U)
5692 #define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
5693 #define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
5694 #define CAN_F10R2_FB19_Pos     (19U)
5695 #define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
5696 #define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
5697 #define CAN_F10R2_FB20_Pos     (20U)
5698 #define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
5699 #define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
5700 #define CAN_F10R2_FB21_Pos     (21U)
5701 #define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
5702 #define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
5703 #define CAN_F10R2_FB22_Pos     (22U)
5704 #define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
5705 #define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
5706 #define CAN_F10R2_FB23_Pos     (23U)
5707 #define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
5708 #define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
5709 #define CAN_F10R2_FB24_Pos     (24U)
5710 #define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
5711 #define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
5712 #define CAN_F10R2_FB25_Pos     (25U)
5713 #define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
5714 #define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
5715 #define CAN_F10R2_FB26_Pos     (26U)
5716 #define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
5717 #define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
5718 #define CAN_F10R2_FB27_Pos     (27U)
5719 #define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
5720 #define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
5721 #define CAN_F10R2_FB28_Pos     (28U)
5722 #define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
5723 #define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
5724 #define CAN_F10R2_FB29_Pos     (29U)
5725 #define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
5726 #define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
5727 #define CAN_F10R2_FB30_Pos     (30U)
5728 #define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
5729 #define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
5730 #define CAN_F10R2_FB31_Pos     (31U)
5731 #define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
5732 #define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
5733 
5734 /*******************  Bit definition for CAN_F11R2 register  ******************/
5735 #define CAN_F11R2_FB0_Pos      (0U)
5736 #define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
5737 #define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
5738 #define CAN_F11R2_FB1_Pos      (1U)
5739 #define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
5740 #define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
5741 #define CAN_F11R2_FB2_Pos      (2U)
5742 #define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
5743 #define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
5744 #define CAN_F11R2_FB3_Pos      (3U)
5745 #define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
5746 #define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
5747 #define CAN_F11R2_FB4_Pos      (4U)
5748 #define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
5749 #define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
5750 #define CAN_F11R2_FB5_Pos      (5U)
5751 #define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
5752 #define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
5753 #define CAN_F11R2_FB6_Pos      (6U)
5754 #define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
5755 #define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
5756 #define CAN_F11R2_FB7_Pos      (7U)
5757 #define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
5758 #define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
5759 #define CAN_F11R2_FB8_Pos      (8U)
5760 #define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
5761 #define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
5762 #define CAN_F11R2_FB9_Pos      (9U)
5763 #define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
5764 #define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
5765 #define CAN_F11R2_FB10_Pos     (10U)
5766 #define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
5767 #define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
5768 #define CAN_F11R2_FB11_Pos     (11U)
5769 #define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
5770 #define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
5771 #define CAN_F11R2_FB12_Pos     (12U)
5772 #define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
5773 #define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
5774 #define CAN_F11R2_FB13_Pos     (13U)
5775 #define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
5776 #define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
5777 #define CAN_F11R2_FB14_Pos     (14U)
5778 #define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
5779 #define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
5780 #define CAN_F11R2_FB15_Pos     (15U)
5781 #define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
5782 #define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
5783 #define CAN_F11R2_FB16_Pos     (16U)
5784 #define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
5785 #define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
5786 #define CAN_F11R2_FB17_Pos     (17U)
5787 #define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
5788 #define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
5789 #define CAN_F11R2_FB18_Pos     (18U)
5790 #define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
5791 #define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
5792 #define CAN_F11R2_FB19_Pos     (19U)
5793 #define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
5794 #define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
5795 #define CAN_F11R2_FB20_Pos     (20U)
5796 #define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
5797 #define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
5798 #define CAN_F11R2_FB21_Pos     (21U)
5799 #define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
5800 #define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
5801 #define CAN_F11R2_FB22_Pos     (22U)
5802 #define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
5803 #define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
5804 #define CAN_F11R2_FB23_Pos     (23U)
5805 #define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
5806 #define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
5807 #define CAN_F11R2_FB24_Pos     (24U)
5808 #define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
5809 #define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
5810 #define CAN_F11R2_FB25_Pos     (25U)
5811 #define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
5812 #define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
5813 #define CAN_F11R2_FB26_Pos     (26U)
5814 #define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
5815 #define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
5816 #define CAN_F11R2_FB27_Pos     (27U)
5817 #define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
5818 #define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
5819 #define CAN_F11R2_FB28_Pos     (28U)
5820 #define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
5821 #define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
5822 #define CAN_F11R2_FB29_Pos     (29U)
5823 #define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
5824 #define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
5825 #define CAN_F11R2_FB30_Pos     (30U)
5826 #define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
5827 #define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
5828 #define CAN_F11R2_FB31_Pos     (31U)
5829 #define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
5830 #define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
5831 
5832 /*******************  Bit definition for CAN_F12R2 register  ******************/
5833 #define CAN_F12R2_FB0_Pos      (0U)
5834 #define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
5835 #define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
5836 #define CAN_F12R2_FB1_Pos      (1U)
5837 #define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
5838 #define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
5839 #define CAN_F12R2_FB2_Pos      (2U)
5840 #define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
5841 #define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
5842 #define CAN_F12R2_FB3_Pos      (3U)
5843 #define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
5844 #define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
5845 #define CAN_F12R2_FB4_Pos      (4U)
5846 #define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
5847 #define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
5848 #define CAN_F12R2_FB5_Pos      (5U)
5849 #define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
5850 #define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
5851 #define CAN_F12R2_FB6_Pos      (6U)
5852 #define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
5853 #define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
5854 #define CAN_F12R2_FB7_Pos      (7U)
5855 #define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
5856 #define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
5857 #define CAN_F12R2_FB8_Pos      (8U)
5858 #define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
5859 #define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
5860 #define CAN_F12R2_FB9_Pos      (9U)
5861 #define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
5862 #define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
5863 #define CAN_F12R2_FB10_Pos     (10U)
5864 #define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
5865 #define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
5866 #define CAN_F12R2_FB11_Pos     (11U)
5867 #define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
5868 #define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
5869 #define CAN_F12R2_FB12_Pos     (12U)
5870 #define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
5871 #define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
5872 #define CAN_F12R2_FB13_Pos     (13U)
5873 #define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
5874 #define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
5875 #define CAN_F12R2_FB14_Pos     (14U)
5876 #define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
5877 #define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
5878 #define CAN_F12R2_FB15_Pos     (15U)
5879 #define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
5880 #define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
5881 #define CAN_F12R2_FB16_Pos     (16U)
5882 #define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
5883 #define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
5884 #define CAN_F12R2_FB17_Pos     (17U)
5885 #define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
5886 #define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
5887 #define CAN_F12R2_FB18_Pos     (18U)
5888 #define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
5889 #define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
5890 #define CAN_F12R2_FB19_Pos     (19U)
5891 #define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
5892 #define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
5893 #define CAN_F12R2_FB20_Pos     (20U)
5894 #define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
5895 #define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
5896 #define CAN_F12R2_FB21_Pos     (21U)
5897 #define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
5898 #define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
5899 #define CAN_F12R2_FB22_Pos     (22U)
5900 #define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
5901 #define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
5902 #define CAN_F12R2_FB23_Pos     (23U)
5903 #define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
5904 #define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
5905 #define CAN_F12R2_FB24_Pos     (24U)
5906 #define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
5907 #define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
5908 #define CAN_F12R2_FB25_Pos     (25U)
5909 #define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
5910 #define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
5911 #define CAN_F12R2_FB26_Pos     (26U)
5912 #define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
5913 #define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
5914 #define CAN_F12R2_FB27_Pos     (27U)
5915 #define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
5916 #define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
5917 #define CAN_F12R2_FB28_Pos     (28U)
5918 #define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
5919 #define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
5920 #define CAN_F12R2_FB29_Pos     (29U)
5921 #define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
5922 #define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
5923 #define CAN_F12R2_FB30_Pos     (30U)
5924 #define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
5925 #define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
5926 #define CAN_F12R2_FB31_Pos     (31U)
5927 #define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
5928 #define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
5929 
5930 /*******************  Bit definition for CAN_F13R2 register  ******************/
5931 #define CAN_F13R2_FB0_Pos      (0U)
5932 #define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
5933 #define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
5934 #define CAN_F13R2_FB1_Pos      (1U)
5935 #define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
5936 #define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
5937 #define CAN_F13R2_FB2_Pos      (2U)
5938 #define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
5939 #define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
5940 #define CAN_F13R2_FB3_Pos      (3U)
5941 #define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
5942 #define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
5943 #define CAN_F13R2_FB4_Pos      (4U)
5944 #define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
5945 #define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
5946 #define CAN_F13R2_FB5_Pos      (5U)
5947 #define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
5948 #define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
5949 #define CAN_F13R2_FB6_Pos      (6U)
5950 #define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
5951 #define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
5952 #define CAN_F13R2_FB7_Pos      (7U)
5953 #define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
5954 #define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
5955 #define CAN_F13R2_FB8_Pos      (8U)
5956 #define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
5957 #define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
5958 #define CAN_F13R2_FB9_Pos      (9U)
5959 #define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
5960 #define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
5961 #define CAN_F13R2_FB10_Pos     (10U)
5962 #define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
5963 #define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
5964 #define CAN_F13R2_FB11_Pos     (11U)
5965 #define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
5966 #define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
5967 #define CAN_F13R2_FB12_Pos     (12U)
5968 #define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
5969 #define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
5970 #define CAN_F13R2_FB13_Pos     (13U)
5971 #define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
5972 #define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
5973 #define CAN_F13R2_FB14_Pos     (14U)
5974 #define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
5975 #define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
5976 #define CAN_F13R2_FB15_Pos     (15U)
5977 #define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
5978 #define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
5979 #define CAN_F13R2_FB16_Pos     (16U)
5980 #define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
5981 #define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
5982 #define CAN_F13R2_FB17_Pos     (17U)
5983 #define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
5984 #define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
5985 #define CAN_F13R2_FB18_Pos     (18U)
5986 #define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
5987 #define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
5988 #define CAN_F13R2_FB19_Pos     (19U)
5989 #define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
5990 #define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
5991 #define CAN_F13R2_FB20_Pos     (20U)
5992 #define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
5993 #define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
5994 #define CAN_F13R2_FB21_Pos     (21U)
5995 #define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
5996 #define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
5997 #define CAN_F13R2_FB22_Pos     (22U)
5998 #define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
5999 #define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
6000 #define CAN_F13R2_FB23_Pos     (23U)
6001 #define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
6002 #define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
6003 #define CAN_F13R2_FB24_Pos     (24U)
6004 #define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
6005 #define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
6006 #define CAN_F13R2_FB25_Pos     (25U)
6007 #define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
6008 #define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
6009 #define CAN_F13R2_FB26_Pos     (26U)
6010 #define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
6011 #define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
6012 #define CAN_F13R2_FB27_Pos     (27U)
6013 #define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
6014 #define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
6015 #define CAN_F13R2_FB28_Pos     (28U)
6016 #define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
6017 #define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
6018 #define CAN_F13R2_FB29_Pos     (29U)
6019 #define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
6020 #define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
6021 #define CAN_F13R2_FB30_Pos     (30U)
6022 #define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
6023 #define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
6024 #define CAN_F13R2_FB31_Pos     (31U)
6025 #define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
6026 #define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
6027 
6028 /******************************************************************************/
6029 /*                                                                            */
6030 /*                     CRC calculation unit (CRC)                             */
6031 /*                                                                            */
6032 /******************************************************************************/
6033 /*******************  Bit definition for CRC_DR register  *********************/
6034 #define CRC_DR_DR_Pos            (0U)
6035 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
6036 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
6037 
6038 /*******************  Bit definition for CRC_IDR register  ********************/
6039 #define CRC_IDR_IDR              ((uint8_t)0xFFU)                              /*!< General-purpose 8-bit data register bits */
6040 
6041 /********************  Bit definition for CRC_CR register  ********************/
6042 #define CRC_CR_RESET_Pos         (0U)
6043 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
6044 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
6045 #define CRC_CR_POLYSIZE_Pos      (3U)
6046 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
6047 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
6048 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
6049 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
6050 #define CRC_CR_REV_IN_Pos        (5U)
6051 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
6052 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
6053 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
6054 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
6055 #define CRC_CR_REV_OUT_Pos       (7U)
6056 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
6057 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
6058 
6059 /*******************  Bit definition for CRC_INIT register  *******************/
6060 #define CRC_INIT_INIT_Pos        (0U)
6061 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
6062 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
6063 
6064 /*******************  Bit definition for CRC_POL register  ********************/
6065 #define CRC_POL_POL_Pos          (0U)
6066 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
6067 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
6068 
6069 /******************************************************************************/
6070 /*                                                                            */
6071 /*                 Digital to Analog Converter (DAC)                          */
6072 /*                                                                            */
6073 /******************************************************************************/
6074 
6075 /*
6076  * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
6077  */
6078 #define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available (may not be available on all DAC instances DACx) */
6079 
6080 
6081 /********************  Bit definition for DAC_CR register  ********************/
6082 #define DAC_CR_EN1_Pos              (0U)
6083 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
6084 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
6085 #define DAC_CR_BOFF1_Pos            (1U)
6086 #define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
6087 #define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
6088 #define DAC_CR_OUTEN1_Pos           (1U)
6089 #define DAC_CR_OUTEN1_Msk           (0x1UL << DAC_CR_OUTEN1_Pos)                /*!< 0x00000002 */
6090 #define DAC_CR_OUTEN1               DAC_CR_OUTEN1_Msk                          /*!< DAC channel1 output switch enable (only for DAC instance: DAC2) */
6091 #define DAC_CR_TEN1_Pos             (2U)
6092 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
6093 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
6094 
6095 #define DAC_CR_TSEL1_Pos            (3U)
6096 #define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
6097 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
6098 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
6099 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
6100 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
6101 
6102 #define DAC_CR_WAVE1_Pos            (6U)
6103 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
6104 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
6105 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
6106 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
6107 
6108 #define DAC_CR_MAMP1_Pos            (8U)
6109 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
6110 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
6111 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
6112 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
6113 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
6114 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
6115 
6116 #define DAC_CR_DMAEN1_Pos           (12U)
6117 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
6118 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
6119 #define DAC_CR_DMAUDRIE1_Pos        (13U)
6120 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
6121 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA underrun IT enable */
6122 #define DAC_CR_EN2_Pos              (16U)
6123 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
6124 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!< DAC channel2 enable */
6125 #define DAC_CR_BOFF2_Pos            (17U)
6126 #define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
6127 #define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!< DAC channel2 output buffer disable */
6128 #define DAC_CR_OUTEN2_Pos           (17U)
6129 #define DAC_CR_OUTEN2_Msk           (0x1UL << DAC_CR_OUTEN2_Pos)                /*!< 0x00020000 */
6130 #define DAC_CR_OUTEN2               DAC_CR_OUTEN2_Msk                          /*!< DAC channel2 output switch enable (only for DAC instance: DAC2) */
6131 #define DAC_CR_TEN2_Pos             (18U)
6132 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
6133 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!< DAC channel2 Trigger enable */
6134 
6135 #define DAC_CR_TSEL2_Pos            (19U)
6136 #define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
6137 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
6138 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
6139 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
6140 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
6141 
6142 #define DAC_CR_WAVE2_Pos            (22U)
6143 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
6144 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
6145 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
6146 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
6147 
6148 #define DAC_CR_MAMP2_Pos            (24U)
6149 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
6150 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
6151 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
6152 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
6153 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
6154 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
6155 
6156 #define DAC_CR_DMAEN2_Pos           (28U)
6157 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
6158 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!< DAC channel2 DMA enabled */
6159 #define DAC_CR_DMAUDRIE2_Pos        (29U)
6160 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
6161 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!< DAC channel2 DMA underrun IT enable */
6162 
6163 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
6164 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
6165 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
6166 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
6167 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
6168 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
6169 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!< DAC channel2 software trigger */
6170 
6171 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
6172 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
6173 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
6174 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
6175 
6176 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
6177 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
6178 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
6179 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
6180 
6181 /******************  Bit definition for DAC_DHR8R1 register  ******************/
6182 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
6183 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
6184 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
6185 
6186 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
6187 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
6188 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
6189 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
6190 
6191 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
6192 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
6193 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
6194 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
6195 
6196 /******************  Bit definition for DAC_DHR8R2 register  ******************/
6197 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
6198 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
6199 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
6200 
6201 /*****************  Bit definition for DAC_DHR12RD register  ******************/
6202 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
6203 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
6204 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
6205 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
6206 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
6207 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
6208 
6209 /*****************  Bit definition for DAC_DHR12LD register  ******************/
6210 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
6211 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
6212 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
6213 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
6214 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
6215 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
6216 
6217 /******************  Bit definition for DAC_DHR8RD register  ******************/
6218 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
6219 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
6220 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
6221 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
6222 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
6223 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
6224 
6225 /*******************  Bit definition for DAC_DOR1 register  *******************/
6226 #define DAC_DOR1_DACC1DOR_Pos       (0U)
6227 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
6228 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!< DAC channel1 data output */
6229 
6230 /*******************  Bit definition for DAC_DOR2 register  *******************/
6231 #define DAC_DOR2_DACC2DOR_Pos       (0U)
6232 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
6233 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!< DAC channel2 data output */
6234 
6235 /********************  Bit definition for DAC_SR register  ********************/
6236 #define DAC_SR_DMAUDR1_Pos          (13U)
6237 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
6238 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
6239 #define DAC_SR_DMAUDR2_Pos          (29U)
6240 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
6241 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!< DAC channel2 DMA underrun flag */
6242 
6243 /******************************************************************************/
6244 /*                                                                            */
6245 /*                                 Debug MCU (DBGMCU)                         */
6246 /*                                                                            */
6247 /******************************************************************************/
6248 /********************  Bit definition for DBGMCU_IDCODE register  *************/
6249 #define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)
6250 #define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
6251 #define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk
6252 #define DBGMCU_IDCODE_REV_ID_Pos                     (16U)
6253 #define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
6254 #define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk
6255 
6256 /********************  Bit definition for DBGMCU_CR register  *****************/
6257 #define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)
6258 #define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
6259 #define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk
6260 #define DBGMCU_CR_DBG_STOP_Pos                       (1U)
6261 #define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
6262 #define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk
6263 #define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)
6264 #define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
6265 #define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk
6266 #define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)
6267 #define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
6268 #define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk
6269 
6270 #define DBGMCU_CR_TRACE_MODE_Pos                     (6U)
6271 #define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
6272 #define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk
6273 #define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
6274 #define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
6275 
6276 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
6277 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)
6278 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
6279 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
6280 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)
6281 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
6282 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
6283 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)
6284 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
6285 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
6286 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)
6287 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
6288 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
6289 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)
6290 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
6291 #define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
6292 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)
6293 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
6294 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
6295 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)
6296 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
6297 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
6298 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)
6299 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
6300 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
6301 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos              (25U)
6302 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
6303 #define DBGMCU_APB1_FZ_DBG_CAN_STOP                  DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk
6304 
6305 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
6306 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)
6307 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
6308 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
6309 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos            (2U)
6310 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00000004 */
6311 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP                DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk
6312 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos            (3U)
6313 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00000008 */
6314 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP                DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk
6315 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos            (4U)
6316 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00000010 */
6317 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP                DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk
6318 #define DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Pos           (8U)
6319 #define DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Msk           (0x1UL << DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Pos) /*!< 0x00000100 */
6320 #define DBGMCU_APB2_FZ_DBG_HRTIM1_STOP               DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Msk
6321 
6322 /******************************************************************************/
6323 /*                                                                            */
6324 /*                             DMA Controller (DMA)                           */
6325 /*                                                                            */
6326 /******************************************************************************/
6327 /*******************  Bit definition for DMA_ISR register  ********************/
6328 #define DMA_ISR_GIF1_Pos       (0U)
6329 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
6330 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
6331 #define DMA_ISR_TCIF1_Pos      (1U)
6332 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
6333 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
6334 #define DMA_ISR_HTIF1_Pos      (2U)
6335 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
6336 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
6337 #define DMA_ISR_TEIF1_Pos      (3U)
6338 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
6339 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
6340 #define DMA_ISR_GIF2_Pos       (4U)
6341 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
6342 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
6343 #define DMA_ISR_TCIF2_Pos      (5U)
6344 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
6345 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
6346 #define DMA_ISR_HTIF2_Pos      (6U)
6347 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
6348 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
6349 #define DMA_ISR_TEIF2_Pos      (7U)
6350 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
6351 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
6352 #define DMA_ISR_GIF3_Pos       (8U)
6353 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
6354 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
6355 #define DMA_ISR_TCIF3_Pos      (9U)
6356 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
6357 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
6358 #define DMA_ISR_HTIF3_Pos      (10U)
6359 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
6360 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
6361 #define DMA_ISR_TEIF3_Pos      (11U)
6362 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
6363 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
6364 #define DMA_ISR_GIF4_Pos       (12U)
6365 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
6366 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
6367 #define DMA_ISR_TCIF4_Pos      (13U)
6368 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
6369 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
6370 #define DMA_ISR_HTIF4_Pos      (14U)
6371 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
6372 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
6373 #define DMA_ISR_TEIF4_Pos      (15U)
6374 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
6375 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
6376 #define DMA_ISR_GIF5_Pos       (16U)
6377 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
6378 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
6379 #define DMA_ISR_TCIF5_Pos      (17U)
6380 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
6381 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
6382 #define DMA_ISR_HTIF5_Pos      (18U)
6383 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
6384 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
6385 #define DMA_ISR_TEIF5_Pos      (19U)
6386 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
6387 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
6388 #define DMA_ISR_GIF6_Pos       (20U)
6389 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
6390 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
6391 #define DMA_ISR_TCIF6_Pos      (21U)
6392 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
6393 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
6394 #define DMA_ISR_HTIF6_Pos      (22U)
6395 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
6396 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
6397 #define DMA_ISR_TEIF6_Pos      (23U)
6398 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
6399 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
6400 #define DMA_ISR_GIF7_Pos       (24U)
6401 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
6402 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
6403 #define DMA_ISR_TCIF7_Pos      (25U)
6404 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
6405 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
6406 #define DMA_ISR_HTIF7_Pos      (26U)
6407 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
6408 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
6409 #define DMA_ISR_TEIF7_Pos      (27U)
6410 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
6411 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
6412 
6413 /*******************  Bit definition for DMA_IFCR register  *******************/
6414 #define DMA_IFCR_CGIF1_Pos     (0U)
6415 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
6416 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear */
6417 #define DMA_IFCR_CTCIF1_Pos    (1U)
6418 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
6419 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
6420 #define DMA_IFCR_CHTIF1_Pos    (2U)
6421 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
6422 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
6423 #define DMA_IFCR_CTEIF1_Pos    (3U)
6424 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
6425 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
6426 #define DMA_IFCR_CGIF2_Pos     (4U)
6427 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
6428 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
6429 #define DMA_IFCR_CTCIF2_Pos    (5U)
6430 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
6431 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
6432 #define DMA_IFCR_CHTIF2_Pos    (6U)
6433 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
6434 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
6435 #define DMA_IFCR_CTEIF2_Pos    (7U)
6436 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
6437 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
6438 #define DMA_IFCR_CGIF3_Pos     (8U)
6439 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
6440 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
6441 #define DMA_IFCR_CTCIF3_Pos    (9U)
6442 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
6443 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
6444 #define DMA_IFCR_CHTIF3_Pos    (10U)
6445 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
6446 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
6447 #define DMA_IFCR_CTEIF3_Pos    (11U)
6448 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
6449 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
6450 #define DMA_IFCR_CGIF4_Pos     (12U)
6451 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
6452 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
6453 #define DMA_IFCR_CTCIF4_Pos    (13U)
6454 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
6455 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
6456 #define DMA_IFCR_CHTIF4_Pos    (14U)
6457 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
6458 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
6459 #define DMA_IFCR_CTEIF4_Pos    (15U)
6460 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
6461 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
6462 #define DMA_IFCR_CGIF5_Pos     (16U)
6463 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
6464 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
6465 #define DMA_IFCR_CTCIF5_Pos    (17U)
6466 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
6467 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
6468 #define DMA_IFCR_CHTIF5_Pos    (18U)
6469 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
6470 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
6471 #define DMA_IFCR_CTEIF5_Pos    (19U)
6472 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
6473 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
6474 #define DMA_IFCR_CGIF6_Pos     (20U)
6475 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
6476 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
6477 #define DMA_IFCR_CTCIF6_Pos    (21U)
6478 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
6479 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
6480 #define DMA_IFCR_CHTIF6_Pos    (22U)
6481 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
6482 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
6483 #define DMA_IFCR_CTEIF6_Pos    (23U)
6484 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
6485 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
6486 #define DMA_IFCR_CGIF7_Pos     (24U)
6487 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
6488 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
6489 #define DMA_IFCR_CTCIF7_Pos    (25U)
6490 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
6491 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
6492 #define DMA_IFCR_CHTIF7_Pos    (26U)
6493 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
6494 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
6495 #define DMA_IFCR_CTEIF7_Pos    (27U)
6496 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
6497 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
6498 
6499 /*******************  Bit definition for DMA_CCR register  ********************/
6500 #define DMA_CCR_EN_Pos         (0U)
6501 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
6502 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
6503 #define DMA_CCR_TCIE_Pos       (1U)
6504 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
6505 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
6506 #define DMA_CCR_HTIE_Pos       (2U)
6507 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
6508 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
6509 #define DMA_CCR_TEIE_Pos       (3U)
6510 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
6511 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
6512 #define DMA_CCR_DIR_Pos        (4U)
6513 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
6514 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
6515 #define DMA_CCR_CIRC_Pos       (5U)
6516 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
6517 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
6518 #define DMA_CCR_PINC_Pos       (6U)
6519 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
6520 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
6521 #define DMA_CCR_MINC_Pos       (7U)
6522 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
6523 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
6524 
6525 #define DMA_CCR_PSIZE_Pos      (8U)
6526 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
6527 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
6528 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
6529 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
6530 
6531 #define DMA_CCR_MSIZE_Pos      (10U)
6532 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
6533 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
6534 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
6535 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
6536 
6537 #define DMA_CCR_PL_Pos         (12U)
6538 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
6539 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
6540 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
6541 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
6542 
6543 #define DMA_CCR_MEM2MEM_Pos    (14U)
6544 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
6545 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
6546 
6547 /******************  Bit definition for DMA_CNDTR register  *******************/
6548 #define DMA_CNDTR_NDT_Pos      (0U)
6549 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
6550 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
6551 
6552 /******************  Bit definition for DMA_CPAR register  ********************/
6553 #define DMA_CPAR_PA_Pos        (0U)
6554 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
6555 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
6556 
6557 /******************  Bit definition for DMA_CMAR register  ********************/
6558 #define DMA_CMAR_MA_Pos        (0U)
6559 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
6560 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
6561 
6562 /******************************************************************************/
6563 /*                                                                            */
6564 /*                    External Interrupt/Event Controller (EXTI)              */
6565 /*                                                                            */
6566 /******************************************************************************/
6567 /*******************  Bit definition for EXTI_IMR register  *******************/
6568 #define EXTI_IMR_MR0_Pos           (0U)
6569 #define EXTI_IMR_MR0_Msk           (0x1UL << EXTI_IMR_MR0_Pos)                  /*!< 0x00000001 */
6570 #define EXTI_IMR_MR0               EXTI_IMR_MR0_Msk                            /*!< Interrupt Mask on line 0 */
6571 #define EXTI_IMR_MR1_Pos           (1U)
6572 #define EXTI_IMR_MR1_Msk           (0x1UL << EXTI_IMR_MR1_Pos)                  /*!< 0x00000002 */
6573 #define EXTI_IMR_MR1               EXTI_IMR_MR1_Msk                            /*!< Interrupt Mask on line 1 */
6574 #define EXTI_IMR_MR2_Pos           (2U)
6575 #define EXTI_IMR_MR2_Msk           (0x1UL << EXTI_IMR_MR2_Pos)                  /*!< 0x00000004 */
6576 #define EXTI_IMR_MR2               EXTI_IMR_MR2_Msk                            /*!< Interrupt Mask on line 2 */
6577 #define EXTI_IMR_MR3_Pos           (3U)
6578 #define EXTI_IMR_MR3_Msk           (0x1UL << EXTI_IMR_MR3_Pos)                  /*!< 0x00000008 */
6579 #define EXTI_IMR_MR3               EXTI_IMR_MR3_Msk                            /*!< Interrupt Mask on line 3 */
6580 #define EXTI_IMR_MR4_Pos           (4U)
6581 #define EXTI_IMR_MR4_Msk           (0x1UL << EXTI_IMR_MR4_Pos)                  /*!< 0x00000010 */
6582 #define EXTI_IMR_MR4               EXTI_IMR_MR4_Msk                            /*!< Interrupt Mask on line 4 */
6583 #define EXTI_IMR_MR5_Pos           (5U)
6584 #define EXTI_IMR_MR5_Msk           (0x1UL << EXTI_IMR_MR5_Pos)                  /*!< 0x00000020 */
6585 #define EXTI_IMR_MR5               EXTI_IMR_MR5_Msk                            /*!< Interrupt Mask on line 5 */
6586 #define EXTI_IMR_MR6_Pos           (6U)
6587 #define EXTI_IMR_MR6_Msk           (0x1UL << EXTI_IMR_MR6_Pos)                  /*!< 0x00000040 */
6588 #define EXTI_IMR_MR6               EXTI_IMR_MR6_Msk                            /*!< Interrupt Mask on line 6 */
6589 #define EXTI_IMR_MR7_Pos           (7U)
6590 #define EXTI_IMR_MR7_Msk           (0x1UL << EXTI_IMR_MR7_Pos)                  /*!< 0x00000080 */
6591 #define EXTI_IMR_MR7               EXTI_IMR_MR7_Msk                            /*!< Interrupt Mask on line 7 */
6592 #define EXTI_IMR_MR8_Pos           (8U)
6593 #define EXTI_IMR_MR8_Msk           (0x1UL << EXTI_IMR_MR8_Pos)                  /*!< 0x00000100 */
6594 #define EXTI_IMR_MR8               EXTI_IMR_MR8_Msk                            /*!< Interrupt Mask on line 8 */
6595 #define EXTI_IMR_MR9_Pos           (9U)
6596 #define EXTI_IMR_MR9_Msk           (0x1UL << EXTI_IMR_MR9_Pos)                  /*!< 0x00000200 */
6597 #define EXTI_IMR_MR9               EXTI_IMR_MR9_Msk                            /*!< Interrupt Mask on line 9 */
6598 #define EXTI_IMR_MR10_Pos          (10U)
6599 #define EXTI_IMR_MR10_Msk          (0x1UL << EXTI_IMR_MR10_Pos)                 /*!< 0x00000400 */
6600 #define EXTI_IMR_MR10              EXTI_IMR_MR10_Msk                           /*!< Interrupt Mask on line 10 */
6601 #define EXTI_IMR_MR11_Pos          (11U)
6602 #define EXTI_IMR_MR11_Msk          (0x1UL << EXTI_IMR_MR11_Pos)                 /*!< 0x00000800 */
6603 #define EXTI_IMR_MR11              EXTI_IMR_MR11_Msk                           /*!< Interrupt Mask on line 11 */
6604 #define EXTI_IMR_MR12_Pos          (12U)
6605 #define EXTI_IMR_MR12_Msk          (0x1UL << EXTI_IMR_MR12_Pos)                 /*!< 0x00001000 */
6606 #define EXTI_IMR_MR12              EXTI_IMR_MR12_Msk                           /*!< Interrupt Mask on line 12 */
6607 #define EXTI_IMR_MR13_Pos          (13U)
6608 #define EXTI_IMR_MR13_Msk          (0x1UL << EXTI_IMR_MR13_Pos)                 /*!< 0x00002000 */
6609 #define EXTI_IMR_MR13              EXTI_IMR_MR13_Msk                           /*!< Interrupt Mask on line 13 */
6610 #define EXTI_IMR_MR14_Pos          (14U)
6611 #define EXTI_IMR_MR14_Msk          (0x1UL << EXTI_IMR_MR14_Pos)                 /*!< 0x00004000 */
6612 #define EXTI_IMR_MR14              EXTI_IMR_MR14_Msk                           /*!< Interrupt Mask on line 14 */
6613 #define EXTI_IMR_MR15_Pos          (15U)
6614 #define EXTI_IMR_MR15_Msk          (0x1UL << EXTI_IMR_MR15_Pos)                 /*!< 0x00008000 */
6615 #define EXTI_IMR_MR15              EXTI_IMR_MR15_Msk                           /*!< Interrupt Mask on line 15 */
6616 #define EXTI_IMR_MR16_Pos          (16U)
6617 #define EXTI_IMR_MR16_Msk          (0x1UL << EXTI_IMR_MR16_Pos)                 /*!< 0x00010000 */
6618 #define EXTI_IMR_MR16              EXTI_IMR_MR16_Msk                           /*!< Interrupt Mask on line 16 */
6619 #define EXTI_IMR_MR17_Pos          (17U)
6620 #define EXTI_IMR_MR17_Msk          (0x1UL << EXTI_IMR_MR17_Pos)                 /*!< 0x00020000 */
6621 #define EXTI_IMR_MR17              EXTI_IMR_MR17_Msk                           /*!< Interrupt Mask on line 17 */
6622 #define EXTI_IMR_MR19_Pos          (19U)
6623 #define EXTI_IMR_MR19_Msk          (0x1UL << EXTI_IMR_MR19_Pos)                 /*!< 0x00080000 */
6624 #define EXTI_IMR_MR19              EXTI_IMR_MR19_Msk                           /*!< Interrupt Mask on line 19 */
6625 #define EXTI_IMR_MR20_Pos          (20U)
6626 #define EXTI_IMR_MR20_Msk          (0x1UL << EXTI_IMR_MR20_Pos)                 /*!< 0x00100000 */
6627 #define EXTI_IMR_MR20              EXTI_IMR_MR20_Msk                           /*!< Interrupt Mask on line 20 */
6628 #define EXTI_IMR_MR22_Pos          (22U)
6629 #define EXTI_IMR_MR22_Msk          (0x1UL << EXTI_IMR_MR22_Pos)                 /*!< 0x00400000 */
6630 #define EXTI_IMR_MR22              EXTI_IMR_MR22_Msk                           /*!< Interrupt Mask on line 22 */
6631 #define EXTI_IMR_MR23_Pos          (23U)
6632 #define EXTI_IMR_MR23_Msk          (0x1UL << EXTI_IMR_MR23_Pos)                 /*!< 0x00800000 */
6633 #define EXTI_IMR_MR23              EXTI_IMR_MR23_Msk                           /*!< Interrupt Mask on line 23 */
6634 #define EXTI_IMR_MR25_Pos          (25U)
6635 #define EXTI_IMR_MR25_Msk          (0x1UL << EXTI_IMR_MR25_Pos)                 /*!< 0x02000000 */
6636 #define EXTI_IMR_MR25              EXTI_IMR_MR25_Msk                           /*!< Interrupt Mask on line 25 */
6637 #define EXTI_IMR_MR30_Pos          (30U)
6638 #define EXTI_IMR_MR30_Msk          (0x1UL << EXTI_IMR_MR30_Pos)                 /*!< 0x40000000 */
6639 #define EXTI_IMR_MR30              EXTI_IMR_MR30_Msk                           /*!< Interrupt Mask on line 30 */
6640 
6641 /* References Defines */
6642 #define  EXTI_IMR_IM0 EXTI_IMR_MR0
6643 #define  EXTI_IMR_IM1 EXTI_IMR_MR1
6644 #define  EXTI_IMR_IM2 EXTI_IMR_MR2
6645 #define  EXTI_IMR_IM3 EXTI_IMR_MR3
6646 #define  EXTI_IMR_IM4 EXTI_IMR_MR4
6647 #define  EXTI_IMR_IM5 EXTI_IMR_MR5
6648 #define  EXTI_IMR_IM6 EXTI_IMR_MR6
6649 #define  EXTI_IMR_IM7 EXTI_IMR_MR7
6650 #define  EXTI_IMR_IM8 EXTI_IMR_MR8
6651 #define  EXTI_IMR_IM9 EXTI_IMR_MR9
6652 #define  EXTI_IMR_IM10 EXTI_IMR_MR10
6653 #define  EXTI_IMR_IM11 EXTI_IMR_MR11
6654 #define  EXTI_IMR_IM12 EXTI_IMR_MR12
6655 #define  EXTI_IMR_IM13 EXTI_IMR_MR13
6656 #define  EXTI_IMR_IM14 EXTI_IMR_MR14
6657 #define  EXTI_IMR_IM15 EXTI_IMR_MR15
6658 #define  EXTI_IMR_IM16 EXTI_IMR_MR16
6659 #define  EXTI_IMR_IM17 EXTI_IMR_MR17
6660 #if defined(EXTI_IMR_MR18)
6661 #define  EXTI_IMR_IM18 EXTI_IMR_MR18
6662 #endif
6663 #define  EXTI_IMR_IM19 EXTI_IMR_MR19
6664 #define  EXTI_IMR_IM20 EXTI_IMR_MR20
6665 #if defined(EXTI_IMR_MR21)
6666 #define  EXTI_IMR_IM21 EXTI_IMR_MR21
6667 #endif
6668 #define  EXTI_IMR_IM22 EXTI_IMR_MR22
6669 #define  EXTI_IMR_IM23 EXTI_IMR_MR23
6670 #if defined(EXTI_IMR_MR24)
6671 #define  EXTI_IMR_IM24 EXTI_IMR_MR24
6672 #endif
6673 #define  EXTI_IMR_IM25 EXTI_IMR_MR25
6674 #if defined(EXTI_IMR_MR26)
6675 #define  EXTI_IMR_IM26 EXTI_IMR_MR26
6676 #endif
6677 #if defined(EXTI_IMR_MR27)
6678 #define  EXTI_IMR_IM27 EXTI_IMR_MR27
6679 #endif
6680 #if defined(EXTI_IMR_MR28)
6681 #define  EXTI_IMR_IM28 EXTI_IMR_MR28
6682 #endif
6683 #if defined(EXTI_IMR_MR29)
6684 #define  EXTI_IMR_IM29 EXTI_IMR_MR29
6685 #endif
6686 #if defined(EXTI_IMR_MR30)
6687 #define  EXTI_IMR_IM30 EXTI_IMR_MR30
6688 #endif
6689 #if defined(EXTI_IMR_MR31)
6690 #define  EXTI_IMR_IM31 EXTI_IMR_MR31
6691 #endif
6692 
6693 #define EXTI_IMR_IM_Pos            (0U)
6694 #define EXTI_IMR_IM_Msk            (0xFFFFFFFFUL << EXTI_IMR_IM_Pos)            /*!< 0xFFFFFFFF */
6695 #define EXTI_IMR_IM                EXTI_IMR_IM_Msk                             /*!< Interrupt Mask All */
6696 
6697 /*******************  Bit definition for EXTI_EMR register  *******************/
6698 #define EXTI_EMR_MR0_Pos           (0U)
6699 #define EXTI_EMR_MR0_Msk           (0x1UL << EXTI_EMR_MR0_Pos)                  /*!< 0x00000001 */
6700 #define EXTI_EMR_MR0               EXTI_EMR_MR0_Msk                            /*!< Event Mask on line 0 */
6701 #define EXTI_EMR_MR1_Pos           (1U)
6702 #define EXTI_EMR_MR1_Msk           (0x1UL << EXTI_EMR_MR1_Pos)                  /*!< 0x00000002 */
6703 #define EXTI_EMR_MR1               EXTI_EMR_MR1_Msk                            /*!< Event Mask on line 1 */
6704 #define EXTI_EMR_MR2_Pos           (2U)
6705 #define EXTI_EMR_MR2_Msk           (0x1UL << EXTI_EMR_MR2_Pos)                  /*!< 0x00000004 */
6706 #define EXTI_EMR_MR2               EXTI_EMR_MR2_Msk                            /*!< Event Mask on line 2 */
6707 #define EXTI_EMR_MR3_Pos           (3U)
6708 #define EXTI_EMR_MR3_Msk           (0x1UL << EXTI_EMR_MR3_Pos)                  /*!< 0x00000008 */
6709 #define EXTI_EMR_MR3               EXTI_EMR_MR3_Msk                            /*!< Event Mask on line 3 */
6710 #define EXTI_EMR_MR4_Pos           (4U)
6711 #define EXTI_EMR_MR4_Msk           (0x1UL << EXTI_EMR_MR4_Pos)                  /*!< 0x00000010 */
6712 #define EXTI_EMR_MR4               EXTI_EMR_MR4_Msk                            /*!< Event Mask on line 4 */
6713 #define EXTI_EMR_MR5_Pos           (5U)
6714 #define EXTI_EMR_MR5_Msk           (0x1UL << EXTI_EMR_MR5_Pos)                  /*!< 0x00000020 */
6715 #define EXTI_EMR_MR5               EXTI_EMR_MR5_Msk                            /*!< Event Mask on line 5 */
6716 #define EXTI_EMR_MR6_Pos           (6U)
6717 #define EXTI_EMR_MR6_Msk           (0x1UL << EXTI_EMR_MR6_Pos)                  /*!< 0x00000040 */
6718 #define EXTI_EMR_MR6               EXTI_EMR_MR6_Msk                            /*!< Event Mask on line 6 */
6719 #define EXTI_EMR_MR7_Pos           (7U)
6720 #define EXTI_EMR_MR7_Msk           (0x1UL << EXTI_EMR_MR7_Pos)                  /*!< 0x00000080 */
6721 #define EXTI_EMR_MR7               EXTI_EMR_MR7_Msk                            /*!< Event Mask on line 7 */
6722 #define EXTI_EMR_MR8_Pos           (8U)
6723 #define EXTI_EMR_MR8_Msk           (0x1UL << EXTI_EMR_MR8_Pos)                  /*!< 0x00000100 */
6724 #define EXTI_EMR_MR8               EXTI_EMR_MR8_Msk                            /*!< Event Mask on line 8 */
6725 #define EXTI_EMR_MR9_Pos           (9U)
6726 #define EXTI_EMR_MR9_Msk           (0x1UL << EXTI_EMR_MR9_Pos)                  /*!< 0x00000200 */
6727 #define EXTI_EMR_MR9               EXTI_EMR_MR9_Msk                            /*!< Event Mask on line 9 */
6728 #define EXTI_EMR_MR10_Pos          (10U)
6729 #define EXTI_EMR_MR10_Msk          (0x1UL << EXTI_EMR_MR10_Pos)                 /*!< 0x00000400 */
6730 #define EXTI_EMR_MR10              EXTI_EMR_MR10_Msk                           /*!< Event Mask on line 10 */
6731 #define EXTI_EMR_MR11_Pos          (11U)
6732 #define EXTI_EMR_MR11_Msk          (0x1UL << EXTI_EMR_MR11_Pos)                 /*!< 0x00000800 */
6733 #define EXTI_EMR_MR11              EXTI_EMR_MR11_Msk                           /*!< Event Mask on line 11 */
6734 #define EXTI_EMR_MR12_Pos          (12U)
6735 #define EXTI_EMR_MR12_Msk          (0x1UL << EXTI_EMR_MR12_Pos)                 /*!< 0x00001000 */
6736 #define EXTI_EMR_MR12              EXTI_EMR_MR12_Msk                           /*!< Event Mask on line 12 */
6737 #define EXTI_EMR_MR13_Pos          (13U)
6738 #define EXTI_EMR_MR13_Msk          (0x1UL << EXTI_EMR_MR13_Pos)                 /*!< 0x00002000 */
6739 #define EXTI_EMR_MR13              EXTI_EMR_MR13_Msk                           /*!< Event Mask on line 13 */
6740 #define EXTI_EMR_MR14_Pos          (14U)
6741 #define EXTI_EMR_MR14_Msk          (0x1UL << EXTI_EMR_MR14_Pos)                 /*!< 0x00004000 */
6742 #define EXTI_EMR_MR14              EXTI_EMR_MR14_Msk                           /*!< Event Mask on line 14 */
6743 #define EXTI_EMR_MR15_Pos          (15U)
6744 #define EXTI_EMR_MR15_Msk          (0x1UL << EXTI_EMR_MR15_Pos)                 /*!< 0x00008000 */
6745 #define EXTI_EMR_MR15              EXTI_EMR_MR15_Msk                           /*!< Event Mask on line 15 */
6746 #define EXTI_EMR_MR16_Pos          (16U)
6747 #define EXTI_EMR_MR16_Msk          (0x1UL << EXTI_EMR_MR16_Pos)                 /*!< 0x00010000 */
6748 #define EXTI_EMR_MR16              EXTI_EMR_MR16_Msk                           /*!< Event Mask on line 16 */
6749 #define EXTI_EMR_MR17_Pos          (17U)
6750 #define EXTI_EMR_MR17_Msk          (0x1UL << EXTI_EMR_MR17_Pos)                 /*!< 0x00020000 */
6751 #define EXTI_EMR_MR17              EXTI_EMR_MR17_Msk                           /*!< Event Mask on line 17 */
6752 #define EXTI_EMR_MR19_Pos          (19U)
6753 #define EXTI_EMR_MR19_Msk          (0x1UL << EXTI_EMR_MR19_Pos)                 /*!< 0x00080000 */
6754 #define EXTI_EMR_MR19              EXTI_EMR_MR19_Msk                           /*!< Event Mask on line 19 */
6755 #define EXTI_EMR_MR20_Pos          (20U)
6756 #define EXTI_EMR_MR20_Msk          (0x1UL << EXTI_EMR_MR20_Pos)                 /*!< 0x00100000 */
6757 #define EXTI_EMR_MR20              EXTI_EMR_MR20_Msk                           /*!< Event Mask on line 20 */
6758 #define EXTI_EMR_MR22_Pos          (22U)
6759 #define EXTI_EMR_MR22_Msk          (0x1UL << EXTI_EMR_MR22_Pos)                 /*!< 0x00400000 */
6760 #define EXTI_EMR_MR22              EXTI_EMR_MR22_Msk                           /*!< Event Mask on line 22 */
6761 #define EXTI_EMR_MR23_Pos          (23U)
6762 #define EXTI_EMR_MR23_Msk          (0x1UL << EXTI_EMR_MR23_Pos)                 /*!< 0x00800000 */
6763 #define EXTI_EMR_MR23              EXTI_EMR_MR23_Msk                           /*!< Event Mask on line 23 */
6764 #define EXTI_EMR_MR25_Pos          (25U)
6765 #define EXTI_EMR_MR25_Msk          (0x1UL << EXTI_EMR_MR25_Pos)                 /*!< 0x02000000 */
6766 #define EXTI_EMR_MR25              EXTI_EMR_MR25_Msk                           /*!< Event Mask on line 25 */
6767 #define EXTI_EMR_MR30_Pos          (30U)
6768 #define EXTI_EMR_MR30_Msk          (0x1UL << EXTI_EMR_MR30_Pos)                 /*!< 0x40000000 */
6769 #define EXTI_EMR_MR30              EXTI_EMR_MR30_Msk                           /*!< Event Mask on line 30 */
6770 
6771 /* References Defines */
6772 #define  EXTI_EMR_EM0 EXTI_EMR_MR0
6773 #define  EXTI_EMR_EM1 EXTI_EMR_MR1
6774 #define  EXTI_EMR_EM2 EXTI_EMR_MR2
6775 #define  EXTI_EMR_EM3 EXTI_EMR_MR3
6776 #define  EXTI_EMR_EM4 EXTI_EMR_MR4
6777 #define  EXTI_EMR_EM5 EXTI_EMR_MR5
6778 #define  EXTI_EMR_EM6 EXTI_EMR_MR6
6779 #define  EXTI_EMR_EM7 EXTI_EMR_MR7
6780 #define  EXTI_EMR_EM8 EXTI_EMR_MR8
6781 #define  EXTI_EMR_EM9 EXTI_EMR_MR9
6782 #define  EXTI_EMR_EM10 EXTI_EMR_MR10
6783 #define  EXTI_EMR_EM11 EXTI_EMR_MR11
6784 #define  EXTI_EMR_EM12 EXTI_EMR_MR12
6785 #define  EXTI_EMR_EM13 EXTI_EMR_MR13
6786 #define  EXTI_EMR_EM14 EXTI_EMR_MR14
6787 #define  EXTI_EMR_EM15 EXTI_EMR_MR15
6788 #define  EXTI_EMR_EM16 EXTI_EMR_MR16
6789 #define  EXTI_EMR_EM17 EXTI_EMR_MR17
6790 #if defined(EXTI_EMR_MR18)
6791 #define  EXTI_EMR_EM18 EXTI_EMR_MR18
6792 #endif
6793 #define  EXTI_EMR_EM19 EXTI_EMR_MR19
6794 #define  EXTI_EMR_EM20 EXTI_EMR_MR20
6795 #if defined(EXTI_EMR_MR21)
6796 #define  EXTI_EMR_EM21 EXTI_EMR_MR21
6797 #endif
6798 #define  EXTI_EMR_EM22 EXTI_EMR_MR22
6799 #define  EXTI_EMR_EM23 EXTI_EMR_MR23
6800 #if defined(EXTI_EMR_MR24)
6801 #define  EXTI_EMR_EM24 EXTI_EMR_MR24
6802 #endif
6803 #define  EXTI_EMR_EM25 EXTI_EMR_MR25
6804 #if defined(EXTI_EMR_MR26)
6805 #define  EXTI_EMR_EM26 EXTI_EMR_MR26
6806 #endif
6807 #if defined(EXTI_EMR_MR27)
6808 #define  EXTI_EMR_EM27 EXTI_EMR_MR27
6809 #endif
6810 #if defined(EXTI_EMR_MR28)
6811 #define  EXTI_EMR_EM28 EXTI_EMR_MR28
6812 #endif
6813 #if defined(EXTI_EMR_MR29)
6814 #define  EXTI_EMR_EM29 EXTI_EMR_MR29
6815 #endif
6816 #if defined(EXTI_EMR_MR30)
6817 #define  EXTI_EMR_EM30 EXTI_EMR_MR30
6818 #endif
6819 #if defined(EXTI_EMR_MR31)
6820 #define  EXTI_EMR_EM31 EXTI_EMR_MR31
6821 #endif
6822 
6823 /******************  Bit definition for EXTI_RTSR register  *******************/
6824 #define EXTI_RTSR_TR0_Pos          (0U)
6825 #define EXTI_RTSR_TR0_Msk          (0x1UL << EXTI_RTSR_TR0_Pos)                 /*!< 0x00000001 */
6826 #define EXTI_RTSR_TR0              EXTI_RTSR_TR0_Msk                           /*!< Rising trigger event configuration bit of line 0 */
6827 #define EXTI_RTSR_TR1_Pos          (1U)
6828 #define EXTI_RTSR_TR1_Msk          (0x1UL << EXTI_RTSR_TR1_Pos)                 /*!< 0x00000002 */
6829 #define EXTI_RTSR_TR1              EXTI_RTSR_TR1_Msk                           /*!< Rising trigger event configuration bit of line 1 */
6830 #define EXTI_RTSR_TR2_Pos          (2U)
6831 #define EXTI_RTSR_TR2_Msk          (0x1UL << EXTI_RTSR_TR2_Pos)                 /*!< 0x00000004 */
6832 #define EXTI_RTSR_TR2              EXTI_RTSR_TR2_Msk                           /*!< Rising trigger event configuration bit of line 2 */
6833 #define EXTI_RTSR_TR3_Pos          (3U)
6834 #define EXTI_RTSR_TR3_Msk          (0x1UL << EXTI_RTSR_TR3_Pos)                 /*!< 0x00000008 */
6835 #define EXTI_RTSR_TR3              EXTI_RTSR_TR3_Msk                           /*!< Rising trigger event configuration bit of line 3 */
6836 #define EXTI_RTSR_TR4_Pos          (4U)
6837 #define EXTI_RTSR_TR4_Msk          (0x1UL << EXTI_RTSR_TR4_Pos)                 /*!< 0x00000010 */
6838 #define EXTI_RTSR_TR4              EXTI_RTSR_TR4_Msk                           /*!< Rising trigger event configuration bit of line 4 */
6839 #define EXTI_RTSR_TR5_Pos          (5U)
6840 #define EXTI_RTSR_TR5_Msk          (0x1UL << EXTI_RTSR_TR5_Pos)                 /*!< 0x00000020 */
6841 #define EXTI_RTSR_TR5              EXTI_RTSR_TR5_Msk                           /*!< Rising trigger event configuration bit of line 5 */
6842 #define EXTI_RTSR_TR6_Pos          (6U)
6843 #define EXTI_RTSR_TR6_Msk          (0x1UL << EXTI_RTSR_TR6_Pos)                 /*!< 0x00000040 */
6844 #define EXTI_RTSR_TR6              EXTI_RTSR_TR6_Msk                           /*!< Rising trigger event configuration bit of line 6 */
6845 #define EXTI_RTSR_TR7_Pos          (7U)
6846 #define EXTI_RTSR_TR7_Msk          (0x1UL << EXTI_RTSR_TR7_Pos)                 /*!< 0x00000080 */
6847 #define EXTI_RTSR_TR7              EXTI_RTSR_TR7_Msk                           /*!< Rising trigger event configuration bit of line 7 */
6848 #define EXTI_RTSR_TR8_Pos          (8U)
6849 #define EXTI_RTSR_TR8_Msk          (0x1UL << EXTI_RTSR_TR8_Pos)                 /*!< 0x00000100 */
6850 #define EXTI_RTSR_TR8              EXTI_RTSR_TR8_Msk                           /*!< Rising trigger event configuration bit of line 8 */
6851 #define EXTI_RTSR_TR9_Pos          (9U)
6852 #define EXTI_RTSR_TR9_Msk          (0x1UL << EXTI_RTSR_TR9_Pos)                 /*!< 0x00000200 */
6853 #define EXTI_RTSR_TR9              EXTI_RTSR_TR9_Msk                           /*!< Rising trigger event configuration bit of line 9 */
6854 #define EXTI_RTSR_TR10_Pos         (10U)
6855 #define EXTI_RTSR_TR10_Msk         (0x1UL << EXTI_RTSR_TR10_Pos)                /*!< 0x00000400 */
6856 #define EXTI_RTSR_TR10             EXTI_RTSR_TR10_Msk                          /*!< Rising trigger event configuration bit of line 10 */
6857 #define EXTI_RTSR_TR11_Pos         (11U)
6858 #define EXTI_RTSR_TR11_Msk         (0x1UL << EXTI_RTSR_TR11_Pos)                /*!< 0x00000800 */
6859 #define EXTI_RTSR_TR11             EXTI_RTSR_TR11_Msk                          /*!< Rising trigger event configuration bit of line 11 */
6860 #define EXTI_RTSR_TR12_Pos         (12U)
6861 #define EXTI_RTSR_TR12_Msk         (0x1UL << EXTI_RTSR_TR12_Pos)                /*!< 0x00001000 */
6862 #define EXTI_RTSR_TR12             EXTI_RTSR_TR12_Msk                          /*!< Rising trigger event configuration bit of line 12 */
6863 #define EXTI_RTSR_TR13_Pos         (13U)
6864 #define EXTI_RTSR_TR13_Msk         (0x1UL << EXTI_RTSR_TR13_Pos)                /*!< 0x00002000 */
6865 #define EXTI_RTSR_TR13             EXTI_RTSR_TR13_Msk                          /*!< Rising trigger event configuration bit of line 13 */
6866 #define EXTI_RTSR_TR14_Pos         (14U)
6867 #define EXTI_RTSR_TR14_Msk         (0x1UL << EXTI_RTSR_TR14_Pos)                /*!< 0x00004000 */
6868 #define EXTI_RTSR_TR14             EXTI_RTSR_TR14_Msk                          /*!< Rising trigger event configuration bit of line 14 */
6869 #define EXTI_RTSR_TR15_Pos         (15U)
6870 #define EXTI_RTSR_TR15_Msk         (0x1UL << EXTI_RTSR_TR15_Pos)                /*!< 0x00008000 */
6871 #define EXTI_RTSR_TR15             EXTI_RTSR_TR15_Msk                          /*!< Rising trigger event configuration bit of line 15 */
6872 #define EXTI_RTSR_TR16_Pos         (16U)
6873 #define EXTI_RTSR_TR16_Msk         (0x1UL << EXTI_RTSR_TR16_Pos)                /*!< 0x00010000 */
6874 #define EXTI_RTSR_TR16             EXTI_RTSR_TR16_Msk                          /*!< Rising trigger event configuration bit of line 16 */
6875 #define EXTI_RTSR_TR17_Pos         (17U)
6876 #define EXTI_RTSR_TR17_Msk         (0x1UL << EXTI_RTSR_TR17_Pos)                /*!< 0x00020000 */
6877 #define EXTI_RTSR_TR17             EXTI_RTSR_TR17_Msk                          /*!< Rising trigger event configuration bit of line 17 */
6878 #define EXTI_RTSR_TR19_Pos         (19U)
6879 #define EXTI_RTSR_TR19_Msk         (0x1UL << EXTI_RTSR_TR19_Pos)                /*!< 0x00080000 */
6880 #define EXTI_RTSR_TR19             EXTI_RTSR_TR19_Msk                          /*!< Rising trigger event configuration bit of line 19 */
6881 #define EXTI_RTSR_TR20_Pos         (20U)
6882 #define EXTI_RTSR_TR20_Msk         (0x1UL << EXTI_RTSR_TR20_Pos)                /*!< 0x00100000 */
6883 #define EXTI_RTSR_TR20             EXTI_RTSR_TR20_Msk                          /*!< Rising trigger event configuration bit of line 20 */
6884 #define EXTI_RTSR_TR22_Pos         (22U)
6885 #define EXTI_RTSR_TR22_Msk         (0x1UL << EXTI_RTSR_TR22_Pos)                /*!< 0x00400000 */
6886 #define EXTI_RTSR_TR22             EXTI_RTSR_TR22_Msk                          /*!< Rising trigger event configuration bit of line 22 */
6887 #define EXTI_RTSR_TR30_Pos         (30U)
6888 #define EXTI_RTSR_TR30_Msk         (0x1UL << EXTI_RTSR_TR30_Pos)                /*!< 0x40000000 */
6889 #define EXTI_RTSR_TR30             EXTI_RTSR_TR30_Msk                          /*!< Rising trigger event configuration bit of line 30 */
6890 
6891 /* References Defines */
6892 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
6893 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
6894 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
6895 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
6896 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
6897 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
6898 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
6899 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
6900 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
6901 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
6902 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
6903 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
6904 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
6905 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
6906 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
6907 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
6908 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
6909 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
6910 #if defined(EXTI_RTSR_TR18)
6911 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
6912 #endif
6913 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
6914 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20
6915 #if defined(EXTI_RTSR_TR21)
6916 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
6917 #endif
6918 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
6919 #if defined(EXTI_RTSR_TR23)
6920 #define EXTI_RTSR_RT23 EXTI_RTSR_TR23
6921 #endif
6922 #if defined(EXTI_RTSR_TR24)
6923 #define EXTI_RTSR_RT24 EXTI_RTSR_TR24
6924 #endif
6925 #if defined(EXTI_RTSR_TR25)
6926 #define EXTI_RTSR_RT25 EXTI_RTSR_TR25
6927 #endif
6928 #if defined(EXTI_RTSR_TR26)
6929 #define EXTI_RTSR_RT26 EXTI_RTSR_TR26
6930 #endif
6931 #if defined(EXTI_RTSR_TR27)
6932 #define EXTI_RTSR_RT27 EXTI_RTSR_TR27
6933 #endif
6934 #if defined(EXTI_RTSR_TR28)
6935 #define EXTI_RTSR_RT28 EXTI_RTSR_TR28
6936 #endif
6937 #if defined(EXTI_RTSR_TR29)
6938 #define EXTI_RTSR_RT29 EXTI_RTSR_TR29
6939 #endif
6940 #if defined(EXTI_RTSR_TR30)
6941 #define EXTI_RTSR_RT30 EXTI_RTSR_TR30
6942 #endif
6943 #if defined(EXTI_RTSR_TR31)
6944 #define EXTI_RTSR_RT31 EXTI_RTSR_TR31
6945 #endif
6946 
6947 /******************  Bit definition for EXTI_FTSR register  *******************/
6948 #define EXTI_FTSR_TR0_Pos          (0U)
6949 #define EXTI_FTSR_TR0_Msk          (0x1UL << EXTI_FTSR_TR0_Pos)                 /*!< 0x00000001 */
6950 #define EXTI_FTSR_TR0              EXTI_FTSR_TR0_Msk                           /*!< Falling trigger event configuration bit of line 0 */
6951 #define EXTI_FTSR_TR1_Pos          (1U)
6952 #define EXTI_FTSR_TR1_Msk          (0x1UL << EXTI_FTSR_TR1_Pos)                 /*!< 0x00000002 */
6953 #define EXTI_FTSR_TR1              EXTI_FTSR_TR1_Msk                           /*!< Falling trigger event configuration bit of line 1 */
6954 #define EXTI_FTSR_TR2_Pos          (2U)
6955 #define EXTI_FTSR_TR2_Msk          (0x1UL << EXTI_FTSR_TR2_Pos)                 /*!< 0x00000004 */
6956 #define EXTI_FTSR_TR2              EXTI_FTSR_TR2_Msk                           /*!< Falling trigger event configuration bit of line 2 */
6957 #define EXTI_FTSR_TR3_Pos          (3U)
6958 #define EXTI_FTSR_TR3_Msk          (0x1UL << EXTI_FTSR_TR3_Pos)                 /*!< 0x00000008 */
6959 #define EXTI_FTSR_TR3              EXTI_FTSR_TR3_Msk                           /*!< Falling trigger event configuration bit of line 3 */
6960 #define EXTI_FTSR_TR4_Pos          (4U)
6961 #define EXTI_FTSR_TR4_Msk          (0x1UL << EXTI_FTSR_TR4_Pos)                 /*!< 0x00000010 */
6962 #define EXTI_FTSR_TR4              EXTI_FTSR_TR4_Msk                           /*!< Falling trigger event configuration bit of line 4 */
6963 #define EXTI_FTSR_TR5_Pos          (5U)
6964 #define EXTI_FTSR_TR5_Msk          (0x1UL << EXTI_FTSR_TR5_Pos)                 /*!< 0x00000020 */
6965 #define EXTI_FTSR_TR5              EXTI_FTSR_TR5_Msk                           /*!< Falling trigger event configuration bit of line 5 */
6966 #define EXTI_FTSR_TR6_Pos          (6U)
6967 #define EXTI_FTSR_TR6_Msk          (0x1UL << EXTI_FTSR_TR6_Pos)                 /*!< 0x00000040 */
6968 #define EXTI_FTSR_TR6              EXTI_FTSR_TR6_Msk                           /*!< Falling trigger event configuration bit of line 6 */
6969 #define EXTI_FTSR_TR7_Pos          (7U)
6970 #define EXTI_FTSR_TR7_Msk          (0x1UL << EXTI_FTSR_TR7_Pos)                 /*!< 0x00000080 */
6971 #define EXTI_FTSR_TR7              EXTI_FTSR_TR7_Msk                           /*!< Falling trigger event configuration bit of line 7 */
6972 #define EXTI_FTSR_TR8_Pos          (8U)
6973 #define EXTI_FTSR_TR8_Msk          (0x1UL << EXTI_FTSR_TR8_Pos)                 /*!< 0x00000100 */
6974 #define EXTI_FTSR_TR8              EXTI_FTSR_TR8_Msk                           /*!< Falling trigger event configuration bit of line 8 */
6975 #define EXTI_FTSR_TR9_Pos          (9U)
6976 #define EXTI_FTSR_TR9_Msk          (0x1UL << EXTI_FTSR_TR9_Pos)                 /*!< 0x00000200 */
6977 #define EXTI_FTSR_TR9              EXTI_FTSR_TR9_Msk                           /*!< Falling trigger event configuration bit of line 9 */
6978 #define EXTI_FTSR_TR10_Pos         (10U)
6979 #define EXTI_FTSR_TR10_Msk         (0x1UL << EXTI_FTSR_TR10_Pos)                /*!< 0x00000400 */
6980 #define EXTI_FTSR_TR10             EXTI_FTSR_TR10_Msk                          /*!< Falling trigger event configuration bit of line 10 */
6981 #define EXTI_FTSR_TR11_Pos         (11U)
6982 #define EXTI_FTSR_TR11_Msk         (0x1UL << EXTI_FTSR_TR11_Pos)                /*!< 0x00000800 */
6983 #define EXTI_FTSR_TR11             EXTI_FTSR_TR11_Msk                          /*!< Falling trigger event configuration bit of line 11 */
6984 #define EXTI_FTSR_TR12_Pos         (12U)
6985 #define EXTI_FTSR_TR12_Msk         (0x1UL << EXTI_FTSR_TR12_Pos)                /*!< 0x00001000 */
6986 #define EXTI_FTSR_TR12             EXTI_FTSR_TR12_Msk                          /*!< Falling trigger event configuration bit of line 12 */
6987 #define EXTI_FTSR_TR13_Pos         (13U)
6988 #define EXTI_FTSR_TR13_Msk         (0x1UL << EXTI_FTSR_TR13_Pos)                /*!< 0x00002000 */
6989 #define EXTI_FTSR_TR13             EXTI_FTSR_TR13_Msk                          /*!< Falling trigger event configuration bit of line 13 */
6990 #define EXTI_FTSR_TR14_Pos         (14U)
6991 #define EXTI_FTSR_TR14_Msk         (0x1UL << EXTI_FTSR_TR14_Pos)                /*!< 0x00004000 */
6992 #define EXTI_FTSR_TR14             EXTI_FTSR_TR14_Msk                          /*!< Falling trigger event configuration bit of line 14 */
6993 #define EXTI_FTSR_TR15_Pos         (15U)
6994 #define EXTI_FTSR_TR15_Msk         (0x1UL << EXTI_FTSR_TR15_Pos)                /*!< 0x00008000 */
6995 #define EXTI_FTSR_TR15             EXTI_FTSR_TR15_Msk                          /*!< Falling trigger event configuration bit of line 15 */
6996 #define EXTI_FTSR_TR16_Pos         (16U)
6997 #define EXTI_FTSR_TR16_Msk         (0x1UL << EXTI_FTSR_TR16_Pos)                /*!< 0x00010000 */
6998 #define EXTI_FTSR_TR16             EXTI_FTSR_TR16_Msk                          /*!< Falling trigger event configuration bit of line 16 */
6999 #define EXTI_FTSR_TR17_Pos         (17U)
7000 #define EXTI_FTSR_TR17_Msk         (0x1UL << EXTI_FTSR_TR17_Pos)                /*!< 0x00020000 */
7001 #define EXTI_FTSR_TR17             EXTI_FTSR_TR17_Msk                          /*!< Falling trigger event configuration bit of line 17 */
7002 #define EXTI_FTSR_TR19_Pos         (19U)
7003 #define EXTI_FTSR_TR19_Msk         (0x1UL << EXTI_FTSR_TR19_Pos)                /*!< 0x00080000 */
7004 #define EXTI_FTSR_TR19             EXTI_FTSR_TR19_Msk                          /*!< Falling trigger event configuration bit of line 19 */
7005 #define EXTI_FTSR_TR20_Pos         (20U)
7006 #define EXTI_FTSR_TR20_Msk         (0x1UL << EXTI_FTSR_TR20_Pos)                /*!< 0x00100000 */
7007 #define EXTI_FTSR_TR20             EXTI_FTSR_TR20_Msk                          /*!< Falling trigger event configuration bit of line 20 */
7008 #define EXTI_FTSR_TR22_Pos         (22U)
7009 #define EXTI_FTSR_TR22_Msk         (0x1UL << EXTI_FTSR_TR22_Pos)                /*!< 0x00400000 */
7010 #define EXTI_FTSR_TR22             EXTI_FTSR_TR22_Msk                          /*!< Falling trigger event configuration bit of line 22 */
7011 #define EXTI_FTSR_TR30_Pos         (30U)
7012 #define EXTI_FTSR_TR30_Msk         (0x1UL << EXTI_FTSR_TR30_Pos)                /*!< 0x40000000 */
7013 #define EXTI_FTSR_TR30             EXTI_FTSR_TR30_Msk                          /*!< Falling trigger event configuration bit of line 30 */
7014 
7015 /* References Defines */
7016 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
7017 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
7018 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
7019 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
7020 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
7021 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
7022 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
7023 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
7024 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
7025 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
7026 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
7027 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
7028 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
7029 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
7030 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
7031 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
7032 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
7033 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
7034 #if defined(EXTI_FTSR_TR18)
7035 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
7036 #endif
7037 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
7038 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20
7039 #if defined(EXTI_FTSR_TR21)
7040 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
7041 #endif
7042 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
7043 #if defined(EXTI_FTSR_TR23)
7044 #define EXTI_FTSR_FT23 EXTI_FTSR_TR23
7045 #endif
7046 #if defined(EXTI_FTSR_TR24)
7047 #define EXTI_FTSR_FT24 EXTI_FTSR_TR24
7048 #endif
7049 #if defined(EXTI_FTSR_TR25)
7050 #define EXTI_FTSR_FT25 EXTI_FTSR_TR25
7051 #endif
7052 #if defined(EXTI_FTSR_TR26)
7053 #define EXTI_FTSR_FT26 EXTI_FTSR_TR26
7054 #endif
7055 #if defined(EXTI_FTSR_TR27)
7056 #define EXTI_FTSR_FT27 EXTI_FTSR_TR27
7057 #endif
7058 #if defined(EXTI_FTSR_TR28)
7059 #define EXTI_FTSR_FT28 EXTI_FTSR_TR28
7060 #endif
7061 #if defined(EXTI_FTSR_TR29)
7062 #define EXTI_FTSR_FT29 EXTI_FTSR_TR29
7063 #endif
7064 #if defined(EXTI_FTSR_TR30)
7065 #define EXTI_FTSR_FT30 EXTI_FTSR_TR30
7066 #endif
7067 #if defined(EXTI_FTSR_TR31)
7068 #define EXTI_FTSR_FT31 EXTI_FTSR_TR31
7069 #endif
7070 
7071 /******************  Bit definition for EXTI_SWIER register  ******************/
7072 #define EXTI_SWIER_SWIER0_Pos      (0U)
7073 #define EXTI_SWIER_SWIER0_Msk      (0x1UL << EXTI_SWIER_SWIER0_Pos)             /*!< 0x00000001 */
7074 #define EXTI_SWIER_SWIER0          EXTI_SWIER_SWIER0_Msk                       /*!< Software Interrupt on line 0 */
7075 #define EXTI_SWIER_SWIER1_Pos      (1U)
7076 #define EXTI_SWIER_SWIER1_Msk      (0x1UL << EXTI_SWIER_SWIER1_Pos)             /*!< 0x00000002 */
7077 #define EXTI_SWIER_SWIER1          EXTI_SWIER_SWIER1_Msk                       /*!< Software Interrupt on line 1 */
7078 #define EXTI_SWIER_SWIER2_Pos      (2U)
7079 #define EXTI_SWIER_SWIER2_Msk      (0x1UL << EXTI_SWIER_SWIER2_Pos)             /*!< 0x00000004 */
7080 #define EXTI_SWIER_SWIER2          EXTI_SWIER_SWIER2_Msk                       /*!< Software Interrupt on line 2 */
7081 #define EXTI_SWIER_SWIER3_Pos      (3U)
7082 #define EXTI_SWIER_SWIER3_Msk      (0x1UL << EXTI_SWIER_SWIER3_Pos)             /*!< 0x00000008 */
7083 #define EXTI_SWIER_SWIER3          EXTI_SWIER_SWIER3_Msk                       /*!< Software Interrupt on line 3 */
7084 #define EXTI_SWIER_SWIER4_Pos      (4U)
7085 #define EXTI_SWIER_SWIER4_Msk      (0x1UL << EXTI_SWIER_SWIER4_Pos)             /*!< 0x00000010 */
7086 #define EXTI_SWIER_SWIER4          EXTI_SWIER_SWIER4_Msk                       /*!< Software Interrupt on line 4 */
7087 #define EXTI_SWIER_SWIER5_Pos      (5U)
7088 #define EXTI_SWIER_SWIER5_Msk      (0x1UL << EXTI_SWIER_SWIER5_Pos)             /*!< 0x00000020 */
7089 #define EXTI_SWIER_SWIER5          EXTI_SWIER_SWIER5_Msk                       /*!< Software Interrupt on line 5 */
7090 #define EXTI_SWIER_SWIER6_Pos      (6U)
7091 #define EXTI_SWIER_SWIER6_Msk      (0x1UL << EXTI_SWIER_SWIER6_Pos)             /*!< 0x00000040 */
7092 #define EXTI_SWIER_SWIER6          EXTI_SWIER_SWIER6_Msk                       /*!< Software Interrupt on line 6 */
7093 #define EXTI_SWIER_SWIER7_Pos      (7U)
7094 #define EXTI_SWIER_SWIER7_Msk      (0x1UL << EXTI_SWIER_SWIER7_Pos)             /*!< 0x00000080 */
7095 #define EXTI_SWIER_SWIER7          EXTI_SWIER_SWIER7_Msk                       /*!< Software Interrupt on line 7 */
7096 #define EXTI_SWIER_SWIER8_Pos      (8U)
7097 #define EXTI_SWIER_SWIER8_Msk      (0x1UL << EXTI_SWIER_SWIER8_Pos)             /*!< 0x00000100 */
7098 #define EXTI_SWIER_SWIER8          EXTI_SWIER_SWIER8_Msk                       /*!< Software Interrupt on line 8 */
7099 #define EXTI_SWIER_SWIER9_Pos      (9U)
7100 #define EXTI_SWIER_SWIER9_Msk      (0x1UL << EXTI_SWIER_SWIER9_Pos)             /*!< 0x00000200 */
7101 #define EXTI_SWIER_SWIER9          EXTI_SWIER_SWIER9_Msk                       /*!< Software Interrupt on line 9 */
7102 #define EXTI_SWIER_SWIER10_Pos     (10U)
7103 #define EXTI_SWIER_SWIER10_Msk     (0x1UL << EXTI_SWIER_SWIER10_Pos)            /*!< 0x00000400 */
7104 #define EXTI_SWIER_SWIER10         EXTI_SWIER_SWIER10_Msk                      /*!< Software Interrupt on line 10 */
7105 #define EXTI_SWIER_SWIER11_Pos     (11U)
7106 #define EXTI_SWIER_SWIER11_Msk     (0x1UL << EXTI_SWIER_SWIER11_Pos)            /*!< 0x00000800 */
7107 #define EXTI_SWIER_SWIER11         EXTI_SWIER_SWIER11_Msk                      /*!< Software Interrupt on line 11 */
7108 #define EXTI_SWIER_SWIER12_Pos     (12U)
7109 #define EXTI_SWIER_SWIER12_Msk     (0x1UL << EXTI_SWIER_SWIER12_Pos)            /*!< 0x00001000 */
7110 #define EXTI_SWIER_SWIER12         EXTI_SWIER_SWIER12_Msk                      /*!< Software Interrupt on line 12 */
7111 #define EXTI_SWIER_SWIER13_Pos     (13U)
7112 #define EXTI_SWIER_SWIER13_Msk     (0x1UL << EXTI_SWIER_SWIER13_Pos)            /*!< 0x00002000 */
7113 #define EXTI_SWIER_SWIER13         EXTI_SWIER_SWIER13_Msk                      /*!< Software Interrupt on line 13 */
7114 #define EXTI_SWIER_SWIER14_Pos     (14U)
7115 #define EXTI_SWIER_SWIER14_Msk     (0x1UL << EXTI_SWIER_SWIER14_Pos)            /*!< 0x00004000 */
7116 #define EXTI_SWIER_SWIER14         EXTI_SWIER_SWIER14_Msk                      /*!< Software Interrupt on line 14 */
7117 #define EXTI_SWIER_SWIER15_Pos     (15U)
7118 #define EXTI_SWIER_SWIER15_Msk     (0x1UL << EXTI_SWIER_SWIER15_Pos)            /*!< 0x00008000 */
7119 #define EXTI_SWIER_SWIER15         EXTI_SWIER_SWIER15_Msk                      /*!< Software Interrupt on line 15 */
7120 #define EXTI_SWIER_SWIER16_Pos     (16U)
7121 #define EXTI_SWIER_SWIER16_Msk     (0x1UL << EXTI_SWIER_SWIER16_Pos)            /*!< 0x00010000 */
7122 #define EXTI_SWIER_SWIER16         EXTI_SWIER_SWIER16_Msk                      /*!< Software Interrupt on line 16 */
7123 #define EXTI_SWIER_SWIER17_Pos     (17U)
7124 #define EXTI_SWIER_SWIER17_Msk     (0x1UL << EXTI_SWIER_SWIER17_Pos)            /*!< 0x00020000 */
7125 #define EXTI_SWIER_SWIER17         EXTI_SWIER_SWIER17_Msk                      /*!< Software Interrupt on line 17 */
7126 #define EXTI_SWIER_SWIER19_Pos     (19U)
7127 #define EXTI_SWIER_SWIER19_Msk     (0x1UL << EXTI_SWIER_SWIER19_Pos)            /*!< 0x00080000 */
7128 #define EXTI_SWIER_SWIER19         EXTI_SWIER_SWIER19_Msk                      /*!< Software Interrupt on line 19 */
7129 #define EXTI_SWIER_SWIER20_Pos     (20U)
7130 #define EXTI_SWIER_SWIER20_Msk     (0x1UL << EXTI_SWIER_SWIER20_Pos)            /*!< 0x00100000 */
7131 #define EXTI_SWIER_SWIER20         EXTI_SWIER_SWIER20_Msk                      /*!< Software Interrupt on line 20 */
7132 #define EXTI_SWIER_SWIER22_Pos     (22U)
7133 #define EXTI_SWIER_SWIER22_Msk     (0x1UL << EXTI_SWIER_SWIER22_Pos)            /*!< 0x00400000 */
7134 #define EXTI_SWIER_SWIER22         EXTI_SWIER_SWIER22_Msk                      /*!< Software Interrupt on line 22 */
7135 #define EXTI_SWIER_SWIER30_Pos     (30U)
7136 #define EXTI_SWIER_SWIER30_Msk     (0x1UL << EXTI_SWIER_SWIER30_Pos)            /*!< 0x40000000 */
7137 #define EXTI_SWIER_SWIER30         EXTI_SWIER_SWIER30_Msk                      /*!< Software Interrupt on line 30 */
7138 
7139 /* References Defines */
7140 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
7141 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
7142 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
7143 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
7144 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
7145 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
7146 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
7147 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
7148 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
7149 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
7150 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
7151 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
7152 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
7153 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
7154 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
7155 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
7156 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
7157 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
7158 #if defined(EXTI_SWIER_SWIER18)
7159 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
7160 #endif
7161 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
7162 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
7163 #if defined(EXTI_SWIER_SWIER21)
7164 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
7165 #endif
7166 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
7167 #if defined(EXTI_SWIER_SWIER23)
7168 #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
7169 #endif
7170 #if defined(EXTI_SWIER_SWIER24)
7171 #define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
7172 #endif
7173 #if defined(EXTI_SWIER_SWIER25)
7174 #define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
7175 #endif
7176 #if defined(EXTI_SWIER_SWIER26)
7177 #define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
7178 #endif
7179 #if defined(EXTI_SWIER_SWIER27)
7180 #define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
7181 #endif
7182 #if defined(EXTI_SWIER_SWIER28)
7183 #define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
7184 #endif
7185 #if defined(EXTI_SWIER_SWIER29)
7186 #define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
7187 #endif
7188 #if defined(EXTI_SWIER_SWIER30)
7189 #define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
7190 #endif
7191 #if defined(EXTI_SWIER_SWIER31)
7192 #define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
7193 #endif
7194 
7195 /*******************  Bit definition for EXTI_PR register  ********************/
7196 #define EXTI_PR_PR0_Pos            (0U)
7197 #define EXTI_PR_PR0_Msk            (0x1UL << EXTI_PR_PR0_Pos)                   /*!< 0x00000001 */
7198 #define EXTI_PR_PR0                EXTI_PR_PR0_Msk                             /*!< Pending bit for line 0 */
7199 #define EXTI_PR_PR1_Pos            (1U)
7200 #define EXTI_PR_PR1_Msk            (0x1UL << EXTI_PR_PR1_Pos)                   /*!< 0x00000002 */
7201 #define EXTI_PR_PR1                EXTI_PR_PR1_Msk                             /*!< Pending bit for line 1 */
7202 #define EXTI_PR_PR2_Pos            (2U)
7203 #define EXTI_PR_PR2_Msk            (0x1UL << EXTI_PR_PR2_Pos)                   /*!< 0x00000004 */
7204 #define EXTI_PR_PR2                EXTI_PR_PR2_Msk                             /*!< Pending bit for line 2 */
7205 #define EXTI_PR_PR3_Pos            (3U)
7206 #define EXTI_PR_PR3_Msk            (0x1UL << EXTI_PR_PR3_Pos)                   /*!< 0x00000008 */
7207 #define EXTI_PR_PR3                EXTI_PR_PR3_Msk                             /*!< Pending bit for line 3 */
7208 #define EXTI_PR_PR4_Pos            (4U)
7209 #define EXTI_PR_PR4_Msk            (0x1UL << EXTI_PR_PR4_Pos)                   /*!< 0x00000010 */
7210 #define EXTI_PR_PR4                EXTI_PR_PR4_Msk                             /*!< Pending bit for line 4 */
7211 #define EXTI_PR_PR5_Pos            (5U)
7212 #define EXTI_PR_PR5_Msk            (0x1UL << EXTI_PR_PR5_Pos)                   /*!< 0x00000020 */
7213 #define EXTI_PR_PR5                EXTI_PR_PR5_Msk                             /*!< Pending bit for line 5 */
7214 #define EXTI_PR_PR6_Pos            (6U)
7215 #define EXTI_PR_PR6_Msk            (0x1UL << EXTI_PR_PR6_Pos)                   /*!< 0x00000040 */
7216 #define EXTI_PR_PR6                EXTI_PR_PR6_Msk                             /*!< Pending bit for line 6 */
7217 #define EXTI_PR_PR7_Pos            (7U)
7218 #define EXTI_PR_PR7_Msk            (0x1UL << EXTI_PR_PR7_Pos)                   /*!< 0x00000080 */
7219 #define EXTI_PR_PR7                EXTI_PR_PR7_Msk                             /*!< Pending bit for line 7 */
7220 #define EXTI_PR_PR8_Pos            (8U)
7221 #define EXTI_PR_PR8_Msk            (0x1UL << EXTI_PR_PR8_Pos)                   /*!< 0x00000100 */
7222 #define EXTI_PR_PR8                EXTI_PR_PR8_Msk                             /*!< Pending bit for line 8 */
7223 #define EXTI_PR_PR9_Pos            (9U)
7224 #define EXTI_PR_PR9_Msk            (0x1UL << EXTI_PR_PR9_Pos)                   /*!< 0x00000200 */
7225 #define EXTI_PR_PR9                EXTI_PR_PR9_Msk                             /*!< Pending bit for line 9 */
7226 #define EXTI_PR_PR10_Pos           (10U)
7227 #define EXTI_PR_PR10_Msk           (0x1UL << EXTI_PR_PR10_Pos)                  /*!< 0x00000400 */
7228 #define EXTI_PR_PR10               EXTI_PR_PR10_Msk                            /*!< Pending bit for line 10 */
7229 #define EXTI_PR_PR11_Pos           (11U)
7230 #define EXTI_PR_PR11_Msk           (0x1UL << EXTI_PR_PR11_Pos)                  /*!< 0x00000800 */
7231 #define EXTI_PR_PR11               EXTI_PR_PR11_Msk                            /*!< Pending bit for line 11 */
7232 #define EXTI_PR_PR12_Pos           (12U)
7233 #define EXTI_PR_PR12_Msk           (0x1UL << EXTI_PR_PR12_Pos)                  /*!< 0x00001000 */
7234 #define EXTI_PR_PR12               EXTI_PR_PR12_Msk                            /*!< Pending bit for line 12 */
7235 #define EXTI_PR_PR13_Pos           (13U)
7236 #define EXTI_PR_PR13_Msk           (0x1UL << EXTI_PR_PR13_Pos)                  /*!< 0x00002000 */
7237 #define EXTI_PR_PR13               EXTI_PR_PR13_Msk                            /*!< Pending bit for line 13 */
7238 #define EXTI_PR_PR14_Pos           (14U)
7239 #define EXTI_PR_PR14_Msk           (0x1UL << EXTI_PR_PR14_Pos)                  /*!< 0x00004000 */
7240 #define EXTI_PR_PR14               EXTI_PR_PR14_Msk                            /*!< Pending bit for line 14 */
7241 #define EXTI_PR_PR15_Pos           (15U)
7242 #define EXTI_PR_PR15_Msk           (0x1UL << EXTI_PR_PR15_Pos)                  /*!< 0x00008000 */
7243 #define EXTI_PR_PR15               EXTI_PR_PR15_Msk                            /*!< Pending bit for line 15 */
7244 #define EXTI_PR_PR16_Pos           (16U)
7245 #define EXTI_PR_PR16_Msk           (0x1UL << EXTI_PR_PR16_Pos)                  /*!< 0x00010000 */
7246 #define EXTI_PR_PR16               EXTI_PR_PR16_Msk                            /*!< Pending bit for line 16 */
7247 #define EXTI_PR_PR17_Pos           (17U)
7248 #define EXTI_PR_PR17_Msk           (0x1UL << EXTI_PR_PR17_Pos)                  /*!< 0x00020000 */
7249 #define EXTI_PR_PR17               EXTI_PR_PR17_Msk                            /*!< Pending bit for line 17 */
7250 #define EXTI_PR_PR19_Pos           (19U)
7251 #define EXTI_PR_PR19_Msk           (0x1UL << EXTI_PR_PR19_Pos)                  /*!< 0x00080000 */
7252 #define EXTI_PR_PR19               EXTI_PR_PR19_Msk                            /*!< Pending bit for line 19 */
7253 #define EXTI_PR_PR20_Pos           (20U)
7254 #define EXTI_PR_PR20_Msk           (0x1UL << EXTI_PR_PR20_Pos)                  /*!< 0x00100000 */
7255 #define EXTI_PR_PR20               EXTI_PR_PR20_Msk                            /*!< Pending bit for line 20 */
7256 #define EXTI_PR_PR22_Pos           (22U)
7257 #define EXTI_PR_PR22_Msk           (0x1UL << EXTI_PR_PR22_Pos)                  /*!< 0x00400000 */
7258 #define EXTI_PR_PR22               EXTI_PR_PR22_Msk                            /*!< Pending bit for line 22 */
7259 #define EXTI_PR_PR30_Pos           (30U)
7260 #define EXTI_PR_PR30_Msk           (0x1UL << EXTI_PR_PR30_Pos)                  /*!< 0x40000000 */
7261 #define EXTI_PR_PR30               EXTI_PR_PR30_Msk                            /*!< Pending bit for line 30 */
7262 
7263 /* References Defines */
7264 #define EXTI_PR_PIF0 EXTI_PR_PR0
7265 #define EXTI_PR_PIF1 EXTI_PR_PR1
7266 #define EXTI_PR_PIF2 EXTI_PR_PR2
7267 #define EXTI_PR_PIF3 EXTI_PR_PR3
7268 #define EXTI_PR_PIF4 EXTI_PR_PR4
7269 #define EXTI_PR_PIF5 EXTI_PR_PR5
7270 #define EXTI_PR_PIF6 EXTI_PR_PR6
7271 #define EXTI_PR_PIF6 EXTI_PR_PR6
7272 #define EXTI_PR_PIF7 EXTI_PR_PR7
7273 #define EXTI_PR_PIF8 EXTI_PR_PR8
7274 #define EXTI_PR_PIF9 EXTI_PR_PR9
7275 #define EXTI_PR_PIF10 EXTI_PR_PR10
7276 #define EXTI_PR_PIF11 EXTI_PR_PR11
7277 #define EXTI_PR_PIF12 EXTI_PR_PR12
7278 #define EXTI_PR_PIF13 EXTI_PR_PR13
7279 #define EXTI_PR_PIF14 EXTI_PR_PR14
7280 #define EXTI_PR_PIF15 EXTI_PR_PR15
7281 #define EXTI_PR_PIF16 EXTI_PR_PR16
7282 #define EXTI_PR_PIF17 EXTI_PR_PR17
7283 #if defined(EXTI_PR_PR18)
7284 #define EXTI_PR_PIF18 EXTI_PR_PR18
7285 #endif
7286 #define EXTI_PR_PIF19 EXTI_PR_PR19
7287 #define EXTI_PR_PIF20 EXTI_PR_PR20
7288 #if defined(EXTI_PR_PR21)
7289 #define EXTI_PR_PIF21 EXTI_PR_PR21
7290 #endif
7291 #define EXTI_PR_PIF22 EXTI_PR_PR22
7292 #if defined(EXTI_PR_PR23)
7293 #define EXTI_PR_PIF23 EXTI_PR_PR23
7294 #endif
7295 #if defined(EXTI_PR_PR24)
7296 #define EXTI_PR_PIF24 EXTI_PR_PR24
7297 #endif
7298 #if defined(EXTI_PR_PR25)
7299 #define EXTI_PR_PIF25 EXTI_PR_PR25
7300 #endif
7301 #if defined(EXTI_PR_PR26)
7302 #define EXTI_PR_PIF26 EXTI_PR_PR26
7303 #endif
7304 #if defined(EXTI_PR_PR27)
7305 #define EXTI_PR_PIF27 EXTI_PR_PR27
7306 #endif
7307 #if defined(EXTI_PR_PR28)
7308 #define EXTI_PR_PIF28 EXTI_PR_PR28
7309 #endif
7310 #if defined(EXTI_PR_PR29)
7311 #define EXTI_PR_PIF29 EXTI_PR_PR29
7312 #endif
7313 #if defined(EXTI_PR_PR30)
7314 #define EXTI_PR_PIF30 EXTI_PR_PR30
7315 #endif
7316 #if defined(EXTI_PR_PR31)
7317 #define EXTI_PR_PIF31 EXTI_PR_PR31
7318 #endif
7319 
7320 #define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
7321 
7322 /*******************  Bit definition for EXTI_IMR2 register  ******************/
7323 #define EXTI_IMR2_MR32_Pos         (0U)
7324 #define EXTI_IMR2_MR32_Msk         (0x1UL << EXTI_IMR2_MR32_Pos)                /*!< 0x00000001 */
7325 #define EXTI_IMR2_MR32             EXTI_IMR2_MR32_Msk                          /*!< Interrupt Mask on line 32 */
7326 
7327 /* References Defines */
7328 
7329 #define EXTI_IMR2_IM32 EXTI_IMR2_MR32
7330 #if defined(EXTI_IMR2_MR33)
7331 #define EXTI_IMR2_IM33 EXTI_IMR2_MR33
7332 #endif
7333 #if defined(EXTI_IMR2_MR34)
7334 #define EXTI_IMR2_IM34 EXTI_IMR2_MR34
7335 #endif
7336 #if defined(EXTI_IMR2_MR35)
7337 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
7338 #endif
7339 
7340 #if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
7341 #define EXTI_IMR2_IM_Pos           (0U)
7342 #define EXTI_IMR2_IM_Msk           (0xFUL << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000F */
7343 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk
7344 #elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
7345 #define EXTI_IMR2_IM_Pos           (0U)
7346 #define EXTI_IMR2_IM_Msk           (0xDUL << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000D */
7347 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk
7348 #else
7349 #define EXTI_IMR2_IM_Pos           (0U)
7350 #define EXTI_IMR2_IM_Msk           (0x1UL << EXTI_IMR2_IM_Pos)                  /*!< 0x00000001 */
7351 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk
7352 #endif
7353 
7354 /*******************  Bit definition for EXTI_EMR2 ****************************/
7355 #define EXTI_EMR2_MR32_Pos         (0U)
7356 #define EXTI_EMR2_MR32_Msk         (0x1UL << EXTI_EMR2_MR32_Pos)                /*!< 0x00000001 */
7357 #define EXTI_EMR2_MR32             EXTI_EMR2_MR32_Msk                          /*!< Event Mask on line 32 */
7358 
7359 /* References Defines */
7360 #define EXTI_EMR2_EM32 EXTI_EMR2_MR32
7361 #if defined(EXTI_EMR2_MR33)
7362 #define EXTI_EMR2_EM33 EXTI_EMR2_MR33
7363 #endif
7364 #if defined(EXTI_EMR2_MR34)
7365 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34
7366 #endif
7367 #if defined(EXTI_EMR2_MR35)
7368 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
7369 #endif
7370 
7371 #if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
7372 #define EXTI_EMR2_EM_Pos           (0U)
7373 #define EXTI_EMR2_EM_Msk           (0xFUL << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */
7374 #define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk
7375 #elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
7376 #define EXTI_EMR2_EM_Pos           (0U)
7377 #define EXTI_EMR2_EM_Msk           (0xDUL << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000D */
7378 #define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk
7379 #else
7380 #define EXTI_EMR2_EM_Pos           (0U)
7381 #define EXTI_EMR2_EM_Msk           (0x1UL << EXTI_EMR2_EM_Pos)                  /*!< 0x00000001 */
7382 #define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk
7383 #endif
7384 
7385 /******************  Bit definition for EXTI_RTSR2 register ********************/
7386 #define EXTI_RTSR2_TR32_Pos        (0U)
7387 #define EXTI_RTSR2_TR32_Msk        (0x1UL << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */
7388 #define EXTI_RTSR2_TR32            EXTI_RTSR2_TR32_Msk                         /*!< Rising trigger event configuration bit of line 32 */
7389 
7390 /* References Defines */
7391 #define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
7392 #if defined(EXTI_RTSR2_TR33)
7393 #define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
7394 #endif
7395 #if defined(EXTI_RTSR2_TR34)
7396 #define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
7397 #endif
7398 #if defined(EXTI_RTSR2_TR35)
7399 #define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
7400 #endif
7401 
7402 /******************  Bit definition for EXTI_FTSR2 register  ******************/
7403 #define EXTI_FTSR2_TR32_Pos        (0U)
7404 #define EXTI_FTSR2_TR32_Msk        (0x1UL << EXTI_FTSR2_TR32_Pos)               /*!< 0x00000001 */
7405 #define EXTI_FTSR2_TR32            EXTI_FTSR2_TR32_Msk                         /*!< Falling trigger event configuration bit of line 32 */
7406 
7407 /* References Defines */
7408 #define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
7409 #if defined(EXTI_FTSR2_TR33)
7410 #define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
7411 #endif
7412 #if defined(EXTI_FTSR2_TR34)
7413 #define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
7414 #endif
7415 #if defined(EXTI_FTSR2_TR35)
7416 #define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
7417 #endif
7418 
7419 /******************  Bit definition for EXTI_SWIER2 register  *****************/
7420 #define EXTI_SWIER2_SWIER32_Pos    (0U)
7421 #define EXTI_SWIER2_SWIER32_Msk    (0x1UL << EXTI_SWIER2_SWIER32_Pos)           /*!< 0x00000001 */
7422 #define EXTI_SWIER2_SWIER32        EXTI_SWIER2_SWIER32_Msk                     /*!< Software Interrupt on line 32 */
7423 
7424 /* References Defines */
7425 #define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
7426 #if defined(EXTI_SWIER2_SWIER33)
7427 #define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
7428 #endif
7429 #if defined(EXTI_SWIER2_SWIER34)
7430 #define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
7431 #endif
7432 #if defined(EXTI_SWIER2_SWIER35)
7433 #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
7434 #endif
7435 
7436 /*******************  Bit definition for EXTI_PR2 register  *******************/
7437 #define EXTI_PR2_PR32_Pos          (0U)
7438 #define EXTI_PR2_PR32_Msk          (0x1UL << EXTI_PR2_PR32_Pos)                 /*!< 0x00000001 */
7439 #define EXTI_PR2_PR32              EXTI_PR2_PR32_Msk                           /*!< Pending bit for line 32 */
7440 
7441 /* References Defines */
7442 #define EXTI_PR2_PIF32 EXTI_PR2_PR32
7443 #if defined(EXTI_PR2_PR33)
7444 #define EXTI_PR2_PIF33 EXTI_PR2_PR33
7445 #endif
7446 #if defined(EXTI_PR2_PR34)
7447 #define EXTI_PR2_PIF34 EXTI_PR2_PR34
7448 #endif
7449 #if defined(EXTI_PR2_PR35)
7450 #define EXTI_PR2_PIF35 EXTI_PR2_PR35
7451 #endif
7452 
7453 
7454 /******************************************************************************/
7455 /*                                                                            */
7456 /*                                    FLASH                                   */
7457 /*                                                                            */
7458 /******************************************************************************/
7459 /*******************  Bit definition for FLASH_ACR register  ******************/
7460 #define FLASH_ACR_LATENCY_Pos                (0U)
7461 #define FLASH_ACR_LATENCY_Msk                (0x7UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000007 */
7462 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< LATENCY[2:0] bits (Latency) */
7463 #define FLASH_ACR_LATENCY_0                  (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
7464 #define FLASH_ACR_LATENCY_1                  (0x2UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000002 */
7465 #define FLASH_ACR_LATENCY_2                  (0x4UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000004 */
7466 
7467 #define FLASH_ACR_HLFCYA_Pos                 (3U)
7468 #define FLASH_ACR_HLFCYA_Msk                 (0x1UL << FLASH_ACR_HLFCYA_Pos)    /*!< 0x00000008 */
7469 #define FLASH_ACR_HLFCYA                     FLASH_ACR_HLFCYA_Msk              /*!< Flash Half Cycle Access Enable */
7470 #define FLASH_ACR_PRFTBE_Pos                 (4U)
7471 #define FLASH_ACR_PRFTBE_Msk                 (0x1UL << FLASH_ACR_PRFTBE_Pos)    /*!< 0x00000010 */
7472 #define FLASH_ACR_PRFTBE                     FLASH_ACR_PRFTBE_Msk              /*!< Prefetch Buffer Enable */
7473 #define FLASH_ACR_PRFTBS_Pos                 (5U)
7474 #define FLASH_ACR_PRFTBS_Msk                 (0x1UL << FLASH_ACR_PRFTBS_Pos)    /*!< 0x00000020 */
7475 #define FLASH_ACR_PRFTBS                     FLASH_ACR_PRFTBS_Msk              /*!< Prefetch Buffer Status */
7476 
7477 /******************  Bit definition for FLASH_KEYR register  ******************/
7478 #define FLASH_KEYR_FKEYR_Pos                 (0U)
7479 #define FLASH_KEYR_FKEYR_Msk                 (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
7480 #define FLASH_KEYR_FKEYR                     FLASH_KEYR_FKEYR_Msk              /*!< FPEC Key */
7481 
7482 #define RDP_KEY_Pos    (0U)
7483 #define RDP_KEY_Msk    (0xA5UL << RDP_KEY_Pos)                                  /*!< 0x000000A5 */
7484 #define RDP_KEY        RDP_KEY_Msk                                             /*!< RDP Key */
7485 #define FLASH_KEY1_Pos                       (0U)
7486 #define FLASH_KEY1_Msk                       (0x45670123UL << FLASH_KEY1_Pos)   /*!< 0x45670123 */
7487 #define FLASH_KEY1                           FLASH_KEY1_Msk                    /*!< FPEC Key1 */
7488 #define FLASH_KEY2_Pos                       (0U)
7489 #define FLASH_KEY2_Msk                       (0xCDEF89ABUL << FLASH_KEY2_Pos)   /*!< 0xCDEF89AB */
7490 #define FLASH_KEY2                           FLASH_KEY2_Msk                    /*!< FPEC Key2 */
7491 
7492 /*****************  Bit definition for FLASH_OPTKEYR register  ****************/
7493 #define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)
7494 #define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
7495 #define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option Byte Key */
7496 
7497 #define  FLASH_OPTKEY1                       FLASH_KEY1                    /*!< Option Byte Key1 */
7498 #define  FLASH_OPTKEY2                       FLASH_KEY2                    /*!< Option Byte Key2 */
7499 
7500 /******************  Bit definition for FLASH_SR register  *******************/
7501 #define FLASH_SR_BSY_Pos                     (0U)
7502 #define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
7503 #define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
7504 #define FLASH_SR_PGERR_Pos                   (2U)
7505 #define FLASH_SR_PGERR_Msk                   (0x1UL << FLASH_SR_PGERR_Pos)      /*!< 0x00000004 */
7506 #define FLASH_SR_PGERR                       FLASH_SR_PGERR_Msk                /*!< Programming Error */
7507 #define FLASH_SR_WRPERR_Pos                  (4U)
7508 #define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000010 */
7509 #define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write Protection Error */
7510 #define FLASH_SR_EOP_Pos                     (5U)
7511 #define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000020 */
7512 #define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End of operation */
7513 
7514 /*******************  Bit definition for FLASH_CR register  *******************/
7515 #define FLASH_CR_PG_Pos                      (0U)
7516 #define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)         /*!< 0x00000001 */
7517 #define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Programming */
7518 #define FLASH_CR_PER_Pos                     (1U)
7519 #define FLASH_CR_PER_Msk                     (0x1UL << FLASH_CR_PER_Pos)        /*!< 0x00000002 */
7520 #define FLASH_CR_PER                         FLASH_CR_PER_Msk                  /*!< Page Erase */
7521 #define FLASH_CR_MER_Pos                     (2U)
7522 #define FLASH_CR_MER_Msk                     (0x1UL << FLASH_CR_MER_Pos)        /*!< 0x00000004 */
7523 #define FLASH_CR_MER                         FLASH_CR_MER_Msk                  /*!< Mass Erase */
7524 #define FLASH_CR_OPTPG_Pos                   (4U)
7525 #define FLASH_CR_OPTPG_Msk                   (0x1UL << FLASH_CR_OPTPG_Pos)      /*!< 0x00000010 */
7526 #define FLASH_CR_OPTPG                       FLASH_CR_OPTPG_Msk                /*!< Option Byte Programming */
7527 #define FLASH_CR_OPTER_Pos                   (5U)
7528 #define FLASH_CR_OPTER_Msk                   (0x1UL << FLASH_CR_OPTER_Pos)      /*!< 0x00000020 */
7529 #define FLASH_CR_OPTER                       FLASH_CR_OPTER_Msk                /*!< Option Byte Erase */
7530 #define FLASH_CR_STRT_Pos                    (6U)
7531 #define FLASH_CR_STRT_Msk                    (0x1UL << FLASH_CR_STRT_Pos)       /*!< 0x00000040 */
7532 #define FLASH_CR_STRT                        FLASH_CR_STRT_Msk                 /*!< Start */
7533 #define FLASH_CR_LOCK_Pos                    (7U)
7534 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)       /*!< 0x00000080 */
7535 #define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Lock */
7536 #define FLASH_CR_OPTWRE_Pos                  (9U)
7537 #define FLASH_CR_OPTWRE_Msk                  (0x1UL << FLASH_CR_OPTWRE_Pos)     /*!< 0x00000200 */
7538 #define FLASH_CR_OPTWRE                      FLASH_CR_OPTWRE_Msk               /*!< Option Bytes Write Enable */
7539 #define FLASH_CR_ERRIE_Pos                   (10U)
7540 #define FLASH_CR_ERRIE_Msk                   (0x1UL << FLASH_CR_ERRIE_Pos)      /*!< 0x00000400 */
7541 #define FLASH_CR_ERRIE                       FLASH_CR_ERRIE_Msk                /*!< Error Interrupt Enable */
7542 #define FLASH_CR_EOPIE_Pos                   (12U)
7543 #define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)      /*!< 0x00001000 */
7544 #define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End of operation interrupt enable */
7545 #define FLASH_CR_OBL_LAUNCH_Pos              (13U)
7546 #define FLASH_CR_OBL_LAUNCH_Msk              (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */
7547 #define FLASH_CR_OBL_LAUNCH                  FLASH_CR_OBL_LAUNCH_Msk           /*!< OptionBytes Loader Launch */
7548 
7549 /*******************  Bit definition for FLASH_AR register  *******************/
7550 #define FLASH_AR_FAR_Pos                     (0U)
7551 #define FLASH_AR_FAR_Msk                     (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
7552 #define FLASH_AR_FAR                         FLASH_AR_FAR_Msk                  /*!< Flash Address */
7553 
7554 /******************  Bit definition for FLASH_OBR register  *******************/
7555 #define FLASH_OBR_OPTERR_Pos                 (0U)
7556 #define FLASH_OBR_OPTERR_Msk                 (0x1UL << FLASH_OBR_OPTERR_Pos)    /*!< 0x00000001 */
7557 #define FLASH_OBR_OPTERR                     FLASH_OBR_OPTERR_Msk              /*!< Option Byte Error */
7558 #define FLASH_OBR_RDPRT_Pos                  (1U)
7559 #define FLASH_OBR_RDPRT_Msk                  (0x3UL << FLASH_OBR_RDPRT_Pos)     /*!< 0x00000006 */
7560 #define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read protection */
7561 #define FLASH_OBR_RDPRT_1                    (0x1UL << FLASH_OBR_RDPRT_Pos)     /*!< 0x00000002 */
7562 #define FLASH_OBR_RDPRT_2                    (0x3UL << FLASH_OBR_RDPRT_Pos)     /*!< 0x00000006 */
7563 
7564 #define FLASH_OBR_USER_Pos                   (8U)
7565 #define FLASH_OBR_USER_Msk                   (0x77UL << FLASH_OBR_USER_Pos)     /*!< 0x00007700 */
7566 #define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
7567 #define FLASH_OBR_IWDG_SW_Pos                (8U)
7568 #define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00000100 */
7569 #define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG SW */
7570 #define FLASH_OBR_nRST_STOP_Pos              (9U)
7571 #define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */
7572 #define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
7573 #define FLASH_OBR_nRST_STDBY_Pos             (10U)
7574 #define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */
7575 #define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
7576 #define FLASH_OBR_nBOOT1_Pos                 (12U)
7577 #define FLASH_OBR_nBOOT1_Msk                 (0x1UL << FLASH_OBR_nBOOT1_Pos)    /*!< 0x00001000 */
7578 #define FLASH_OBR_nBOOT1                     FLASH_OBR_nBOOT1_Msk              /*!< nBOOT1 */
7579 #define FLASH_OBR_VDDA_MONITOR_Pos           (13U)
7580 #define FLASH_OBR_VDDA_MONITOR_Msk           (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
7581 #define FLASH_OBR_VDDA_MONITOR               FLASH_OBR_VDDA_MONITOR_Msk        /*!< VDDA_MONITOR */
7582 #define FLASH_OBR_SRAM_PE_Pos                (14U)
7583 #define FLASH_OBR_SRAM_PE_Msk                (0x1UL << FLASH_OBR_SRAM_PE_Pos)   /*!< 0x00004000 */
7584 #define FLASH_OBR_SRAM_PE                    FLASH_OBR_SRAM_PE_Msk             /*!< SRAM_PE */
7585 #define FLASH_OBR_DATA0_Pos                  (16U)
7586 #define FLASH_OBR_DATA0_Msk                  (0xFFUL << FLASH_OBR_DATA0_Pos)    /*!< 0x00FF0000 */
7587 #define FLASH_OBR_DATA0                      FLASH_OBR_DATA0_Msk               /*!< Data0 */
7588 #define FLASH_OBR_DATA1_Pos                  (24U)
7589 #define FLASH_OBR_DATA1_Msk                  (0xFFUL << FLASH_OBR_DATA1_Pos)    /*!< 0xFF000000 */
7590 #define FLASH_OBR_DATA1                      FLASH_OBR_DATA1_Msk               /*!< Data1 */
7591 
7592 /* Legacy defines */
7593 #define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
7594 
7595 /******************  Bit definition for FLASH_WRPR register  ******************/
7596 #define FLASH_WRPR_WRP_Pos                   (0U)
7597 #define FLASH_WRPR_WRP_Msk                   (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
7598 #define FLASH_WRPR_WRP                       FLASH_WRPR_WRP_Msk                /*!< Write Protect */
7599 
7600 /*----------------------------------------------------------------------------*/
7601 
7602 /******************  Bit definition for OB_RDP register  **********************/
7603 #define OB_RDP_RDP_Pos       (0U)
7604 #define OB_RDP_RDP_Msk       (0xFFUL << OB_RDP_RDP_Pos)                         /*!< 0x000000FF */
7605 #define OB_RDP_RDP           OB_RDP_RDP_Msk                                    /*!< Read protection option byte */
7606 #define OB_RDP_nRDP_Pos      (8U)
7607 #define OB_RDP_nRDP_Msk      (0xFFUL << OB_RDP_nRDP_Pos)                        /*!< 0x0000FF00 */
7608 #define OB_RDP_nRDP          OB_RDP_nRDP_Msk                                   /*!< Read protection complemented option byte */
7609 
7610 /******************  Bit definition for OB_USER register  *********************/
7611 #define OB_USER_USER_Pos     (16U)
7612 #define OB_USER_USER_Msk     (0xFFUL << OB_USER_USER_Pos)                       /*!< 0x00FF0000 */
7613 #define OB_USER_USER         OB_USER_USER_Msk                                  /*!< User option byte */
7614 #define OB_USER_nUSER_Pos    (24U)
7615 #define OB_USER_nUSER_Msk    (0xFFUL << OB_USER_nUSER_Pos)                      /*!< 0xFF000000 */
7616 #define OB_USER_nUSER        OB_USER_nUSER_Msk                                 /*!< User complemented option byte */
7617 
7618 /******************  Bit definition for FLASH_WRP0 register  ******************/
7619 #define OB_WRP0_WRP0_Pos     (0U)
7620 #define OB_WRP0_WRP0_Msk     (0xFFUL << OB_WRP0_WRP0_Pos)                       /*!< 0x000000FF */
7621 #define OB_WRP0_WRP0         OB_WRP0_WRP0_Msk                                  /*!< Flash memory write protection option bytes */
7622 #define OB_WRP0_nWRP0_Pos    (8U)
7623 #define OB_WRP0_nWRP0_Msk    (0xFFUL << OB_WRP0_nWRP0_Pos)                      /*!< 0x0000FF00 */
7624 #define OB_WRP0_nWRP0        OB_WRP0_nWRP0_Msk                                 /*!< Flash memory write protection complemented option bytes */
7625 
7626 /******************  Bit definition for FLASH_WRP1 register  ******************/
7627 #define OB_WRP1_WRP1_Pos     (16U)
7628 #define OB_WRP1_WRP1_Msk     (0xFFUL << OB_WRP1_WRP1_Pos)                       /*!< 0x00FF0000 */
7629 #define OB_WRP1_WRP1         OB_WRP1_WRP1_Msk                                  /*!< Flash memory write protection option bytes */
7630 #define OB_WRP1_nWRP1_Pos    (24U)
7631 #define OB_WRP1_nWRP1_Msk    (0xFFUL << OB_WRP1_nWRP1_Pos)                      /*!< 0xFF000000 */
7632 #define OB_WRP1_nWRP1        OB_WRP1_nWRP1_Msk                                 /*!< Flash memory write protection complemented option bytes */
7633 
7634 
7635 /******************************************************************************/
7636 /*                                                                            */
7637 /*                            General Purpose I/O (GPIO)                      */
7638 /*                                                                            */
7639 /******************************************************************************/
7640 /*******************  Bit definition for GPIO_MODER register  *****************/
7641 #define GPIO_MODER_MODER0_Pos            (0U)
7642 #define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */
7643 #define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk
7644 #define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */
7645 #define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */
7646 #define GPIO_MODER_MODER1_Pos            (2U)
7647 #define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */
7648 #define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk
7649 #define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */
7650 #define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */
7651 #define GPIO_MODER_MODER2_Pos            (4U)
7652 #define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */
7653 #define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk
7654 #define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */
7655 #define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */
7656 #define GPIO_MODER_MODER3_Pos            (6U)
7657 #define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */
7658 #define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk
7659 #define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */
7660 #define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */
7661 #define GPIO_MODER_MODER4_Pos            (8U)
7662 #define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */
7663 #define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk
7664 #define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */
7665 #define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */
7666 #define GPIO_MODER_MODER5_Pos            (10U)
7667 #define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */
7668 #define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk
7669 #define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */
7670 #define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */
7671 #define GPIO_MODER_MODER6_Pos            (12U)
7672 #define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */
7673 #define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk
7674 #define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */
7675 #define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */
7676 #define GPIO_MODER_MODER7_Pos            (14U)
7677 #define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */
7678 #define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk
7679 #define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */
7680 #define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */
7681 #define GPIO_MODER_MODER8_Pos            (16U)
7682 #define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */
7683 #define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk
7684 #define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */
7685 #define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */
7686 #define GPIO_MODER_MODER9_Pos            (18U)
7687 #define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */
7688 #define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk
7689 #define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */
7690 #define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */
7691 #define GPIO_MODER_MODER10_Pos           (20U)
7692 #define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */
7693 #define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk
7694 #define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */
7695 #define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */
7696 #define GPIO_MODER_MODER11_Pos           (22U)
7697 #define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */
7698 #define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk
7699 #define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */
7700 #define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */
7701 #define GPIO_MODER_MODER12_Pos           (24U)
7702 #define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */
7703 #define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk
7704 #define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */
7705 #define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */
7706 #define GPIO_MODER_MODER13_Pos           (26U)
7707 #define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */
7708 #define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk
7709 #define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */
7710 #define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */
7711 #define GPIO_MODER_MODER14_Pos           (28U)
7712 #define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */
7713 #define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk
7714 #define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */
7715 #define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */
7716 #define GPIO_MODER_MODER15_Pos           (30U)
7717 #define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */
7718 #define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk
7719 #define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */
7720 #define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */
7721 
7722 /******************  Bit definition for GPIO_OTYPER register  *****************/
7723 #define GPIO_OTYPER_OT_0                 (0x00000001U)
7724 #define GPIO_OTYPER_OT_1                 (0x00000002U)
7725 #define GPIO_OTYPER_OT_2                 (0x00000004U)
7726 #define GPIO_OTYPER_OT_3                 (0x00000008U)
7727 #define GPIO_OTYPER_OT_4                 (0x00000010U)
7728 #define GPIO_OTYPER_OT_5                 (0x00000020U)
7729 #define GPIO_OTYPER_OT_6                 (0x00000040U)
7730 #define GPIO_OTYPER_OT_7                 (0x00000080U)
7731 #define GPIO_OTYPER_OT_8                 (0x00000100U)
7732 #define GPIO_OTYPER_OT_9                 (0x00000200U)
7733 #define GPIO_OTYPER_OT_10                (0x00000400U)
7734 #define GPIO_OTYPER_OT_11                (0x00000800U)
7735 #define GPIO_OTYPER_OT_12                (0x00001000U)
7736 #define GPIO_OTYPER_OT_13                (0x00002000U)
7737 #define GPIO_OTYPER_OT_14                (0x00004000U)
7738 #define GPIO_OTYPER_OT_15                (0x00008000U)
7739 
7740 /****************  Bit definition for GPIO_OSPEEDR register  ******************/
7741 #define GPIO_OSPEEDER_OSPEEDR0_Pos       (0U)
7742 #define GPIO_OSPEEDER_OSPEEDR0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos)  /*!< 0x00000003 */
7743 #define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDER_OSPEEDR0_Msk
7744 #define GPIO_OSPEEDER_OSPEEDR0_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos)  /*!< 0x00000001 */
7745 #define GPIO_OSPEEDER_OSPEEDR0_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos)  /*!< 0x00000002 */
7746 #define GPIO_OSPEEDER_OSPEEDR1_Pos       (2U)
7747 #define GPIO_OSPEEDER_OSPEEDR1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos)  /*!< 0x0000000C */
7748 #define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDER_OSPEEDR1_Msk
7749 #define GPIO_OSPEEDER_OSPEEDR1_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos)  /*!< 0x00000004 */
7750 #define GPIO_OSPEEDER_OSPEEDR1_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos)  /*!< 0x00000008 */
7751 #define GPIO_OSPEEDER_OSPEEDR2_Pos       (4U)
7752 #define GPIO_OSPEEDER_OSPEEDR2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos)  /*!< 0x00000030 */
7753 #define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDER_OSPEEDR2_Msk
7754 #define GPIO_OSPEEDER_OSPEEDR2_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos)  /*!< 0x00000010 */
7755 #define GPIO_OSPEEDER_OSPEEDR2_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos)  /*!< 0x00000020 */
7756 #define GPIO_OSPEEDER_OSPEEDR3_Pos       (6U)
7757 #define GPIO_OSPEEDER_OSPEEDR3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos)  /*!< 0x000000C0 */
7758 #define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDER_OSPEEDR3_Msk
7759 #define GPIO_OSPEEDER_OSPEEDR3_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos)  /*!< 0x00000040 */
7760 #define GPIO_OSPEEDER_OSPEEDR3_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos)  /*!< 0x00000080 */
7761 #define GPIO_OSPEEDER_OSPEEDR4_Pos       (8U)
7762 #define GPIO_OSPEEDER_OSPEEDR4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos)  /*!< 0x00000300 */
7763 #define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDER_OSPEEDR4_Msk
7764 #define GPIO_OSPEEDER_OSPEEDR4_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos)  /*!< 0x00000100 */
7765 #define GPIO_OSPEEDER_OSPEEDR4_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos)  /*!< 0x00000200 */
7766 #define GPIO_OSPEEDER_OSPEEDR5_Pos       (10U)
7767 #define GPIO_OSPEEDER_OSPEEDR5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos)  /*!< 0x00000C00 */
7768 #define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDER_OSPEEDR5_Msk
7769 #define GPIO_OSPEEDER_OSPEEDR5_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos)  /*!< 0x00000400 */
7770 #define GPIO_OSPEEDER_OSPEEDR5_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos)  /*!< 0x00000800 */
7771 #define GPIO_OSPEEDER_OSPEEDR6_Pos       (12U)
7772 #define GPIO_OSPEEDER_OSPEEDR6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos)  /*!< 0x00003000 */
7773 #define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDER_OSPEEDR6_Msk
7774 #define GPIO_OSPEEDER_OSPEEDR6_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos)  /*!< 0x00001000 */
7775 #define GPIO_OSPEEDER_OSPEEDR6_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos)  /*!< 0x00002000 */
7776 #define GPIO_OSPEEDER_OSPEEDR7_Pos       (14U)
7777 #define GPIO_OSPEEDER_OSPEEDR7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos)  /*!< 0x0000C000 */
7778 #define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDER_OSPEEDR7_Msk
7779 #define GPIO_OSPEEDER_OSPEEDR7_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos)  /*!< 0x00004000 */
7780 #define GPIO_OSPEEDER_OSPEEDR7_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos)  /*!< 0x00008000 */
7781 #define GPIO_OSPEEDER_OSPEEDR8_Pos       (16U)
7782 #define GPIO_OSPEEDER_OSPEEDR8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos)  /*!< 0x00030000 */
7783 #define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDER_OSPEEDR8_Msk
7784 #define GPIO_OSPEEDER_OSPEEDR8_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos)  /*!< 0x00010000 */
7785 #define GPIO_OSPEEDER_OSPEEDR8_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos)  /*!< 0x00020000 */
7786 #define GPIO_OSPEEDER_OSPEEDR9_Pos       (18U)
7787 #define GPIO_OSPEEDER_OSPEEDR9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos)  /*!< 0x000C0000 */
7788 #define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDER_OSPEEDR9_Msk
7789 #define GPIO_OSPEEDER_OSPEEDR9_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos)  /*!< 0x00040000 */
7790 #define GPIO_OSPEEDER_OSPEEDR9_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos)  /*!< 0x00080000 */
7791 #define GPIO_OSPEEDER_OSPEEDR10_Pos      (20U)
7792 #define GPIO_OSPEEDER_OSPEEDR10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
7793 #define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDER_OSPEEDR10_Msk
7794 #define GPIO_OSPEEDER_OSPEEDR10_0        (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
7795 #define GPIO_OSPEEDER_OSPEEDR10_1        (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
7796 #define GPIO_OSPEEDER_OSPEEDR11_Pos      (22U)
7797 #define GPIO_OSPEEDER_OSPEEDR11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
7798 #define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDER_OSPEEDR11_Msk
7799 #define GPIO_OSPEEDER_OSPEEDR11_0        (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
7800 #define GPIO_OSPEEDER_OSPEEDR11_1        (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
7801 #define GPIO_OSPEEDER_OSPEEDR12_Pos      (24U)
7802 #define GPIO_OSPEEDER_OSPEEDR12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
7803 #define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDER_OSPEEDR12_Msk
7804 #define GPIO_OSPEEDER_OSPEEDR12_0        (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
7805 #define GPIO_OSPEEDER_OSPEEDR12_1        (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
7806 #define GPIO_OSPEEDER_OSPEEDR13_Pos      (26U)
7807 #define GPIO_OSPEEDER_OSPEEDR13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
7808 #define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDER_OSPEEDR13_Msk
7809 #define GPIO_OSPEEDER_OSPEEDR13_0        (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
7810 #define GPIO_OSPEEDER_OSPEEDR13_1        (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
7811 #define GPIO_OSPEEDER_OSPEEDR14_Pos      (28U)
7812 #define GPIO_OSPEEDER_OSPEEDR14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
7813 #define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDER_OSPEEDR14_Msk
7814 #define GPIO_OSPEEDER_OSPEEDR14_0        (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
7815 #define GPIO_OSPEEDER_OSPEEDR14_1        (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
7816 #define GPIO_OSPEEDER_OSPEEDR15_Pos      (30U)
7817 #define GPIO_OSPEEDER_OSPEEDR15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
7818 #define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDER_OSPEEDR15_Msk
7819 #define GPIO_OSPEEDER_OSPEEDR15_0        (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
7820 #define GPIO_OSPEEDER_OSPEEDR15_1        (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
7821 
7822 /*******************  Bit definition for GPIO_PUPDR register ******************/
7823 #define GPIO_PUPDR_PUPDR0_Pos            (0U)
7824 #define GPIO_PUPDR_PUPDR0_Msk            (0x3UL << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000003 */
7825 #define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPDR0_Msk
7826 #define GPIO_PUPDR_PUPDR0_0              (0x1UL << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000001 */
7827 #define GPIO_PUPDR_PUPDR0_1              (0x2UL << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000002 */
7828 #define GPIO_PUPDR_PUPDR1_Pos            (2U)
7829 #define GPIO_PUPDR_PUPDR1_Msk            (0x3UL << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x0000000C */
7830 #define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPDR1_Msk
7831 #define GPIO_PUPDR_PUPDR1_0              (0x1UL << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x00000004 */
7832 #define GPIO_PUPDR_PUPDR1_1              (0x2UL << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x00000008 */
7833 #define GPIO_PUPDR_PUPDR2_Pos            (4U)
7834 #define GPIO_PUPDR_PUPDR2_Msk            (0x3UL << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000030 */
7835 #define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPDR2_Msk
7836 #define GPIO_PUPDR_PUPDR2_0              (0x1UL << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000010 */
7837 #define GPIO_PUPDR_PUPDR2_1              (0x2UL << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000020 */
7838 #define GPIO_PUPDR_PUPDR3_Pos            (6U)
7839 #define GPIO_PUPDR_PUPDR3_Msk            (0x3UL << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x000000C0 */
7840 #define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPDR3_Msk
7841 #define GPIO_PUPDR_PUPDR3_0              (0x1UL << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x00000040 */
7842 #define GPIO_PUPDR_PUPDR3_1              (0x2UL << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x00000080 */
7843 #define GPIO_PUPDR_PUPDR4_Pos            (8U)
7844 #define GPIO_PUPDR_PUPDR4_Msk            (0x3UL << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000300 */
7845 #define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPDR4_Msk
7846 #define GPIO_PUPDR_PUPDR4_0              (0x1UL << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000100 */
7847 #define GPIO_PUPDR_PUPDR4_1              (0x2UL << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000200 */
7848 #define GPIO_PUPDR_PUPDR5_Pos            (10U)
7849 #define GPIO_PUPDR_PUPDR5_Msk            (0x3UL << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000C00 */
7850 #define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPDR5_Msk
7851 #define GPIO_PUPDR_PUPDR5_0              (0x1UL << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000400 */
7852 #define GPIO_PUPDR_PUPDR5_1              (0x2UL << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000800 */
7853 #define GPIO_PUPDR_PUPDR6_Pos            (12U)
7854 #define GPIO_PUPDR_PUPDR6_Msk            (0x3UL << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00003000 */
7855 #define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPDR6_Msk
7856 #define GPIO_PUPDR_PUPDR6_0              (0x1UL << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00001000 */
7857 #define GPIO_PUPDR_PUPDR6_1              (0x2UL << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00002000 */
7858 #define GPIO_PUPDR_PUPDR7_Pos            (14U)
7859 #define GPIO_PUPDR_PUPDR7_Msk            (0x3UL << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x0000C000 */
7860 #define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPDR7_Msk
7861 #define GPIO_PUPDR_PUPDR7_0              (0x1UL << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x00004000 */
7862 #define GPIO_PUPDR_PUPDR7_1              (0x2UL << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x00008000 */
7863 #define GPIO_PUPDR_PUPDR8_Pos            (16U)
7864 #define GPIO_PUPDR_PUPDR8_Msk            (0x3UL << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00030000 */
7865 #define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPDR8_Msk
7866 #define GPIO_PUPDR_PUPDR8_0              (0x1UL << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00010000 */
7867 #define GPIO_PUPDR_PUPDR8_1              (0x2UL << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00020000 */
7868 #define GPIO_PUPDR_PUPDR9_Pos            (18U)
7869 #define GPIO_PUPDR_PUPDR9_Msk            (0x3UL << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x000C0000 */
7870 #define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPDR9_Msk
7871 #define GPIO_PUPDR_PUPDR9_0              (0x1UL << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x00040000 */
7872 #define GPIO_PUPDR_PUPDR9_1              (0x2UL << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x00080000 */
7873 #define GPIO_PUPDR_PUPDR10_Pos           (20U)
7874 #define GPIO_PUPDR_PUPDR10_Msk           (0x3UL << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00300000 */
7875 #define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPDR10_Msk
7876 #define GPIO_PUPDR_PUPDR10_0             (0x1UL << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00100000 */
7877 #define GPIO_PUPDR_PUPDR10_1             (0x2UL << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00200000 */
7878 #define GPIO_PUPDR_PUPDR11_Pos           (22U)
7879 #define GPIO_PUPDR_PUPDR11_Msk           (0x3UL << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00C00000 */
7880 #define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPDR11_Msk
7881 #define GPIO_PUPDR_PUPDR11_0             (0x1UL << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00400000 */
7882 #define GPIO_PUPDR_PUPDR11_1             (0x2UL << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00800000 */
7883 #define GPIO_PUPDR_PUPDR12_Pos           (24U)
7884 #define GPIO_PUPDR_PUPDR12_Msk           (0x3UL << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x03000000 */
7885 #define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPDR12_Msk
7886 #define GPIO_PUPDR_PUPDR12_0             (0x1UL << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x01000000 */
7887 #define GPIO_PUPDR_PUPDR12_1             (0x2UL << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x02000000 */
7888 #define GPIO_PUPDR_PUPDR13_Pos           (26U)
7889 #define GPIO_PUPDR_PUPDR13_Msk           (0x3UL << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x0C000000 */
7890 #define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPDR13_Msk
7891 #define GPIO_PUPDR_PUPDR13_0             (0x1UL << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x04000000 */
7892 #define GPIO_PUPDR_PUPDR13_1             (0x2UL << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x08000000 */
7893 #define GPIO_PUPDR_PUPDR14_Pos           (28U)
7894 #define GPIO_PUPDR_PUPDR14_Msk           (0x3UL << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x30000000 */
7895 #define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPDR14_Msk
7896 #define GPIO_PUPDR_PUPDR14_0             (0x1UL << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x10000000 */
7897 #define GPIO_PUPDR_PUPDR14_1             (0x2UL << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x20000000 */
7898 #define GPIO_PUPDR_PUPDR15_Pos           (30U)
7899 #define GPIO_PUPDR_PUPDR15_Msk           (0x3UL << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0xC0000000 */
7900 #define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPDR15_Msk
7901 #define GPIO_PUPDR_PUPDR15_0             (0x1UL << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0x40000000 */
7902 #define GPIO_PUPDR_PUPDR15_1             (0x2UL << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0x80000000 */
7903 
7904 /*******************  Bit definition for GPIO_IDR register  *******************/
7905 #define GPIO_IDR_0                       (0x00000001U)
7906 #define GPIO_IDR_1                       (0x00000002U)
7907 #define GPIO_IDR_2                       (0x00000004U)
7908 #define GPIO_IDR_3                       (0x00000008U)
7909 #define GPIO_IDR_4                       (0x00000010U)
7910 #define GPIO_IDR_5                       (0x00000020U)
7911 #define GPIO_IDR_6                       (0x00000040U)
7912 #define GPIO_IDR_7                       (0x00000080U)
7913 #define GPIO_IDR_8                       (0x00000100U)
7914 #define GPIO_IDR_9                       (0x00000200U)
7915 #define GPIO_IDR_10                      (0x00000400U)
7916 #define GPIO_IDR_11                      (0x00000800U)
7917 #define GPIO_IDR_12                      (0x00001000U)
7918 #define GPIO_IDR_13                      (0x00002000U)
7919 #define GPIO_IDR_14                      (0x00004000U)
7920 #define GPIO_IDR_15                      (0x00008000U)
7921 
7922 /******************  Bit definition for GPIO_ODR register  ********************/
7923 #define GPIO_ODR_0                       (0x00000001U)
7924 #define GPIO_ODR_1                       (0x00000002U)
7925 #define GPIO_ODR_2                       (0x00000004U)
7926 #define GPIO_ODR_3                       (0x00000008U)
7927 #define GPIO_ODR_4                       (0x00000010U)
7928 #define GPIO_ODR_5                       (0x00000020U)
7929 #define GPIO_ODR_6                       (0x00000040U)
7930 #define GPIO_ODR_7                       (0x00000080U)
7931 #define GPIO_ODR_8                       (0x00000100U)
7932 #define GPIO_ODR_9                       (0x00000200U)
7933 #define GPIO_ODR_10                      (0x00000400U)
7934 #define GPIO_ODR_11                      (0x00000800U)
7935 #define GPIO_ODR_12                      (0x00001000U)
7936 #define GPIO_ODR_13                      (0x00002000U)
7937 #define GPIO_ODR_14                      (0x00004000U)
7938 #define GPIO_ODR_15                      (0x00008000U)
7939 
7940 /****************** Bit definition for GPIO_BSRR register  ********************/
7941 #define GPIO_BSRR_BS_0                   (0x00000001U)
7942 #define GPIO_BSRR_BS_1                   (0x00000002U)
7943 #define GPIO_BSRR_BS_2                   (0x00000004U)
7944 #define GPIO_BSRR_BS_3                   (0x00000008U)
7945 #define GPIO_BSRR_BS_4                   (0x00000010U)
7946 #define GPIO_BSRR_BS_5                   (0x00000020U)
7947 #define GPIO_BSRR_BS_6                   (0x00000040U)
7948 #define GPIO_BSRR_BS_7                   (0x00000080U)
7949 #define GPIO_BSRR_BS_8                   (0x00000100U)
7950 #define GPIO_BSRR_BS_9                   (0x00000200U)
7951 #define GPIO_BSRR_BS_10                  (0x00000400U)
7952 #define GPIO_BSRR_BS_11                  (0x00000800U)
7953 #define GPIO_BSRR_BS_12                  (0x00001000U)
7954 #define GPIO_BSRR_BS_13                  (0x00002000U)
7955 #define GPIO_BSRR_BS_14                  (0x00004000U)
7956 #define GPIO_BSRR_BS_15                  (0x00008000U)
7957 #define GPIO_BSRR_BR_0                   (0x00010000U)
7958 #define GPIO_BSRR_BR_1                   (0x00020000U)
7959 #define GPIO_BSRR_BR_2                   (0x00040000U)
7960 #define GPIO_BSRR_BR_3                   (0x00080000U)
7961 #define GPIO_BSRR_BR_4                   (0x00100000U)
7962 #define GPIO_BSRR_BR_5                   (0x00200000U)
7963 #define GPIO_BSRR_BR_6                   (0x00400000U)
7964 #define GPIO_BSRR_BR_7                   (0x00800000U)
7965 #define GPIO_BSRR_BR_8                   (0x01000000U)
7966 #define GPIO_BSRR_BR_9                   (0x02000000U)
7967 #define GPIO_BSRR_BR_10                  (0x04000000U)
7968 #define GPIO_BSRR_BR_11                  (0x08000000U)
7969 #define GPIO_BSRR_BR_12                  (0x10000000U)
7970 #define GPIO_BSRR_BR_13                  (0x20000000U)
7971 #define GPIO_BSRR_BR_14                  (0x40000000U)
7972 #define GPIO_BSRR_BR_15                  (0x80000000U)
7973 
7974 /****************** Bit definition for GPIO_LCKR register  ********************/
7975 #define GPIO_LCKR_LCK0_Pos               (0U)
7976 #define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */
7977 #define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk
7978 #define GPIO_LCKR_LCK1_Pos               (1U)
7979 #define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */
7980 #define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk
7981 #define GPIO_LCKR_LCK2_Pos               (2U)
7982 #define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */
7983 #define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk
7984 #define GPIO_LCKR_LCK3_Pos               (3U)
7985 #define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */
7986 #define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk
7987 #define GPIO_LCKR_LCK4_Pos               (4U)
7988 #define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */
7989 #define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk
7990 #define GPIO_LCKR_LCK5_Pos               (5U)
7991 #define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */
7992 #define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk
7993 #define GPIO_LCKR_LCK6_Pos               (6U)
7994 #define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */
7995 #define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk
7996 #define GPIO_LCKR_LCK7_Pos               (7U)
7997 #define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */
7998 #define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk
7999 #define GPIO_LCKR_LCK8_Pos               (8U)
8000 #define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */
8001 #define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk
8002 #define GPIO_LCKR_LCK9_Pos               (9U)
8003 #define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */
8004 #define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk
8005 #define GPIO_LCKR_LCK10_Pos              (10U)
8006 #define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */
8007 #define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk
8008 #define GPIO_LCKR_LCK11_Pos              (11U)
8009 #define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */
8010 #define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk
8011 #define GPIO_LCKR_LCK12_Pos              (12U)
8012 #define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */
8013 #define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk
8014 #define GPIO_LCKR_LCK13_Pos              (13U)
8015 #define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */
8016 #define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk
8017 #define GPIO_LCKR_LCK14_Pos              (14U)
8018 #define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */
8019 #define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk
8020 #define GPIO_LCKR_LCK15_Pos              (15U)
8021 #define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */
8022 #define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk
8023 #define GPIO_LCKR_LCKK_Pos               (16U)
8024 #define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */
8025 #define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk
8026 
8027 /****************** Bit definition for GPIO_AFRL register  ********************/
8028 #define GPIO_AFRL_AFRL0_Pos              (0U)
8029 #define GPIO_AFRL_AFRL0_Msk              (0xFUL << GPIO_AFRL_AFRL0_Pos)         /*!< 0x0000000F */
8030 #define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFRL0_Msk
8031 #define GPIO_AFRL_AFRL1_Pos              (4U)
8032 #define GPIO_AFRL_AFRL1_Msk              (0xFUL << GPIO_AFRL_AFRL1_Pos)         /*!< 0x000000F0 */
8033 #define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFRL1_Msk
8034 #define GPIO_AFRL_AFRL2_Pos              (8U)
8035 #define GPIO_AFRL_AFRL2_Msk              (0xFUL << GPIO_AFRL_AFRL2_Pos)         /*!< 0x00000F00 */
8036 #define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFRL2_Msk
8037 #define GPIO_AFRL_AFRL3_Pos              (12U)
8038 #define GPIO_AFRL_AFRL3_Msk              (0xFUL << GPIO_AFRL_AFRL3_Pos)         /*!< 0x0000F000 */
8039 #define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFRL3_Msk
8040 #define GPIO_AFRL_AFRL4_Pos              (16U)
8041 #define GPIO_AFRL_AFRL4_Msk              (0xFUL << GPIO_AFRL_AFRL4_Pos)         /*!< 0x000F0000 */
8042 #define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFRL4_Msk
8043 #define GPIO_AFRL_AFRL5_Pos              (20U)
8044 #define GPIO_AFRL_AFRL5_Msk              (0xFUL << GPIO_AFRL_AFRL5_Pos)         /*!< 0x00F00000 */
8045 #define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFRL5_Msk
8046 #define GPIO_AFRL_AFRL6_Pos              (24U)
8047 #define GPIO_AFRL_AFRL6_Msk              (0xFUL << GPIO_AFRL_AFRL6_Pos)         /*!< 0x0F000000 */
8048 #define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFRL6_Msk
8049 #define GPIO_AFRL_AFRL7_Pos              (28U)
8050 #define GPIO_AFRL_AFRL7_Msk              (0xFUL << GPIO_AFRL_AFRL7_Pos)         /*!< 0xF0000000 */
8051 #define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFRL7_Msk
8052 
8053 /****************** Bit definition for GPIO_AFRH register  ********************/
8054 #define GPIO_AFRH_AFRH0_Pos              (0U)
8055 #define GPIO_AFRH_AFRH0_Msk              (0xFUL << GPIO_AFRH_AFRH0_Pos)         /*!< 0x0000000F */
8056 #define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFRH0_Msk
8057 #define GPIO_AFRH_AFRH1_Pos              (4U)
8058 #define GPIO_AFRH_AFRH1_Msk              (0xFUL << GPIO_AFRH_AFRH1_Pos)         /*!< 0x000000F0 */
8059 #define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFRH1_Msk
8060 #define GPIO_AFRH_AFRH2_Pos              (8U)
8061 #define GPIO_AFRH_AFRH2_Msk              (0xFUL << GPIO_AFRH_AFRH2_Pos)         /*!< 0x00000F00 */
8062 #define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFRH2_Msk
8063 #define GPIO_AFRH_AFRH3_Pos              (12U)
8064 #define GPIO_AFRH_AFRH3_Msk              (0xFUL << GPIO_AFRH_AFRH3_Pos)         /*!< 0x0000F000 */
8065 #define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFRH3_Msk
8066 #define GPIO_AFRH_AFRH4_Pos              (16U)
8067 #define GPIO_AFRH_AFRH4_Msk              (0xFUL << GPIO_AFRH_AFRH4_Pos)         /*!< 0x000F0000 */
8068 #define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFRH4_Msk
8069 #define GPIO_AFRH_AFRH5_Pos              (20U)
8070 #define GPIO_AFRH_AFRH5_Msk              (0xFUL << GPIO_AFRH_AFRH5_Pos)         /*!< 0x00F00000 */
8071 #define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFRH5_Msk
8072 #define GPIO_AFRH_AFRH6_Pos              (24U)
8073 #define GPIO_AFRH_AFRH6_Msk              (0xFUL << GPIO_AFRH_AFRH6_Pos)         /*!< 0x0F000000 */
8074 #define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFRH6_Msk
8075 #define GPIO_AFRH_AFRH7_Pos              (28U)
8076 #define GPIO_AFRH_AFRH7_Msk              (0xFUL << GPIO_AFRH_AFRH7_Pos)         /*!< 0xF0000000 */
8077 #define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFRH7_Msk
8078 
8079 /****************** Bit definition for GPIO_BRR register  *********************/
8080 #define GPIO_BRR_BR_0                    (0x00000001U)
8081 #define GPIO_BRR_BR_1                    (0x00000002U)
8082 #define GPIO_BRR_BR_2                    (0x00000004U)
8083 #define GPIO_BRR_BR_3                    (0x00000008U)
8084 #define GPIO_BRR_BR_4                    (0x00000010U)
8085 #define GPIO_BRR_BR_5                    (0x00000020U)
8086 #define GPIO_BRR_BR_6                    (0x00000040U)
8087 #define GPIO_BRR_BR_7                    (0x00000080U)
8088 #define GPIO_BRR_BR_8                    (0x00000100U)
8089 #define GPIO_BRR_BR_9                    (0x00000200U)
8090 #define GPIO_BRR_BR_10                   (0x00000400U)
8091 #define GPIO_BRR_BR_11                   (0x00000800U)
8092 #define GPIO_BRR_BR_12                   (0x00001000U)
8093 #define GPIO_BRR_BR_13                   (0x00002000U)
8094 #define GPIO_BRR_BR_14                   (0x00004000U)
8095 #define GPIO_BRR_BR_15                   (0x00008000U)
8096 
8097 /******************************************************************************/
8098 /*                                                                            */
8099 /*                        High Resolution Timer (HRTIM)                       */
8100 /*                                                                            */
8101 /******************************************************************************/
8102 /******************** Master Timer control register ***************************/
8103 #define HRTIM_MCR_CK_PSC_Pos          (0U)
8104 #define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000007 */
8105 #define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */
8106 #define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */
8107 #define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */
8108 #define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */
8109 
8110 #define HRTIM_MCR_CONT_Pos            (3U)
8111 #define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)             /*!< 0x00000008 */
8112 #define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */
8113 #define HRTIM_MCR_RETRIG_Pos          (4U)
8114 #define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)           /*!< 0x00000010 */
8115 #define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */
8116 #define HRTIM_MCR_HALF_Pos            (5U)
8117 #define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)             /*!< 0x00000020 */
8118 #define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */
8119 
8120 #define HRTIM_MCR_SYNC_IN_Pos         (8U)
8121 #define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000300 */
8122 #define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */
8123 #define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */
8124 #define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */
8125 #define HRTIM_MCR_SYNCRSTM_Pos        (10U)
8126 #define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)         /*!< 0x00000400 */
8127 #define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */
8128 #define HRTIM_MCR_SYNCSTRTM_Pos       (11U)
8129 #define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)        /*!< 0x00000800 */
8130 #define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */
8131 #define HRTIM_MCR_SYNC_OUT_Pos        (12U)
8132 #define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00003000 */
8133 #define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */
8134 #define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */
8135 #define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */
8136 #define HRTIM_MCR_SYNC_SRC_Pos        (14U)
8137 #define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x0000C000 */
8138 #define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */
8139 #define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */
8140 #define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */
8141 
8142 #define HRTIM_MCR_MCEN_Pos            (16U)
8143 #define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)             /*!< 0x00010000 */
8144 #define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */
8145 #define HRTIM_MCR_TACEN_Pos           (17U)
8146 #define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)            /*!< 0x00020000 */
8147 #define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */
8148 #define HRTIM_MCR_TBCEN_Pos           (18U)
8149 #define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)            /*!< 0x00040000 */
8150 #define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */
8151 #define HRTIM_MCR_TCCEN_Pos           (19U)
8152 #define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)            /*!< 0x00080000 */
8153 #define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */
8154 #define HRTIM_MCR_TDCEN_Pos           (20U)
8155 #define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)            /*!< 0x00100000 */
8156 #define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */
8157 #define HRTIM_MCR_TECEN_Pos           (21U)
8158 #define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)            /*!< 0x00200000 */
8159 #define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */
8160 
8161 #define HRTIM_MCR_DACSYNC_Pos         (25U)
8162 #define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x06000000 */
8163 #define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */
8164 #define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */
8165 #define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */
8166 
8167 #define HRTIM_MCR_PREEN_Pos           (27U)
8168 #define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)            /*!< 0x08000000 */
8169 #define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */
8170 #define HRTIM_MCR_MREPU_Pos           (29U)
8171 #define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)            /*!< 0x20000000 */
8172 #define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */
8173 
8174 #define HRTIM_MCR_BRSTDMA_Pos         (30U)
8175 #define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0xC0000000 */
8176 #define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */
8177 #define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */
8178 #define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */
8179 
8180 /******************** Master Timer Interrupt status register ******************/
8181 #define HRTIM_MISR_MCMP1_Pos          (0U)
8182 #define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)           /*!< 0x00000001 */
8183 #define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */
8184 #define HRTIM_MISR_MCMP2_Pos          (1U)
8185 #define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)           /*!< 0x00000002 */
8186 #define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */
8187 #define HRTIM_MISR_MCMP3_Pos          (2U)
8188 #define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)           /*!< 0x00000004 */
8189 #define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */
8190 #define HRTIM_MISR_MCMP4_Pos          (3U)
8191 #define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)           /*!< 0x00000008 */
8192 #define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */
8193 #define HRTIM_MISR_MREP_Pos           (4U)
8194 #define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)            /*!< 0x00000010 */
8195 #define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */
8196 #define HRTIM_MISR_SYNC_Pos           (5U)
8197 #define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)            /*!< 0x00000020 */
8198 #define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */
8199 #define HRTIM_MISR_MUPD_Pos           (6U)
8200 #define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)            /*!< 0x00000040 */
8201 #define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */
8202 
8203 /******************** Master Timer Interrupt clear register *******************/
8204 #define HRTIM_MICR_MCMP1_Pos          (0U)
8205 #define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)           /*!< 0x00000001 */
8206 #define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */
8207 #define HRTIM_MICR_MCMP2_Pos          (1U)
8208 #define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)           /*!< 0x00000002 */
8209 #define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */
8210 #define HRTIM_MICR_MCMP3_Pos          (2U)
8211 #define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)           /*!< 0x00000004 */
8212 #define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */
8213 #define HRTIM_MICR_MCMP4_Pos          (3U)
8214 #define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)           /*!< 0x00000008 */
8215 #define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */
8216 #define HRTIM_MICR_MREP_Pos           (4U)
8217 #define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)            /*!< 0x00000010 */
8218 #define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */
8219 #define HRTIM_MICR_SYNC_Pos           (5U)
8220 #define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)            /*!< 0x00000020 */
8221 #define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */
8222 #define HRTIM_MICR_MUPD_Pos           (6U)
8223 #define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)            /*!< 0x00000040 */
8224 #define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */
8225 
8226 /******************** Master Timer DMA/Interrupt enable register **************/
8227 #define HRTIM_MDIER_MCMP1IE_Pos       (0U)
8228 #define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)        /*!< 0x00000001 */
8229 #define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */
8230 #define HRTIM_MDIER_MCMP2IE_Pos       (1U)
8231 #define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)        /*!< 0x00000002 */
8232 #define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */
8233 #define HRTIM_MDIER_MCMP3IE_Pos       (2U)
8234 #define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)        /*!< 0x00000004 */
8235 #define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */
8236 #define HRTIM_MDIER_MCMP4IE_Pos       (3U)
8237 #define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)        /*!< 0x00000008 */
8238 #define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */
8239 #define HRTIM_MDIER_MREPIE_Pos        (4U)
8240 #define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)         /*!< 0x00000010 */
8241 #define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */
8242 #define HRTIM_MDIER_SYNCIE_Pos        (5U)
8243 #define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)         /*!< 0x00000020 */
8244 #define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */
8245 #define HRTIM_MDIER_MUPDIE_Pos        (6U)
8246 #define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)         /*!< 0x00000040 */
8247 #define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */
8248 
8249 #define HRTIM_MDIER_MCMP1DE_Pos       (16U)
8250 #define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)        /*!< 0x00010000 */
8251 #define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */
8252 #define HRTIM_MDIER_MCMP2DE_Pos       (17U)
8253 #define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)        /*!< 0x00020000 */
8254 #define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */
8255 #define HRTIM_MDIER_MCMP3DE_Pos       (18U)
8256 #define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)        /*!< 0x00040000 */
8257 #define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */
8258 #define HRTIM_MDIER_MCMP4DE_Pos       (19U)
8259 #define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)        /*!< 0x00080000 */
8260 #define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */
8261 #define HRTIM_MDIER_MREPDE_Pos        (20U)
8262 #define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)         /*!< 0x00100000 */
8263 #define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */
8264 #define HRTIM_MDIER_SYNCDE_Pos        (21U)
8265 #define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)         /*!< 0x00200000 */
8266 #define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */
8267 #define HRTIM_MDIER_MUPDDE_Pos        (22U)
8268 #define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)         /*!< 0x00400000 */
8269 #define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */
8270 
8271 /*******************  Bit definition for HRTIM_MCNTR register  ****************/
8272 #define HRTIM_MCNTR_MCNTR_Pos         (0U)
8273 #define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0xFFFF */
8274 #define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */
8275 
8276 /*******************  Bit definition for HRTIM_MPER register  *****************/
8277 #define HRTIM_MPER_MPER_Pos           (0U)
8278 #define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0xFFFF */
8279 #define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */
8280 
8281 /*******************  Bit definition for HRTIM_MREP register  *****************/
8282 #define HRTIM_MREP_MREP_Pos           (0U)
8283 #define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0xFF */
8284 #define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */
8285 
8286 /*******************  Bit definition for HRTIM_MCMP1R register  *****************/
8287 #define HRTIM_MCMP1R_MCMP1R_Pos       (0U)
8288 #define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0xFFFF */
8289 #define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */
8290 
8291 /*******************  Bit definition for HRTIM_MCMP2R register  *****************/
8292 #define HRTIM_MCMP2R_MCMP2R_Pos       (0U)
8293 #define HRTIM_MCMP2R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP2R_MCMP2R_Pos)    /*!< 0xFFFF */
8294 #define HRTIM_MCMP2R_MCMP2R           HRTIM_MCMP2R_MCMP2R_Msk                  /*!<Compare Value */
8295 
8296 /*******************  Bit definition for HRTIM_MCMP3R register  *****************/
8297 #define HRTIM_MCMP3R_MCMP3R_Pos       (0U)
8298 #define HRTIM_MCMP3R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP3R_MCMP3R_Pos)    /*!< 0xFFFF */
8299 #define HRTIM_MCMP3R_MCMP3R           HRTIM_MCMP3R_MCMP3R_Msk                  /*!<Compare Value */
8300 
8301 /*******************  Bit definition for HRTIM_MCMP4R register  *****************/
8302 #define HRTIM_MCMP4R_MCMP4R_Pos       (0U)
8303 #define HRTIM_MCMP4R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP4R_MCMP4R_Pos)    /*!< 0xFFFF */
8304 #define HRTIM_MCMP4R_MCMP4R           HRTIM_MCMP4R_MCMP4R_Msk                  /*!<Compare Value */
8305 
8306 /* Legacy defines */
8307 #define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP2R_MCMP2R
8308 #define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP3R_MCMP3R
8309 #define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP4R_MCMP4R
8310 
8311 /******************** Slave control register **********************************/
8312 #define HRTIM_TIMCR_CK_PSC_Pos        (0U)
8313 #define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000007 */
8314 #define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/
8315 #define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */
8316 #define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */
8317 #define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */
8318 
8319 #define HRTIM_TIMCR_CONT_Pos          (3U)
8320 #define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)           /*!< 0x00000008 */
8321 #define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */
8322 #define HRTIM_TIMCR_RETRIG_Pos        (4U)
8323 #define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)         /*!< 0x00000010 */
8324 #define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */
8325 #define HRTIM_TIMCR_HALF_Pos          (5U)
8326 #define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)           /*!< 0x00000020 */
8327 #define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */
8328 #define HRTIM_TIMCR_PSHPLL_Pos        (6U)
8329 #define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)         /*!< 0x00000040 */
8330 #define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */
8331 
8332 #define HRTIM_TIMCR_SYNCRST_Pos       (10U)
8333 #define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)        /*!< 0x00000400 */
8334 #define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */
8335 #define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)
8336 #define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)       /*!< 0x00000800 */
8337 #define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */
8338 
8339 #define HRTIM_TIMCR_DELCMP2_Pos       (12U)
8340 #define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00003000 */
8341 #define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */
8342 #define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */
8343 #define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */
8344 #define HRTIM_TIMCR_DELCMP4_Pos       (14U)
8345 #define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x0000C000 */
8346 #define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */
8347 #define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */
8348 #define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */
8349 
8350 #define HRTIM_TIMCR_TREPU_Pos         (17U)
8351 #define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)          /*!< 0x00020000 */
8352 #define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */
8353 #define HRTIM_TIMCR_TRSTU_Pos         (18U)
8354 #define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)          /*!< 0x00040000 */
8355 #define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */
8356 #define HRTIM_TIMCR_TAU_Pos           (19U)
8357 #define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)            /*!< 0x00080000 */
8358 #define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */
8359 #define HRTIM_TIMCR_TBU_Pos           (20U)
8360 #define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)            /*!< 0x00100000 */
8361 #define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */
8362 #define HRTIM_TIMCR_TCU_Pos           (21U)
8363 #define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)            /*!< 0x00200000 */
8364 #define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */
8365 #define HRTIM_TIMCR_TDU_Pos           (22U)
8366 #define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)            /*!< 0x00400000 */
8367 #define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */
8368 #define HRTIM_TIMCR_TEU_Pos           (23U)
8369 #define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)            /*!< 0x00800000 */
8370 #define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */
8371 #define HRTIM_TIMCR_MSTU_Pos          (24U)
8372 #define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)           /*!< 0x01000000 */
8373 #define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */
8374 
8375 #define HRTIM_TIMCR_DACSYNC_Pos       (25U)
8376 #define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x06000000 */
8377 #define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */
8378 #define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */
8379 #define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */
8380 #define HRTIM_TIMCR_PREEN_Pos         (27U)
8381 #define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)          /*!< 0x08000000 */
8382 #define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */
8383 
8384 #define HRTIM_TIMCR_UPDGAT_Pos        (28U)
8385 #define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0xF0000000 */
8386 #define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */
8387 #define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */
8388 #define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */
8389 #define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */
8390 #define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */
8391 
8392 /******************** Slave Interrupt status register **************************/
8393 /* Aliases to keep compatibility after HRTIM_TIMICR_DLYPRTxC constants removal */
8394 #define HRTIM_TIMICR_DLYPRT1C_Pos     HRTIM_TIMICR_RSTC_Pos
8395 #define HRTIM_TIMICR_DLYPRT1C_Msk     HRTIM_TIMICR_DLYPRTC_Msk
8396 #define HRTIM_TIMICR_DLYPRT1C         HRTIM_TIMICR_DLYPRTC
8397 #define HRTIM_TIMICR_DLYPRT2C_Pos     HRTIM_TIMICR_RSTC_Pos
8398 #define HRTIM_TIMICR_DLYPRT2C_Msk     HRTIM_TIMICR_DLYPRTC_Msk
8399 #define HRTIM_TIMICR_DLYPRT2C         HRTIM_TIMICR_DLYPRTC
8400 
8401 #define HRTIM_TIMISR_CMP1_Pos         (0U)
8402 #define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)          /*!< 0x00000001 */
8403 #define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */
8404 #define HRTIM_TIMISR_CMP2_Pos         (1U)
8405 #define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)          /*!< 0x00000002 */
8406 #define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */
8407 #define HRTIM_TIMISR_CMP3_Pos         (2U)
8408 #define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)          /*!< 0x00000004 */
8409 #define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */
8410 #define HRTIM_TIMISR_CMP4_Pos         (3U)
8411 #define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)          /*!< 0x00000008 */
8412 #define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */
8413 #define HRTIM_TIMISR_REP_Pos          (4U)
8414 #define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)           /*!< 0x00000010 */
8415 #define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */
8416 #define HRTIM_TIMISR_UPD_Pos          (6U)
8417 #define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)           /*!< 0x00000040 */
8418 #define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */
8419 #define HRTIM_TIMISR_CPT1_Pos         (7U)
8420 #define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)          /*!< 0x00000080 */
8421 #define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */
8422 #define HRTIM_TIMISR_CPT2_Pos         (8U)
8423 #define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)          /*!< 0x00000100 */
8424 #define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */
8425 #define HRTIM_TIMISR_SET1_Pos         (9U)
8426 #define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)          /*!< 0x00000200 */
8427 #define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */
8428 #define HRTIM_TIMISR_RST1_Pos         (10U)
8429 #define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)          /*!< 0x00000400 */
8430 #define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */
8431 #define HRTIM_TIMISR_SET2_Pos         (11U)
8432 #define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)          /*!< 0x00000800 */
8433 #define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */
8434 #define HRTIM_TIMISR_RST2_Pos         (12U)
8435 #define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)          /*!< 0x00001000 */
8436 #define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */
8437 #define HRTIM_TIMISR_RST_Pos          (13U)
8438 #define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)           /*!< 0x00002000 */
8439 #define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */
8440 #define HRTIM_TIMISR_DLYPRT_Pos       (14U)
8441 #define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)        /*!< 0x00004000 */
8442 #define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Delay protection clear flag */
8443 #define HRTIM_TIMISR_CPPSTAT_Pos      (16U)
8444 #define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)       /*!< 0x00010000 */
8445 #define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */
8446 #define HRTIM_TIMISR_IPPSTAT_Pos      (17U)
8447 #define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)       /*!< 0x00020000 */
8448 #define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */
8449 #define HRTIM_TIMISR_O1STAT_Pos       (18U)
8450 #define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)        /*!< 0x00040000 */
8451 #define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */
8452 #define HRTIM_TIMISR_O2STAT_Pos       (19U)
8453 #define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)        /*!< 0x00080000 */
8454 #define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */
8455 #define HRTIM_TIMISR_O1CPY_Pos        (20U)
8456 #define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)         /*!< 0x00100000 */
8457 #define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */
8458 #define HRTIM_TIMISR_O2CPY_Pos        (21U)
8459 #define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)         /*!< 0x00200000 */
8460 #define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */
8461 
8462 /******************** Slave Interrupt clear register **************************/
8463 #define HRTIM_TIMICR_CMP1C_Pos        (0U)
8464 #define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)         /*!< 0x00000001 */
8465 #define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */
8466 #define HRTIM_TIMICR_CMP2C_Pos        (1U)
8467 #define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)         /*!< 0x00000002 */
8468 #define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */
8469 #define HRTIM_TIMICR_CMP3C_Pos        (2U)
8470 #define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)         /*!< 0x00000004 */
8471 #define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */
8472 #define HRTIM_TIMICR_CMP4C_Pos        (3U)
8473 #define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)         /*!< 0x00000008 */
8474 #define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */
8475 #define HRTIM_TIMICR_REPC_Pos         (4U)
8476 #define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)          /*!< 0x00000010 */
8477 #define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */
8478 #define HRTIM_TIMICR_UPDC_Pos         (6U)
8479 #define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)          /*!< 0x00000040 */
8480 #define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */
8481 #define HRTIM_TIMICR_CPT1C_Pos        (7U)
8482 #define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)         /*!< 0x00000080 */
8483 #define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */
8484 #define HRTIM_TIMICR_CPT2C_Pos        (8U)
8485 #define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)         /*!< 0x00000100 */
8486 #define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */
8487 #define HRTIM_TIMICR_SET1C_Pos        (9U)
8488 #define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)         /*!< 0x00000200 */
8489 #define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */
8490 #define HRTIM_TIMICR_RST1C_Pos        (10U)
8491 #define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)         /*!< 0x00000400 */
8492 #define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */
8493 #define HRTIM_TIMICR_SET2C_Pos        (11U)
8494 #define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)         /*!< 0x00000800 */
8495 #define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */
8496 #define HRTIM_TIMICR_RST2C_Pos        (12U)
8497 #define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)         /*!< 0x00001000 */
8498 #define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */
8499 #define HRTIM_TIMICR_RSTC_Pos         (13U)
8500 #define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)          /*!< 0x00002000 */
8501 #define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */
8502 #define HRTIM_TIMICR_DLYPRTC_Pos      (14U)
8503 #define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */
8504 #define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                /*!< Slave output 1 delay protection clear flag */
8505 
8506 /******************** Slave DMA/Interrupt enable register *********************/
8507 #define HRTIM_TIMDIER_CMP1IE_Pos      (0U)
8508 #define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)       /*!< 0x00000001 */
8509 #define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */
8510 #define HRTIM_TIMDIER_CMP2IE_Pos      (1U)
8511 #define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)       /*!< 0x00000002 */
8512 #define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */
8513 #define HRTIM_TIMDIER_CMP3IE_Pos      (2U)
8514 #define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)       /*!< 0x00000004 */
8515 #define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */
8516 #define HRTIM_TIMDIER_CMP4IE_Pos      (3U)
8517 #define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)       /*!< 0x00000008 */
8518 #define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */
8519 #define HRTIM_TIMDIER_REPIE_Pos       (4U)
8520 #define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)        /*!< 0x00000010 */
8521 #define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */
8522 #define HRTIM_TIMDIER_UPDIE_Pos       (6U)
8523 #define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)        /*!< 0x00000040 */
8524 #define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */
8525 #define HRTIM_TIMDIER_CPT1IE_Pos      (7U)
8526 #define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)       /*!< 0x00000080 */
8527 #define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */
8528 #define HRTIM_TIMDIER_CPT2IE_Pos      (8U)
8529 #define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)       /*!< 0x00000100 */
8530 #define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */
8531 #define HRTIM_TIMDIER_SET1IE_Pos      (9U)
8532 #define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)       /*!< 0x00000200 */
8533 #define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */
8534 #define HRTIM_TIMDIER_RST1IE_Pos      (10U)
8535 #define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)       /*!< 0x00000400 */
8536 #define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */
8537 #define HRTIM_TIMDIER_SET2IE_Pos      (11U)
8538 #define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)       /*!< 0x00000800 */
8539 #define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */
8540 #define HRTIM_TIMDIER_RST2IE_Pos      (12U)
8541 #define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)       /*!< 0x00001000 */
8542 #define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */
8543 #define HRTIM_TIMDIER_RSTIE_Pos       (13U)
8544 #define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)        /*!< 0x00002000 */
8545 #define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */
8546 #define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)
8547 #define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)     /*!< 0x00004000 */
8548 #define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */
8549 
8550 #define HRTIM_TIMDIER_CMP1DE_Pos      (16U)
8551 #define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)       /*!< 0x00010000 */
8552 #define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */
8553 #define HRTIM_TIMDIER_CMP2DE_Pos      (17U)
8554 #define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)       /*!< 0x00020000 */
8555 #define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */
8556 #define HRTIM_TIMDIER_CMP3DE_Pos      (18U)
8557 #define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)       /*!< 0x00040000 */
8558 #define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */
8559 #define HRTIM_TIMDIER_CMP4DE_Pos      (19U)
8560 #define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)       /*!< 0x00080000 */
8561 #define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */
8562 #define HRTIM_TIMDIER_REPDE_Pos       (20U)
8563 #define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)        /*!< 0x00100000 */
8564 #define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */
8565 #define HRTIM_TIMDIER_UPDDE_Pos       (22U)
8566 #define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)        /*!< 0x00400000 */
8567 #define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */
8568 #define HRTIM_TIMDIER_CPT1DE_Pos      (23U)
8569 #define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)       /*!< 0x00800000 */
8570 #define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */
8571 #define HRTIM_TIMDIER_CPT2DE_Pos      (24U)
8572 #define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)       /*!< 0x01000000 */
8573 #define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */
8574 #define HRTIM_TIMDIER_SET1DE_Pos      (25U)
8575 #define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)       /*!< 0x02000000 */
8576 #define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */
8577 #define HRTIM_TIMDIER_RST1DE_Pos      (26U)
8578 #define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)       /*!< 0x04000000 */
8579 #define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */
8580 #define HRTIM_TIMDIER_SET2DE_Pos      (27U)
8581 #define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)       /*!< 0x08000000 */
8582 #define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */
8583 #define HRTIM_TIMDIER_RST2DE_Pos      (28U)
8584 #define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)       /*!< 0x10000000 */
8585 #define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */
8586 #define HRTIM_TIMDIER_RSTDE_Pos       (29U)
8587 #define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)        /*!< 0x20000000 */
8588 #define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */
8589 #define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)
8590 #define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)     /*!< 0x40000000 */
8591 #define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */
8592 
8593 /******************  Bit definition for HRTIM_CNTR register  ****************/
8594 #define HRTIM_CNTR_CNTR_Pos           (0U)
8595 #define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0xFFFF */
8596 #define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */
8597 
8598 /*******************  Bit definition for HRTIM_PER register  *****************/
8599 #define HRTIM_PER_PER_Pos             (0U)
8600 #define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0xFFFF */
8601 #define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */
8602 
8603 /*******************  Bit definition for HRTIM_REP register  *****************/
8604 #define HRTIM_REP_REP_Pos             (0U)
8605 #define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0xFF */
8606 #define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */
8607 
8608 /*******************  Bit definition for HRTIM_CMP1R register  *****************/
8609 #define HRTIM_CMP1R_CMP1R_Pos         (0U)
8610 #define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0xFFFF */
8611 #define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */
8612 
8613 /*******************  Bit definition for HRTIM_CMP1CR register  *****************/
8614 #define HRTIM_CMP1CR_CMP1CR_Pos       (0U)
8615 #define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos)    /*!< 0xFFFF */
8616 #define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */
8617 
8618 /*******************  Bit definition for HRTIM_CMP2R register  *****************/
8619 #define HRTIM_CMP2R_CMP2R_Pos         (0U)
8620 #define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0xFFFF */
8621 #define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */
8622 
8623 /*******************  Bit definition for HRTIM_CMP3R register  *****************/
8624 #define HRTIM_CMP3R_CMP3R_Pos         (0U)
8625 #define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0xFFFF */
8626 #define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */
8627 
8628 /*******************  Bit definition for HRTIM_CMP4R register  *****************/
8629 #define HRTIM_CMP4R_CMP4R_Pos         (0U)
8630 #define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0xFFFF */
8631 #define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */
8632 
8633 /*******************  Bit definition for HRTIM_CPT1R register  ****************/
8634 #define HRTIM_CPT1R_CPT1R_Pos         (0U)
8635 #define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0xFFFF */
8636 #define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */
8637 
8638 /*******************  Bit definition for HRTIM_CPT2R register  ****************/
8639 #define HRTIM_CPT2R_CPT2R_Pos         (0U)
8640 #define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0xFFFF */
8641 #define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */
8642 
8643 /******************** Bit definition for Slave Deadtime register **************/
8644 #define HRTIM_DTR_DTR_Pos             (0U)
8645 #define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)            /*!< 0x000001FF */
8646 #define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */
8647 #define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */
8648 #define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */
8649 #define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */
8650 #define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */
8651 #define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */
8652 #define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */
8653 #define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */
8654 #define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */
8655 #define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */
8656 #define HRTIM_DTR_SDTR_Pos            (9U)
8657 #define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)             /*!< 0x00000200 */
8658 #define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */
8659 #define HRTIM_DTR_DTPRSC_Pos          (10U)
8660 #define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001C00 */
8661 #define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */
8662 #define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */
8663 #define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */
8664 #define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */
8665 #define HRTIM_DTR_DTRSLK_Pos          (14U)
8666 #define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)           /*!< 0x00004000 */
8667 #define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */
8668 #define HRTIM_DTR_DTRLK_Pos           (15U)
8669 #define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)            /*!< 0x00008000 */
8670 #define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */
8671 #define HRTIM_DTR_DTF_Pos             (16U)
8672 #define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)            /*!< 0x01FF0000 */
8673 #define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */
8674 #define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */
8675 #define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */
8676 #define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */
8677 #define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */
8678 #define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */
8679 #define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */
8680 #define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */
8681 #define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */
8682 #define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */
8683 #define HRTIM_DTR_SDTF_Pos            (25U)
8684 #define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)             /*!< 0x02000000 */
8685 #define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */
8686 #define HRTIM_DTR_DTFSLK_Pos          (30U)
8687 #define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)           /*!< 0x40000000 */
8688 #define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */
8689 #define HRTIM_DTR_DTFLK_Pos           (31U)
8690 #define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)            /*!< 0x80000000 */
8691 #define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */
8692 
8693 /**** Bit definition for Slave Output 1 set register **************************/
8694 #define HRTIM_SET1R_SST_Pos           (0U)
8695 #define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)            /*!< 0x00000001 */
8696 #define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */
8697 #define HRTIM_SET1R_RESYNC_Pos        (1U)
8698 #define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)         /*!< 0x00000002 */
8699 #define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */
8700 #define HRTIM_SET1R_PER_Pos           (2U)
8701 #define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)            /*!< 0x00000004 */
8702 #define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */
8703 #define HRTIM_SET1R_CMP1_Pos          (3U)
8704 #define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)           /*!< 0x00000008 */
8705 #define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */
8706 #define HRTIM_SET1R_CMP2_Pos          (4U)
8707 #define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)           /*!< 0x00000010 */
8708 #define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */
8709 #define HRTIM_SET1R_CMP3_Pos          (5U)
8710 #define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)           /*!< 0x00000020 */
8711 #define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */
8712 #define HRTIM_SET1R_CMP4_Pos          (6U)
8713 #define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)           /*!< 0x00000040 */
8714 #define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */
8715 
8716 #define HRTIM_SET1R_MSTPER_Pos        (7U)
8717 #define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)         /*!< 0x00000080 */
8718 #define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */
8719 #define HRTIM_SET1R_MSTCMP1_Pos       (8U)
8720 #define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)        /*!< 0x00000100 */
8721 #define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */
8722 #define HRTIM_SET1R_MSTCMP2_Pos       (9U)
8723 #define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)        /*!< 0x00000200 */
8724 #define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */
8725 #define HRTIM_SET1R_MSTCMP3_Pos       (10U)
8726 #define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)        /*!< 0x00000400 */
8727 #define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */
8728 #define HRTIM_SET1R_MSTCMP4_Pos       (11U)
8729 #define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)        /*!< 0x00000800 */
8730 #define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */
8731 
8732 #define HRTIM_SET1R_TIMEVNT1_Pos      (12U)
8733 #define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)       /*!< 0x00001000 */
8734 #define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
8735 #define HRTIM_SET1R_TIMEVNT2_Pos      (13U)
8736 #define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)       /*!< 0x00002000 */
8737 #define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
8738 #define HRTIM_SET1R_TIMEVNT3_Pos      (14U)
8739 #define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)       /*!< 0x00004000 */
8740 #define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
8741 #define HRTIM_SET1R_TIMEVNT4_Pos      (15U)
8742 #define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)       /*!< 0x00008000 */
8743 #define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
8744 #define HRTIM_SET1R_TIMEVNT5_Pos      (16U)
8745 #define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)       /*!< 0x00010000 */
8746 #define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
8747 #define HRTIM_SET1R_TIMEVNT6_Pos      (17U)
8748 #define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)       /*!< 0x00020000 */
8749 #define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
8750 #define HRTIM_SET1R_TIMEVNT7_Pos      (18U)
8751 #define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)       /*!< 0x00040000 */
8752 #define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
8753 #define HRTIM_SET1R_TIMEVNT8_Pos      (19U)
8754 #define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)       /*!< 0x00080000 */
8755 #define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
8756 #define HRTIM_SET1R_TIMEVNT9_Pos      (20U)
8757 #define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)       /*!< 0x00100000 */
8758 #define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
8759 
8760 #define HRTIM_SET1R_EXTVNT1_Pos       (21U)
8761 #define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)        /*!< 0x00200000 */
8762 #define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */
8763 #define HRTIM_SET1R_EXTVNT2_Pos       (22U)
8764 #define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)        /*!< 0x00400000 */
8765 #define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */
8766 #define HRTIM_SET1R_EXTVNT3_Pos       (23U)
8767 #define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)        /*!< 0x00800000 */
8768 #define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */
8769 #define HRTIM_SET1R_EXTVNT4_Pos       (24U)
8770 #define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)        /*!< 0x01000000 */
8771 #define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */
8772 #define HRTIM_SET1R_EXTVNT5_Pos       (25U)
8773 #define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)        /*!< 0x02000000 */
8774 #define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */
8775 #define HRTIM_SET1R_EXTVNT6_Pos       (26U)
8776 #define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)        /*!< 0x04000000 */
8777 #define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */
8778 #define HRTIM_SET1R_EXTVNT7_Pos       (27U)
8779 #define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)        /*!< 0x08000000 */
8780 #define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */
8781 #define HRTIM_SET1R_EXTVNT8_Pos       (28U)
8782 #define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)        /*!< 0x10000000 */
8783 #define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */
8784 #define HRTIM_SET1R_EXTVNT9_Pos       (29U)
8785 #define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)        /*!< 0x20000000 */
8786 #define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */
8787 #define HRTIM_SET1R_EXTVNT10_Pos      (30U)
8788 #define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)       /*!< 0x40000000 */
8789 #define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */
8790 
8791 #define HRTIM_SET1R_UPDATE_Pos        (31U)
8792 #define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)         /*!< 0x80000000 */
8793 #define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
8794 
8795 /**** Bit definition for Slave Output 1 reset register ************************/
8796 #define HRTIM_RST1R_SRT_Pos           (0U)
8797 #define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)            /*!< 0x00000001 */
8798 #define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */
8799 #define HRTIM_RST1R_RESYNC_Pos        (1U)
8800 #define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)         /*!< 0x00000002 */
8801 #define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */
8802 #define HRTIM_RST1R_PER_Pos           (2U)
8803 #define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)            /*!< 0x00000004 */
8804 #define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */
8805 #define HRTIM_RST1R_CMP1_Pos          (3U)
8806 #define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)           /*!< 0x00000008 */
8807 #define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */
8808 #define HRTIM_RST1R_CMP2_Pos          (4U)
8809 #define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)           /*!< 0x00000010 */
8810 #define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */
8811 #define HRTIM_RST1R_CMP3_Pos          (5U)
8812 #define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)           /*!< 0x00000020 */
8813 #define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */
8814 #define HRTIM_RST1R_CMP4_Pos          (6U)
8815 #define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)           /*!< 0x00000040 */
8816 #define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */
8817 
8818 #define HRTIM_RST1R_MSTPER_Pos        (7U)
8819 #define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)         /*!< 0x00000080 */
8820 #define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */
8821 #define HRTIM_RST1R_MSTCMP1_Pos       (8U)
8822 #define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)        /*!< 0x00000100 */
8823 #define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */
8824 #define HRTIM_RST1R_MSTCMP2_Pos       (9U)
8825 #define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)        /*!< 0x00000200 */
8826 #define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */
8827 #define HRTIM_RST1R_MSTCMP3_Pos       (10U)
8828 #define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)        /*!< 0x00000400 */
8829 #define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */
8830 #define HRTIM_RST1R_MSTCMP4_Pos       (11U)
8831 #define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)        /*!< 0x00000800 */
8832 #define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */
8833 
8834 #define HRTIM_RST1R_TIMEVNT1_Pos      (12U)
8835 #define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)       /*!< 0x00001000 */
8836 #define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
8837 #define HRTIM_RST1R_TIMEVNT2_Pos      (13U)
8838 #define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)       /*!< 0x00002000 */
8839 #define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
8840 #define HRTIM_RST1R_TIMEVNT3_Pos      (14U)
8841 #define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)       /*!< 0x00004000 */
8842 #define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
8843 #define HRTIM_RST1R_TIMEVNT4_Pos      (15U)
8844 #define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)       /*!< 0x00008000 */
8845 #define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
8846 #define HRTIM_RST1R_TIMEVNT5_Pos      (16U)
8847 #define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)       /*!< 0x00010000 */
8848 #define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
8849 #define HRTIM_RST1R_TIMEVNT6_Pos      (17U)
8850 #define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)       /*!< 0x00020000 */
8851 #define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
8852 #define HRTIM_RST1R_TIMEVNT7_Pos      (18U)
8853 #define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)       /*!< 0x00040000 */
8854 #define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
8855 #define HRTIM_RST1R_TIMEVNT8_Pos      (19U)
8856 #define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)       /*!< 0x00080000 */
8857 #define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
8858 #define HRTIM_RST1R_TIMEVNT9_Pos      (20U)
8859 #define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)       /*!< 0x00100000 */
8860 #define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
8861 
8862 #define HRTIM_RST1R_EXTVNT1_Pos       (21U)
8863 #define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)        /*!< 0x00200000 */
8864 #define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */
8865 #define HRTIM_RST1R_EXTVNT2_Pos       (22U)
8866 #define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)        /*!< 0x00400000 */
8867 #define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */
8868 #define HRTIM_RST1R_EXTVNT3_Pos       (23U)
8869 #define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)        /*!< 0x00800000 */
8870 #define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */
8871 #define HRTIM_RST1R_EXTVNT4_Pos       (24U)
8872 #define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)        /*!< 0x01000000 */
8873 #define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */
8874 #define HRTIM_RST1R_EXTVNT5_Pos       (25U)
8875 #define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)        /*!< 0x02000000 */
8876 #define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */
8877 #define HRTIM_RST1R_EXTVNT6_Pos       (26U)
8878 #define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)        /*!< 0x04000000 */
8879 #define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */
8880 #define HRTIM_RST1R_EXTVNT7_Pos       (27U)
8881 #define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)        /*!< 0x08000000 */
8882 #define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */
8883 #define HRTIM_RST1R_EXTVNT8_Pos       (28U)
8884 #define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)        /*!< 0x10000000 */
8885 #define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */
8886 #define HRTIM_RST1R_EXTVNT9_Pos       (29U)
8887 #define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)        /*!< 0x20000000 */
8888 #define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */
8889 #define HRTIM_RST1R_EXTVNT10_Pos      (30U)
8890 #define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)       /*!< 0x40000000 */
8891 #define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */
8892 
8893 #define HRTIM_RST1R_UPDATE_Pos        (31U)
8894 #define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)         /*!< 0x80000000 */
8895 #define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
8896 
8897 
8898 /**** Bit definition for Slave Output 2 set register **************************/
8899 #define HRTIM_SET2R_SST_Pos           (0U)
8900 #define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)            /*!< 0x00000001 */
8901 #define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */
8902 #define HRTIM_SET2R_RESYNC_Pos        (1U)
8903 #define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)         /*!< 0x00000002 */
8904 #define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */
8905 #define HRTIM_SET2R_PER_Pos           (2U)
8906 #define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)            /*!< 0x00000004 */
8907 #define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */
8908 #define HRTIM_SET2R_CMP1_Pos          (3U)
8909 #define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)           /*!< 0x00000008 */
8910 #define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */
8911 #define HRTIM_SET2R_CMP2_Pos          (4U)
8912 #define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)           /*!< 0x00000010 */
8913 #define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */
8914 #define HRTIM_SET2R_CMP3_Pos          (5U)
8915 #define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)           /*!< 0x00000020 */
8916 #define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */
8917 #define HRTIM_SET2R_CMP4_Pos          (6U)
8918 #define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)           /*!< 0x00000040 */
8919 #define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */
8920 
8921 #define HRTIM_SET2R_MSTPER_Pos        (7U)
8922 #define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)         /*!< 0x00000080 */
8923 #define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */
8924 #define HRTIM_SET2R_MSTCMP1_Pos       (8U)
8925 #define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)        /*!< 0x00000100 */
8926 #define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */
8927 #define HRTIM_SET2R_MSTCMP2_Pos       (9U)
8928 #define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)        /*!< 0x00000200 */
8929 #define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */
8930 #define HRTIM_SET2R_MSTCMP3_Pos       (10U)
8931 #define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)        /*!< 0x00000400 */
8932 #define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */
8933 #define HRTIM_SET2R_MSTCMP4_Pos       (11U)
8934 #define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)        /*!< 0x00000800 */
8935 #define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */
8936 
8937 #define HRTIM_SET2R_TIMEVNT1_Pos      (12U)
8938 #define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)       /*!< 0x00001000 */
8939 #define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
8940 #define HRTIM_SET2R_TIMEVNT2_Pos      (13U)
8941 #define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)       /*!< 0x00002000 */
8942 #define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
8943 #define HRTIM_SET2R_TIMEVNT3_Pos      (14U)
8944 #define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)       /*!< 0x00004000 */
8945 #define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
8946 #define HRTIM_SET2R_TIMEVNT4_Pos      (15U)
8947 #define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)       /*!< 0x00008000 */
8948 #define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
8949 #define HRTIM_SET2R_TIMEVNT5_Pos      (16U)
8950 #define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)       /*!< 0x00010000 */
8951 #define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
8952 #define HRTIM_SET2R_TIMEVNT6_Pos      (17U)
8953 #define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)       /*!< 0x00020000 */
8954 #define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
8955 #define HRTIM_SET2R_TIMEVNT7_Pos      (18U)
8956 #define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)       /*!< 0x00040000 */
8957 #define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
8958 #define HRTIM_SET2R_TIMEVNT8_Pos      (19U)
8959 #define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)       /*!< 0x00080000 */
8960 #define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
8961 #define HRTIM_SET2R_TIMEVNT9_Pos      (20U)
8962 #define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)       /*!< 0x00100000 */
8963 #define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
8964 
8965 #define HRTIM_SET2R_EXTVNT1_Pos       (21U)
8966 #define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)        /*!< 0x00200000 */
8967 #define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */
8968 #define HRTIM_SET2R_EXTVNT2_Pos       (22U)
8969 #define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)        /*!< 0x00400000 */
8970 #define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */
8971 #define HRTIM_SET2R_EXTVNT3_Pos       (23U)
8972 #define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)        /*!< 0x00800000 */
8973 #define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */
8974 #define HRTIM_SET2R_EXTVNT4_Pos       (24U)
8975 #define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)        /*!< 0x01000000 */
8976 #define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */
8977 #define HRTIM_SET2R_EXTVNT5_Pos       (25U)
8978 #define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)        /*!< 0x02000000 */
8979 #define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */
8980 #define HRTIM_SET2R_EXTVNT6_Pos       (26U)
8981 #define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)        /*!< 0x04000000 */
8982 #define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */
8983 #define HRTIM_SET2R_EXTVNT7_Pos       (27U)
8984 #define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)        /*!< 0x08000000 */
8985 #define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */
8986 #define HRTIM_SET2R_EXTVNT8_Pos       (28U)
8987 #define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)        /*!< 0x10000000 */
8988 #define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */
8989 #define HRTIM_SET2R_EXTVNT9_Pos       (29U)
8990 #define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)        /*!< 0x20000000 */
8991 #define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */
8992 #define HRTIM_SET2R_EXTVNT10_Pos      (30U)
8993 #define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)       /*!< 0x40000000 */
8994 #define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */
8995 
8996 #define HRTIM_SET2R_UPDATE_Pos        (31U)
8997 #define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)         /*!< 0x80000000 */
8998 #define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
8999 
9000 /**** Bit definition for Slave Output 2 reset register ************************/
9001 #define HRTIM_RST2R_SRT_Pos           (0U)
9002 #define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)            /*!< 0x00000001 */
9003 #define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */
9004 #define HRTIM_RST2R_RESYNC_Pos        (1U)
9005 #define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)         /*!< 0x00000002 */
9006 #define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */
9007 #define HRTIM_RST2R_PER_Pos           (2U)
9008 #define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)            /*!< 0x00000004 */
9009 #define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */
9010 #define HRTIM_RST2R_CMP1_Pos          (3U)
9011 #define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)           /*!< 0x00000008 */
9012 #define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */
9013 #define HRTIM_RST2R_CMP2_Pos          (4U)
9014 #define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)           /*!< 0x00000010 */
9015 #define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */
9016 #define HRTIM_RST2R_CMP3_Pos          (5U)
9017 #define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)           /*!< 0x00000020 */
9018 #define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */
9019 #define HRTIM_RST2R_CMP4_Pos          (6U)
9020 #define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)           /*!< 0x00000040 */
9021 #define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */
9022 
9023 #define HRTIM_RST2R_MSTPER_Pos        (7U)
9024 #define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)         /*!< 0x00000080 */
9025 #define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */
9026 #define HRTIM_RST2R_MSTCMP1_Pos       (8U)
9027 #define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)        /*!< 0x00000100 */
9028 #define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */
9029 #define HRTIM_RST2R_MSTCMP2_Pos       (9U)
9030 #define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)        /*!< 0x00000200 */
9031 #define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */
9032 #define HRTIM_RST2R_MSTCMP3_Pos       (10U)
9033 #define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)        /*!< 0x00000400 */
9034 #define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */
9035 #define HRTIM_RST2R_MSTCMP4_Pos       (11U)
9036 #define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)        /*!< 0x00000800 */
9037 #define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */
9038 
9039 #define HRTIM_RST2R_TIMEVNT1_Pos      (12U)
9040 #define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)       /*!< 0x00001000 */
9041 #define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
9042 #define HRTIM_RST2R_TIMEVNT2_Pos      (13U)
9043 #define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)       /*!< 0x00002000 */
9044 #define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
9045 #define HRTIM_RST2R_TIMEVNT3_Pos      (14U)
9046 #define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)       /*!< 0x00004000 */
9047 #define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
9048 #define HRTIM_RST2R_TIMEVNT4_Pos      (15U)
9049 #define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)       /*!< 0x00008000 */
9050 #define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
9051 #define HRTIM_RST2R_TIMEVNT5_Pos      (16U)
9052 #define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)       /*!< 0x00010000 */
9053 #define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
9054 #define HRTIM_RST2R_TIMEVNT6_Pos      (17U)
9055 #define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)       /*!< 0x00020000 */
9056 #define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
9057 #define HRTIM_RST2R_TIMEVNT7_Pos      (18U)
9058 #define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)       /*!< 0x00040000 */
9059 #define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
9060 #define HRTIM_RST2R_TIMEVNT8_Pos      (19U)
9061 #define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)       /*!< 0x00080000 */
9062 #define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
9063 #define HRTIM_RST2R_TIMEVNT9_Pos      (20U)
9064 #define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)       /*!< 0x00100000 */
9065 #define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
9066 
9067 #define HRTIM_RST2R_EXTVNT1_Pos       (21U)
9068 #define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)        /*!< 0x00200000 */
9069 #define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */
9070 #define HRTIM_RST2R_EXTVNT2_Pos       (22U)
9071 #define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)        /*!< 0x00400000 */
9072 #define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */
9073 #define HRTIM_RST2R_EXTVNT3_Pos       (23U)
9074 #define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)        /*!< 0x00800000 */
9075 #define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */
9076 #define HRTIM_RST2R_EXTVNT4_Pos       (24U)
9077 #define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)        /*!< 0x01000000 */
9078 #define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */
9079 #define HRTIM_RST2R_EXTVNT5_Pos       (25U)
9080 #define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)        /*!< 0x02000000 */
9081 #define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */
9082 #define HRTIM_RST2R_EXTVNT6_Pos       (26U)
9083 #define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)        /*!< 0x04000000 */
9084 #define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */
9085 #define HRTIM_RST2R_EXTVNT7_Pos       (27U)
9086 #define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)        /*!< 0x08000000 */
9087 #define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */
9088 #define HRTIM_RST2R_EXTVNT8_Pos       (28U)
9089 #define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)        /*!< 0x10000000 */
9090 #define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */
9091 #define HRTIM_RST2R_EXTVNT9_Pos       (29U)
9092 #define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)        /*!< 0x20000000 */
9093 #define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */
9094 #define HRTIM_RST2R_EXTVNT10_Pos      (30U)
9095 #define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)       /*!< 0x40000000 */
9096 #define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */
9097 
9098 #define HRTIM_RST2R_UPDATE_Pos        (31U)
9099 #define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)         /*!< 0x80000000 */
9100 #define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
9101 
9102 /**** Bit definition for Slave external event filtering  register 1 ***********/
9103 #define HRTIM_EEFR1_EE1LTCH_Pos       (0U)
9104 #define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)        /*!< 0x00000001 */
9105 #define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */
9106 #define HRTIM_EEFR1_EE1FLTR_Pos       (1U)
9107 #define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x0000001E */
9108 #define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */
9109 #define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */
9110 #define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */
9111 #define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */
9112 #define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */
9113 
9114 #define HRTIM_EEFR1_EE2LTCH_Pos       (6U)
9115 #define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)        /*!< 0x00000040 */
9116 #define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */
9117 #define HRTIM_EEFR1_EE2FLTR_Pos       (7U)
9118 #define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000780 */
9119 #define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */
9120 #define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */
9121 #define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */
9122 #define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */
9123 #define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */
9124 
9125 #define HRTIM_EEFR1_EE3LTCH_Pos       (12U)
9126 #define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)        /*!< 0x00001000 */
9127 #define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */
9128 #define HRTIM_EEFR1_EE3FLTR_Pos       (13U)
9129 #define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x0001E000 */
9130 #define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */
9131 #define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */
9132 #define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */
9133 #define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */
9134 #define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */
9135 
9136 #define HRTIM_EEFR1_EE4LTCH_Pos       (18U)
9137 #define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)        /*!< 0x00040000 */
9138 #define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */
9139 #define HRTIM_EEFR1_EE4FLTR_Pos       (19U)
9140 #define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00780000 */
9141 #define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */
9142 #define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */
9143 #define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */
9144 #define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */
9145 #define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */
9146 
9147 #define HRTIM_EEFR1_EE5LTCH_Pos       (24U)
9148 #define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)        /*!< 0x01000000 */
9149 #define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */
9150 #define HRTIM_EEFR1_EE5FLTR_Pos       (25U)
9151 #define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x1E000000 */
9152 #define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */
9153 #define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */
9154 #define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */
9155 #define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */
9156 #define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */
9157 
9158 /**** Bit definition for Slave external event filtering  register 2 ***********/
9159 #define HRTIM_EEFR2_EE6LTCH_Pos       (0U)
9160 #define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)        /*!< 0x00000001 */
9161 #define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */
9162 #define HRTIM_EEFR2_EE6FLTR_Pos       (1U)
9163 #define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x0000001E */
9164 #define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */
9165 #define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */
9166 #define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */
9167 #define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */
9168 #define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */
9169 
9170 #define HRTIM_EEFR2_EE7LTCH_Pos       (6U)
9171 #define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)        /*!< 0x00000040 */
9172 #define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */
9173 #define HRTIM_EEFR2_EE7FLTR_Pos       (7U)
9174 #define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000780 */
9175 #define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */
9176 #define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */
9177 #define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */
9178 #define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */
9179 #define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */
9180 
9181 #define HRTIM_EEFR2_EE8LTCH_Pos       (12U)
9182 #define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)        /*!< 0x00001000 */
9183 #define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */
9184 #define HRTIM_EEFR2_EE8FLTR_Pos       (13U)
9185 #define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x0001E000 */
9186 #define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */
9187 #define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */
9188 #define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */
9189 #define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */
9190 #define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */
9191 
9192 #define HRTIM_EEFR2_EE9LTCH_Pos       (18U)
9193 #define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)        /*!< 0x00040000 */
9194 #define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */
9195 #define HRTIM_EEFR2_EE9FLTR_Pos       (19U)
9196 #define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00780000 */
9197 #define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */
9198 #define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */
9199 #define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */
9200 #define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */
9201 #define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */
9202 
9203 #define HRTIM_EEFR2_EE10LTCH_Pos      (24U)
9204 #define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)       /*!< 0x01000000 */
9205 #define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */
9206 #define HRTIM_EEFR2_EE10FLTR_Pos      (25U)
9207 #define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x1E000000 */
9208 #define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */
9209 #define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */
9210 #define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */
9211 #define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */
9212 #define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */
9213 
9214 /**** Bit definition for Slave Timer reset register ***************************/
9215 #define HRTIM_RSTR_UPDATE_Pos         (1U)
9216 #define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)          /*!< 0x00000002 */
9217 #define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */
9218 #define HRTIM_RSTR_CMP2_Pos           (2U)
9219 #define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)            /*!< 0x00000004 */
9220 #define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */
9221 #define HRTIM_RSTR_CMP4_Pos           (3U)
9222 #define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)            /*!< 0x00000008 */
9223 #define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */
9224 
9225 #define HRTIM_RSTR_MSTPER_Pos         (4U)
9226 #define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)          /*!< 0x00000010 */
9227 #define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */
9228 #define HRTIM_RSTR_MSTCMP1_Pos        (5U)
9229 #define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)         /*!< 0x00000020 */
9230 #define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */
9231 #define HRTIM_RSTR_MSTCMP2_Pos        (6U)
9232 #define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)         /*!< 0x00000040 */
9233 #define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */
9234 #define HRTIM_RSTR_MSTCMP3_Pos        (7U)
9235 #define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)         /*!< 0x00000080 */
9236 #define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */
9237 #define HRTIM_RSTR_MSTCMP4_Pos        (8U)
9238 #define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)         /*!< 0x00000100 */
9239 #define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */
9240 
9241 #define HRTIM_RSTR_EXTEVNT1_Pos       (9U)
9242 #define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)        /*!< 0x00000200 */
9243 #define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */
9244 #define HRTIM_RSTR_EXTEVNT2_Pos       (10U)
9245 #define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)        /*!< 0x00000400 */
9246 #define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */
9247 #define HRTIM_RSTR_EXTEVNT3_Pos       (11U)
9248 #define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)        /*!< 0x00000800 */
9249 #define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */
9250 #define HRTIM_RSTR_EXTEVNT4_Pos       (12U)
9251 #define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)        /*!< 0x00001000 */
9252 #define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */
9253 #define HRTIM_RSTR_EXTEVNT5_Pos       (13U)
9254 #define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)        /*!< 0x00002000 */
9255 #define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */
9256 #define HRTIM_RSTR_EXTEVNT6_Pos       (14U)
9257 #define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)        /*!< 0x00004000 */
9258 #define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */
9259 #define HRTIM_RSTR_EXTEVNT7_Pos       (15U)
9260 #define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)        /*!< 0x00008000 */
9261 #define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */
9262 #define HRTIM_RSTR_EXTEVNT8_Pos       (16U)
9263 #define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)        /*!< 0x00010000 */
9264 #define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */
9265 #define HRTIM_RSTR_EXTEVNT9_Pos       (17U)
9266 #define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)        /*!< 0x00020000 */
9267 #define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */
9268 #define HRTIM_RSTR_EXTEVNT10_Pos      (18U)
9269 #define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)       /*!< 0x00040000 */
9270 #define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
9271 
9272 /* Slave Timer A reset enable bits upon other slave timers events */
9273 #define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
9274 #define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)        /*!< 0x00080000 */
9275 #define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
9276 #define HRTIM_RSTR_TIMBCMP2_Pos       (20U)
9277 #define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)        /*!< 0x00100000 */
9278 #define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
9279 #define HRTIM_RSTR_TIMBCMP4_Pos       (21U)
9280 #define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)        /*!< 0x00200000 */
9281 #define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
9282 
9283 #define HRTIM_RSTR_TIMCCMP1_Pos       (22U)
9284 #define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)        /*!< 0x00400000 */
9285 #define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
9286 #define HRTIM_RSTR_TIMCCMP2_Pos       (23U)
9287 #define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)        /*!< 0x00800000 */
9288 #define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
9289 #define HRTIM_RSTR_TIMCCMP4_Pos       (24U)
9290 #define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)        /*!< 0x01000000 */
9291 #define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
9292 
9293 #define HRTIM_RSTR_TIMDCMP1_Pos       (25U)
9294 #define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)        /*!< 0x02000000 */
9295 #define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
9296 #define HRTIM_RSTR_TIMDCMP2_Pos       (26U)
9297 #define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)        /*!< 0x04000000 */
9298 #define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
9299 #define HRTIM_RSTR_TIMDCMP4_Pos       (27U)
9300 #define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)        /*!< 0x08000000 */
9301 #define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
9302 
9303 #define HRTIM_RSTR_TIMECMP1_Pos       (28U)
9304 #define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)        /*!< 0x10000000 */
9305 #define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
9306 #define HRTIM_RSTR_TIMECMP2_Pos       (29U)
9307 #define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)        /*!< 0x20000000 */
9308 #define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
9309 #define HRTIM_RSTR_TIMECMP4_Pos       (30U)
9310 #define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)        /*!< 0x40000000 */
9311 #define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
9312 
9313 /* Slave Timer B reset enable bits upon other slave timers events */
9314 #define HRTIM_RSTBR_TIMACMP1_Pos       (19U)
9315 #define HRTIM_RSTBR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)        /*!< 0x00080000 */
9316 #define HRTIM_RSTBR_TIMACMP1           HRTIM_RSTBR_TIMACMP1_Msk                  /*!< Timer A compare 1 */
9317 #define HRTIM_RSTBR_TIMACMP2_Pos       (20U)
9318 #define HRTIM_RSTBR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)        /*!< 0x00100000 */
9319 #define HRTIM_RSTBR_TIMACMP2           HRTIM_RSTBR_TIMACMP2_Msk                  /*!< Timer A compare 2 */
9320 #define HRTIM_RSTBR_TIMACMP4_Pos       (21U)
9321 #define HRTIM_RSTBR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)        /*!< 0x00200000 */
9322 #define HRTIM_RSTBR_TIMACMP4           HRTIM_RSTBR_TIMACMP4_Msk                  /*!< Timer A compare 4 */
9323 
9324 #define HRTIM_RSTBR_TIMCCMP1_Pos       (22U)
9325 #define HRTIM_RSTBR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)        /*!< 0x00400000 */
9326 #define HRTIM_RSTBR_TIMCCMP1           HRTIM_RSTBR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
9327 #define HRTIM_RSTBR_TIMCCMP2_Pos       (23U)
9328 #define HRTIM_RSTBR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)        /*!< 0x00800000 */
9329 #define HRTIM_RSTBR_TIMCCMP2           HRTIM_RSTBR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
9330 #define HRTIM_RSTBR_TIMCCMP4_Pos       (24U)
9331 #define HRTIM_RSTBR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)        /*!< 0x01000000 */
9332 #define HRTIM_RSTBR_TIMCCMP4           HRTIM_RSTBR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
9333 
9334 #define HRTIM_RSTBR_TIMDCMP1_Pos       (25U)
9335 #define HRTIM_RSTBR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)        /*!< 0x02000000 */
9336 #define HRTIM_RSTBR_TIMDCMP1           HRTIM_RSTBR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
9337 #define HRTIM_RSTBR_TIMDCMP2_Pos       (26U)
9338 #define HRTIM_RSTBR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)        /*!< 0x04000000 */
9339 #define HRTIM_RSTBR_TIMDCMP2           HRTIM_RSTBR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
9340 #define HRTIM_RSTBR_TIMDCMP4_Pos       (27U)
9341 #define HRTIM_RSTBR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)        /*!< 0x08000000 */
9342 #define HRTIM_RSTBR_TIMDCMP4           HRTIM_RSTBR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
9343 
9344 #define HRTIM_RSTBR_TIMECMP1_Pos       (28U)
9345 #define HRTIM_RSTBR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)        /*!< 0x10000000 */
9346 #define HRTIM_RSTBR_TIMECMP1           HRTIM_RSTBR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
9347 #define HRTIM_RSTBR_TIMECMP2_Pos       (29U)
9348 #define HRTIM_RSTBR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)        /*!< 0x20000000 */
9349 #define HRTIM_RSTBR_TIMECMP2           HRTIM_RSTBR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
9350 #define HRTIM_RSTBR_TIMECMP4_Pos       (30U)
9351 #define HRTIM_RSTBR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)        /*!< 0x40000000 */
9352 #define HRTIM_RSTBR_TIMECMP4           HRTIM_RSTBR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
9353 
9354 /* Slave Timer C reset enable bits upon other slave timers events */
9355 #define HRTIM_RSTCR_TIMACMP1_Pos       (19U)
9356 #define HRTIM_RSTCR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)        /*!< 0x00080000 */
9357 #define HRTIM_RSTCR_TIMACMP1           HRTIM_RSTCR_TIMACMP1_Msk                  /*!< Timer A compare 1 */
9358 #define HRTIM_RSTCR_TIMACMP2_Pos       (20U)
9359 #define HRTIM_RSTCR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)        /*!< 0x00100000 */
9360 #define HRTIM_RSTCR_TIMACMP2           HRTIM_RSTCR_TIMACMP2_Msk                  /*!< Timer A compare 2 */
9361 #define HRTIM_RSTCR_TIMACMP4_Pos       (21U)
9362 #define HRTIM_RSTCR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)        /*!< 0x00200000 */
9363 #define HRTIM_RSTCR_TIMACMP4           HRTIM_RSTCR_TIMACMP4_Msk                  /*!< Timer A compare 4 */
9364 
9365 #define HRTIM_RSTCR_TIMBCMP1_Pos       (22U)
9366 #define HRTIM_RSTCR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)        /*!< 0x00400000 */
9367 #define HRTIM_RSTCR_TIMBCMP1           HRTIM_RSTCR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
9368 #define HRTIM_RSTCR_TIMBCMP2_Pos       (23U)
9369 #define HRTIM_RSTCR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)        /*!< 0x00800000 */
9370 #define HRTIM_RSTCR_TIMBCMP2           HRTIM_RSTCR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
9371 #define HRTIM_RSTCR_TIMBCMP4_Pos       (24U)
9372 #define HRTIM_RSTCR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)        /*!< 0x01000000 */
9373 #define HRTIM_RSTCR_TIMBCMP4           HRTIM_RSTCR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
9374 
9375 #define HRTIM_RSTCR_TIMDCMP1_Pos       (25U)
9376 #define HRTIM_RSTCR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)        /*!< 0x02000000 */
9377 #define HRTIM_RSTCR_TIMDCMP1           HRTIM_RSTCR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
9378 #define HRTIM_RSTCR_TIMDCMP2_Pos       (26U)
9379 #define HRTIM_RSTCR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)        /*!< 0x04000000 */
9380 #define HRTIM_RSTCR_TIMDCMP2           HRTIM_RSTCR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
9381 #define HRTIM_RSTCR_TIMDCMP4_Pos       (27U)
9382 #define HRTIM_RSTCR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)        /*!< 0x08000000 */
9383 #define HRTIM_RSTCR_TIMDCMP4           HRTIM_RSTCR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
9384 
9385 #define HRTIM_RSTCR_TIMECMP1_Pos       (28U)
9386 #define HRTIM_RSTCR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)        /*!< 0x10000000 */
9387 #define HRTIM_RSTCR_TIMECMP1           HRTIM_RSTCR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
9388 #define HRTIM_RSTCR_TIMECMP2_Pos       (29U)
9389 #define HRTIM_RSTCR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)        /*!< 0x20000000 */
9390 #define HRTIM_RSTCR_TIMECMP2           HRTIM_RSTCR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
9391 #define HRTIM_RSTCR_TIMECMP4_Pos       (30U)
9392 #define HRTIM_RSTCR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)        /*!< 0x40000000 */
9393 #define HRTIM_RSTCR_TIMECMP4           HRTIM_RSTCR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
9394 
9395 /* Slave Timer D reset enable bits upon other slave timers events */
9396 #define HRTIM_RSTDR_TIMACMP1_Pos       (19U)
9397 #define HRTIM_RSTDR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)        /*!< 0x00080000 */
9398 #define HRTIM_RSTDR_TIMACMP1           HRTIM_RSTDR_TIMACMP1_Msk                  /*!< Timer A compare 1 */
9399 #define HRTIM_RSTDR_TIMACMP2_Pos       (20U)
9400 #define HRTIM_RSTDR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)        /*!< 0x00100000 */
9401 #define HRTIM_RSTDR_TIMACMP2           HRTIM_RSTDR_TIMACMP2_Msk                  /*!< Timer A compare 2 */
9402 #define HRTIM_RSTDR_TIMACMP4_Pos       (21U)
9403 #define HRTIM_RSTDR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)        /*!< 0x00200000 */
9404 #define HRTIM_RSTDR_TIMACMP4           HRTIM_RSTDR_TIMACMP4_Msk                  /*!< Timer A compare 4 */
9405 
9406 #define HRTIM_RSTDR_TIMBCMP1_Pos       (22U)
9407 #define HRTIM_RSTDR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)        /*!< 0x00400000 */
9408 #define HRTIM_RSTDR_TIMBCMP1           HRTIM_RSTDR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
9409 #define HRTIM_RSTDR_TIMBCMP2_Pos       (23U)
9410 #define HRTIM_RSTDR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)        /*!< 0x00800000 */
9411 #define HRTIM_RSTDR_TIMBCMP2           HRTIM_RSTDR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
9412 #define HRTIM_RSTDR_TIMBCMP4_Pos       (24U)
9413 #define HRTIM_RSTDR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)        /*!< 0x01000000 */
9414 #define HRTIM_RSTDR_TIMBCMP4           HRTIM_RSTDR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
9415 
9416 #define HRTIM_RSTDR_TIMCCMP1_Pos       (25U)
9417 #define HRTIM_RSTDR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)        /*!< 0x02000000 */
9418 #define HRTIM_RSTDR_TIMCCMP1           HRTIM_RSTDR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
9419 #define HRTIM_RSTDR_TIMCCMP2_Pos       (26U)
9420 #define HRTIM_RSTDR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)        /*!< 0x04000000 */
9421 #define HRTIM_RSTDR_TIMCCMP2           HRTIM_RSTDR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
9422 #define HRTIM_RSTDR_TIMCCMP4_Pos       (27U)
9423 #define HRTIM_RSTDR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)        /*!< 0x08000000 */
9424 #define HRTIM_RSTDR_TIMCCMP4           HRTIM_RSTDR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
9425 
9426 #define HRTIM_RSTDR_TIMECMP1_Pos       (28U)
9427 #define HRTIM_RSTDR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)        /*!< 0x10000000 */
9428 #define HRTIM_RSTDR_TIMECMP1           HRTIM_RSTDR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
9429 #define HRTIM_RSTDR_TIMECMP2_Pos       (29U)
9430 #define HRTIM_RSTDR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)        /*!< 0x20000000 */
9431 #define HRTIM_RSTDR_TIMECMP2           HRTIM_RSTDR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
9432 #define HRTIM_RSTDR_TIMECMP4_Pos       (30U)
9433 #define HRTIM_RSTDR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)        /*!< 0x40000000 */
9434 #define HRTIM_RSTDR_TIMECMP4           HRTIM_RSTDR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
9435 
9436 #define HRTIM_RSTER_TIMACMP1_Pos       (19U)
9437 #define HRTIM_RSTER_TIMACMP1_Msk       (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)        /*!< 0x00080000 */
9438 #define HRTIM_RSTER_TIMACMP1           HRTIM_RSTER_TIMACMP1_Msk                  /*!< Timer A compare 1 */
9439 #define HRTIM_RSTER_TIMACMP2_Pos       (20U)
9440 #define HRTIM_RSTER_TIMACMP2_Msk       (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)        /*!< 0x00100000 */
9441 #define HRTIM_RSTER_TIMACMP2           HRTIM_RSTER_TIMACMP2_Msk                  /*!< Timer A compare 2 */
9442 #define HRTIM_RSTER_TIMACMP4_Pos       (21U)
9443 #define HRTIM_RSTER_TIMACMP4_Msk       (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)        /*!< 0x00200000 */
9444 #define HRTIM_RSTER_TIMACMP4           HRTIM_RSTER_TIMACMP4_Msk                  /*!< Timer A compare 4 */
9445 
9446 #define HRTIM_RSTER_TIMBCMP1_Pos       (22U)
9447 #define HRTIM_RSTER_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)        /*!< 0x00400000 */
9448 #define HRTIM_RSTER_TIMBCMP1           HRTIM_RSTER_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
9449 #define HRTIM_RSTER_TIMBCMP2_Pos       (23U)
9450 #define HRTIM_RSTER_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)        /*!< 0x00800000 */
9451 #define HRTIM_RSTER_TIMBCMP2           HRTIM_RSTER_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
9452 #define HRTIM_RSTER_TIMBCMP4_Pos       (24U)
9453 #define HRTIM_RSTER_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)        /*!< 0x01000000 */
9454 #define HRTIM_RSTER_TIMBCMP4           HRTIM_RSTER_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
9455 
9456 #define HRTIM_RSTER_TIMCCMP1_Pos       (25U)
9457 #define HRTIM_RSTER_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)        /*!< 0x02000000 */
9458 #define HRTIM_RSTER_TIMCCMP1           HRTIM_RSTER_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
9459 #define HRTIM_RSTER_TIMCCMP2_Pos       (26U)
9460 #define HRTIM_RSTER_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)        /*!< 0x04000000 */
9461 #define HRTIM_RSTER_TIMCCMP2           HRTIM_RSTER_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
9462 #define HRTIM_RSTER_TIMCCMP4_Pos       (27U)
9463 #define HRTIM_RSTER_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)        /*!< 0x08000000 */
9464 #define HRTIM_RSTER_TIMCCMP4           HRTIM_RSTER_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
9465 
9466 #define HRTIM_RSTER_TIMDCMP1_Pos       (28U)
9467 #define HRTIM_RSTER_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)        /*!< 0x10000000 */
9468 #define HRTIM_RSTER_TIMDCMP1           HRTIM_RSTER_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
9469 #define HRTIM_RSTER_TIMDCMP2_Pos       (29U)
9470 #define HRTIM_RSTER_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)        /*!< 0x20000000 */
9471 #define HRTIM_RSTER_TIMDCMP2           HRTIM_RSTER_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
9472 #define HRTIM_RSTER_TIMDCMP4_Pos       (30U)
9473 #define HRTIM_RSTER_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)        /*!< 0x40000000 */
9474 #define HRTIM_RSTER_TIMDCMP4           HRTIM_RSTER_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
9475 
9476 /**** Bit definition for Slave Timer Chopper register *************************/
9477 #define HRTIM_CHPR_CARFRQ_Pos         (0U)
9478 #define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x0000000F */
9479 #define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */
9480 #define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */
9481 #define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */
9482 #define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */
9483 #define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */
9484 
9485 #define HRTIM_CHPR_CARDTY_Pos         (4U)
9486 #define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000070 */
9487 #define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */
9488 #define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */
9489 #define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */
9490 #define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */
9491 
9492 #define HRTIM_CHPR_STRPW_Pos          (7U)
9493 #define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000780 */
9494 #define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */
9495 #define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */
9496 #define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */
9497 #define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */
9498 #define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */
9499 
9500 /**** Bit definition for Slave Timer Capture 1 control register ***************/
9501 #define HRTIM_CPT1CR_SWCPT_Pos        (0U)
9502 #define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)         /*!< 0x00000001 */
9503 #define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */
9504 #define HRTIM_CPT1CR_UPDCPT_Pos       (1U)
9505 #define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)        /*!< 0x00000002 */
9506 #define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */
9507 #define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)
9508 #define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)      /*!< 0x00000004 */
9509 #define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */
9510 #define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)
9511 #define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)      /*!< 0x00000008 */
9512 #define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */
9513 #define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)
9514 #define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)      /*!< 0x00000010 */
9515 #define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */
9516 #define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)
9517 #define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)      /*!< 0x00000020 */
9518 #define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */
9519 #define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)
9520 #define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)      /*!< 0x00000040 */
9521 #define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */
9522 #define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)
9523 #define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)      /*!< 0x00000080 */
9524 #define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */
9525 #define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)
9526 #define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)      /*!< 0x00000100 */
9527 #define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */
9528 #define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)
9529 #define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)      /*!< 0x00000200 */
9530 #define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */
9531 #define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)
9532 #define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)      /*!< 0x00000400 */
9533 #define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */
9534 #define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)
9535 #define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)     /*!< 0x00000800 */
9536 #define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */
9537 
9538 #define HRTIM_CPT1CR_TA1SET_Pos       (12U)
9539 #define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)        /*!< 0x00001000 */
9540 #define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */
9541 #define HRTIM_CPT1CR_TA1RST_Pos       (13U)
9542 #define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)        /*!< 0x00002000 */
9543 #define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
9544 #define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)
9545 #define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)      /*!< 0x00004000 */
9546 #define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
9547 #define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)
9548 #define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)      /*!< 0x00008000 */
9549 #define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
9550 
9551 #define HRTIM_CPT1CR_TB1SET_Pos       (16U)
9552 #define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)        /*!< 0x00010000 */
9553 #define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */
9554 #define HRTIM_CPT1CR_TB1RST_Pos       (17U)
9555 #define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)        /*!< 0x00020000 */
9556 #define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
9557 #define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)
9558 #define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)      /*!< 0x00040000 */
9559 #define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
9560 #define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)
9561 #define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)      /*!< 0x00080000 */
9562 #define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
9563 
9564 #define HRTIM_CPT1CR_TC1SET_Pos       (20U)
9565 #define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)        /*!< 0x00100000 */
9566 #define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */
9567 #define HRTIM_CPT1CR_TC1RST_Pos       (21U)
9568 #define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)        /*!< 0x00200000 */
9569 #define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
9570 #define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)
9571 #define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)      /*!< 0x00400000 */
9572 #define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
9573 #define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)
9574 #define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)      /*!< 0x00800000 */
9575 #define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
9576 
9577 #define HRTIM_CPT1CR_TD1SET_Pos       (24U)
9578 #define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)        /*!< 0x01000000 */
9579 #define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */
9580 #define HRTIM_CPT1CR_TD1RST_Pos       (25U)
9581 #define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)        /*!< 0x02000000 */
9582 #define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
9583 #define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)
9584 #define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)      /*!< 0x04000000 */
9585 #define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
9586 #define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)
9587 #define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)      /*!< 0x08000000 */
9588 #define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
9589 
9590 #define HRTIM_CPT1CR_TE1SET_Pos       (28U)
9591 #define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)        /*!< 0x10000000 */
9592 #define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */
9593 #define HRTIM_CPT1CR_TE1RST_Pos       (29U)
9594 #define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)        /*!< 0x20000000 */
9595 #define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
9596 #define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)
9597 #define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)      /*!< 0x40000000 */
9598 #define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
9599 #define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)
9600 #define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)      /*!< 0x80000000 */
9601 #define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
9602 
9603 /**** Bit definition for Slave Timer Capture 2 control register ***************/
9604 #define HRTIM_CPT2CR_SWCPT_Pos        (0U)
9605 #define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)         /*!< 0x00000001 */
9606 #define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */
9607 #define HRTIM_CPT2CR_UPDCPT_Pos       (1U)
9608 #define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)        /*!< 0x00000002 */
9609 #define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */
9610 #define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)
9611 #define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)      /*!< 0x00000004 */
9612 #define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */
9613 #define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)
9614 #define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)      /*!< 0x00000008 */
9615 #define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */
9616 #define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)
9617 #define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)      /*!< 0x00000010 */
9618 #define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */
9619 #define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)
9620 #define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)      /*!< 0x00000020 */
9621 #define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */
9622 #define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)
9623 #define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)      /*!< 0x00000040 */
9624 #define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */
9625 #define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)
9626 #define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)      /*!< 0x00000080 */
9627 #define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */
9628 #define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)
9629 #define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)      /*!< 0x00000100 */
9630 #define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */
9631 #define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)
9632 #define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)      /*!< 0x00000200 */
9633 #define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */
9634 #define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)
9635 #define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)      /*!< 0x00000400 */
9636 #define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */
9637 #define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)
9638 #define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)     /*!< 0x00000800 */
9639 #define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */
9640 
9641 #define HRTIM_CPT2CR_TA1SET_Pos       (12U)
9642 #define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)        /*!< 0x00001000 */
9643 #define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */
9644 #define HRTIM_CPT2CR_TA1RST_Pos       (13U)
9645 #define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)        /*!< 0x00002000 */
9646 #define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
9647 #define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)
9648 #define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)      /*!< 0x00004000 */
9649 #define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
9650 #define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)
9651 #define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)      /*!< 0x00008000 */
9652 #define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
9653 
9654 #define HRTIM_CPT2CR_TB1SET_Pos       (16U)
9655 #define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)        /*!< 0x00010000 */
9656 #define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */
9657 #define HRTIM_CPT2CR_TB1RST_Pos       (17U)
9658 #define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)        /*!< 0x00020000 */
9659 #define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
9660 #define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)
9661 #define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)      /*!< 0x00040000 */
9662 #define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
9663 #define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)
9664 #define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)      /*!< 0x00080000 */
9665 #define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
9666 
9667 #define HRTIM_CPT2CR_TC1SET_Pos       (20U)
9668 #define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)        /*!< 0x00100000 */
9669 #define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */
9670 #define HRTIM_CPT2CR_TC1RST_Pos       (21U)
9671 #define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)        /*!< 0x00200000 */
9672 #define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
9673 #define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)
9674 #define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)      /*!< 0x00400000 */
9675 #define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
9676 #define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)
9677 #define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)      /*!< 0x00800000 */
9678 #define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
9679 
9680 #define HRTIM_CPT2CR_TD1SET_Pos       (24U)
9681 #define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)        /*!< 0x01000000 */
9682 #define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */
9683 #define HRTIM_CPT2CR_TD1RST_Pos       (25U)
9684 #define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)        /*!< 0x02000000 */
9685 #define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
9686 #define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)
9687 #define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)      /*!< 0x04000000 */
9688 #define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
9689 #define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)
9690 #define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)      /*!< 0x08000000 */
9691 #define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
9692 
9693 #define HRTIM_CPT2CR_TE1SET_Pos       (28U)
9694 #define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)        /*!< 0x10000000 */
9695 #define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */
9696 #define HRTIM_CPT2CR_TE1RST_Pos       (29U)
9697 #define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)        /*!< 0x20000000 */
9698 #define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
9699 #define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)
9700 #define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)      /*!< 0x40000000 */
9701 #define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
9702 #define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)
9703 #define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)      /*!< 0x80000000 */
9704 #define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
9705 
9706 /**** Bit definition for Slave Timer Output register **************************/
9707 #define HRTIM_OUTR_POL1_Pos           (1U)
9708 #define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)            /*!< 0x00000002 */
9709 #define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */
9710 #define HRTIM_OUTR_IDLM1_Pos          (2U)
9711 #define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)           /*!< 0x00000004 */
9712 #define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */
9713 #define HRTIM_OUTR_IDLES1_Pos         (3U)
9714 #define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)          /*!< 0x00000008 */
9715 #define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */
9716 #define HRTIM_OUTR_FAULT1_Pos         (4U)
9717 #define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000030 */
9718 #define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */
9719 #define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */
9720 #define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */
9721 #define HRTIM_OUTR_CHP1_Pos           (6U)
9722 #define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)            /*!< 0x00000040 */
9723 #define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */
9724 #define HRTIM_OUTR_DIDL1_Pos          (7U)
9725 #define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)           /*!< 0x00000080 */
9726 #define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */
9727 
9728 #define HRTIM_OUTR_DTEN_Pos           (8U)
9729 #define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)            /*!< 0x00000100 */
9730 #define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */
9731 #define HRTIM_OUTR_DLYPRTEN_Pos       (9U)
9732 #define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)        /*!< 0x00000200 */
9733 #define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */
9734 #define HRTIM_OUTR_DLYPRT_Pos         (10U)
9735 #define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001C00 */
9736 #define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */
9737 #define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */
9738 #define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */
9739 #define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */
9740 
9741 #define HRTIM_OUTR_POL2_Pos           (17U)
9742 #define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)            /*!< 0x00020000 */
9743 #define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */
9744 #define HRTIM_OUTR_IDLM2_Pos          (18U)
9745 #define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)           /*!< 0x00040000 */
9746 #define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */
9747 #define HRTIM_OUTR_IDLES2_Pos         (19U)
9748 #define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)          /*!< 0x00080000 */
9749 #define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */
9750 #define HRTIM_OUTR_FAULT2_Pos         (20U)
9751 #define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00300000 */
9752 #define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */
9753 #define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */
9754 #define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */
9755 #define HRTIM_OUTR_CHP2_Pos           (22U)
9756 #define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)            /*!< 0x00400000 */
9757 #define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */
9758 #define HRTIM_OUTR_DIDL2_Pos          (23U)
9759 #define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)           /*!< 0x00800000 */
9760 #define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */
9761 
9762 /**** Bit definition for Slave Timer Fault register ***************************/
9763 #define HRTIM_FLTR_FLT1EN_Pos         (0U)
9764 #define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)          /*!< 0x00000001 */
9765 #define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */
9766 #define HRTIM_FLTR_FLT2EN_Pos         (1U)
9767 #define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)          /*!< 0x00000002 */
9768 #define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */
9769 #define HRTIM_FLTR_FLT3EN_Pos         (2U)
9770 #define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)          /*!< 0x00000004 */
9771 #define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */
9772 #define HRTIM_FLTR_FLT4EN_Pos         (3U)
9773 #define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)          /*!< 0x00000008 */
9774 #define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */
9775 #define HRTIM_FLTR_FLT5EN_Pos         (4U)
9776 #define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)          /*!< 0x00000010 */
9777 #define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */
9778 #define HRTIM_FLTR_FLTLCK_Pos         (31U)
9779 #define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)          /*!< 0x80000000 */
9780 #define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */
9781 
9782 /**** Bit definition for Common HRTIM Timer control register 1 ****************/
9783 #define HRTIM_CR1_MUDIS_Pos           (0U)
9784 #define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)            /*!< 0x00000001 */
9785 #define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/
9786 #define HRTIM_CR1_TAUDIS_Pos          (1U)
9787 #define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)           /*!< 0x00000002 */
9788 #define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/
9789 #define HRTIM_CR1_TBUDIS_Pos          (2U)
9790 #define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)           /*!< 0x00000004 */
9791 #define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/
9792 #define HRTIM_CR1_TCUDIS_Pos          (3U)
9793 #define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)           /*!< 0x00000008 */
9794 #define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/
9795 #define HRTIM_CR1_TDUDIS_Pos          (4U)
9796 #define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)           /*!< 0x00000010 */
9797 #define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/
9798 #define HRTIM_CR1_TEUDIS_Pos          (5U)
9799 #define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)           /*!< 0x00000020 */
9800 #define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/
9801 #define HRTIM_CR1_ADC1USRC_Pos        (16U)
9802 #define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00070000 */
9803 #define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */
9804 #define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */
9805 #define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */
9806 #define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */
9807 #define HRTIM_CR1_ADC2USRC_Pos        (19U)
9808 #define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00380000 */
9809 #define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */
9810 #define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */
9811 #define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */
9812 #define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */
9813 #define HRTIM_CR1_ADC3USRC_Pos        (22U)
9814 #define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01C00000 */
9815 #define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */
9816 #define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */
9817 #define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */
9818 #define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */
9819 #define HRTIM_CR1_ADC4USRC_Pos        (25U)
9820 #define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0E000000 */
9821 #define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */
9822 #define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */
9823 #define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */
9824 #define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */
9825 
9826 /**** Bit definition for Common HRTIM Timer control register 2 ****************/
9827 #define HRTIM_CR2_MSWU_Pos            (0U)
9828 #define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)             /*!< 0x00000001 */
9829 #define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */
9830 #define HRTIM_CR2_TASWU_Pos           (1U)
9831 #define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)            /*!< 0x00000002 */
9832 #define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */
9833 #define HRTIM_CR2_TBSWU_Pos           (2U)
9834 #define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)            /*!< 0x00000004 */
9835 #define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */
9836 #define HRTIM_CR2_TCSWU_Pos           (3U)
9837 #define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)            /*!< 0x00000008 */
9838 #define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */
9839 #define HRTIM_CR2_TDSWU_Pos           (4U)
9840 #define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)            /*!< 0x00000010 */
9841 #define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */
9842 #define HRTIM_CR2_TESWU_Pos           (5U)
9843 #define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)            /*!< 0x00000020 */
9844 #define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */
9845 #define HRTIM_CR2_MRST_Pos            (8U)
9846 #define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)             /*!< 0x00000100 */
9847 #define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */
9848 #define HRTIM_CR2_TARST_Pos           (9U)
9849 #define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)            /*!< 0x00000200 */
9850 #define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */
9851 #define HRTIM_CR2_TBRST_Pos           (10U)
9852 #define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)            /*!< 0x00000400 */
9853 #define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */
9854 #define HRTIM_CR2_TCRST_Pos           (11U)
9855 #define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)            /*!< 0x00000800 */
9856 #define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */
9857 #define HRTIM_CR2_TDRST_Pos           (12U)
9858 #define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)            /*!< 0x00001000 */
9859 #define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */
9860 #define HRTIM_CR2_TERST_Pos           (13U)
9861 #define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)            /*!< 0x00002000 */
9862 #define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */
9863 
9864 /**** Bit definition for Common HRTIM Timer interrupt status register *********/
9865 #define HRTIM_ISR_FLT1_Pos            (0U)
9866 #define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)             /*!< 0x00000001 */
9867 #define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */
9868 #define HRTIM_ISR_FLT2_Pos            (1U)
9869 #define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)             /*!< 0x00000002 */
9870 #define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */
9871 #define HRTIM_ISR_FLT3_Pos            (2U)
9872 #define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)             /*!< 0x00000004 */
9873 #define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */
9874 #define HRTIM_ISR_FLT4_Pos            (3U)
9875 #define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)             /*!< 0x00000008 */
9876 #define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */
9877 #define HRTIM_ISR_FLT5_Pos            (4U)
9878 #define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)             /*!< 0x00000010 */
9879 #define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */
9880 #define HRTIM_ISR_SYSFLT_Pos          (5U)
9881 #define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)           /*!< 0x00000020 */
9882 #define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */
9883 #define HRTIM_ISR_DLLRDY_Pos          (16U)
9884 #define HRTIM_ISR_DLLRDY_Msk          (0x1UL << HRTIM_ISR_DLLRDY_Pos)           /*!< 0x00010000 */
9885 #define HRTIM_ISR_DLLRDY              HRTIM_ISR_DLLRDY_Msk                     /*!< DLL ready interrupt flag */
9886 #define HRTIM_ISR_BMPER_Pos           (17U)
9887 #define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)            /*!< 0x00020000 */
9888 #define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */
9889 
9890 /**** Bit definition for Common HRTIM Timer interrupt clear register **********/
9891 #define HRTIM_ICR_FLT1C_Pos           (0U)
9892 #define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)            /*!< 0x00000001 */
9893 #define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */
9894 #define HRTIM_ICR_FLT2C_Pos           (1U)
9895 #define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)            /*!< 0x00000002 */
9896 #define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */
9897 #define HRTIM_ICR_FLT3C_Pos           (2U)
9898 #define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)            /*!< 0x00000004 */
9899 #define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */
9900 #define HRTIM_ICR_FLT4C_Pos           (3U)
9901 #define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)            /*!< 0x00000008 */
9902 #define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */
9903 #define HRTIM_ICR_FLT5C_Pos           (4U)
9904 #define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)            /*!< 0x00000010 */
9905 #define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */
9906 #define HRTIM_ICR_SYSFLTC_Pos         (5U)
9907 #define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)          /*!< 0x00000020 */
9908 #define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */
9909 #define HRTIM_ICR_DLLRDYC_Pos         (16U)
9910 #define HRTIM_ICR_DLLRDYC_Msk         (0x1UL << HRTIM_ICR_DLLRDYC_Pos)          /*!< 0x00010000 */
9911 #define HRTIM_ICR_DLLRDYC             HRTIM_ICR_DLLRDYC_Msk                    /*!< DLL ready interrupt flag clear */
9912 #define HRTIM_ICR_BMPERC_Pos          (17U)
9913 #define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)           /*!< 0x00020000 */
9914 #define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */
9915 
9916 /**** Bit definition for Common HRTIM Timer interrupt enable register *********/
9917 #define HRTIM_IER_FLT1_Pos            (0U)
9918 #define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)             /*!< 0x00000001 */
9919 #define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */
9920 #define HRTIM_IER_FLT2_Pos            (1U)
9921 #define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)             /*!< 0x00000002 */
9922 #define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */
9923 #define HRTIM_IER_FLT3_Pos            (2U)
9924 #define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)             /*!< 0x00000004 */
9925 #define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */
9926 #define HRTIM_IER_FLT4_Pos            (3U)
9927 #define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)             /*!< 0x00000008 */
9928 #define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */
9929 #define HRTIM_IER_FLT5_Pos            (4U)
9930 #define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)             /*!< 0x00000010 */
9931 #define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */
9932 #define HRTIM_IER_SYSFLT_Pos          (5U)
9933 #define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)           /*!< 0x00000020 */
9934 #define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */
9935 #define HRTIM_IER_DLLRDY_Pos          (16U)
9936 #define HRTIM_IER_DLLRDY_Msk          (0x1UL << HRTIM_IER_DLLRDY_Pos)           /*!< 0x00010000 */
9937 #define HRTIM_IER_DLLRDY              HRTIM_IER_DLLRDY_Msk                     /*!< DLL ready interrupt enable */
9938 #define HRTIM_IER_BMPER_Pos           (17U)
9939 #define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)            /*!< 0x00020000 */
9940 #define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */
9941 
9942 /**** Bit definition for Common HRTIM Timer output enable register ************/
9943 #define HRTIM_OENR_TA1OEN_Pos         (0U)
9944 #define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)          /*!< 0x00000001 */
9945 #define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */
9946 #define HRTIM_OENR_TA2OEN_Pos         (1U)
9947 #define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)          /*!< 0x00000002 */
9948 #define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */
9949 #define HRTIM_OENR_TB1OEN_Pos         (2U)
9950 #define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)          /*!< 0x00000004 */
9951 #define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */
9952 #define HRTIM_OENR_TB2OEN_Pos         (3U)
9953 #define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)          /*!< 0x00000008 */
9954 #define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */
9955 #define HRTIM_OENR_TC1OEN_Pos         (4U)
9956 #define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)          /*!< 0x00000010 */
9957 #define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */
9958 #define HRTIM_OENR_TC2OEN_Pos         (5U)
9959 #define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)          /*!< 0x00000020 */
9960 #define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */
9961 #define HRTIM_OENR_TD1OEN_Pos         (6U)
9962 #define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)          /*!< 0x00000040 */
9963 #define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */
9964 #define HRTIM_OENR_TD2OEN_Pos         (7U)
9965 #define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)          /*!< 0x00000080 */
9966 #define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */
9967 #define HRTIM_OENR_TE1OEN_Pos         (8U)
9968 #define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)          /*!< 0x00000100 */
9969 #define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */
9970 #define HRTIM_OENR_TE2OEN_Pos         (9U)
9971 #define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)          /*!< 0x00000200 */
9972 #define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */
9973 
9974 /**** Bit definition for Common HRTIM Timer output disable register ***********/
9975 #define HRTIM_ODISR_TA1ODIS_Pos       (0U)
9976 #define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)        /*!< 0x00000001 */
9977 #define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */
9978 #define HRTIM_ODISR_TA2ODIS_Pos       (1U)
9979 #define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)        /*!< 0x00000002 */
9980 #define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */
9981 #define HRTIM_ODISR_TB1ODIS_Pos       (2U)
9982 #define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)        /*!< 0x00000004 */
9983 #define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */
9984 #define HRTIM_ODISR_TB2ODIS_Pos       (3U)
9985 #define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)        /*!< 0x00000008 */
9986 #define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */
9987 #define HRTIM_ODISR_TC1ODIS_Pos       (4U)
9988 #define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)        /*!< 0x00000010 */
9989 #define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */
9990 #define HRTIM_ODISR_TC2ODIS_Pos       (5U)
9991 #define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)        /*!< 0x00000020 */
9992 #define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */
9993 #define HRTIM_ODISR_TD1ODIS_Pos       (6U)
9994 #define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)        /*!< 0x00000040 */
9995 #define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */
9996 #define HRTIM_ODISR_TD2ODIS_Pos       (7U)
9997 #define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)        /*!< 0x00000080 */
9998 #define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */
9999 #define HRTIM_ODISR_TE1ODIS_Pos       (8U)
10000 #define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)        /*!< 0x00000100 */
10001 #define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */
10002 #define HRTIM_ODISR_TE2ODIS_Pos       (9U)
10003 #define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)        /*!< 0x00000200 */
10004 #define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */
10005 
10006 /**** Bit definition for Common HRTIM Timer output disable status register *****/
10007 #define HRTIM_ODSR_TA1ODS_Pos         (0U)
10008 #define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)          /*!< 0x00000001 */
10009 #define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */
10010 #define HRTIM_ODSR_TA2ODS_Pos         (1U)
10011 #define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)          /*!< 0x00000002 */
10012 #define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */
10013 #define HRTIM_ODSR_TB1ODS_Pos         (2U)
10014 #define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)          /*!< 0x00000004 */
10015 #define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */
10016 #define HRTIM_ODSR_TB2ODS_Pos         (3U)
10017 #define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)          /*!< 0x00000008 */
10018 #define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */
10019 #define HRTIM_ODSR_TC1ODS_Pos         (4U)
10020 #define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)          /*!< 0x00000010 */
10021 #define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */
10022 #define HRTIM_ODSR_TC2ODS_Pos         (5U)
10023 #define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)          /*!< 0x00000020 */
10024 #define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */
10025 #define HRTIM_ODSR_TD1ODS_Pos         (6U)
10026 #define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)          /*!< 0x00000040 */
10027 #define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */
10028 #define HRTIM_ODSR_TD2ODS_Pos         (7U)
10029 #define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)          /*!< 0x00000080 */
10030 #define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */
10031 #define HRTIM_ODSR_TE1ODS_Pos         (8U)
10032 #define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)          /*!< 0x00000100 */
10033 #define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */
10034 #define HRTIM_ODSR_TE2ODS_Pos         (9U)
10035 #define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)          /*!< 0x00000200 */
10036 #define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */
10037 
10038 /**** Bit definition for Common HRTIM Timer Burst mode control register ********/
10039 #define HRTIM_BMCR_BME_Pos            (0U)
10040 #define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)             /*!< 0x00000001 */
10041 #define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enbale */
10042 #define HRTIM_BMCR_BMOM_Pos           (1U)
10043 #define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)            /*!< 0x00000002 */
10044 #define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */
10045 #define HRTIM_BMCR_BMCLK_Pos          (2U)
10046 #define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x0000003C */
10047 #define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */
10048 #define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */
10049 #define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */
10050 #define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */
10051 #define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */
10052 #define HRTIM_BMCR_BMPRSC_Pos         (6U)
10053 #define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x000003C0 */
10054 #define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */
10055 #define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */
10056 #define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */
10057 #define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */
10058 #define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */
10059 #define HRTIM_BMCR_BMPREN_Pos         (10U)
10060 #define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)          /*!< 0x00000400 */
10061 #define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */
10062 #define HRTIM_BMCR_MTBM_Pos           (16U)
10063 #define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)            /*!< 0x00010000 */
10064 #define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */
10065 #define HRTIM_BMCR_TABM_Pos           (17U)
10066 #define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)            /*!< 0x00020000 */
10067 #define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */
10068 #define HRTIM_BMCR_TBBM_Pos           (18U)
10069 #define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)            /*!< 0x00040000 */
10070 #define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */
10071 #define HRTIM_BMCR_TCBM_Pos           (19U)
10072 #define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)            /*!< 0x00080000 */
10073 #define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */
10074 #define HRTIM_BMCR_TDBM_Pos           (20U)
10075 #define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)            /*!< 0x00100000 */
10076 #define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */
10077 #define HRTIM_BMCR_TEBM_Pos           (21U)
10078 #define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)            /*!< 0x00200000 */
10079 #define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */
10080 #define HRTIM_BMCR_BMSTAT_Pos         (31U)
10081 #define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)          /*!< 0x80000000 */
10082 #define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */
10083 
10084 /**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
10085 #define HRTIM_BMTRGR_SW_Pos           (0U)
10086 #define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)            /*!< 0x00000001 */
10087 #define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */
10088 #define HRTIM_BMTRGR_MSTRST_Pos       (1U)
10089 #define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)        /*!< 0x00000002 */
10090 #define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */
10091 #define HRTIM_BMTRGR_MSTREP_Pos       (2U)
10092 #define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)        /*!< 0x00000004 */
10093 #define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */
10094 #define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)
10095 #define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)       /*!< 0x00000008 */
10096 #define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */
10097 #define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)
10098 #define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)       /*!< 0x00000010 */
10099 #define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */
10100 #define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)
10101 #define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)       /*!< 0x00000020 */
10102 #define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */
10103 #define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)
10104 #define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)       /*!< 0x00000040 */
10105 #define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */
10106 #define HRTIM_BMTRGR_TARST_Pos        (7U)
10107 #define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)         /*!< 0x00000080 */
10108 #define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */
10109 #define HRTIM_BMTRGR_TAREP_Pos        (8U)
10110 #define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)         /*!< 0x00000100 */
10111 #define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */
10112 #define HRTIM_BMTRGR_TACMP1_Pos       (9U)
10113 #define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)        /*!< 0x00000200 */
10114 #define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */
10115 #define HRTIM_BMTRGR_TACMP2_Pos       (10U)
10116 #define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)        /*!< 0x00000400 */
10117 #define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */
10118 #define HRTIM_BMTRGR_TBRST_Pos        (11U)
10119 #define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)         /*!< 0x00000800 */
10120 #define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */
10121 #define HRTIM_BMTRGR_TBREP_Pos        (12U)
10122 #define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)         /*!< 0x00001000 */
10123 #define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */
10124 #define HRTIM_BMTRGR_TBCMP1_Pos       (13U)
10125 #define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)        /*!< 0x00002000 */
10126 #define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */
10127 #define HRTIM_BMTRGR_TBCMP2_Pos       (14U)
10128 #define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)        /*!< 0x00004000 */
10129 #define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */
10130 #define HRTIM_BMTRGR_TCRST_Pos        (15U)
10131 #define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)         /*!< 0x00008000 */
10132 #define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */
10133 #define HRTIM_BMTRGR_TCREP_Pos        (16U)
10134 #define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)         /*!< 0x00010000 */
10135 #define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */
10136 #define HRTIM_BMTRGR_TCCMP1_Pos       (17U)
10137 #define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)        /*!< 0x00020000 */
10138 #define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */
10139 #define HRTIM_BMTRGR_TCCMP2_Pos       (18U)
10140 #define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)        /*!< 0x00040000 */
10141 #define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */
10142 #define HRTIM_BMTRGR_TDRST_Pos        (19U)
10143 #define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)         /*!< 0x00080000 */
10144 #define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */
10145 #define HRTIM_BMTRGR_TDREP_Pos        (20U)
10146 #define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)         /*!< 0x00100000 */
10147 #define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */
10148 #define HRTIM_BMTRGR_TDCMP1_Pos       (21U)
10149 #define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)        /*!< 0x00200000 */
10150 #define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */
10151 #define HRTIM_BMTRGR_TDCMP2_Pos       (22U)
10152 #define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)        /*!< 0x00400000 */
10153 #define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */
10154 #define HRTIM_BMTRGR_TERST_Pos        (23U)
10155 #define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)         /*!< 0x00800000 */
10156 #define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */
10157 #define HRTIM_BMTRGR_TEREP_Pos        (24U)
10158 #define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)         /*!< 0x01000000 */
10159 #define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */
10160 #define HRTIM_BMTRGR_TECMP1_Pos       (25U)
10161 #define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)        /*!< 0x02000000 */
10162 #define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */
10163 #define HRTIM_BMTRGR_TECMP2_Pos       (26U)
10164 #define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)        /*!< 0x04000000 */
10165 #define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */
10166 #define HRTIM_BMTRGR_TAEEV7_Pos       (27U)
10167 #define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)        /*!< 0x08000000 */
10168 #define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */
10169 #define HRTIM_BMTRGR_TDEEV8_Pos       (28U)
10170 #define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)        /*!< 0x10000000 */
10171 #define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */
10172 #define HRTIM_BMTRGR_EEV7_Pos         (29U)
10173 #define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)          /*!< 0x20000000 */
10174 #define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */
10175 #define HRTIM_BMTRGR_EEV8_Pos         (30U)
10176 #define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)          /*!< 0x40000000 */
10177 #define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */
10178 #define HRTIM_BMTRGR_OCHPEV_Pos       (31U)
10179 #define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)        /*!< 0x80000000 */
10180 #define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */
10181 
10182 /*******************  Bit definition for HRTIM_BMCMPR register  ***************/
10183 #define HRTIM_BMCMPR_BMCMPR_Pos       (0U)
10184 #define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)     /*!< 0x0000FFFF */
10185 #define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                   /*!<!<Burst Compare Value */
10186 
10187 /*******************  Bit definition for HRTIM_BMPER register  ****************/
10188 #define HRTIM_BMPER_BMPER_Pos         (0U)
10189 #define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)       /*!< 0x0000FFFF */
10190 #define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                     /*!<!<Burst period Value */
10191 
10192 /*******************  Bit definition for HRTIM_EECR1 register  ****************/
10193 #define HRTIM_EECR1_EE1SRC_Pos        (0U)
10194 #define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000003 */
10195 #define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */
10196 #define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */
10197 #define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */
10198 #define HRTIM_EECR1_EE1POL_Pos        (2U)
10199 #define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)         /*!< 0x00000004 */
10200 #define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */
10201 #define HRTIM_EECR1_EE1SNS_Pos        (3U)
10202 #define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000018 */
10203 #define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */
10204 #define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */
10205 #define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */
10206 #define HRTIM_EECR1_EE1FAST_Pos       (5U)
10207 #define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)        /*!< 0x00000020 */
10208 #define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */
10209 
10210 #define HRTIM_EECR1_EE2SRC_Pos        (6U)
10211 #define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x000000C0 */
10212 #define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */
10213 #define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */
10214 #define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */
10215 #define HRTIM_EECR1_EE2POL_Pos        (8U)
10216 #define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)         /*!< 0x00000100 */
10217 #define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */
10218 #define HRTIM_EECR1_EE2SNS_Pos        (9U)
10219 #define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000600 */
10220 #define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */
10221 #define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */
10222 #define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */
10223 #define HRTIM_EECR1_EE2FAST_Pos       (11U)
10224 #define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)        /*!< 0x00000800 */
10225 #define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */
10226 
10227 #define HRTIM_EECR1_EE3SRC_Pos        (12U)
10228 #define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00003000 */
10229 #define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */
10230 #define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */
10231 #define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */
10232 #define HRTIM_EECR1_EE3POL_Pos        (14U)
10233 #define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)         /*!< 0x00004000 */
10234 #define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */
10235 #define HRTIM_EECR1_EE3SNS_Pos        (15U)
10236 #define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00018000 */
10237 #define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */
10238 #define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */
10239 #define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */
10240 #define HRTIM_EECR1_EE3FAST_Pos       (17U)
10241 #define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)        /*!< 0x00020000 */
10242 #define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */
10243 
10244 #define HRTIM_EECR1_EE4SRC_Pos        (18U)
10245 #define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x000C0000 */
10246 #define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */
10247 #define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */
10248 #define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */
10249 #define HRTIM_EECR1_EE4POL_Pos        (20U)
10250 #define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)         /*!< 0x00100000 */
10251 #define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */
10252 #define HRTIM_EECR1_EE4SNS_Pos        (21U)
10253 #define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00600000 */
10254 #define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */
10255 #define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */
10256 #define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */
10257 #define HRTIM_EECR1_EE4FAST_Pos       (23U)
10258 #define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)        /*!< 0x00800000 */
10259 #define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */
10260 
10261 #define HRTIM_EECR1_EE5SRC_Pos        (24U)
10262 #define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x03000000 */
10263 #define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */
10264 #define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */
10265 #define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */
10266 #define HRTIM_EECR1_EE5POL_Pos        (26U)
10267 #define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)         /*!< 0x04000000 */
10268 #define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */
10269 #define HRTIM_EECR1_EE5SNS_Pos        (27U)
10270 #define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x18000000 */
10271 #define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */
10272 #define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */
10273 #define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */
10274 #define HRTIM_EECR1_EE5FAST_Pos       (29U)
10275 #define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)        /*!< 0x20000000 */
10276 #define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */
10277 
10278 /*******************  Bit definition for HRTIM_EECR2 register  ****************/
10279 #define HRTIM_EECR2_EE6SRC_Pos        (0U)
10280 #define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000003 */
10281 #define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */
10282 #define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */
10283 #define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */
10284 #define HRTIM_EECR2_EE6POL_Pos        (2U)
10285 #define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)         /*!< 0x00000004 */
10286 #define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */
10287 #define HRTIM_EECR2_EE6SNS_Pos        (3U)
10288 #define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000018 */
10289 #define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */
10290 #define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */
10291 #define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */
10292 
10293 #define HRTIM_EECR2_EE7SRC_Pos        (6U)
10294 #define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x000000C0 */
10295 #define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */
10296 #define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */
10297 #define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */
10298 #define HRTIM_EECR2_EE7POL_Pos        (8U)
10299 #define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)         /*!< 0x00000100 */
10300 #define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */
10301 #define HRTIM_EECR2_EE7SNS_Pos        (9U)
10302 #define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000600 */
10303 #define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */
10304 #define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */
10305 #define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */
10306 
10307 #define HRTIM_EECR2_EE8SRC_Pos        (12U)
10308 #define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00003000 */
10309 #define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */
10310 #define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */
10311 #define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */
10312 #define HRTIM_EECR2_EE8POL_Pos        (14U)
10313 #define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)         /*!< 0x00004000 */
10314 #define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */
10315 #define HRTIM_EECR2_EE8SNS_Pos        (15U)
10316 #define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00018000 */
10317 #define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */
10318 #define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */
10319 #define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */
10320 
10321 #define HRTIM_EECR2_EE9SRC_Pos        (18U)
10322 #define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x000C0000 */
10323 #define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */
10324 #define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */
10325 #define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */
10326 #define HRTIM_EECR2_EE9POL_Pos        (20U)
10327 #define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)         /*!< 0x00100000 */
10328 #define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */
10329 #define HRTIM_EECR2_EE9SNS_Pos        (21U)
10330 #define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00600000 */
10331 #define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */
10332 #define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */
10333 #define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */
10334 
10335 #define HRTIM_EECR2_EE10SRC_Pos       (24U)
10336 #define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x03000000 */
10337 #define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */
10338 #define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */
10339 #define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */
10340 #define HRTIM_EECR2_EE10POL_Pos       (26U)
10341 #define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)        /*!< 0x04000000 */
10342 #define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */
10343 #define HRTIM_EECR2_EE10SNS_Pos       (27U)
10344 #define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x18000000 */
10345 #define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */
10346 #define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */
10347 #define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */
10348 
10349 /*******************  Bit definition for HRTIM_EECR3 register  ****************/
10350 #define HRTIM_EECR3_EE6F_Pos          (0U)
10351 #define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x0000000F */
10352 #define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */
10353 #define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */
10354 #define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */
10355 #define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */
10356 #define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */
10357 #define HRTIM_EECR3_EE7F_Pos          (6U)
10358 #define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x000003C0 */
10359 #define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */
10360 #define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */
10361 #define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */
10362 #define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */
10363 #define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */
10364 #define HRTIM_EECR3_EE8F_Pos          (12U)
10365 #define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x0000F000 */
10366 #define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */
10367 #define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */
10368 #define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */
10369 #define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */
10370 #define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */
10371 #define HRTIM_EECR3_EE9F_Pos          (18U)
10372 #define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x003C0000 */
10373 #define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */
10374 #define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */
10375 #define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */
10376 #define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */
10377 #define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */
10378 #define HRTIM_EECR3_EE10F_Pos         (24U)
10379 #define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x0F000000 */
10380 #define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */
10381 #define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */
10382 #define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */
10383 #define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */
10384 #define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */
10385 #define HRTIM_EECR3_EEVSD_Pos         (30U)
10386 #define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0xC0000000 */
10387 #define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */
10388 #define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */
10389 #define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */
10390 
10391 /*******************  Bit definition for HRTIM_ADC1R register  ****************/
10392 #define HRTIM_ADC1R_AD1MC1_Pos        (0U)
10393 #define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)         /*!< 0x00000001 */
10394 #define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */
10395 #define HRTIM_ADC1R_AD1MC2_Pos        (1U)
10396 #define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)         /*!< 0x00000002 */
10397 #define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */
10398 #define HRTIM_ADC1R_AD1MC3_Pos        (2U)
10399 #define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)         /*!< 0x00000004 */
10400 #define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */
10401 #define HRTIM_ADC1R_AD1MC4_Pos        (3U)
10402 #define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)         /*!< 0x00000008 */
10403 #define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */
10404 #define HRTIM_ADC1R_AD1MPER_Pos       (4U)
10405 #define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)        /*!< 0x00000010 */
10406 #define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */
10407 #define HRTIM_ADC1R_AD1EEV1_Pos       (5U)
10408 #define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)        /*!< 0x00000020 */
10409 #define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */
10410 #define HRTIM_ADC1R_AD1EEV2_Pos       (6U)
10411 #define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)        /*!< 0x00000040 */
10412 #define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */
10413 #define HRTIM_ADC1R_AD1EEV3_Pos       (7U)
10414 #define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)        /*!< 0x00000080 */
10415 #define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */
10416 #define HRTIM_ADC1R_AD1EEV4_Pos       (8U)
10417 #define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)        /*!< 0x00000100 */
10418 #define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */
10419 #define HRTIM_ADC1R_AD1EEV5_Pos       (9U)
10420 #define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)        /*!< 0x00000200 */
10421 #define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */
10422 #define HRTIM_ADC1R_AD1TAC2_Pos       (10U)
10423 #define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)        /*!< 0x00000400 */
10424 #define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */
10425 #define HRTIM_ADC1R_AD1TAC3_Pos       (11U)
10426 #define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)        /*!< 0x00000800 */
10427 #define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */
10428 #define HRTIM_ADC1R_AD1TAC4_Pos       (12U)
10429 #define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)        /*!< 0x00001000 */
10430 #define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */
10431 #define HRTIM_ADC1R_AD1TAPER_Pos      (13U)
10432 #define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)       /*!< 0x00002000 */
10433 #define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */
10434 #define HRTIM_ADC1R_AD1TARST_Pos      (14U)
10435 #define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)       /*!< 0x00004000 */
10436 #define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */
10437 #define HRTIM_ADC1R_AD1TBC2_Pos       (15U)
10438 #define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)        /*!< 0x00008000 */
10439 #define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */
10440 #define HRTIM_ADC1R_AD1TBC3_Pos       (16U)
10441 #define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)        /*!< 0x00010000 */
10442 #define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */
10443 #define HRTIM_ADC1R_AD1TBC4_Pos       (17U)
10444 #define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)        /*!< 0x00020000 */
10445 #define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */
10446 #define HRTIM_ADC1R_AD1TBPER_Pos      (18U)
10447 #define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)       /*!< 0x00040000 */
10448 #define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */
10449 #define HRTIM_ADC1R_AD1TBRST_Pos      (19U)
10450 #define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)       /*!< 0x00080000 */
10451 #define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */
10452 #define HRTIM_ADC1R_AD1TCC2_Pos       (20U)
10453 #define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)        /*!< 0x00100000 */
10454 #define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */
10455 #define HRTIM_ADC1R_AD1TCC3_Pos       (21U)
10456 #define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)        /*!< 0x00200000 */
10457 #define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */
10458 #define HRTIM_ADC1R_AD1TCC4_Pos       (22U)
10459 #define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)        /*!< 0x00400000 */
10460 #define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */
10461 #define HRTIM_ADC1R_AD1TCPER_Pos      (23U)
10462 #define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)       /*!< 0x00800000 */
10463 #define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */
10464 #define HRTIM_ADC1R_AD1TDC2_Pos       (24U)
10465 #define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)        /*!< 0x01000000 */
10466 #define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */
10467 #define HRTIM_ADC1R_AD1TDC3_Pos       (25U)
10468 #define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)        /*!< 0x02000000 */
10469 #define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */
10470 #define HRTIM_ADC1R_AD1TDC4_Pos       (26U)
10471 #define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)        /*!< 0x04000000 */
10472 #define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */
10473 #define HRTIM_ADC1R_AD1TDPER_Pos      (27U)
10474 #define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)       /*!< 0x08000000 */
10475 #define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */
10476 #define HRTIM_ADC1R_AD1TEC2_Pos       (28U)
10477 #define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)        /*!< 0x10000000 */
10478 #define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */
10479 #define HRTIM_ADC1R_AD1TEC3_Pos       (29U)
10480 #define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)        /*!< 0x20000000 */
10481 #define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */
10482 #define HRTIM_ADC1R_AD1TEC4_Pos       (30U)
10483 #define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)        /*!< 0x40000000 */
10484 #define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */
10485 #define HRTIM_ADC1R_AD1TEPER_Pos      (31U)
10486 #define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)       /*!< 0x80000000 */
10487 #define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */
10488 
10489 /*******************  Bit definition for HRTIM_ADC2R register  ****************/
10490 #define HRTIM_ADC2R_AD2MC1_Pos        (0U)
10491 #define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)         /*!< 0x00000001 */
10492 #define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */
10493 #define HRTIM_ADC2R_AD2MC2_Pos        (1U)
10494 #define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)         /*!< 0x00000002 */
10495 #define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */
10496 #define HRTIM_ADC2R_AD2MC3_Pos        (2U)
10497 #define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)         /*!< 0x00000004 */
10498 #define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */
10499 #define HRTIM_ADC2R_AD2MC4_Pos        (3U)
10500 #define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)         /*!< 0x00000008 */
10501 #define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */
10502 #define HRTIM_ADC2R_AD2MPER_Pos       (4U)
10503 #define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)        /*!< 0x00000010 */
10504 #define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */
10505 #define HRTIM_ADC2R_AD2EEV6_Pos       (5U)
10506 #define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)        /*!< 0x00000020 */
10507 #define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */
10508 #define HRTIM_ADC2R_AD2EEV7_Pos       (6U)
10509 #define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)        /*!< 0x00000040 */
10510 #define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */
10511 #define HRTIM_ADC2R_AD2EEV8_Pos       (7U)
10512 #define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)        /*!< 0x00000080 */
10513 #define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */
10514 #define HRTIM_ADC2R_AD2EEV9_Pos       (8U)
10515 #define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)        /*!< 0x00000100 */
10516 #define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */
10517 #define HRTIM_ADC2R_AD2EEV10_Pos      (9U)
10518 #define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)       /*!< 0x00000200 */
10519 #define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */
10520 #define HRTIM_ADC2R_AD2TAC2_Pos       (10U)
10521 #define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)        /*!< 0x00000400 */
10522 #define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */
10523 #define HRTIM_ADC2R_AD2TAC3_Pos       (11U)
10524 #define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)        /*!< 0x00000800 */
10525 #define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */
10526 #define HRTIM_ADC2R_AD2TAC4_Pos       (12U)
10527 #define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)        /*!< 0x00001000 */
10528 #define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/
10529 #define HRTIM_ADC2R_AD2TAPER_Pos      (13U)
10530 #define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)       /*!< 0x00002000 */
10531 #define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */
10532 #define HRTIM_ADC2R_AD2TBC2_Pos       (14U)
10533 #define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)        /*!< 0x00004000 */
10534 #define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */
10535 #define HRTIM_ADC2R_AD2TBC3_Pos       (15U)
10536 #define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)        /*!< 0x00008000 */
10537 #define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */
10538 #define HRTIM_ADC2R_AD2TBC4_Pos       (16U)
10539 #define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)        /*!< 0x00010000 */
10540 #define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */
10541 #define HRTIM_ADC2R_AD2TBPER_Pos      (17U)
10542 #define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)       /*!< 0x00020000 */
10543 #define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */
10544 #define HRTIM_ADC2R_AD2TCC2_Pos       (18U)
10545 #define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)        /*!< 0x00040000 */
10546 #define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */
10547 #define HRTIM_ADC2R_AD2TCC3_Pos       (19U)
10548 #define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)        /*!< 0x00080000 */
10549 #define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */
10550 #define HRTIM_ADC2R_AD2TCC4_Pos       (20U)
10551 #define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)        /*!< 0x00100000 */
10552 #define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */
10553 #define HRTIM_ADC2R_AD2TCPER_Pos      (21U)
10554 #define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)       /*!< 0x00200000 */
10555 #define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */
10556 #define HRTIM_ADC2R_AD2TCRST_Pos      (22U)
10557 #define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)       /*!< 0x00400000 */
10558 #define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */
10559 #define HRTIM_ADC2R_AD2TDC2_Pos       (23U)
10560 #define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)        /*!< 0x00800000 */
10561 #define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */
10562 #define HRTIM_ADC2R_AD2TDC3_Pos       (24U)
10563 #define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)        /*!< 0x01000000 */
10564 #define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */
10565 #define HRTIM_ADC2R_AD2TDC4_Pos       (25U)
10566 #define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)        /*!< 0x02000000 */
10567 #define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/
10568 #define HRTIM_ADC2R_AD2TDPER_Pos      (26U)
10569 #define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)       /*!< 0x04000000 */
10570 #define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */
10571 #define HRTIM_ADC2R_AD2TDRST_Pos      (27U)
10572 #define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)       /*!< 0x08000000 */
10573 #define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */
10574 #define HRTIM_ADC2R_AD2TEC2_Pos       (28U)
10575 #define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)        /*!< 0x10000000 */
10576 #define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */
10577 #define HRTIM_ADC2R_AD2TEC3_Pos       (29U)
10578 #define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)        /*!< 0x20000000 */
10579 #define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */
10580 #define HRTIM_ADC2R_AD2TEC4_Pos       (30U)
10581 #define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)        /*!< 0x40000000 */
10582 #define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */
10583 #define HRTIM_ADC2R_AD2TERST_Pos      (31U)
10584 #define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)       /*!< 0x80000000 */
10585 #define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */
10586 
10587 /*******************  Bit definition for HRTIM_ADC3R register  ****************/
10588 #define HRTIM_ADC3R_AD3MC1_Pos        (0U)
10589 #define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)         /*!< 0x00000001 */
10590 #define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */
10591 #define HRTIM_ADC3R_AD3MC2_Pos        (1U)
10592 #define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)         /*!< 0x00000002 */
10593 #define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */
10594 #define HRTIM_ADC3R_AD3MC3_Pos        (2U)
10595 #define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)         /*!< 0x00000004 */
10596 #define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */
10597 #define HRTIM_ADC3R_AD3MC4_Pos        (3U)
10598 #define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)         /*!< 0x00000008 */
10599 #define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */
10600 #define HRTIM_ADC3R_AD3MPER_Pos       (4U)
10601 #define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)        /*!< 0x00000010 */
10602 #define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */
10603 #define HRTIM_ADC3R_AD3EEV1_Pos       (5U)
10604 #define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)        /*!< 0x00000020 */
10605 #define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */
10606 #define HRTIM_ADC3R_AD3EEV2_Pos       (6U)
10607 #define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)        /*!< 0x00000040 */
10608 #define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */
10609 #define HRTIM_ADC3R_AD3EEV3_Pos       (7U)
10610 #define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)        /*!< 0x00000080 */
10611 #define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */
10612 #define HRTIM_ADC3R_AD3EEV4_Pos       (8U)
10613 #define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)        /*!< 0x00000100 */
10614 #define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */
10615 #define HRTIM_ADC3R_AD3EEV5_Pos       (9U)
10616 #define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)        /*!< 0x00000200 */
10617 #define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */
10618 #define HRTIM_ADC3R_AD3TAC2_Pos       (10U)
10619 #define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)        /*!< 0x00000400 */
10620 #define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */
10621 #define HRTIM_ADC3R_AD3TAC3_Pos       (11U)
10622 #define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)        /*!< 0x00000800 */
10623 #define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */
10624 #define HRTIM_ADC3R_AD3TAC4_Pos       (12U)
10625 #define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)        /*!< 0x00001000 */
10626 #define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */
10627 #define HRTIM_ADC3R_AD3TAPER_Pos      (13U)
10628 #define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)       /*!< 0x00002000 */
10629 #define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */
10630 #define HRTIM_ADC3R_AD3TARST_Pos      (14U)
10631 #define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)       /*!< 0x00004000 */
10632 #define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */
10633 #define HRTIM_ADC3R_AD3TBC2_Pos       (15U)
10634 #define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)        /*!< 0x00008000 */
10635 #define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */
10636 #define HRTIM_ADC3R_AD3TBC3_Pos       (16U)
10637 #define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)        /*!< 0x00010000 */
10638 #define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */
10639 #define HRTIM_ADC3R_AD3TBC4_Pos       (17U)
10640 #define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)        /*!< 0x00020000 */
10641 #define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */
10642 #define HRTIM_ADC3R_AD3TBPER_Pos      (18U)
10643 #define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)       /*!< 0x00040000 */
10644 #define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */
10645 #define HRTIM_ADC3R_AD3TBRST_Pos      (19U)
10646 #define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)       /*!< 0x00080000 */
10647 #define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */
10648 #define HRTIM_ADC3R_AD3TCC2_Pos       (20U)
10649 #define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)        /*!< 0x00100000 */
10650 #define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */
10651 #define HRTIM_ADC3R_AD3TCC3_Pos       (21U)
10652 #define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)        /*!< 0x00200000 */
10653 #define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */
10654 #define HRTIM_ADC3R_AD3TCC4_Pos       (22U)
10655 #define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)        /*!< 0x00400000 */
10656 #define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */
10657 #define HRTIM_ADC3R_AD3TCPER_Pos      (23U)
10658 #define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)       /*!< 0x00800000 */
10659 #define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */
10660 #define HRTIM_ADC3R_AD3TDC2_Pos       (24U)
10661 #define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)        /*!< 0x01000000 */
10662 #define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */
10663 #define HRTIM_ADC3R_AD3TDC3_Pos       (25U)
10664 #define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)        /*!< 0x02000000 */
10665 #define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */
10666 #define HRTIM_ADC3R_AD3TDC4_Pos       (26U)
10667 #define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)        /*!< 0x04000000 */
10668 #define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */
10669 #define HRTIM_ADC3R_AD3TDPER_Pos      (27U)
10670 #define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)       /*!< 0x08000000 */
10671 #define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */
10672 #define HRTIM_ADC3R_AD3TEC2_Pos       (28U)
10673 #define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)        /*!< 0x10000000 */
10674 #define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */
10675 #define HRTIM_ADC3R_AD3TEC3_Pos       (29U)
10676 #define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)        /*!< 0x20000000 */
10677 #define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */
10678 #define HRTIM_ADC3R_AD3TEC4_Pos       (30U)
10679 #define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)        /*!< 0x40000000 */
10680 #define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */
10681 #define HRTIM_ADC3R_AD3TEPER_Pos      (31U)
10682 #define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)       /*!< 0x80000000 */
10683 #define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */
10684 
10685 /*******************  Bit definition for HRTIM_ADC4R register  ****************/
10686 #define HRTIM_ADC4R_AD4MC1_Pos        (0U)
10687 #define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)         /*!< 0x00000001 */
10688 #define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */
10689 #define HRTIM_ADC4R_AD4MC2_Pos        (1U)
10690 #define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)         /*!< 0x00000002 */
10691 #define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */
10692 #define HRTIM_ADC4R_AD4MC3_Pos        (2U)
10693 #define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)         /*!< 0x00000004 */
10694 #define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */
10695 #define HRTIM_ADC4R_AD4MC4_Pos        (3U)
10696 #define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)         /*!< 0x00000008 */
10697 #define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */
10698 #define HRTIM_ADC4R_AD4MPER_Pos       (4U)
10699 #define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)        /*!< 0x00000010 */
10700 #define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */
10701 #define HRTIM_ADC4R_AD4EEV6_Pos       (5U)
10702 #define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)        /*!< 0x00000020 */
10703 #define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */
10704 #define HRTIM_ADC4R_AD4EEV7_Pos       (6U)
10705 #define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)        /*!< 0x00000040 */
10706 #define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */
10707 #define HRTIM_ADC4R_AD4EEV8_Pos       (7U)
10708 #define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)        /*!< 0x00000080 */
10709 #define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */
10710 #define HRTIM_ADC4R_AD4EEV9_Pos       (8U)
10711 #define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)        /*!< 0x00000100 */
10712 #define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */
10713 #define HRTIM_ADC4R_AD4EEV10_Pos      (9U)
10714 #define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)       /*!< 0x00000200 */
10715 #define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */
10716 #define HRTIM_ADC4R_AD4TAC2_Pos       (10U)
10717 #define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)        /*!< 0x00000400 */
10718 #define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */
10719 #define HRTIM_ADC4R_AD4TAC3_Pos       (11U)
10720 #define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)        /*!< 0x00000800 */
10721 #define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */
10722 #define HRTIM_ADC4R_AD4TAC4_Pos       (12U)
10723 #define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)        /*!< 0x00001000 */
10724 #define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/
10725 #define HRTIM_ADC4R_AD4TAPER_Pos      (13U)
10726 #define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)       /*!< 0x00002000 */
10727 #define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */
10728 #define HRTIM_ADC4R_AD4TBC2_Pos       (14U)
10729 #define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)        /*!< 0x00004000 */
10730 #define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */
10731 #define HRTIM_ADC4R_AD4TBC3_Pos       (15U)
10732 #define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)        /*!< 0x00008000 */
10733 #define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */
10734 #define HRTIM_ADC4R_AD4TBC4_Pos       (16U)
10735 #define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)        /*!< 0x00010000 */
10736 #define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */
10737 #define HRTIM_ADC4R_AD4TBPER_Pos      (17U)
10738 #define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)       /*!< 0x00020000 */
10739 #define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */
10740 #define HRTIM_ADC4R_AD4TCC2_Pos       (18U)
10741 #define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)        /*!< 0x00040000 */
10742 #define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */
10743 #define HRTIM_ADC4R_AD4TCC3_Pos       (19U)
10744 #define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)        /*!< 0x00080000 */
10745 #define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */
10746 #define HRTIM_ADC4R_AD4TCC4_Pos       (20U)
10747 #define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)        /*!< 0x00100000 */
10748 #define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */
10749 #define HRTIM_ADC4R_AD4TCPER_Pos      (21U)
10750 #define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)       /*!< 0x00200000 */
10751 #define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */
10752 #define HRTIM_ADC4R_AD4TCRST_Pos      (22U)
10753 #define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)       /*!< 0x00400000 */
10754 #define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */
10755 #define HRTIM_ADC4R_AD4TDC2_Pos       (23U)
10756 #define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)        /*!< 0x00800000 */
10757 #define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */
10758 #define HRTIM_ADC4R_AD4TDC3_Pos       (24U)
10759 #define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)        /*!< 0x01000000 */
10760 #define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */
10761 #define HRTIM_ADC4R_AD4TDC4_Pos       (25U)
10762 #define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)        /*!< 0x02000000 */
10763 #define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/
10764 #define HRTIM_ADC4R_AD4TDPER_Pos      (26U)
10765 #define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)       /*!< 0x04000000 */
10766 #define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */
10767 #define HRTIM_ADC4R_AD4TDRST_Pos      (27U)
10768 #define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)       /*!< 0x08000000 */
10769 #define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */
10770 #define HRTIM_ADC4R_AD4TEC2_Pos       (28U)
10771 #define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)        /*!< 0x10000000 */
10772 #define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */
10773 #define HRTIM_ADC4R_AD4TEC3_Pos       (29U)
10774 #define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)        /*!< 0x20000000 */
10775 #define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */
10776 #define HRTIM_ADC4R_AD4TEC4_Pos       (30U)
10777 #define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)        /*!< 0x40000000 */
10778 #define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */
10779 #define HRTIM_ADC4R_AD4TERST_Pos      (31U)
10780 #define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)       /*!< 0x80000000 */
10781 #define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */
10782 
10783 /*******************  Bit definition for HRTIM_DLLCR register  ****************/
10784 #define HRTIM_DLLCR_CAL_Pos           (0U)
10785 #define HRTIM_DLLCR_CAL_Msk           (0x1UL << HRTIM_DLLCR_CAL_Pos)            /*!< 0x00000001 */
10786 #define HRTIM_DLLCR_CAL               HRTIM_DLLCR_CAL_Msk                      /*!< DLL calibration start */
10787 #define HRTIM_DLLCR_CALEN_Pos         (1U)
10788 #define HRTIM_DLLCR_CALEN_Msk         (0x1UL << HRTIM_DLLCR_CALEN_Pos)          /*!< 0x00000002 */
10789 #define HRTIM_DLLCR_CALEN             HRTIM_DLLCR_CALEN_Msk                    /*!< DLL calibration enable */
10790 #define HRTIM_DLLCR_CALRTE_Pos        (2U)
10791 #define HRTIM_DLLCR_CALRTE_Msk        (0x3UL << HRTIM_DLLCR_CALRTE_Pos)         /*!< 0x0000000C */
10792 #define HRTIM_DLLCR_CALRTE            HRTIM_DLLCR_CALRTE_Msk                   /*!< DLL calibration rate */
10793 #define HRTIM_DLLCR_CALRTE_0          (0x1UL << HRTIM_DLLCR_CALRTE_Pos)         /*!< 0x00000004 */
10794 #define HRTIM_DLLCR_CALRTE_1          (0x2UL << HRTIM_DLLCR_CALRTE_Pos)         /*!< 0x00000008 */
10795 
10796 /*******************  Bit definition for HRTIM_FLTINR1 register  ***************/
10797 #define HRTIM_FLTINR1_FLT1E_Pos       (0U)
10798 #define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)        /*!< 0x00000001 */
10799 #define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */
10800 #define HRTIM_FLTINR1_FLT1P_Pos       (1U)
10801 #define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)        /*!< 0x00000002 */
10802 #define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */
10803 #define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)
10804 #define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)      /*!< 0x00000004 */
10805 #define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */
10806 #define HRTIM_FLTINR1_FLT1F_Pos       (3U)
10807 #define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000078 */
10808 #define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */
10809 #define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */
10810 #define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */
10811 #define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */
10812 #define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */
10813 #define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)
10814 #define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)      /*!< 0x00000080 */
10815 #define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */
10816 
10817 #define HRTIM_FLTINR1_FLT2E_Pos       (8U)
10818 #define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)        /*!< 0x00000100 */
10819 #define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */
10820 #define HRTIM_FLTINR1_FLT2P_Pos       (9U)
10821 #define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)        /*!< 0x00000200 */
10822 #define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */
10823 #define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)
10824 #define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)      /*!< 0x00000400 */
10825 #define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */
10826 #define HRTIM_FLTINR1_FLT2F_Pos       (11U)
10827 #define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00007800 */
10828 #define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */
10829 #define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */
10830 #define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */
10831 #define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */
10832 #define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */
10833 #define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)
10834 #define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)      /*!< 0x00008000 */
10835 #define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */
10836 
10837 #define HRTIM_FLTINR1_FLT3E_Pos       (16U)
10838 #define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)        /*!< 0x00010000 */
10839 #define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */
10840 #define HRTIM_FLTINR1_FLT3P_Pos       (17U)
10841 #define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)        /*!< 0x00020000 */
10842 #define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */
10843 #define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)
10844 #define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)      /*!< 0x00040000 */
10845 #define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */
10846 #define HRTIM_FLTINR1_FLT3F_Pos       (19U)
10847 #define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00780000 */
10848 #define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */
10849 #define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */
10850 #define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */
10851 #define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */
10852 #define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */
10853 #define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)
10854 #define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)      /*!< 0x00800000 */
10855 #define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */
10856 
10857 #define HRTIM_FLTINR1_FLT4E_Pos       (24U)
10858 #define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)        /*!< 0x01000000 */
10859 #define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */
10860 #define HRTIM_FLTINR1_FLT4P_Pos       (25U)
10861 #define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)        /*!< 0x02000000 */
10862 #define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */
10863 #define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)
10864 #define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)      /*!< 0x04000000 */
10865 #define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */
10866 #define HRTIM_FLTINR1_FLT4F_Pos       (27U)
10867 #define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x78000000 */
10868 #define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */
10869 #define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */
10870 #define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */
10871 #define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */
10872 #define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */
10873 #define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)
10874 #define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)      /*!< 0x80000000 */
10875 #define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */
10876 
10877 /*******************  Bit definition for HRTIM_FLTINR2 register  ***************/
10878 #define HRTIM_FLTINR2_FLT5E_Pos       (0U)
10879 #define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)        /*!< 0x00000001 */
10880 #define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */
10881 #define HRTIM_FLTINR2_FLT5P_Pos       (1U)
10882 #define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)        /*!< 0x00000002 */
10883 #define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */
10884 #define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)
10885 #define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)      /*!< 0x00000004 */
10886 #define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */
10887 #define HRTIM_FLTINR2_FLT5F_Pos       (3U)
10888 #define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000078 */
10889 #define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */
10890 #define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */
10891 #define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */
10892 #define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */
10893 #define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */
10894 #define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)
10895 #define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)      /*!< 0x00000080 */
10896 #define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */
10897 #define HRTIM_FLTINR2_FLTSD_Pos       (24U)
10898 #define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x03000000 */
10899 #define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */
10900 #define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */
10901 #define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */
10902 
10903 /*******************  Bit definition for HRTIM_BDMUPR register  ***************/
10904 #define HRTIM_BDMUPR_MCR_Pos          (0U)
10905 #define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)           /*!< 0x00000001 */
10906 #define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */
10907 #define HRTIM_BDMUPR_MICR_Pos         (1U)
10908 #define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)          /*!< 0x00000002 */
10909 #define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */
10910 #define HRTIM_BDMUPR_MDIER_Pos        (2U)
10911 #define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)         /*!< 0x00000004 */
10912 #define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */
10913 #define HRTIM_BDMUPR_MCNT_Pos         (3U)
10914 #define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)          /*!< 0x00000008 */
10915 #define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */
10916 #define HRTIM_BDMUPR_MPER_Pos         (4U)
10917 #define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)          /*!< 0x00000010 */
10918 #define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */
10919 #define HRTIM_BDMUPR_MREP_Pos         (5U)
10920 #define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)          /*!< 0x00000020 */
10921 #define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */
10922 #define HRTIM_BDMUPR_MCMP1_Pos        (6U)
10923 #define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)         /*!< 0x00000040 */
10924 #define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */
10925 #define HRTIM_BDMUPR_MCMP2_Pos        (7U)
10926 #define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)         /*!< 0x00000080 */
10927 #define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */
10928 #define HRTIM_BDMUPR_MCMP3_Pos        (8U)
10929 #define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)         /*!< 0x00000100 */
10930 #define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */
10931 #define HRTIM_BDMUPR_MCMP4_Pos        (9U)
10932 #define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)         /*!< 0x00000200 */
10933 #define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */
10934 
10935 /*******************  Bit definition for HRTIM_BDTUPR register  ***************/
10936 #define HRTIM_BDTUPR_TIMCR_Pos        (0U)
10937 #define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)         /*!< 0x00000001 */
10938 #define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */
10939 #define HRTIM_BDTUPR_TIMICR_Pos       (1U)
10940 #define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)        /*!< 0x00000002 */
10941 #define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */
10942 #define HRTIM_BDTUPR_TIMDIER_Pos      (2U)
10943 #define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)       /*!< 0x00000004 */
10944 #define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */
10945 #define HRTIM_BDTUPR_TIMCNT_Pos       (3U)
10946 #define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)        /*!< 0x00000008 */
10947 #define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */
10948 #define HRTIM_BDTUPR_TIMPER_Pos       (4U)
10949 #define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)        /*!< 0x00000010 */
10950 #define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */
10951 #define HRTIM_BDTUPR_TIMREP_Pos       (5U)
10952 #define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)        /*!< 0x00000020 */
10953 #define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */
10954 #define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)
10955 #define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)       /*!< 0x00000040 */
10956 #define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */
10957 #define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)
10958 #define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)       /*!< 0x00000080 */
10959 #define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */
10960 #define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)
10961 #define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)       /*!< 0x00000100 */
10962 #define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */
10963 #define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)
10964 #define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)       /*!< 0x00000200 */
10965 #define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */
10966 #define HRTIM_BDTUPR_TIMDTR_Pos       (10U)
10967 #define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)        /*!< 0x00000400 */
10968 #define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */
10969 #define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)
10970 #define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)      /*!< 0x00000800 */
10971 #define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */
10972 #define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)
10973 #define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)      /*!< 0x00001000 */
10974 #define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */
10975 #define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)
10976 #define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)      /*!< 0x00002000 */
10977 #define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */
10978 #define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)
10979 #define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)      /*!< 0x00004000 */
10980 #define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */
10981 #define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)
10982 #define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)      /*!< 0x00008000 */
10983 #define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */
10984 #define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)
10985 #define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)      /*!< 0x00010000 */
10986 #define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */
10987 #define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)
10988 #define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)       /*!< 0x00020000 */
10989 #define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */
10990 #define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)
10991 #define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)       /*!< 0x00040000 */
10992 #define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */
10993 #define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)
10994 #define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)       /*!< 0x00080000 */
10995 #define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */
10996 #define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)
10997 #define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)       /*!< 0x00100000 */
10998 #define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */
10999 
11000 /*******************  Bit definition for HRTIM_BDMADR register  ***************/
11001 #define HRTIM_BDMADR_BDMADR_Pos       (0U)
11002 #define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */
11003 #define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */
11004 
11005 /******************************************************************************/
11006 /*                                                                            */
11007 /*                      Inter-integrated Circuit Interface (I2C)              */
11008 /*                                                                            */
11009 /******************************************************************************/
11010 /*******************  Bit definition for I2C_CR1 register  *******************/
11011 #define I2C_CR1_PE_Pos               (0U)
11012 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
11013 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
11014 #define I2C_CR1_TXIE_Pos             (1U)
11015 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
11016 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
11017 #define I2C_CR1_RXIE_Pos             (2U)
11018 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
11019 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
11020 #define I2C_CR1_ADDRIE_Pos           (3U)
11021 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
11022 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
11023 #define I2C_CR1_NACKIE_Pos           (4U)
11024 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
11025 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
11026 #define I2C_CR1_STOPIE_Pos           (5U)
11027 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
11028 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
11029 #define I2C_CR1_TCIE_Pos             (6U)
11030 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
11031 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
11032 #define I2C_CR1_ERRIE_Pos            (7U)
11033 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
11034 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
11035 #define I2C_CR1_DNF_Pos              (8U)
11036 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
11037 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
11038 #define I2C_CR1_ANFOFF_Pos           (12U)
11039 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
11040 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
11041 #define I2C_CR1_SWRST_Pos            (13U)
11042 #define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)               /*!< 0x00002000 */
11043 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset */
11044 #define I2C_CR1_TXDMAEN_Pos          (14U)
11045 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
11046 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
11047 #define I2C_CR1_RXDMAEN_Pos          (15U)
11048 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
11049 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
11050 #define I2C_CR1_SBC_Pos              (16U)
11051 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
11052 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
11053 #define I2C_CR1_NOSTRETCH_Pos        (17U)
11054 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
11055 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
11056 #define I2C_CR1_WUPEN_Pos            (18U)
11057 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
11058 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
11059 #define I2C_CR1_GCEN_Pos             (19U)
11060 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
11061 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
11062 #define I2C_CR1_SMBHEN_Pos           (20U)
11063 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
11064 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
11065 #define I2C_CR1_SMBDEN_Pos           (21U)
11066 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
11067 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
11068 #define I2C_CR1_ALERTEN_Pos          (22U)
11069 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
11070 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
11071 #define I2C_CR1_PECEN_Pos            (23U)
11072 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
11073 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
11074 
11075 /* Legacy defines */
11076 #define I2C_CR1_DFN I2C_CR1_DNF
11077 
11078 /******************  Bit definition for I2C_CR2 register  ********************/
11079 #define I2C_CR2_SADD_Pos             (0U)
11080 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
11081 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
11082 #define I2C_CR2_RD_WRN_Pos           (10U)
11083 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
11084 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
11085 #define I2C_CR2_ADD10_Pos            (11U)
11086 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
11087 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
11088 #define I2C_CR2_HEAD10R_Pos          (12U)
11089 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
11090 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
11091 #define I2C_CR2_START_Pos            (13U)
11092 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
11093 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
11094 #define I2C_CR2_STOP_Pos             (14U)
11095 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
11096 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
11097 #define I2C_CR2_NACK_Pos             (15U)
11098 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
11099 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
11100 #define I2C_CR2_NBYTES_Pos           (16U)
11101 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
11102 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
11103 #define I2C_CR2_RELOAD_Pos           (24U)
11104 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
11105 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
11106 #define I2C_CR2_AUTOEND_Pos          (25U)
11107 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
11108 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
11109 #define I2C_CR2_PECBYTE_Pos          (26U)
11110 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
11111 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
11112 
11113 /*******************  Bit definition for I2C_OAR1 register  ******************/
11114 #define I2C_OAR1_OA1_Pos             (0U)
11115 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
11116 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
11117 #define I2C_OAR1_OA1MODE_Pos         (10U)
11118 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
11119 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
11120 #define I2C_OAR1_OA1EN_Pos           (15U)
11121 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
11122 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
11123 
11124 /*******************  Bit definition for I2C_OAR2 register  *******************/
11125 #define I2C_OAR2_OA2_Pos             (1U)
11126 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
11127 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
11128 #define I2C_OAR2_OA2MSK_Pos          (8U)
11129 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
11130 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
11131 #define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
11132 #define I2C_OAR2_OA2MASK01_Pos       (8U)
11133 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
11134 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
11135 #define I2C_OAR2_OA2MASK02_Pos       (9U)
11136 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
11137 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
11138 #define I2C_OAR2_OA2MASK03_Pos       (8U)
11139 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
11140 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
11141 #define I2C_OAR2_OA2MASK04_Pos       (10U)
11142 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
11143 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
11144 #define I2C_OAR2_OA2MASK05_Pos       (8U)
11145 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
11146 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
11147 #define I2C_OAR2_OA2MASK06_Pos       (9U)
11148 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
11149 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
11150 #define I2C_OAR2_OA2MASK07_Pos       (8U)
11151 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
11152 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
11153 #define I2C_OAR2_OA2EN_Pos           (15U)
11154 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
11155 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
11156 
11157 /*******************  Bit definition for I2C_TIMINGR register *****************/
11158 #define I2C_TIMINGR_SCLL_Pos         (0U)
11159 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
11160 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
11161 #define I2C_TIMINGR_SCLH_Pos         (8U)
11162 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
11163 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
11164 #define I2C_TIMINGR_SDADEL_Pos       (16U)
11165 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
11166 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
11167 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
11168 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
11169 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
11170 #define I2C_TIMINGR_PRESC_Pos        (28U)
11171 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
11172 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
11173 
11174 /******************* Bit definition for I2C_TIMEOUTR register *****************/
11175 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
11176 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
11177 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
11178 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
11179 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
11180 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
11181 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
11182 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
11183 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
11184 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
11185 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
11186 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
11187 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
11188 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
11189 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
11190 
11191 /******************  Bit definition for I2C_ISR register  *********************/
11192 #define I2C_ISR_TXE_Pos              (0U)
11193 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
11194 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
11195 #define I2C_ISR_TXIS_Pos             (1U)
11196 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
11197 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
11198 #define I2C_ISR_RXNE_Pos             (2U)
11199 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
11200 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
11201 #define I2C_ISR_ADDR_Pos             (3U)
11202 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
11203 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
11204 #define I2C_ISR_NACKF_Pos            (4U)
11205 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
11206 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
11207 #define I2C_ISR_STOPF_Pos            (5U)
11208 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
11209 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
11210 #define I2C_ISR_TC_Pos               (6U)
11211 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
11212 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
11213 #define I2C_ISR_TCR_Pos              (7U)
11214 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
11215 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
11216 #define I2C_ISR_BERR_Pos             (8U)
11217 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
11218 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
11219 #define I2C_ISR_ARLO_Pos             (9U)
11220 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
11221 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
11222 #define I2C_ISR_OVR_Pos              (10U)
11223 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
11224 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
11225 #define I2C_ISR_PECERR_Pos           (11U)
11226 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
11227 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
11228 #define I2C_ISR_TIMEOUT_Pos          (12U)
11229 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
11230 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
11231 #define I2C_ISR_ALERT_Pos            (13U)
11232 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
11233 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
11234 #define I2C_ISR_BUSY_Pos             (15U)
11235 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
11236 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
11237 #define I2C_ISR_DIR_Pos              (16U)
11238 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
11239 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
11240 #define I2C_ISR_ADDCODE_Pos          (17U)
11241 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
11242 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
11243 
11244 /******************  Bit definition for I2C_ICR register  *********************/
11245 #define I2C_ICR_ADDRCF_Pos           (3U)
11246 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
11247 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
11248 #define I2C_ICR_NACKCF_Pos           (4U)
11249 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
11250 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
11251 #define I2C_ICR_STOPCF_Pos           (5U)
11252 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
11253 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
11254 #define I2C_ICR_BERRCF_Pos           (8U)
11255 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
11256 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
11257 #define I2C_ICR_ARLOCF_Pos           (9U)
11258 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
11259 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
11260 #define I2C_ICR_OVRCF_Pos            (10U)
11261 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
11262 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
11263 #define I2C_ICR_PECCF_Pos            (11U)
11264 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
11265 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
11266 #define I2C_ICR_TIMOUTCF_Pos         (12U)
11267 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
11268 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
11269 #define I2C_ICR_ALERTCF_Pos          (13U)
11270 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
11271 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
11272 
11273 /******************  Bit definition for I2C_PECR register  ********************/
11274 #define I2C_PECR_PEC_Pos             (0U)
11275 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
11276 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
11277 
11278 /******************  Bit definition for I2C_RXDR register  *********************/
11279 #define I2C_RXDR_RXDATA_Pos          (0U)
11280 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
11281 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
11282 
11283 /******************  Bit definition for I2C_TXDR register  *********************/
11284 #define I2C_TXDR_TXDATA_Pos          (0U)
11285 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
11286 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
11287 
11288 
11289 /******************************************************************************/
11290 /*                                                                            */
11291 /*                           Independent WATCHDOG (IWDG)                      */
11292 /*                                                                            */
11293 /******************************************************************************/
11294 /*******************  Bit definition for IWDG_KR register  ********************/
11295 #define IWDG_KR_KEY_Pos      (0U)
11296 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
11297 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
11298 
11299 /*******************  Bit definition for IWDG_PR register  ********************/
11300 #define IWDG_PR_PR_Pos       (0U)
11301 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
11302 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
11303 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
11304 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
11305 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
11306 
11307 /*******************  Bit definition for IWDG_RLR register  *******************/
11308 #define IWDG_RLR_RL_Pos      (0U)
11309 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
11310 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
11311 
11312 /*******************  Bit definition for IWDG_SR register  ********************/
11313 #define IWDG_SR_PVU_Pos      (0U)
11314 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
11315 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
11316 #define IWDG_SR_RVU_Pos      (1U)
11317 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
11318 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
11319 #define IWDG_SR_WVU_Pos      (2U)
11320 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
11321 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
11322 
11323 /*******************  Bit definition for IWDG_KR register  ********************/
11324 #define IWDG_WINR_WIN_Pos    (0U)
11325 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
11326 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
11327 
11328 /******************************************************************************/
11329 /*                                                                            */
11330 /*                             Power Control                                  */
11331 /*                                                                            */
11332 /******************************************************************************/
11333 #define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
11334 /********************  Bit definition for PWR_CR register  ********************/
11335 #define PWR_CR_LPDS_Pos            (0U)
11336 #define PWR_CR_LPDS_Msk            (0x1UL << PWR_CR_LPDS_Pos)                   /*!< 0x00000001 */
11337 #define PWR_CR_LPDS                PWR_CR_LPDS_Msk                             /*!< Low-power Deepsleep */
11338 #define PWR_CR_PDDS_Pos            (1U)
11339 #define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
11340 #define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
11341 #define PWR_CR_CWUF_Pos            (2U)
11342 #define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
11343 #define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
11344 #define PWR_CR_CSBF_Pos            (3U)
11345 #define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
11346 #define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
11347 #define PWR_CR_PVDE_Pos            (4U)
11348 #define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
11349 #define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
11350 
11351 #define PWR_CR_PLS_Pos             (5U)
11352 #define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
11353 #define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
11354 #define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
11355 #define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
11356 #define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
11357 
11358 /*!< PVD level configuration */
11359 #define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
11360 #define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
11361 #define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
11362 #define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
11363 #define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
11364 #define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
11365 #define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
11366 #define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
11367 
11368 #define PWR_CR_DBP_Pos             (8U)
11369 #define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
11370 #define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
11371 
11372 /*******************  Bit definition for PWR_CSR register  ********************/
11373 #define PWR_CSR_WUF_Pos            (0U)
11374 #define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
11375 #define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
11376 #define PWR_CSR_SBF_Pos            (1U)
11377 #define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
11378 #define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
11379 #define PWR_CSR_PVDO_Pos           (2U)
11380 #define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
11381 #define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
11382 
11383 #define PWR_CSR_EWUP1_Pos          (8U)
11384 #define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
11385 #define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
11386 #define PWR_CSR_EWUP2_Pos          (9U)
11387 #define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
11388 #define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
11389 #define PWR_CSR_EWUP3_Pos          (10U)
11390 #define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
11391 #define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
11392 
11393 /******************************************************************************/
11394 /*                                                                            */
11395 /*                         Reset and Clock Control                            */
11396 /*                                                                            */
11397 /******************************************************************************/
11398 /*
11399 * @brief Specific device feature definitions  (not present on all devices in the STM32F3 serie)
11400 */
11401 
11402 /********************  Bit definition for RCC_CR register  ********************/
11403 #define RCC_CR_HSION_Pos                         (0U)
11404 #define RCC_CR_HSION_Msk                         (0x1UL << RCC_CR_HSION_Pos)    /*!< 0x00000001 */
11405 #define RCC_CR_HSION                             RCC_CR_HSION_Msk
11406 #define RCC_CR_HSIRDY_Pos                        (1U)
11407 #define RCC_CR_HSIRDY_Msk                        (0x1UL << RCC_CR_HSIRDY_Pos)   /*!< 0x00000002 */
11408 #define RCC_CR_HSIRDY                            RCC_CR_HSIRDY_Msk
11409 
11410 #define RCC_CR_HSITRIM_Pos                       (3U)
11411 #define RCC_CR_HSITRIM_Msk                       (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
11412 #define RCC_CR_HSITRIM                           RCC_CR_HSITRIM_Msk
11413 #define RCC_CR_HSITRIM_0                         (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
11414 #define RCC_CR_HSITRIM_1                         (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
11415 #define RCC_CR_HSITRIM_2                         (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
11416 #define RCC_CR_HSITRIM_3                         (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
11417 #define RCC_CR_HSITRIM_4                         (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
11418 
11419 #define RCC_CR_HSICAL_Pos                        (8U)
11420 #define RCC_CR_HSICAL_Msk                        (0xFFUL << RCC_CR_HSICAL_Pos)  /*!< 0x0000FF00 */
11421 #define RCC_CR_HSICAL                            RCC_CR_HSICAL_Msk
11422 #define RCC_CR_HSICAL_0                          (0x01UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000100 */
11423 #define RCC_CR_HSICAL_1                          (0x02UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000200 */
11424 #define RCC_CR_HSICAL_2                          (0x04UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000400 */
11425 #define RCC_CR_HSICAL_3                          (0x08UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000800 */
11426 #define RCC_CR_HSICAL_4                          (0x10UL << RCC_CR_HSICAL_Pos)  /*!< 0x00001000 */
11427 #define RCC_CR_HSICAL_5                          (0x20UL << RCC_CR_HSICAL_Pos)  /*!< 0x00002000 */
11428 #define RCC_CR_HSICAL_6                          (0x40UL << RCC_CR_HSICAL_Pos)  /*!< 0x00004000 */
11429 #define RCC_CR_HSICAL_7                          (0x80UL << RCC_CR_HSICAL_Pos)  /*!< 0x00008000 */
11430 
11431 #define RCC_CR_HSEON_Pos                         (16U)
11432 #define RCC_CR_HSEON_Msk                         (0x1UL << RCC_CR_HSEON_Pos)    /*!< 0x00010000 */
11433 #define RCC_CR_HSEON                             RCC_CR_HSEON_Msk
11434 #define RCC_CR_HSERDY_Pos                        (17U)
11435 #define RCC_CR_HSERDY_Msk                        (0x1UL << RCC_CR_HSERDY_Pos)   /*!< 0x00020000 */
11436 #define RCC_CR_HSERDY                            RCC_CR_HSERDY_Msk
11437 #define RCC_CR_HSEBYP_Pos                        (18U)
11438 #define RCC_CR_HSEBYP_Msk                        (0x1UL << RCC_CR_HSEBYP_Pos)   /*!< 0x00040000 */
11439 #define RCC_CR_HSEBYP                            RCC_CR_HSEBYP_Msk
11440 #define RCC_CR_CSSON_Pos                         (19U)
11441 #define RCC_CR_CSSON_Msk                         (0x1UL << RCC_CR_CSSON_Pos)    /*!< 0x00080000 */
11442 #define RCC_CR_CSSON                             RCC_CR_CSSON_Msk
11443 #define RCC_CR_PLLON_Pos                         (24U)
11444 #define RCC_CR_PLLON_Msk                         (0x1UL << RCC_CR_PLLON_Pos)    /*!< 0x01000000 */
11445 #define RCC_CR_PLLON                             RCC_CR_PLLON_Msk
11446 #define RCC_CR_PLLRDY_Pos                        (25U)
11447 #define RCC_CR_PLLRDY_Msk                        (0x1UL << RCC_CR_PLLRDY_Pos)   /*!< 0x02000000 */
11448 #define RCC_CR_PLLRDY                            RCC_CR_PLLRDY_Msk
11449 
11450 /********************  Bit definition for RCC_CFGR register  ******************/
11451 /*!< SW configuration */
11452 #define RCC_CFGR_SW_Pos                          (0U)
11453 #define RCC_CFGR_SW_Msk                          (0x3UL << RCC_CFGR_SW_Pos)     /*!< 0x00000003 */
11454 #define RCC_CFGR_SW                              RCC_CFGR_SW_Msk               /*!< SW[1:0] bits (System clock Switch) */
11455 #define RCC_CFGR_SW_0                            (0x1UL << RCC_CFGR_SW_Pos)     /*!< 0x00000001 */
11456 #define RCC_CFGR_SW_1                            (0x2UL << RCC_CFGR_SW_Pos)     /*!< 0x00000002 */
11457 
11458 #define RCC_CFGR_SW_HSI                          (0x00000000U)                 /*!< HSI selected as system clock */
11459 #define RCC_CFGR_SW_HSE                          (0x00000001U)                 /*!< HSE selected as system clock */
11460 #define RCC_CFGR_SW_PLL                          (0x00000002U)                 /*!< PLL selected as system clock */
11461 
11462 /*!< SWS configuration */
11463 #define RCC_CFGR_SWS_Pos                         (2U)
11464 #define RCC_CFGR_SWS_Msk                         (0x3UL << RCC_CFGR_SWS_Pos)    /*!< 0x0000000C */
11465 #define RCC_CFGR_SWS                             RCC_CFGR_SWS_Msk              /*!< SWS[1:0] bits (System Clock Switch Status) */
11466 #define RCC_CFGR_SWS_0                           (0x1UL << RCC_CFGR_SWS_Pos)    /*!< 0x00000004 */
11467 #define RCC_CFGR_SWS_1                           (0x2UL << RCC_CFGR_SWS_Pos)    /*!< 0x00000008 */
11468 
11469 #define RCC_CFGR_SWS_HSI                         (0x00000000U)                 /*!< HSI oscillator used as system clock */
11470 #define RCC_CFGR_SWS_HSE                         (0x00000004U)                 /*!< HSE oscillator used as system clock */
11471 #define RCC_CFGR_SWS_PLL                         (0x00000008U)                 /*!< PLL used as system clock */
11472 
11473 /*!< HPRE configuration */
11474 #define RCC_CFGR_HPRE_Pos                        (4U)
11475 #define RCC_CFGR_HPRE_Msk                        (0xFUL << RCC_CFGR_HPRE_Pos)   /*!< 0x000000F0 */
11476 #define RCC_CFGR_HPRE                            RCC_CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB prescaler) */
11477 #define RCC_CFGR_HPRE_0                          (0x1UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000010 */
11478 #define RCC_CFGR_HPRE_1                          (0x2UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000020 */
11479 #define RCC_CFGR_HPRE_2                          (0x4UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000040 */
11480 #define RCC_CFGR_HPRE_3                          (0x8UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000080 */
11481 
11482 #define RCC_CFGR_HPRE_DIV1                       (0x00000000U)                 /*!< SYSCLK not divided */
11483 #define RCC_CFGR_HPRE_DIV2                       (0x00000080U)                 /*!< SYSCLK divided by 2 */
11484 #define RCC_CFGR_HPRE_DIV4                       (0x00000090U)                 /*!< SYSCLK divided by 4 */
11485 #define RCC_CFGR_HPRE_DIV8                       (0x000000A0U)                 /*!< SYSCLK divided by 8 */
11486 #define RCC_CFGR_HPRE_DIV16                      (0x000000B0U)                 /*!< SYSCLK divided by 16 */
11487 #define RCC_CFGR_HPRE_DIV64                      (0x000000C0U)                 /*!< SYSCLK divided by 64 */
11488 #define RCC_CFGR_HPRE_DIV128                     (0x000000D0U)                 /*!< SYSCLK divided by 128 */
11489 #define RCC_CFGR_HPRE_DIV256                     (0x000000E0U)                 /*!< SYSCLK divided by 256 */
11490 #define RCC_CFGR_HPRE_DIV512                     (0x000000F0U)                 /*!< SYSCLK divided by 512 */
11491 
11492 /*!< PPRE1 configuration */
11493 #define RCC_CFGR_PPRE1_Pos                       (8U)
11494 #define RCC_CFGR_PPRE1_Msk                       (0x7UL << RCC_CFGR_PPRE1_Pos)  /*!< 0x00000700 */
11495 #define RCC_CFGR_PPRE1                           RCC_CFGR_PPRE1_Msk            /*!< PRE1[2:0] bits (APB1 prescaler) */
11496 #define RCC_CFGR_PPRE1_0                         (0x1UL << RCC_CFGR_PPRE1_Pos)  /*!< 0x00000100 */
11497 #define RCC_CFGR_PPRE1_1                         (0x2UL << RCC_CFGR_PPRE1_Pos)  /*!< 0x00000200 */
11498 #define RCC_CFGR_PPRE1_2                         (0x4UL << RCC_CFGR_PPRE1_Pos)  /*!< 0x00000400 */
11499 
11500 #define RCC_CFGR_PPRE1_DIV1                      (0x00000000U)                 /*!< HCLK not divided */
11501 #define RCC_CFGR_PPRE1_DIV2                      (0x00000400U)                 /*!< HCLK divided by 2 */
11502 #define RCC_CFGR_PPRE1_DIV4                      (0x00000500U)                 /*!< HCLK divided by 4 */
11503 #define RCC_CFGR_PPRE1_DIV8                      (0x00000600U)                 /*!< HCLK divided by 8 */
11504 #define RCC_CFGR_PPRE1_DIV16                     (0x00000700U)                 /*!< HCLK divided by 16 */
11505 
11506 /*!< PPRE2 configuration */
11507 #define RCC_CFGR_PPRE2_Pos                       (11U)
11508 #define RCC_CFGR_PPRE2_Msk                       (0x7UL << RCC_CFGR_PPRE2_Pos)  /*!< 0x00003800 */
11509 #define RCC_CFGR_PPRE2                           RCC_CFGR_PPRE2_Msk            /*!< PRE2[2:0] bits (APB2 prescaler) */
11510 #define RCC_CFGR_PPRE2_0                         (0x1UL << RCC_CFGR_PPRE2_Pos)  /*!< 0x00000800 */
11511 #define RCC_CFGR_PPRE2_1                         (0x2UL << RCC_CFGR_PPRE2_Pos)  /*!< 0x00001000 */
11512 #define RCC_CFGR_PPRE2_2                         (0x4UL << RCC_CFGR_PPRE2_Pos)  /*!< 0x00002000 */
11513 
11514 #define RCC_CFGR_PPRE2_DIV1                      (0x00000000U)                 /*!< HCLK not divided */
11515 #define RCC_CFGR_PPRE2_DIV2                      (0x00002000U)                 /*!< HCLK divided by 2 */
11516 #define RCC_CFGR_PPRE2_DIV4                      (0x00002800U)                 /*!< HCLK divided by 4 */
11517 #define RCC_CFGR_PPRE2_DIV8                      (0x00003000U)                 /*!< HCLK divided by 8 */
11518 #define RCC_CFGR_PPRE2_DIV16                     (0x00003800U)                 /*!< HCLK divided by 16 */
11519 
11520 #define RCC_CFGR_PLLSRC_Pos                      (16U)
11521 #define RCC_CFGR_PLLSRC_Msk                      (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
11522 #define RCC_CFGR_PLLSRC                          RCC_CFGR_PLLSRC_Msk           /*!< PLL entry clock source */
11523 #define RCC_CFGR_PLLSRC_HSI_DIV2                 (0x00000000U)                 /*!< HSI clock divided by 2 selected as PLL entry clock source */
11524 #define RCC_CFGR_PLLSRC_HSE_PREDIV               (0x00010000U)                 /*!< HSE/PREDIV clock selected as PLL entry clock source */
11525 
11526 #define RCC_CFGR_PLLXTPRE_Pos                    (17U)
11527 #define RCC_CFGR_PLLXTPRE_Msk                    (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
11528 #define RCC_CFGR_PLLXTPRE                        RCC_CFGR_PLLXTPRE_Msk         /*!< HSE divider for PLL entry */
11529 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1        (0x00000000U)                 /*!< HSE/PREDIV clock not divided for PLL entry */
11530 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2        (0x00020000U)                 /*!< HSE/PREDIV clock divided by 2 for PLL entry */
11531 
11532 /*!< PLLMUL configuration */
11533 #define RCC_CFGR_PLLMUL_Pos                      (18U)
11534 #define RCC_CFGR_PLLMUL_Msk                      (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
11535 #define RCC_CFGR_PLLMUL                          RCC_CFGR_PLLMUL_Msk           /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
11536 #define RCC_CFGR_PLLMUL_0                        (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
11537 #define RCC_CFGR_PLLMUL_1                        (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
11538 #define RCC_CFGR_PLLMUL_2                        (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
11539 #define RCC_CFGR_PLLMUL_3                        (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
11540 
11541 #define RCC_CFGR_PLLMUL2                         (0x00000000U)                 /*!< PLL input clock*2 */
11542 #define RCC_CFGR_PLLMUL3                         (0x00040000U)                 /*!< PLL input clock*3 */
11543 #define RCC_CFGR_PLLMUL4                         (0x00080000U)                 /*!< PLL input clock*4 */
11544 #define RCC_CFGR_PLLMUL5                         (0x000C0000U)                 /*!< PLL input clock*5 */
11545 #define RCC_CFGR_PLLMUL6                         (0x00100000U)                 /*!< PLL input clock*6 */
11546 #define RCC_CFGR_PLLMUL7                         (0x00140000U)                 /*!< PLL input clock*7 */
11547 #define RCC_CFGR_PLLMUL8                         (0x00180000U)                 /*!< PLL input clock*8 */
11548 #define RCC_CFGR_PLLMUL9                         (0x001C0000U)                 /*!< PLL input clock*9 */
11549 #define RCC_CFGR_PLLMUL10                        (0x00200000U)                 /*!< PLL input clock10 */
11550 #define RCC_CFGR_PLLMUL11                        (0x00240000U)                 /*!< PLL input clock*11 */
11551 #define RCC_CFGR_PLLMUL12                        (0x00280000U)                 /*!< PLL input clock*12 */
11552 #define RCC_CFGR_PLLMUL13                        (0x002C0000U)                 /*!< PLL input clock*13 */
11553 #define RCC_CFGR_PLLMUL14                        (0x00300000U)                 /*!< PLL input clock*14 */
11554 #define RCC_CFGR_PLLMUL15                        (0x00340000U)                 /*!< PLL input clock*15 */
11555 #define RCC_CFGR_PLLMUL16                        (0x00380000U)                 /*!< PLL input clock*16 */
11556 
11557 /*!< MCO configuration */
11558 #define RCC_CFGR_MCO_Pos                         (24U)
11559 #define RCC_CFGR_MCO_Msk                         (0x7UL << RCC_CFGR_MCO_Pos)    /*!< 0x07000000 */
11560 #define RCC_CFGR_MCO                             RCC_CFGR_MCO_Msk              /*!< MCO[2:0] bits (Microcontroller Clock Output) */
11561 #define RCC_CFGR_MCO_0                           (0x1UL << RCC_CFGR_MCO_Pos)    /*!< 0x01000000 */
11562 #define RCC_CFGR_MCO_1                           (0x2UL << RCC_CFGR_MCO_Pos)    /*!< 0x02000000 */
11563 #define RCC_CFGR_MCO_2                           (0x4UL << RCC_CFGR_MCO_Pos)    /*!< 0x04000000 */
11564 
11565 #define RCC_CFGR_MCO_NOCLOCK                     (0x00000000U)                 /*!< No clock */
11566 #define RCC_CFGR_MCO_LSI                         (0x02000000U)                 /*!< LSI clock selected as MCO source */
11567 #define RCC_CFGR_MCO_LSE                         (0x03000000U)                 /*!< LSE clock selected as MCO source */
11568 #define RCC_CFGR_MCO_SYSCLK                      (0x04000000U)                 /*!< System clock selected as MCO source */
11569 #define RCC_CFGR_MCO_HSI                         (0x05000000U)                 /*!< HSI clock selected as MCO source */
11570 #define RCC_CFGR_MCO_HSE                         (0x06000000U)                 /*!< HSE clock selected as MCO source  */
11571 #define RCC_CFGR_MCO_PLL                         (0x07000000U)                 /*!< PLL clock divided by 2 selected as MCO source */
11572 
11573 #define RCC_CFGR_MCOPRE_Pos                      (28U)
11574 #define RCC_CFGR_MCOPRE_Msk                      (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
11575 #define RCC_CFGR_MCOPRE                          RCC_CFGR_MCOPRE_Msk           /*!< MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler) */
11576 #define RCC_CFGR_MCOPRE_0                        (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
11577 #define RCC_CFGR_MCOPRE_1                        (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
11578 #define RCC_CFGR_MCOPRE_2                        (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
11579 
11580 #define RCC_CFGR_MCOPRE_DIV1                     (0x00000000U)                 /*!< MCO is divided by 1 */
11581 #define RCC_CFGR_MCOPRE_DIV2                     (0x10000000U)                 /*!< MCO is divided by 2 */
11582 #define RCC_CFGR_MCOPRE_DIV4                     (0x20000000U)                 /*!< MCO is divided by 4 */
11583 #define RCC_CFGR_MCOPRE_DIV8                     (0x30000000U)                 /*!< MCO is divided by 8 */
11584 #define RCC_CFGR_MCOPRE_DIV16                    (0x40000000U)                 /*!< MCO is divided by 16 */
11585 #define RCC_CFGR_MCOPRE_DIV32                    (0x50000000U)                 /*!< MCO is divided by 32 */
11586 #define RCC_CFGR_MCOPRE_DIV64                    (0x60000000U)                 /*!< MCO is divided by 64 */
11587 #define RCC_CFGR_MCOPRE_DIV128                   (0x70000000U)                 /*!< MCO is divided by 128 */
11588 
11589 #define RCC_CFGR_PLLNODIV_Pos                    (31U)
11590 #define RCC_CFGR_PLLNODIV_Msk                    (0x1UL << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */
11591 #define RCC_CFGR_PLLNODIV                        RCC_CFGR_PLLNODIV_Msk         /*!< Do not divide PLL to MCO */
11592 
11593 /* Reference defines */
11594 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO
11595 #define RCC_CFGR_MCOSEL_0                    RCC_CFGR_MCO_0
11596 #define RCC_CFGR_MCOSEL_1                    RCC_CFGR_MCO_1
11597 #define RCC_CFGR_MCOSEL_2                    RCC_CFGR_MCO_2
11598 #define RCC_CFGR_MCOSEL_NOCLOCK              RCC_CFGR_MCO_NOCLOCK
11599 #define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCO_LSI
11600 #define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCO_LSE
11601 #define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCO_SYSCLK
11602 #define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCO_HSI
11603 #define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCO_HSE
11604 #define RCC_CFGR_MCOSEL_PLL_DIV2             RCC_CFGR_MCO_PLL
11605 
11606 /*********************  Bit definition for RCC_CIR register  ********************/
11607 #define RCC_CIR_LSIRDYF_Pos                      (0U)
11608 #define RCC_CIR_LSIRDYF_Msk                      (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
11609 #define RCC_CIR_LSIRDYF                          RCC_CIR_LSIRDYF_Msk           /*!< LSI Ready Interrupt flag */
11610 #define RCC_CIR_LSERDYF_Pos                      (1U)
11611 #define RCC_CIR_LSERDYF_Msk                      (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
11612 #define RCC_CIR_LSERDYF                          RCC_CIR_LSERDYF_Msk           /*!< LSE Ready Interrupt flag */
11613 #define RCC_CIR_HSIRDYF_Pos                      (2U)
11614 #define RCC_CIR_HSIRDYF_Msk                      (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
11615 #define RCC_CIR_HSIRDYF                          RCC_CIR_HSIRDYF_Msk           /*!< HSI Ready Interrupt flag */
11616 #define RCC_CIR_HSERDYF_Pos                      (3U)
11617 #define RCC_CIR_HSERDYF_Msk                      (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
11618 #define RCC_CIR_HSERDYF                          RCC_CIR_HSERDYF_Msk           /*!< HSE Ready Interrupt flag */
11619 #define RCC_CIR_PLLRDYF_Pos                      (4U)
11620 #define RCC_CIR_PLLRDYF_Msk                      (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
11621 #define RCC_CIR_PLLRDYF                          RCC_CIR_PLLRDYF_Msk           /*!< PLL Ready Interrupt flag */
11622 #define RCC_CIR_CSSF_Pos                         (7U)
11623 #define RCC_CIR_CSSF_Msk                         (0x1UL << RCC_CIR_CSSF_Pos)    /*!< 0x00000080 */
11624 #define RCC_CIR_CSSF                             RCC_CIR_CSSF_Msk              /*!< Clock Security System Interrupt flag */
11625 #define RCC_CIR_LSIRDYIE_Pos                     (8U)
11626 #define RCC_CIR_LSIRDYIE_Msk                     (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
11627 #define RCC_CIR_LSIRDYIE                         RCC_CIR_LSIRDYIE_Msk          /*!< LSI Ready Interrupt Enable */
11628 #define RCC_CIR_LSERDYIE_Pos                     (9U)
11629 #define RCC_CIR_LSERDYIE_Msk                     (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
11630 #define RCC_CIR_LSERDYIE                         RCC_CIR_LSERDYIE_Msk          /*!< LSE Ready Interrupt Enable */
11631 #define RCC_CIR_HSIRDYIE_Pos                     (10U)
11632 #define RCC_CIR_HSIRDYIE_Msk                     (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
11633 #define RCC_CIR_HSIRDYIE                         RCC_CIR_HSIRDYIE_Msk          /*!< HSI Ready Interrupt Enable */
11634 #define RCC_CIR_HSERDYIE_Pos                     (11U)
11635 #define RCC_CIR_HSERDYIE_Msk                     (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
11636 #define RCC_CIR_HSERDYIE                         RCC_CIR_HSERDYIE_Msk          /*!< HSE Ready Interrupt Enable */
11637 #define RCC_CIR_PLLRDYIE_Pos                     (12U)
11638 #define RCC_CIR_PLLRDYIE_Msk                     (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
11639 #define RCC_CIR_PLLRDYIE                         RCC_CIR_PLLRDYIE_Msk          /*!< PLL Ready Interrupt Enable */
11640 #define RCC_CIR_LSIRDYC_Pos                      (16U)
11641 #define RCC_CIR_LSIRDYC_Msk                      (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
11642 #define RCC_CIR_LSIRDYC                          RCC_CIR_LSIRDYC_Msk           /*!< LSI Ready Interrupt Clear */
11643 #define RCC_CIR_LSERDYC_Pos                      (17U)
11644 #define RCC_CIR_LSERDYC_Msk                      (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
11645 #define RCC_CIR_LSERDYC                          RCC_CIR_LSERDYC_Msk           /*!< LSE Ready Interrupt Clear */
11646 #define RCC_CIR_HSIRDYC_Pos                      (18U)
11647 #define RCC_CIR_HSIRDYC_Msk                      (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
11648 #define RCC_CIR_HSIRDYC                          RCC_CIR_HSIRDYC_Msk           /*!< HSI Ready Interrupt Clear */
11649 #define RCC_CIR_HSERDYC_Pos                      (19U)
11650 #define RCC_CIR_HSERDYC_Msk                      (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
11651 #define RCC_CIR_HSERDYC                          RCC_CIR_HSERDYC_Msk           /*!< HSE Ready Interrupt Clear */
11652 #define RCC_CIR_PLLRDYC_Pos                      (20U)
11653 #define RCC_CIR_PLLRDYC_Msk                      (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
11654 #define RCC_CIR_PLLRDYC                          RCC_CIR_PLLRDYC_Msk           /*!< PLL Ready Interrupt Clear */
11655 #define RCC_CIR_CSSC_Pos                         (23U)
11656 #define RCC_CIR_CSSC_Msk                         (0x1UL << RCC_CIR_CSSC_Pos)    /*!< 0x00800000 */
11657 #define RCC_CIR_CSSC                             RCC_CIR_CSSC_Msk              /*!< Clock Security System Interrupt Clear */
11658 
11659 /******************  Bit definition for RCC_APB2RSTR register  *****************/
11660 #define RCC_APB2RSTR_SYSCFGRST_Pos               (0U)
11661 #define RCC_APB2RSTR_SYSCFGRST_Msk               (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
11662 #define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG reset */
11663 #define RCC_APB2RSTR_TIM1RST_Pos                 (11U)
11664 #define RCC_APB2RSTR_TIM1RST_Msk                 (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
11665 #define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 reset */
11666 #define RCC_APB2RSTR_SPI1RST_Pos                 (12U)
11667 #define RCC_APB2RSTR_SPI1RST_Msk                 (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
11668 #define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 reset */
11669 #define RCC_APB2RSTR_USART1RST_Pos               (14U)
11670 #define RCC_APB2RSTR_USART1RST_Msk               (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
11671 #define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 reset */
11672 #define RCC_APB2RSTR_TIM15RST_Pos                (16U)
11673 #define RCC_APB2RSTR_TIM15RST_Msk                (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
11674 #define RCC_APB2RSTR_TIM15RST                    RCC_APB2RSTR_TIM15RST_Msk     /*!< TIM15 reset */
11675 #define RCC_APB2RSTR_TIM16RST_Pos                (17U)
11676 #define RCC_APB2RSTR_TIM16RST_Msk                (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
11677 #define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 reset */
11678 #define RCC_APB2RSTR_TIM17RST_Pos                (18U)
11679 #define RCC_APB2RSTR_TIM17RST_Msk                (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
11680 #define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 reset */
11681 #define RCC_APB2RSTR_HRTIM1RST_Pos               (29U)
11682 #define RCC_APB2RSTR_HRTIM1RST_Msk               (0x1UL << RCC_APB2RSTR_HRTIM1RST_Pos) /*!< 0x20000000 */
11683 #define RCC_APB2RSTR_HRTIM1RST                   RCC_APB2RSTR_HRTIM1RST_Msk    /*!< HRTIM1 reset */
11684 
11685 /******************  Bit definition for RCC_APB1RSTR register  ******************/
11686 #define RCC_APB1RSTR_TIM2RST_Pos                 (0U)
11687 #define RCC_APB1RSTR_TIM2RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
11688 #define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 reset */
11689 #define RCC_APB1RSTR_TIM3RST_Pos                 (1U)
11690 #define RCC_APB1RSTR_TIM3RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
11691 #define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 reset */
11692 #define RCC_APB1RSTR_TIM6RST_Pos                 (4U)
11693 #define RCC_APB1RSTR_TIM6RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
11694 #define RCC_APB1RSTR_TIM6RST                     RCC_APB1RSTR_TIM6RST_Msk      /*!< Timer 6 reset */
11695 #define RCC_APB1RSTR_TIM7RST_Pos                 (5U)
11696 #define RCC_APB1RSTR_TIM7RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
11697 #define RCC_APB1RSTR_TIM7RST                     RCC_APB1RSTR_TIM7RST_Msk      /*!< Timer 7 reset */
11698 #define RCC_APB1RSTR_WWDGRST_Pos                 (11U)
11699 #define RCC_APB1RSTR_WWDGRST_Msk                 (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
11700 #define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog reset */
11701 #define RCC_APB1RSTR_USART2RST_Pos               (17U)
11702 #define RCC_APB1RSTR_USART2RST_Msk               (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
11703 #define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 reset */
11704 #define RCC_APB1RSTR_USART3RST_Pos               (18U)
11705 #define RCC_APB1RSTR_USART3RST_Msk               (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
11706 #define RCC_APB1RSTR_USART3RST                   RCC_APB1RSTR_USART3RST_Msk    /*!< USART 3 reset */
11707 #define RCC_APB1RSTR_I2C1RST_Pos                 (21U)
11708 #define RCC_APB1RSTR_I2C1RST_Msk                 (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
11709 #define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 reset */
11710 #define RCC_APB1RSTR_CANRST_Pos                  (25U)
11711 #define RCC_APB1RSTR_CANRST_Msk                  (0x1UL << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
11712 #define RCC_APB1RSTR_CANRST                      RCC_APB1RSTR_CANRST_Msk       /*!< CAN reset */
11713 #define RCC_APB1RSTR_DAC2RST_Pos                 (26U)
11714 #define RCC_APB1RSTR_DAC2RST_Msk                 (0x1UL << RCC_APB1RSTR_DAC2RST_Pos) /*!< 0x04000000 */
11715 #define RCC_APB1RSTR_DAC2RST                     RCC_APB1RSTR_DAC2RST_Msk      /*!< DAC 2 reset */
11716 #define RCC_APB1RSTR_PWRRST_Pos                  (28U)
11717 #define RCC_APB1RSTR_PWRRST_Msk                  (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
11718 #define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR reset */
11719 #define RCC_APB1RSTR_DAC1RST_Pos                 (29U)
11720 #define RCC_APB1RSTR_DAC1RST_Msk                 (0x1UL << RCC_APB1RSTR_DAC1RST_Pos) /*!< 0x20000000 */
11721 #define RCC_APB1RSTR_DAC1RST                     RCC_APB1RSTR_DAC1RST_Msk      /*!< DAC 1 reset */
11722 
11723 /******************  Bit definition for RCC_AHBENR register  ******************/
11724 #define RCC_AHBENR_DMA1EN_Pos                    (0U)
11725 #define RCC_AHBENR_DMA1EN_Msk                    (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
11726 #define RCC_AHBENR_DMA1EN                        RCC_AHBENR_DMA1EN_Msk         /*!< DMA1 clock enable */
11727 #define RCC_AHBENR_SRAMEN_Pos                    (2U)
11728 #define RCC_AHBENR_SRAMEN_Msk                    (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
11729 #define RCC_AHBENR_SRAMEN                        RCC_AHBENR_SRAMEN_Msk         /*!< SRAM interface clock enable */
11730 #define RCC_AHBENR_FLITFEN_Pos                   (4U)
11731 #define RCC_AHBENR_FLITFEN_Msk                   (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
11732 #define RCC_AHBENR_FLITFEN                       RCC_AHBENR_FLITFEN_Msk        /*!< FLITF clock enable */
11733 #define RCC_AHBENR_CRCEN_Pos                     (6U)
11734 #define RCC_AHBENR_CRCEN_Msk                     (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
11735 #define RCC_AHBENR_CRCEN                         RCC_AHBENR_CRCEN_Msk          /*!< CRC clock enable */
11736 #define RCC_AHBENR_GPIOAEN_Pos                   (17U)
11737 #define RCC_AHBENR_GPIOAEN_Msk                   (0x1UL << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
11738 #define RCC_AHBENR_GPIOAEN                       RCC_AHBENR_GPIOAEN_Msk        /*!< GPIOA clock enable */
11739 #define RCC_AHBENR_GPIOBEN_Pos                   (18U)
11740 #define RCC_AHBENR_GPIOBEN_Msk                   (0x1UL << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
11741 #define RCC_AHBENR_GPIOBEN                       RCC_AHBENR_GPIOBEN_Msk        /*!< GPIOB clock enable */
11742 #define RCC_AHBENR_GPIOCEN_Pos                   (19U)
11743 #define RCC_AHBENR_GPIOCEN_Msk                   (0x1UL << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
11744 #define RCC_AHBENR_GPIOCEN                       RCC_AHBENR_GPIOCEN_Msk        /*!< GPIOC clock enable */
11745 #define RCC_AHBENR_GPIODEN_Pos                   (20U)
11746 #define RCC_AHBENR_GPIODEN_Msk                   (0x1UL << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */
11747 #define RCC_AHBENR_GPIODEN                       RCC_AHBENR_GPIODEN_Msk        /*!< GPIOD clock enable */
11748 #define RCC_AHBENR_GPIOFEN_Pos                   (22U)
11749 #define RCC_AHBENR_GPIOFEN_Msk                   (0x1UL << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
11750 #define RCC_AHBENR_GPIOFEN                       RCC_AHBENR_GPIOFEN_Msk        /*!< GPIOF clock enable */
11751 #define RCC_AHBENR_TSCEN_Pos                     (24U)
11752 #define RCC_AHBENR_TSCEN_Msk                     (0x1UL << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */
11753 #define RCC_AHBENR_TSCEN                         RCC_AHBENR_TSCEN_Msk          /*!< TS clock enable */
11754 #define RCC_AHBENR_ADC12EN_Pos                   (28U)
11755 #define RCC_AHBENR_ADC12EN_Msk                   (0x1UL << RCC_AHBENR_ADC12EN_Pos) /*!< 0x10000000 */
11756 #define RCC_AHBENR_ADC12EN                       RCC_AHBENR_ADC12EN_Msk        /*!< ADC1/ ADC2 clock enable */
11757 
11758 /*****************  Bit definition for RCC_APB2ENR register  ******************/
11759 #define RCC_APB2ENR_SYSCFGEN_Pos                 (0U)
11760 #define RCC_APB2ENR_SYSCFGEN_Msk                 (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
11761 #define RCC_APB2ENR_SYSCFGEN                     RCC_APB2ENR_SYSCFGEN_Msk      /*!< SYSCFG clock enable */
11762 #define RCC_APB2ENR_TIM1EN_Pos                   (11U)
11763 #define RCC_APB2ENR_TIM1EN_Msk                   (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
11764 #define RCC_APB2ENR_TIM1EN                       RCC_APB2ENR_TIM1EN_Msk        /*!< TIM1 clock enable */
11765 #define RCC_APB2ENR_SPI1EN_Pos                   (12U)
11766 #define RCC_APB2ENR_SPI1EN_Msk                   (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
11767 #define RCC_APB2ENR_SPI1EN                       RCC_APB2ENR_SPI1EN_Msk        /*!< SPI1 clock enable */
11768 #define RCC_APB2ENR_USART1EN_Pos                 (14U)
11769 #define RCC_APB2ENR_USART1EN_Msk                 (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
11770 #define RCC_APB2ENR_USART1EN                     RCC_APB2ENR_USART1EN_Msk      /*!< USART1 clock enable */
11771 #define RCC_APB2ENR_TIM15EN_Pos                  (16U)
11772 #define RCC_APB2ENR_TIM15EN_Msk                  (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
11773 #define RCC_APB2ENR_TIM15EN                      RCC_APB2ENR_TIM15EN_Msk       /*!< TIM15 clock enable */
11774 #define RCC_APB2ENR_TIM16EN_Pos                  (17U)
11775 #define RCC_APB2ENR_TIM16EN_Msk                  (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
11776 #define RCC_APB2ENR_TIM16EN                      RCC_APB2ENR_TIM16EN_Msk       /*!< TIM16 clock enable */
11777 #define RCC_APB2ENR_TIM17EN_Pos                  (18U)
11778 #define RCC_APB2ENR_TIM17EN_Msk                  (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
11779 #define RCC_APB2ENR_TIM17EN                      RCC_APB2ENR_TIM17EN_Msk       /*!< TIM17 clock enable */
11780 #define RCC_APB2ENR_HRTIM1EN_Pos                 (29U)
11781 #define RCC_APB2ENR_HRTIM1EN_Msk                 (0x1UL << RCC_APB2ENR_HRTIM1EN_Pos) /*!< 0x20000000 */
11782 #define RCC_APB2ENR_HRTIM1EN                     RCC_APB2ENR_HRTIM1EN_Msk      /*!< HRTIM1 reset */
11783 
11784 /******************  Bit definition for RCC_APB1ENR register  ******************/
11785 #define RCC_APB1ENR_TIM2EN_Pos                   (0U)
11786 #define RCC_APB1ENR_TIM2EN_Msk                   (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
11787 #define RCC_APB1ENR_TIM2EN                       RCC_APB1ENR_TIM2EN_Msk        /*!< Timer 2 clock enable */
11788 #define RCC_APB1ENR_TIM3EN_Pos                   (1U)
11789 #define RCC_APB1ENR_TIM3EN_Msk                   (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
11790 #define RCC_APB1ENR_TIM3EN                       RCC_APB1ENR_TIM3EN_Msk        /*!< Timer 3 clock enable */
11791 #define RCC_APB1ENR_TIM6EN_Pos                   (4U)
11792 #define RCC_APB1ENR_TIM6EN_Msk                   (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
11793 #define RCC_APB1ENR_TIM6EN                       RCC_APB1ENR_TIM6EN_Msk        /*!< Timer 6 clock enable */
11794 #define RCC_APB1ENR_TIM7EN_Pos                   (5U)
11795 #define RCC_APB1ENR_TIM7EN_Msk                   (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
11796 #define RCC_APB1ENR_TIM7EN                       RCC_APB1ENR_TIM7EN_Msk        /*!< Timer 7 clock enable */
11797 #define RCC_APB1ENR_WWDGEN_Pos                   (11U)
11798 #define RCC_APB1ENR_WWDGEN_Msk                   (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
11799 #define RCC_APB1ENR_WWDGEN                       RCC_APB1ENR_WWDGEN_Msk        /*!< Window Watchdog clock enable */
11800 #define RCC_APB1ENR_USART2EN_Pos                 (17U)
11801 #define RCC_APB1ENR_USART2EN_Msk                 (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
11802 #define RCC_APB1ENR_USART2EN                     RCC_APB1ENR_USART2EN_Msk      /*!< USART 2 clock enable */
11803 #define RCC_APB1ENR_USART3EN_Pos                 (18U)
11804 #define RCC_APB1ENR_USART3EN_Msk                 (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
11805 #define RCC_APB1ENR_USART3EN                     RCC_APB1ENR_USART3EN_Msk      /*!< USART 3 clock enable */
11806 #define RCC_APB1ENR_I2C1EN_Pos                   (21U)
11807 #define RCC_APB1ENR_I2C1EN_Msk                   (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
11808 #define RCC_APB1ENR_I2C1EN                       RCC_APB1ENR_I2C1EN_Msk        /*!< I2C 1 clock enable */
11809 #define RCC_APB1ENR_CANEN_Pos                    (25U)
11810 #define RCC_APB1ENR_CANEN_Msk                    (0x1UL << RCC_APB1ENR_CANEN_Pos) /*!< 0x02000000 */
11811 #define RCC_APB1ENR_CANEN                        RCC_APB1ENR_CANEN_Msk         /*!< CAN clock enable */
11812 #define RCC_APB1ENR_DAC2EN_Pos                   (26U)
11813 #define RCC_APB1ENR_DAC2EN_Msk                   (0x1UL << RCC_APB1ENR_DAC2EN_Pos) /*!< 0x04000000 */
11814 #define RCC_APB1ENR_DAC2EN                       RCC_APB1ENR_DAC2EN_Msk        /*!< DAC 2 clock enable */
11815 #define RCC_APB1ENR_PWREN_Pos                    (28U)
11816 #define RCC_APB1ENR_PWREN_Msk                    (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
11817 #define RCC_APB1ENR_PWREN                        RCC_APB1ENR_PWREN_Msk         /*!< PWR clock enable */
11818 #define RCC_APB1ENR_DAC1EN_Pos                   (29U)
11819 #define RCC_APB1ENR_DAC1EN_Msk                   (0x1UL << RCC_APB1ENR_DAC1EN_Pos) /*!< 0x20000000 */
11820 #define RCC_APB1ENR_DAC1EN                       RCC_APB1ENR_DAC1EN_Msk        /*!< DAC 1 clock enable */
11821 
11822 /********************  Bit definition for RCC_BDCR register  ******************/
11823 #define RCC_BDCR_LSE_Pos                         (0U)
11824 #define RCC_BDCR_LSE_Msk                         (0x7UL << RCC_BDCR_LSE_Pos)    /*!< 0x00000007 */
11825 #define RCC_BDCR_LSE                             RCC_BDCR_LSE_Msk              /*!< External Low Speed oscillator [2:0] bits */
11826 #define RCC_BDCR_LSEON_Pos                       (0U)
11827 #define RCC_BDCR_LSEON_Msk                       (0x1UL << RCC_BDCR_LSEON_Pos)  /*!< 0x00000001 */
11828 #define RCC_BDCR_LSEON                           RCC_BDCR_LSEON_Msk            /*!< External Low Speed oscillator enable */
11829 #define RCC_BDCR_LSERDY_Pos                      (1U)
11830 #define RCC_BDCR_LSERDY_Msk                      (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
11831 #define RCC_BDCR_LSERDY                          RCC_BDCR_LSERDY_Msk           /*!< External Low Speed oscillator Ready */
11832 #define RCC_BDCR_LSEBYP_Pos                      (2U)
11833 #define RCC_BDCR_LSEBYP_Msk                      (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
11834 #define RCC_BDCR_LSEBYP                          RCC_BDCR_LSEBYP_Msk           /*!< External Low Speed oscillator Bypass */
11835 
11836 #define RCC_BDCR_LSEDRV_Pos                      (3U)
11837 #define RCC_BDCR_LSEDRV_Msk                      (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
11838 #define RCC_BDCR_LSEDRV                          RCC_BDCR_LSEDRV_Msk           /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
11839 #define RCC_BDCR_LSEDRV_0                        (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
11840 #define RCC_BDCR_LSEDRV_1                        (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
11841 
11842 #define RCC_BDCR_RTCSEL_Pos                      (8U)
11843 #define RCC_BDCR_RTCSEL_Msk                      (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
11844 #define RCC_BDCR_RTCSEL                          RCC_BDCR_RTCSEL_Msk           /*!< RTCSEL[1:0] bits (RTC clock source selection) */
11845 #define RCC_BDCR_RTCSEL_0                        (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
11846 #define RCC_BDCR_RTCSEL_1                        (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
11847 
11848 /*!< RTC configuration */
11849 #define RCC_BDCR_RTCSEL_NOCLOCK                  (0x00000000U)                 /*!< No clock */
11850 #define RCC_BDCR_RTCSEL_LSE                      (0x00000100U)                 /*!< LSE oscillator clock used as RTC clock */
11851 #define RCC_BDCR_RTCSEL_LSI                      (0x00000200U)                 /*!< LSI oscillator clock used as RTC clock */
11852 #define RCC_BDCR_RTCSEL_HSE                      (0x00000300U)                 /*!< HSE oscillator clock divided by 32 used as RTC clock */
11853 
11854 #define RCC_BDCR_RTCEN_Pos                       (15U)
11855 #define RCC_BDCR_RTCEN_Msk                       (0x1UL << RCC_BDCR_RTCEN_Pos)  /*!< 0x00008000 */
11856 #define RCC_BDCR_RTCEN                           RCC_BDCR_RTCEN_Msk            /*!< RTC clock enable */
11857 #define RCC_BDCR_BDRST_Pos                       (16U)
11858 #define RCC_BDCR_BDRST_Msk                       (0x1UL << RCC_BDCR_BDRST_Pos)  /*!< 0x00010000 */
11859 #define RCC_BDCR_BDRST                           RCC_BDCR_BDRST_Msk            /*!< Backup domain software reset  */
11860 
11861 /********************  Bit definition for RCC_CSR register  *******************/
11862 #define RCC_CSR_LSION_Pos                        (0U)
11863 #define RCC_CSR_LSION_Msk                        (0x1UL << RCC_CSR_LSION_Pos)   /*!< 0x00000001 */
11864 #define RCC_CSR_LSION                            RCC_CSR_LSION_Msk             /*!< Internal Low Speed oscillator enable */
11865 #define RCC_CSR_LSIRDY_Pos                       (1U)
11866 #define RCC_CSR_LSIRDY_Msk                       (0x1UL << RCC_CSR_LSIRDY_Pos)  /*!< 0x00000002 */
11867 #define RCC_CSR_LSIRDY                           RCC_CSR_LSIRDY_Msk            /*!< Internal Low Speed oscillator Ready */
11868 #define RCC_CSR_V18PWRRSTF_Pos                   (23U)
11869 #define RCC_CSR_V18PWRRSTF_Msk                   (0x1UL << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
11870 #define RCC_CSR_V18PWRRSTF                       RCC_CSR_V18PWRRSTF_Msk        /*!< V1.8 power domain reset flag */
11871 #define RCC_CSR_RMVF_Pos                         (24U)
11872 #define RCC_CSR_RMVF_Msk                         (0x1UL << RCC_CSR_RMVF_Pos)    /*!< 0x01000000 */
11873 #define RCC_CSR_RMVF                             RCC_CSR_RMVF_Msk              /*!< Remove reset flag */
11874 #define RCC_CSR_OBLRSTF_Pos                      (25U)
11875 #define RCC_CSR_OBLRSTF_Msk                      (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
11876 #define RCC_CSR_OBLRSTF                          RCC_CSR_OBLRSTF_Msk           /*!< OBL reset flag */
11877 #define RCC_CSR_PINRSTF_Pos                      (26U)
11878 #define RCC_CSR_PINRSTF_Msk                      (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
11879 #define RCC_CSR_PINRSTF                          RCC_CSR_PINRSTF_Msk           /*!< PIN reset flag */
11880 #define RCC_CSR_PORRSTF_Pos                      (27U)
11881 #define RCC_CSR_PORRSTF_Msk                      (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
11882 #define RCC_CSR_PORRSTF                          RCC_CSR_PORRSTF_Msk           /*!< POR/PDR reset flag */
11883 #define RCC_CSR_SFTRSTF_Pos                      (28U)
11884 #define RCC_CSR_SFTRSTF_Msk                      (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
11885 #define RCC_CSR_SFTRSTF                          RCC_CSR_SFTRSTF_Msk           /*!< Software Reset flag */
11886 #define RCC_CSR_IWDGRSTF_Pos                     (29U)
11887 #define RCC_CSR_IWDGRSTF_Msk                     (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
11888 #define RCC_CSR_IWDGRSTF                         RCC_CSR_IWDGRSTF_Msk          /*!< Independent Watchdog reset flag */
11889 #define RCC_CSR_WWDGRSTF_Pos                     (30U)
11890 #define RCC_CSR_WWDGRSTF_Msk                     (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
11891 #define RCC_CSR_WWDGRSTF                         RCC_CSR_WWDGRSTF_Msk          /*!< Window watchdog reset flag */
11892 #define RCC_CSR_LPWRRSTF_Pos                     (31U)
11893 #define RCC_CSR_LPWRRSTF_Msk                     (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
11894 #define RCC_CSR_LPWRRSTF                         RCC_CSR_LPWRRSTF_Msk          /*!< Low-Power reset flag */
11895 
11896 /*******************  Bit definition for RCC_AHBRSTR register  ****************/
11897 #define RCC_AHBRSTR_GPIOARST_Pos                 (17U)
11898 #define RCC_AHBRSTR_GPIOARST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
11899 #define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA reset */
11900 #define RCC_AHBRSTR_GPIOBRST_Pos                 (18U)
11901 #define RCC_AHBRSTR_GPIOBRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
11902 #define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB reset */
11903 #define RCC_AHBRSTR_GPIOCRST_Pos                 (19U)
11904 #define RCC_AHBRSTR_GPIOCRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
11905 #define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC reset */
11906 #define RCC_AHBRSTR_GPIODRST_Pos                 (20U)
11907 #define RCC_AHBRSTR_GPIODRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
11908 #define RCC_AHBRSTR_GPIODRST                     RCC_AHBRSTR_GPIODRST_Msk      /*!< GPIOD reset */
11909 #define RCC_AHBRSTR_GPIOFRST_Pos                 (22U)
11910 #define RCC_AHBRSTR_GPIOFRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
11911 #define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF reset */
11912 #define RCC_AHBRSTR_TSCRST_Pos                   (24U)
11913 #define RCC_AHBRSTR_TSCRST_Msk                   (0x1UL << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
11914 #define RCC_AHBRSTR_TSCRST                       RCC_AHBRSTR_TSCRST_Msk        /*!< TSC reset */
11915 #define RCC_AHBRSTR_ADC12RST_Pos                 (28U)
11916 #define RCC_AHBRSTR_ADC12RST_Msk                 (0x1UL << RCC_AHBRSTR_ADC12RST_Pos) /*!< 0x10000000 */
11917 #define RCC_AHBRSTR_ADC12RST                     RCC_AHBRSTR_ADC12RST_Msk      /*!< ADC1 & ADC2 reset */
11918 
11919 /*******************  Bit definition for RCC_CFGR2 register  ******************/
11920 /*!< PREDIV configuration */
11921 #define RCC_CFGR2_PREDIV_Pos                     (0U)
11922 #define RCC_CFGR2_PREDIV_Msk                     (0xFUL << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
11923 #define RCC_CFGR2_PREDIV                         RCC_CFGR2_PREDIV_Msk          /*!< PREDIV[3:0] bits */
11924 #define RCC_CFGR2_PREDIV_0                       (0x1UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
11925 #define RCC_CFGR2_PREDIV_1                       (0x2UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
11926 #define RCC_CFGR2_PREDIV_2                       (0x4UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
11927 #define RCC_CFGR2_PREDIV_3                       (0x8UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
11928 
11929 #define RCC_CFGR2_PREDIV_DIV1                    (0x00000000U)                 /*!< PREDIV input clock not divided */
11930 #define RCC_CFGR2_PREDIV_DIV2                    (0x00000001U)                 /*!< PREDIV input clock divided by 2 */
11931 #define RCC_CFGR2_PREDIV_DIV3                    (0x00000002U)                 /*!< PREDIV input clock divided by 3 */
11932 #define RCC_CFGR2_PREDIV_DIV4                    (0x00000003U)                 /*!< PREDIV input clock divided by 4 */
11933 #define RCC_CFGR2_PREDIV_DIV5                    (0x00000004U)                 /*!< PREDIV input clock divided by 5 */
11934 #define RCC_CFGR2_PREDIV_DIV6                    (0x00000005U)                 /*!< PREDIV input clock divided by 6 */
11935 #define RCC_CFGR2_PREDIV_DIV7                    (0x00000006U)                 /*!< PREDIV input clock divided by 7 */
11936 #define RCC_CFGR2_PREDIV_DIV8                    (0x00000007U)                 /*!< PREDIV input clock divided by 8 */
11937 #define RCC_CFGR2_PREDIV_DIV9                    (0x00000008U)                 /*!< PREDIV input clock divided by 9 */
11938 #define RCC_CFGR2_PREDIV_DIV10                   (0x00000009U)                 /*!< PREDIV input clock divided by 10 */
11939 #define RCC_CFGR2_PREDIV_DIV11                   (0x0000000AU)                 /*!< PREDIV input clock divided by 11 */
11940 #define RCC_CFGR2_PREDIV_DIV12                   (0x0000000BU)                 /*!< PREDIV input clock divided by 12 */
11941 #define RCC_CFGR2_PREDIV_DIV13                   (0x0000000CU)                 /*!< PREDIV input clock divided by 13 */
11942 #define RCC_CFGR2_PREDIV_DIV14                   (0x0000000DU)                 /*!< PREDIV input clock divided by 14 */
11943 #define RCC_CFGR2_PREDIV_DIV15                   (0x0000000EU)                 /*!< PREDIV input clock divided by 15 */
11944 #define RCC_CFGR2_PREDIV_DIV16                   (0x0000000FU)                 /*!< PREDIV input clock divided by 16 */
11945 
11946 /*!< ADCPRE12 configuration */
11947 #define RCC_CFGR2_ADCPRE12_Pos                   (4U)
11948 #define RCC_CFGR2_ADCPRE12_Msk                   (0x1FUL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x000001F0 */
11949 #define RCC_CFGR2_ADCPRE12                       RCC_CFGR2_ADCPRE12_Msk        /*!< ADCPRE12[8:4] bits */
11950 #define RCC_CFGR2_ADCPRE12_0                     (0x01UL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000010 */
11951 #define RCC_CFGR2_ADCPRE12_1                     (0x02UL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000020 */
11952 #define RCC_CFGR2_ADCPRE12_2                     (0x04UL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000040 */
11953 #define RCC_CFGR2_ADCPRE12_3                     (0x08UL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000080 */
11954 #define RCC_CFGR2_ADCPRE12_4                     (0x10UL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000100 */
11955 
11956 #define RCC_CFGR2_ADCPRE12_NO                    (0x00000000U)                 /*!< ADC12 clock disabled, ADC12 can use AHB clock */
11957 #define RCC_CFGR2_ADCPRE12_DIV1                  (0x00000100U)                 /*!< ADC12 PLL clock divided by 1 */
11958 #define RCC_CFGR2_ADCPRE12_DIV2                  (0x00000110U)                 /*!< ADC12 PLL clock divided by 2 */
11959 #define RCC_CFGR2_ADCPRE12_DIV4                  (0x00000120U)                 /*!< ADC12 PLL clock divided by 4 */
11960 #define RCC_CFGR2_ADCPRE12_DIV6                  (0x00000130U)                 /*!< ADC12 PLL clock divided by 6 */
11961 #define RCC_CFGR2_ADCPRE12_DIV8                  (0x00000140U)                 /*!< ADC12 PLL clock divided by 8 */
11962 #define RCC_CFGR2_ADCPRE12_DIV10                 (0x00000150U)                 /*!< ADC12 PLL clock divided by 10 */
11963 #define RCC_CFGR2_ADCPRE12_DIV12                 (0x00000160U)                 /*!< ADC12 PLL clock divided by 12 */
11964 #define RCC_CFGR2_ADCPRE12_DIV16                 (0x00000170U)                 /*!< ADC12 PLL clock divided by 16 */
11965 #define RCC_CFGR2_ADCPRE12_DIV32                 (0x00000180U)                 /*!< ADC12 PLL clock divided by 32 */
11966 #define RCC_CFGR2_ADCPRE12_DIV64                 (0x00000190U)                 /*!< ADC12 PLL clock divided by 64 */
11967 #define RCC_CFGR2_ADCPRE12_DIV128                (0x000001A0U)                 /*!< ADC12 PLL clock divided by 128 */
11968 #define RCC_CFGR2_ADCPRE12_DIV256                (0x000001B0U)                 /*!< ADC12 PLL clock divided by 256 */
11969 
11970 /*******************  Bit definition for RCC_CFGR3 register  ******************/
11971 #define RCC_CFGR3_USART1SW_Pos                   (0U)
11972 #define RCC_CFGR3_USART1SW_Msk                   (0x3UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
11973 #define RCC_CFGR3_USART1SW                       RCC_CFGR3_USART1SW_Msk        /*!< USART1SW[1:0] bits */
11974 #define RCC_CFGR3_USART1SW_0                     (0x1UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
11975 #define RCC_CFGR3_USART1SW_1                     (0x2UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
11976 
11977 #define RCC_CFGR3_USART1SW_PCLK1                 (0x00000000U)                 /*!< PCLK1 clock used as USART1 clock source */
11978 #define RCC_CFGR3_USART1SW_SYSCLK                (0x00000001U)                 /*!< System clock selected as USART1 clock source */
11979 #define RCC_CFGR3_USART1SW_LSE                   (0x00000002U)                 /*!< LSE oscillator clock used as USART1 clock source */
11980 #define RCC_CFGR3_USART1SW_HSI                   (0x00000003U)                 /*!< HSI oscillator clock used as USART1 clock source */
11981 /* Legacy defines */
11982 #define  RCC_CFGR3_USART1SW_PCLK             RCC_CFGR3_USART1SW_PCLK1
11983 
11984 #define RCC_CFGR3_I2CSW_Pos                      (4U)
11985 #define RCC_CFGR3_I2CSW_Msk                      (0x1UL << RCC_CFGR3_I2CSW_Pos) /*!< 0x00000010 */
11986 #define RCC_CFGR3_I2CSW                          RCC_CFGR3_I2CSW_Msk           /*!< I2CSW bits */
11987 #define RCC_CFGR3_I2C1SW_Pos                     (4U)
11988 #define RCC_CFGR3_I2C1SW_Msk                     (0x1UL << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
11989 #define RCC_CFGR3_I2C1SW                         RCC_CFGR3_I2C1SW_Msk          /*!< I2C1SW bits */
11990 
11991 #define RCC_CFGR3_I2C1SW_HSI                     (0x00000000U)                 /*!< HSI oscillator clock used as I2C1 clock source */
11992 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos              (4U)
11993 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk              (0x1UL << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
11994 #define RCC_CFGR3_I2C1SW_SYSCLK                  RCC_CFGR3_I2C1SW_SYSCLK_Msk   /*!< System clock selected as I2C1 clock source */
11995 #define RCC_CFGR3_TIMSW_Pos                      (8U)
11996 #define RCC_CFGR3_TIMSW_Msk                      (0x1UL << RCC_CFGR3_TIMSW_Pos) /*!< 0x00000100 */
11997 #define RCC_CFGR3_TIMSW                          RCC_CFGR3_TIMSW_Msk           /*!< TIMSW bits */
11998 #define RCC_CFGR3_TIM1SW_Pos                     (8U)
11999 #define RCC_CFGR3_TIM1SW_Msk                     (0x1UL << RCC_CFGR3_TIM1SW_Pos) /*!< 0x00000100 */
12000 #define RCC_CFGR3_TIM1SW                         RCC_CFGR3_TIM1SW_Msk          /*!< TIM1SW bits */
12001 #define RCC_CFGR3_TIM1SW_PCLK2                   (0x00000000U)                 /*!< PCLK2 used as TIM1 clock source */
12002 #define RCC_CFGR3_TIM1SW_PLL_Pos                 (8U)
12003 #define RCC_CFGR3_TIM1SW_PLL_Msk                 (0x1UL << RCC_CFGR3_TIM1SW_PLL_Pos) /*!< 0x00000100 */
12004 #define RCC_CFGR3_TIM1SW_PLL                     RCC_CFGR3_TIM1SW_PLL_Msk      /*!< PLL clock used as TIM1 clock source */
12005 
12006 #define RCC_CFGR3_HRTIMSW_Pos                    (12U)
12007 #define RCC_CFGR3_HRTIMSW_Msk                    (0x1UL << RCC_CFGR3_HRTIMSW_Pos) /*!< 0x00001000 */
12008 #define RCC_CFGR3_HRTIMSW                        RCC_CFGR3_HRTIMSW_Msk         /*!< HRTIM1SW bits */
12009 #define RCC_CFGR3_HRTIM1SW_Pos                   (12U)
12010 #define RCC_CFGR3_HRTIM1SW_Msk                   (0x1UL << RCC_CFGR3_HRTIM1SW_Pos) /*!< 0x00001000 */
12011 #define RCC_CFGR3_HRTIM1SW                       RCC_CFGR3_HRTIM1SW_Msk        /*!< HRTIM1SW bits */
12012 
12013 #define RCC_CFGR3_HRTIM1SW_PCLK2                 (0x00000000U)                 /*!< PCLK2 used as  HRTIM1 clock source */
12014 #define RCC_CFGR3_HRTIM1SW_PLL_Pos               (12U)
12015 #define RCC_CFGR3_HRTIM1SW_PLL_Msk               (0x1UL << RCC_CFGR3_HRTIM1SW_PLL_Pos) /*!< 0x00001000 */
12016 #define RCC_CFGR3_HRTIM1SW_PLL                   RCC_CFGR3_HRTIM1SW_PLL_Msk    /*!< PLL clock used as  HRTIM1 clock source */
12017 
12018 /* Legacy defines */
12019 #define  RCC_CFGR3_TIM1SW_HCLK                RCC_CFGR3_TIM1SW_PCLK2
12020 #define  RCC_CFGR3_HRTIM1SW_HCLK              RCC_CFGR3_HRTIM1SW_PCLK2
12021 
12022 /******************************************************************************/
12023 /*                                                                            */
12024 /*                           Real-Time Clock (RTC)                            */
12025 /*                                                                            */
12026 /******************************************************************************/
12027 /*
12028 * @brief Specific device feature definitions  (not present on all devices in the STM32F3 serie)
12029 */
12030 #define RTC_TAMPER1_SUPPORT  /*!< TAMPER 1 feature support */
12031 #define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */
12032 #define RTC_BACKUP_SUPPORT   /*!< BACKUP register feature support */
12033 #define RTC_WAKEUP_SUPPORT   /*!< WAKEUP feature support */
12034 
12035 /********************  Bits definition for RTC_TR register  *******************/
12036 #define RTC_TR_PM_Pos                (22U)
12037 #define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                   /*!< 0x00400000 */
12038 #define RTC_TR_PM                    RTC_TR_PM_Msk
12039 #define RTC_TR_HT_Pos                (20U)
12040 #define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                   /*!< 0x00300000 */
12041 #define RTC_TR_HT                    RTC_TR_HT_Msk
12042 #define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                   /*!< 0x00100000 */
12043 #define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                   /*!< 0x00200000 */
12044 #define RTC_TR_HU_Pos                (16U)
12045 #define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                   /*!< 0x000F0000 */
12046 #define RTC_TR_HU                    RTC_TR_HU_Msk
12047 #define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                   /*!< 0x00010000 */
12048 #define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                   /*!< 0x00020000 */
12049 #define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                   /*!< 0x00040000 */
12050 #define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                   /*!< 0x00080000 */
12051 #define RTC_TR_MNT_Pos               (12U)
12052 #define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                  /*!< 0x00007000 */
12053 #define RTC_TR_MNT                   RTC_TR_MNT_Msk
12054 #define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                  /*!< 0x00001000 */
12055 #define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                  /*!< 0x00002000 */
12056 #define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                  /*!< 0x00004000 */
12057 #define RTC_TR_MNU_Pos               (8U)
12058 #define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                  /*!< 0x00000F00 */
12059 #define RTC_TR_MNU                   RTC_TR_MNU_Msk
12060 #define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                  /*!< 0x00000100 */
12061 #define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                  /*!< 0x00000200 */
12062 #define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                  /*!< 0x00000400 */
12063 #define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                  /*!< 0x00000800 */
12064 #define RTC_TR_ST_Pos                (4U)
12065 #define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                   /*!< 0x00000070 */
12066 #define RTC_TR_ST                    RTC_TR_ST_Msk
12067 #define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                   /*!< 0x00000010 */
12068 #define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                   /*!< 0x00000020 */
12069 #define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                   /*!< 0x00000040 */
12070 #define RTC_TR_SU_Pos                (0U)
12071 #define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                   /*!< 0x0000000F */
12072 #define RTC_TR_SU                    RTC_TR_SU_Msk
12073 #define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                   /*!< 0x00000001 */
12074 #define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                   /*!< 0x00000002 */
12075 #define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                   /*!< 0x00000004 */
12076 #define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                   /*!< 0x00000008 */
12077 
12078 /********************  Bits definition for RTC_DR register  *******************/
12079 #define RTC_DR_YT_Pos                (20U)
12080 #define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                   /*!< 0x00F00000 */
12081 #define RTC_DR_YT                    RTC_DR_YT_Msk
12082 #define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                   /*!< 0x00100000 */
12083 #define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                   /*!< 0x00200000 */
12084 #define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                   /*!< 0x00400000 */
12085 #define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                   /*!< 0x00800000 */
12086 #define RTC_DR_YU_Pos                (16U)
12087 #define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                   /*!< 0x000F0000 */
12088 #define RTC_DR_YU                    RTC_DR_YU_Msk
12089 #define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                   /*!< 0x00010000 */
12090 #define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                   /*!< 0x00020000 */
12091 #define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                   /*!< 0x00040000 */
12092 #define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                   /*!< 0x00080000 */
12093 #define RTC_DR_WDU_Pos               (13U)
12094 #define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                  /*!< 0x0000E000 */
12095 #define RTC_DR_WDU                   RTC_DR_WDU_Msk
12096 #define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                  /*!< 0x00002000 */
12097 #define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                  /*!< 0x00004000 */
12098 #define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                  /*!< 0x00008000 */
12099 #define RTC_DR_MT_Pos                (12U)
12100 #define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                   /*!< 0x00001000 */
12101 #define RTC_DR_MT                    RTC_DR_MT_Msk
12102 #define RTC_DR_MU_Pos                (8U)
12103 #define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                   /*!< 0x00000F00 */
12104 #define RTC_DR_MU                    RTC_DR_MU_Msk
12105 #define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                   /*!< 0x00000100 */
12106 #define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                   /*!< 0x00000200 */
12107 #define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                   /*!< 0x00000400 */
12108 #define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                   /*!< 0x00000800 */
12109 #define RTC_DR_DT_Pos                (4U)
12110 #define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                   /*!< 0x00000030 */
12111 #define RTC_DR_DT                    RTC_DR_DT_Msk
12112 #define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                   /*!< 0x00000010 */
12113 #define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                   /*!< 0x00000020 */
12114 #define RTC_DR_DU_Pos                (0U)
12115 #define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                   /*!< 0x0000000F */
12116 #define RTC_DR_DU                    RTC_DR_DU_Msk
12117 #define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                   /*!< 0x00000001 */
12118 #define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                   /*!< 0x00000002 */
12119 #define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                   /*!< 0x00000004 */
12120 #define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                   /*!< 0x00000008 */
12121 
12122 /********************  Bits definition for RTC_CR register  *******************/
12123 #define RTC_CR_COE_Pos               (23U)
12124 #define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                  /*!< 0x00800000 */
12125 #define RTC_CR_COE                   RTC_CR_COE_Msk
12126 #define RTC_CR_OSEL_Pos              (21U)
12127 #define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                 /*!< 0x00600000 */
12128 #define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
12129 #define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                 /*!< 0x00200000 */
12130 #define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                 /*!< 0x00400000 */
12131 #define RTC_CR_POL_Pos               (20U)
12132 #define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                  /*!< 0x00100000 */
12133 #define RTC_CR_POL                   RTC_CR_POL_Msk
12134 #define RTC_CR_COSEL_Pos             (19U)
12135 #define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
12136 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
12137 #define RTC_CR_BKP_Pos               (18U)
12138 #define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
12139 #define RTC_CR_BKP                   RTC_CR_BKP_Msk
12140 #define RTC_CR_SUB1H_Pos             (17U)
12141 #define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
12142 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
12143 #define RTC_CR_ADD1H_Pos             (16U)
12144 #define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)                /*!< 0x00010000 */
12145 #define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
12146 #define RTC_CR_TSIE_Pos              (15U)
12147 #define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                 /*!< 0x00008000 */
12148 #define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
12149 #define RTC_CR_WUTIE_Pos             (14U)
12150 #define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)                /*!< 0x00004000 */
12151 #define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
12152 #define RTC_CR_ALRBIE_Pos            (13U)
12153 #define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)               /*!< 0x00002000 */
12154 #define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
12155 #define RTC_CR_ALRAIE_Pos            (12U)
12156 #define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)               /*!< 0x00001000 */
12157 #define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
12158 #define RTC_CR_TSE_Pos               (11U)
12159 #define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                  /*!< 0x00000800 */
12160 #define RTC_CR_TSE                   RTC_CR_TSE_Msk
12161 #define RTC_CR_WUTE_Pos              (10U)
12162 #define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                 /*!< 0x00000400 */
12163 #define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
12164 #define RTC_CR_ALRBE_Pos             (9U)
12165 #define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)                /*!< 0x00000200 */
12166 #define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
12167 #define RTC_CR_ALRAE_Pos             (8U)
12168 #define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)                /*!< 0x00000100 */
12169 #define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
12170 #define RTC_CR_FMT_Pos               (6U)
12171 #define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                  /*!< 0x00000040 */
12172 #define RTC_CR_FMT                   RTC_CR_FMT_Msk
12173 #define RTC_CR_BYPSHAD_Pos           (5U)
12174 #define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)              /*!< 0x00000020 */
12175 #define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
12176 #define RTC_CR_REFCKON_Pos           (4U)
12177 #define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)              /*!< 0x00000010 */
12178 #define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
12179 #define RTC_CR_TSEDGE_Pos            (3U)
12180 #define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)               /*!< 0x00000008 */
12181 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
12182 #define RTC_CR_WUCKSEL_Pos           (0U)
12183 #define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000007 */
12184 #define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
12185 #define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000001 */
12186 #define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */
12187 #define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */
12188 
12189 /* Legacy defines */
12190 #define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
12191 #define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
12192 #define RTC_CR_BCK                   RTC_CR_BKP
12193 
12194 /********************  Bits definition for RTC_ISR register  ******************/
12195 #define RTC_ISR_RECALPF_Pos          (16U)
12196 #define RTC_ISR_RECALPF_Msk          (0x1UL << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */
12197 #define RTC_ISR_RECALPF              RTC_ISR_RECALPF_Msk
12198 #define RTC_ISR_TAMP2F_Pos           (14U)
12199 #define RTC_ISR_TAMP2F_Msk           (0x1UL << RTC_ISR_TAMP2F_Pos)              /*!< 0x00004000 */
12200 #define RTC_ISR_TAMP2F               RTC_ISR_TAMP2F_Msk
12201 #define RTC_ISR_TAMP1F_Pos           (13U)
12202 #define RTC_ISR_TAMP1F_Msk           (0x1UL << RTC_ISR_TAMP1F_Pos)              /*!< 0x00002000 */
12203 #define RTC_ISR_TAMP1F               RTC_ISR_TAMP1F_Msk
12204 #define RTC_ISR_TSOVF_Pos            (12U)
12205 #define RTC_ISR_TSOVF_Msk            (0x1UL << RTC_ISR_TSOVF_Pos)               /*!< 0x00001000 */
12206 #define RTC_ISR_TSOVF                RTC_ISR_TSOVF_Msk
12207 #define RTC_ISR_TSF_Pos              (11U)
12208 #define RTC_ISR_TSF_Msk              (0x1UL << RTC_ISR_TSF_Pos)                 /*!< 0x00000800 */
12209 #define RTC_ISR_TSF                  RTC_ISR_TSF_Msk
12210 #define RTC_ISR_WUTF_Pos             (10U)
12211 #define RTC_ISR_WUTF_Msk             (0x1UL << RTC_ISR_WUTF_Pos)                /*!< 0x00000400 */
12212 #define RTC_ISR_WUTF                 RTC_ISR_WUTF_Msk
12213 #define RTC_ISR_ALRBF_Pos            (9U)
12214 #define RTC_ISR_ALRBF_Msk            (0x1UL << RTC_ISR_ALRBF_Pos)               /*!< 0x00000200 */
12215 #define RTC_ISR_ALRBF                RTC_ISR_ALRBF_Msk
12216 #define RTC_ISR_ALRAF_Pos            (8U)
12217 #define RTC_ISR_ALRAF_Msk            (0x1UL << RTC_ISR_ALRAF_Pos)               /*!< 0x00000100 */
12218 #define RTC_ISR_ALRAF                RTC_ISR_ALRAF_Msk
12219 #define RTC_ISR_INIT_Pos             (7U)
12220 #define RTC_ISR_INIT_Msk             (0x1UL << RTC_ISR_INIT_Pos)                /*!< 0x00000080 */
12221 #define RTC_ISR_INIT                 RTC_ISR_INIT_Msk
12222 #define RTC_ISR_INITF_Pos            (6U)
12223 #define RTC_ISR_INITF_Msk            (0x1UL << RTC_ISR_INITF_Pos)               /*!< 0x00000040 */
12224 #define RTC_ISR_INITF                RTC_ISR_INITF_Msk
12225 #define RTC_ISR_RSF_Pos              (5U)
12226 #define RTC_ISR_RSF_Msk              (0x1UL << RTC_ISR_RSF_Pos)                 /*!< 0x00000020 */
12227 #define RTC_ISR_RSF                  RTC_ISR_RSF_Msk
12228 #define RTC_ISR_INITS_Pos            (4U)
12229 #define RTC_ISR_INITS_Msk            (0x1UL << RTC_ISR_INITS_Pos)               /*!< 0x00000010 */
12230 #define RTC_ISR_INITS                RTC_ISR_INITS_Msk
12231 #define RTC_ISR_SHPF_Pos             (3U)
12232 #define RTC_ISR_SHPF_Msk             (0x1UL << RTC_ISR_SHPF_Pos)                /*!< 0x00000008 */
12233 #define RTC_ISR_SHPF                 RTC_ISR_SHPF_Msk
12234 #define RTC_ISR_WUTWF_Pos            (2U)
12235 #define RTC_ISR_WUTWF_Msk            (0x1UL << RTC_ISR_WUTWF_Pos)               /*!< 0x00000004 */
12236 #define RTC_ISR_WUTWF                RTC_ISR_WUTWF_Msk
12237 #define RTC_ISR_ALRBWF_Pos           (1U)
12238 #define RTC_ISR_ALRBWF_Msk           (0x1UL << RTC_ISR_ALRBWF_Pos)              /*!< 0x00000002 */
12239 #define RTC_ISR_ALRBWF               RTC_ISR_ALRBWF_Msk
12240 #define RTC_ISR_ALRAWF_Pos           (0U)
12241 #define RTC_ISR_ALRAWF_Msk           (0x1UL << RTC_ISR_ALRAWF_Pos)              /*!< 0x00000001 */
12242 #define RTC_ISR_ALRAWF               RTC_ISR_ALRAWF_Msk
12243 
12244 /********************  Bits definition for RTC_PRER register  *****************/
12245 #define RTC_PRER_PREDIV_A_Pos        (16U)
12246 #define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)          /*!< 0x007F0000 */
12247 #define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
12248 #define RTC_PRER_PREDIV_S_Pos        (0U)
12249 #define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)        /*!< 0x00007FFF */
12250 #define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
12251 
12252 /********************  Bits definition for RTC_WUTR register  *****************/
12253 #define RTC_WUTR_WUT_Pos             (0U)
12254 #define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)             /*!< 0x0000FFFF */
12255 #define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
12256 
12257 /********************  Bits definition for RTC_ALRMAR register  ***************/
12258 #define RTC_ALRMAR_MSK4_Pos          (31U)
12259 #define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)             /*!< 0x80000000 */
12260 #define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
12261 #define RTC_ALRMAR_WDSEL_Pos         (30U)
12262 #define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)            /*!< 0x40000000 */
12263 #define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
12264 #define RTC_ALRMAR_DT_Pos            (28U)
12265 #define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)               /*!< 0x30000000 */
12266 #define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
12267 #define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)               /*!< 0x10000000 */
12268 #define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)               /*!< 0x20000000 */
12269 #define RTC_ALRMAR_DU_Pos            (24U)
12270 #define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)               /*!< 0x0F000000 */
12271 #define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
12272 #define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)               /*!< 0x01000000 */
12273 #define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)               /*!< 0x02000000 */
12274 #define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)               /*!< 0x04000000 */
12275 #define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)               /*!< 0x08000000 */
12276 #define RTC_ALRMAR_MSK3_Pos          (23U)
12277 #define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)             /*!< 0x00800000 */
12278 #define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
12279 #define RTC_ALRMAR_PM_Pos            (22U)
12280 #define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)               /*!< 0x00400000 */
12281 #define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
12282 #define RTC_ALRMAR_HT_Pos            (20U)
12283 #define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)               /*!< 0x00300000 */
12284 #define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
12285 #define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)               /*!< 0x00100000 */
12286 #define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)               /*!< 0x00200000 */
12287 #define RTC_ALRMAR_HU_Pos            (16U)
12288 #define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)               /*!< 0x000F0000 */
12289 #define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
12290 #define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00010000 */
12291 #define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00020000 */
12292 #define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00040000 */
12293 #define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00080000 */
12294 #define RTC_ALRMAR_MSK2_Pos          (15U)
12295 #define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)             /*!< 0x00008000 */
12296 #define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
12297 #define RTC_ALRMAR_MNT_Pos           (12U)
12298 #define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00007000 */
12299 #define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
12300 #define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00001000 */
12301 #define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00002000 */
12302 #define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00004000 */
12303 #define RTC_ALRMAR_MNU_Pos           (8U)
12304 #define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000F00 */
12305 #define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
12306 #define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000100 */
12307 #define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000200 */
12308 #define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000400 */
12309 #define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000800 */
12310 #define RTC_ALRMAR_MSK1_Pos          (7U)
12311 #define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)             /*!< 0x00000080 */
12312 #define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
12313 #define RTC_ALRMAR_ST_Pos            (4U)
12314 #define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000070 */
12315 #define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
12316 #define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000010 */
12317 #define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000020 */
12318 #define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000040 */
12319 #define RTC_ALRMAR_SU_Pos            (0U)
12320 #define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)               /*!< 0x0000000F */
12321 #define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
12322 #define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000001 */
12323 #define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000002 */
12324 #define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000004 */
12325 #define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000008 */
12326 
12327 /********************  Bits definition for RTC_ALRMBR register  ***************/
12328 #define RTC_ALRMBR_MSK4_Pos          (31U)
12329 #define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)             /*!< 0x80000000 */
12330 #define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
12331 #define RTC_ALRMBR_WDSEL_Pos         (30U)
12332 #define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)            /*!< 0x40000000 */
12333 #define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
12334 #define RTC_ALRMBR_DT_Pos            (28U)
12335 #define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)               /*!< 0x30000000 */
12336 #define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
12337 #define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)               /*!< 0x10000000 */
12338 #define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)               /*!< 0x20000000 */
12339 #define RTC_ALRMBR_DU_Pos            (24U)
12340 #define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)               /*!< 0x0F000000 */
12341 #define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
12342 #define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)               /*!< 0x01000000 */
12343 #define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)               /*!< 0x02000000 */
12344 #define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)               /*!< 0x04000000 */
12345 #define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)               /*!< 0x08000000 */
12346 #define RTC_ALRMBR_MSK3_Pos          (23U)
12347 #define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)             /*!< 0x00800000 */
12348 #define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
12349 #define RTC_ALRMBR_PM_Pos            (22U)
12350 #define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)               /*!< 0x00400000 */
12351 #define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
12352 #define RTC_ALRMBR_HT_Pos            (20U)
12353 #define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)               /*!< 0x00300000 */
12354 #define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
12355 #define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)               /*!< 0x00100000 */
12356 #define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)               /*!< 0x00200000 */
12357 #define RTC_ALRMBR_HU_Pos            (16U)
12358 #define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)               /*!< 0x000F0000 */
12359 #define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
12360 #define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)               /*!< 0x00010000 */
12361 #define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)               /*!< 0x00020000 */
12362 #define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)               /*!< 0x00040000 */
12363 #define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)               /*!< 0x00080000 */
12364 #define RTC_ALRMBR_MSK2_Pos          (15U)
12365 #define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)             /*!< 0x00008000 */
12366 #define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
12367 #define RTC_ALRMBR_MNT_Pos           (12U)
12368 #define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)              /*!< 0x00007000 */
12369 #define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
12370 #define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)              /*!< 0x00001000 */
12371 #define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)              /*!< 0x00002000 */
12372 #define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)              /*!< 0x00004000 */
12373 #define RTC_ALRMBR_MNU_Pos           (8U)
12374 #define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)              /*!< 0x00000F00 */
12375 #define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
12376 #define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)              /*!< 0x00000100 */
12377 #define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)              /*!< 0x00000200 */
12378 #define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)              /*!< 0x00000400 */
12379 #define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)              /*!< 0x00000800 */
12380 #define RTC_ALRMBR_MSK1_Pos          (7U)
12381 #define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)             /*!< 0x00000080 */
12382 #define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
12383 #define RTC_ALRMBR_ST_Pos            (4U)
12384 #define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)               /*!< 0x00000070 */
12385 #define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
12386 #define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)               /*!< 0x00000010 */
12387 #define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)               /*!< 0x00000020 */
12388 #define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)               /*!< 0x00000040 */
12389 #define RTC_ALRMBR_SU_Pos            (0U)
12390 #define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)               /*!< 0x0000000F */
12391 #define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
12392 #define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)               /*!< 0x00000001 */
12393 #define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)               /*!< 0x00000002 */
12394 #define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)               /*!< 0x00000004 */
12395 #define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)               /*!< 0x00000008 */
12396 
12397 /********************  Bits definition for RTC_WPR register  ******************/
12398 #define RTC_WPR_KEY_Pos              (0U)
12399 #define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)                /*!< 0x000000FF */
12400 #define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
12401 
12402 /********************  Bits definition for RTC_SSR register  ******************/
12403 #define RTC_SSR_SS_Pos               (0U)
12404 #define RTC_SSR_SS_Msk               (0xFFFFUL << RTC_SSR_SS_Pos)               /*!< 0x0000FFFF */
12405 #define RTC_SSR_SS                   RTC_SSR_SS_Msk
12406 
12407 /********************  Bits definition for RTC_SHIFTR register  ***************/
12408 #define RTC_SHIFTR_SUBFS_Pos         (0U)
12409 #define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)         /*!< 0x00007FFF */
12410 #define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
12411 #define RTC_SHIFTR_ADD1S_Pos         (31U)
12412 #define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)            /*!< 0x80000000 */
12413 #define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
12414 
12415 /********************  Bits definition for RTC_TSTR register  *****************/
12416 #define RTC_TSTR_PM_Pos              (22U)
12417 #define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                 /*!< 0x00400000 */
12418 #define RTC_TSTR_PM                  RTC_TSTR_PM_Msk
12419 #define RTC_TSTR_HT_Pos              (20U)
12420 #define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                 /*!< 0x00300000 */
12421 #define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
12422 #define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                 /*!< 0x00100000 */
12423 #define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                 /*!< 0x00200000 */
12424 #define RTC_TSTR_HU_Pos              (16U)
12425 #define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                 /*!< 0x000F0000 */
12426 #define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
12427 #define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                 /*!< 0x00010000 */
12428 #define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                 /*!< 0x00020000 */
12429 #define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                 /*!< 0x00040000 */
12430 #define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                 /*!< 0x00080000 */
12431 #define RTC_TSTR_MNT_Pos             (12U)
12432 #define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)                /*!< 0x00007000 */
12433 #define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
12434 #define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)                /*!< 0x00001000 */
12435 #define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)                /*!< 0x00002000 */
12436 #define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)                /*!< 0x00004000 */
12437 #define RTC_TSTR_MNU_Pos             (8U)
12438 #define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)                /*!< 0x00000F00 */
12439 #define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
12440 #define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000100 */
12441 #define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000200 */
12442 #define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000400 */
12443 #define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000800 */
12444 #define RTC_TSTR_ST_Pos              (4U)
12445 #define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000070 */
12446 #define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
12447 #define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000010 */
12448 #define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000020 */
12449 #define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000040 */
12450 #define RTC_TSTR_SU_Pos              (0U)
12451 #define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                 /*!< 0x0000000F */
12452 #define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
12453 #define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000001 */
12454 #define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000002 */
12455 #define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000004 */
12456 #define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000008 */
12457 
12458 /********************  Bits definition for RTC_TSDR register  *****************/
12459 #define RTC_TSDR_WDU_Pos             (13U)
12460 #define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)                /*!< 0x0000E000 */
12461 #define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk
12462 #define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)                /*!< 0x00002000 */
12463 #define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)                /*!< 0x00004000 */
12464 #define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)                /*!< 0x00008000 */
12465 #define RTC_TSDR_MT_Pos              (12U)
12466 #define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                 /*!< 0x00001000 */
12467 #define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
12468 #define RTC_TSDR_MU_Pos              (8U)
12469 #define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                 /*!< 0x00000F00 */
12470 #define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
12471 #define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000100 */
12472 #define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000200 */
12473 #define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000400 */
12474 #define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000800 */
12475 #define RTC_TSDR_DT_Pos              (4U)
12476 #define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                 /*!< 0x00000030 */
12477 #define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
12478 #define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                 /*!< 0x00000010 */
12479 #define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                 /*!< 0x00000020 */
12480 #define RTC_TSDR_DU_Pos              (0U)
12481 #define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                 /*!< 0x0000000F */
12482 #define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
12483 #define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000001 */
12484 #define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000002 */
12485 #define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000004 */
12486 #define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000008 */
12487 
12488 /********************  Bits definition for RTC_TSSSR register  ****************/
12489 #define RTC_TSSSR_SS_Pos             (0U)
12490 #define RTC_TSSSR_SS_Msk             (0xFFFFUL << RTC_TSSSR_SS_Pos)             /*!< 0x0000FFFF */
12491 #define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk
12492 
12493 /********************  Bits definition for RTC_CAL register  *****************/
12494 #define RTC_CALR_CALP_Pos            (15U)
12495 #define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)               /*!< 0x00008000 */
12496 #define RTC_CALR_CALP                RTC_CALR_CALP_Msk
12497 #define RTC_CALR_CALW8_Pos           (14U)
12498 #define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)              /*!< 0x00004000 */
12499 #define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
12500 #define RTC_CALR_CALW16_Pos          (13U)
12501 #define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)             /*!< 0x00002000 */
12502 #define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
12503 #define RTC_CALR_CALM_Pos            (0U)
12504 #define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)             /*!< 0x000001FF */
12505 #define RTC_CALR_CALM                RTC_CALR_CALM_Msk
12506 #define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)             /*!< 0x00000001 */
12507 #define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)             /*!< 0x00000002 */
12508 #define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)             /*!< 0x00000004 */
12509 #define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)             /*!< 0x00000008 */
12510 #define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)             /*!< 0x00000010 */
12511 #define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)             /*!< 0x00000020 */
12512 #define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)             /*!< 0x00000040 */
12513 #define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)             /*!< 0x00000080 */
12514 #define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)             /*!< 0x00000100 */
12515 
12516 /********************  Bits definition for RTC_TAFCR register  ****************/
12517 #define RTC_TAFCR_PC15MODE_Pos       (23U)
12518 #define RTC_TAFCR_PC15MODE_Msk       (0x1UL << RTC_TAFCR_PC15MODE_Pos)          /*!< 0x00800000 */
12519 #define RTC_TAFCR_PC15MODE           RTC_TAFCR_PC15MODE_Msk
12520 #define RTC_TAFCR_PC15VALUE_Pos      (22U)
12521 #define RTC_TAFCR_PC15VALUE_Msk      (0x1UL << RTC_TAFCR_PC15VALUE_Pos)         /*!< 0x00400000 */
12522 #define RTC_TAFCR_PC15VALUE          RTC_TAFCR_PC15VALUE_Msk
12523 #define RTC_TAFCR_PC14MODE_Pos       (21U)
12524 #define RTC_TAFCR_PC14MODE_Msk       (0x1UL << RTC_TAFCR_PC14MODE_Pos)          /*!< 0x00200000 */
12525 #define RTC_TAFCR_PC14MODE           RTC_TAFCR_PC14MODE_Msk
12526 #define RTC_TAFCR_PC14VALUE_Pos      (20U)
12527 #define RTC_TAFCR_PC14VALUE_Msk      (0x1UL << RTC_TAFCR_PC14VALUE_Pos)         /*!< 0x00100000 */
12528 #define RTC_TAFCR_PC14VALUE          RTC_TAFCR_PC14VALUE_Msk
12529 #define RTC_TAFCR_PC13MODE_Pos       (19U)
12530 #define RTC_TAFCR_PC13MODE_Msk       (0x1UL << RTC_TAFCR_PC13MODE_Pos)          /*!< 0x00080000 */
12531 #define RTC_TAFCR_PC13MODE           RTC_TAFCR_PC13MODE_Msk
12532 #define RTC_TAFCR_PC13VALUE_Pos      (18U)
12533 #define RTC_TAFCR_PC13VALUE_Msk      (0x1UL << RTC_TAFCR_PC13VALUE_Pos)         /*!< 0x00040000 */
12534 #define RTC_TAFCR_PC13VALUE          RTC_TAFCR_PC13VALUE_Msk
12535 #define RTC_TAFCR_TAMPPUDIS_Pos      (15U)
12536 #define RTC_TAFCR_TAMPPUDIS_Msk      (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)         /*!< 0x00008000 */
12537 #define RTC_TAFCR_TAMPPUDIS          RTC_TAFCR_TAMPPUDIS_Msk
12538 #define RTC_TAFCR_TAMPPRCH_Pos       (13U)
12539 #define RTC_TAFCR_TAMPPRCH_Msk       (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00006000 */
12540 #define RTC_TAFCR_TAMPPRCH           RTC_TAFCR_TAMPPRCH_Msk
12541 #define RTC_TAFCR_TAMPPRCH_0         (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00002000 */
12542 #define RTC_TAFCR_TAMPPRCH_1         (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00004000 */
12543 #define RTC_TAFCR_TAMPFLT_Pos        (11U)
12544 #define RTC_TAFCR_TAMPFLT_Msk        (0x3UL << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00001800 */
12545 #define RTC_TAFCR_TAMPFLT            RTC_TAFCR_TAMPFLT_Msk
12546 #define RTC_TAFCR_TAMPFLT_0          (0x1UL << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00000800 */
12547 #define RTC_TAFCR_TAMPFLT_1          (0x2UL << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00001000 */
12548 #define RTC_TAFCR_TAMPFREQ_Pos       (8U)
12549 #define RTC_TAFCR_TAMPFREQ_Msk       (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000700 */
12550 #define RTC_TAFCR_TAMPFREQ           RTC_TAFCR_TAMPFREQ_Msk
12551 #define RTC_TAFCR_TAMPFREQ_0         (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000100 */
12552 #define RTC_TAFCR_TAMPFREQ_1         (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000200 */
12553 #define RTC_TAFCR_TAMPFREQ_2         (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000400 */
12554 #define RTC_TAFCR_TAMPTS_Pos         (7U)
12555 #define RTC_TAFCR_TAMPTS_Msk         (0x1UL << RTC_TAFCR_TAMPTS_Pos)            /*!< 0x00000080 */
12556 #define RTC_TAFCR_TAMPTS             RTC_TAFCR_TAMPTS_Msk
12557 #define RTC_TAFCR_TAMP2TRG_Pos       (4U)
12558 #define RTC_TAFCR_TAMP2TRG_Msk       (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)          /*!< 0x00000010 */
12559 #define RTC_TAFCR_TAMP2TRG           RTC_TAFCR_TAMP2TRG_Msk
12560 #define RTC_TAFCR_TAMP2E_Pos         (3U)
12561 #define RTC_TAFCR_TAMP2E_Msk         (0x1UL << RTC_TAFCR_TAMP2E_Pos)            /*!< 0x00000008 */
12562 #define RTC_TAFCR_TAMP2E             RTC_TAFCR_TAMP2E_Msk
12563 #define RTC_TAFCR_TAMPIE_Pos         (2U)
12564 #define RTC_TAFCR_TAMPIE_Msk         (0x1UL << RTC_TAFCR_TAMPIE_Pos)            /*!< 0x00000004 */
12565 #define RTC_TAFCR_TAMPIE             RTC_TAFCR_TAMPIE_Msk
12566 #define RTC_TAFCR_TAMP1TRG_Pos       (1U)
12567 #define RTC_TAFCR_TAMP1TRG_Msk       (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)          /*!< 0x00000002 */
12568 #define RTC_TAFCR_TAMP1TRG           RTC_TAFCR_TAMP1TRG_Msk
12569 #define RTC_TAFCR_TAMP1E_Pos         (0U)
12570 #define RTC_TAFCR_TAMP1E_Msk         (0x1UL << RTC_TAFCR_TAMP1E_Pos)            /*!< 0x00000001 */
12571 #define RTC_TAFCR_TAMP1E             RTC_TAFCR_TAMP1E_Msk
12572 
12573 /* Reference defines */
12574 #define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_PC13VALUE
12575 
12576 /********************  Bits definition for RTC_ALRMASSR register  *************/
12577 #define RTC_ALRMASSR_MASKSS_Pos      (24U)
12578 #define RTC_ALRMASSR_MASKSS_Msk      (0xFUL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x0F000000 */
12579 #define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
12580 #define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x01000000 */
12581 #define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x02000000 */
12582 #define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x04000000 */
12583 #define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x08000000 */
12584 #define RTC_ALRMASSR_SS_Pos          (0U)
12585 #define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)          /*!< 0x00007FFF */
12586 #define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
12587 
12588 /********************  Bits definition for RTC_ALRMBSSR register  *************/
12589 #define RTC_ALRMBSSR_MASKSS_Pos      (24U)
12590 #define RTC_ALRMBSSR_MASKSS_Msk      (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x0F000000 */
12591 #define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
12592 #define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x01000000 */
12593 #define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x02000000 */
12594 #define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x04000000 */
12595 #define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x08000000 */
12596 #define RTC_ALRMBSSR_SS_Pos          (0U)
12597 #define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)          /*!< 0x00007FFF */
12598 #define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
12599 
12600 /********************  Bits definition for RTC_BKP0R register  ****************/
12601 #define RTC_BKP0R_Pos                (0U)
12602 #define RTC_BKP0R_Msk                (0xFFFFFFFFUL << RTC_BKP0R_Pos)            /*!< 0xFFFFFFFF */
12603 #define RTC_BKP0R                    RTC_BKP0R_Msk
12604 
12605 /********************  Bits definition for RTC_BKP1R register  ****************/
12606 #define RTC_BKP1R_Pos                (0U)
12607 #define RTC_BKP1R_Msk                (0xFFFFFFFFUL << RTC_BKP1R_Pos)            /*!< 0xFFFFFFFF */
12608 #define RTC_BKP1R                    RTC_BKP1R_Msk
12609 
12610 /********************  Bits definition for RTC_BKP2R register  ****************/
12611 #define RTC_BKP2R_Pos                (0U)
12612 #define RTC_BKP2R_Msk                (0xFFFFFFFFUL << RTC_BKP2R_Pos)            /*!< 0xFFFFFFFF */
12613 #define RTC_BKP2R                    RTC_BKP2R_Msk
12614 
12615 /********************  Bits definition for RTC_BKP3R register  ****************/
12616 #define RTC_BKP3R_Pos                (0U)
12617 #define RTC_BKP3R_Msk                (0xFFFFFFFFUL << RTC_BKP3R_Pos)            /*!< 0xFFFFFFFF */
12618 #define RTC_BKP3R                    RTC_BKP3R_Msk
12619 
12620 /********************  Bits definition for RTC_BKP4R register  ****************/
12621 #define RTC_BKP4R_Pos                (0U)
12622 #define RTC_BKP4R_Msk                (0xFFFFFFFFUL << RTC_BKP4R_Pos)            /*!< 0xFFFFFFFF */
12623 #define RTC_BKP4R                    RTC_BKP4R_Msk
12624 
12625 /******************** Number of backup registers ******************************/
12626 #define RTC_BKP_NUMBER                       5
12627 
12628 /******************************************************************************/
12629 /*                                                                            */
12630 /*                        Serial Peripheral Interface (SPI)                   */
12631 /*                                                                            */
12632 /******************************************************************************/
12633 
12634 /*
12635  * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
12636  */
12637 /* Note: No specific macro feature on this device */
12638 
12639 /*******************  Bit definition for SPI_CR1 register  ********************/
12640 #define SPI_CR1_CPHA_Pos            (0U)
12641 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
12642 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
12643 #define SPI_CR1_CPOL_Pos            (1U)
12644 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
12645 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
12646 #define SPI_CR1_MSTR_Pos            (2U)
12647 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
12648 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
12649 #define SPI_CR1_BR_Pos              (3U)
12650 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
12651 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
12652 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
12653 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
12654 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
12655 #define SPI_CR1_SPE_Pos             (6U)
12656 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
12657 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
12658 #define SPI_CR1_LSBFIRST_Pos        (7U)
12659 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
12660 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
12661 #define SPI_CR1_SSI_Pos             (8U)
12662 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
12663 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
12664 #define SPI_CR1_SSM_Pos             (9U)
12665 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
12666 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
12667 #define SPI_CR1_RXONLY_Pos          (10U)
12668 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
12669 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
12670 #define SPI_CR1_CRCL_Pos            (11U)
12671 #define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                 /*!< 0x00000800 */
12672 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
12673 #define SPI_CR1_CRCNEXT_Pos         (12U)
12674 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
12675 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
12676 #define SPI_CR1_CRCEN_Pos           (13U)
12677 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
12678 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
12679 #define SPI_CR1_BIDIOE_Pos          (14U)
12680 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
12681 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
12682 #define SPI_CR1_BIDIMODE_Pos        (15U)
12683 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
12684 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
12685 
12686 /*******************  Bit definition for SPI_CR2 register  ********************/
12687 #define SPI_CR2_RXDMAEN_Pos         (0U)
12688 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
12689 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
12690 #define SPI_CR2_TXDMAEN_Pos         (1U)
12691 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
12692 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
12693 #define SPI_CR2_SSOE_Pos            (2U)
12694 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
12695 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
12696 #define SPI_CR2_NSSP_Pos            (3U)
12697 #define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                 /*!< 0x00000008 */
12698 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
12699 #define SPI_CR2_FRF_Pos             (4U)
12700 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
12701 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
12702 #define SPI_CR2_ERRIE_Pos           (5U)
12703 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
12704 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
12705 #define SPI_CR2_RXNEIE_Pos          (6U)
12706 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
12707 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
12708 #define SPI_CR2_TXEIE_Pos           (7U)
12709 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
12710 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
12711 #define SPI_CR2_DS_Pos              (8U)
12712 #define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                   /*!< 0x00000F00 */
12713 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
12714 #define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                   /*!< 0x00000100 */
12715 #define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                   /*!< 0x00000200 */
12716 #define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                   /*!< 0x00000400 */
12717 #define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                   /*!< 0x00000800 */
12718 #define SPI_CR2_FRXTH_Pos           (12U)
12719 #define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)                /*!< 0x00001000 */
12720 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
12721 #define SPI_CR2_LDMARX_Pos          (13U)
12722 #define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)               /*!< 0x00002000 */
12723 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
12724 #define SPI_CR2_LDMATX_Pos          (14U)
12725 #define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)               /*!< 0x00004000 */
12726 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
12727 
12728 /********************  Bit definition for SPI_SR register  ********************/
12729 #define SPI_SR_RXNE_Pos             (0U)
12730 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
12731 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
12732 #define SPI_SR_TXE_Pos              (1U)
12733 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
12734 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
12735 #define SPI_SR_CRCERR_Pos           (4U)
12736 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
12737 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
12738 #define SPI_SR_MODF_Pos             (5U)
12739 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
12740 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
12741 #define SPI_SR_OVR_Pos              (6U)
12742 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
12743 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
12744 #define SPI_SR_BSY_Pos              (7U)
12745 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
12746 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
12747 #define SPI_SR_FRE_Pos              (8U)
12748 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
12749 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
12750 #define SPI_SR_FRLVL_Pos            (9U)
12751 #define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                 /*!< 0x00000600 */
12752 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
12753 #define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                 /*!< 0x00000200 */
12754 #define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                 /*!< 0x00000400 */
12755 #define SPI_SR_FTLVL_Pos            (11U)
12756 #define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                 /*!< 0x00001800 */
12757 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
12758 #define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                 /*!< 0x00000800 */
12759 #define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                 /*!< 0x00001000 */
12760 
12761 /********************  Bit definition for SPI_DR register  ********************/
12762 #define SPI_DR_DR_Pos               (0U)
12763 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
12764 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
12765 
12766 /*******************  Bit definition for SPI_CRCPR register  ******************/
12767 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
12768 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
12769 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
12770 
12771 /******************  Bit definition for SPI_RXCRCR register  ******************/
12772 #define SPI_RXCRCR_RXCRC_Pos        (0U)
12773 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
12774 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
12775 
12776 /******************  Bit definition for SPI_TXCRCR register  ******************/
12777 #define SPI_TXCRCR_TXCRC_Pos        (0U)
12778 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
12779 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
12780 
12781 /******************************************************************************/
12782 /*                                                                            */
12783 /*                        System Configuration(SYSCFG)                        */
12784 /*                                                                            */
12785 /******************************************************************************/
12786 /*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
12787 #define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)
12788 #define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
12789 #define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
12790 #define SYSCFG_CFGR1_MEM_MODE_0                  (0x00000001U)                 /*!< Bit 0 */
12791 #define SYSCFG_CFGR1_MEM_MODE_1                  (0x00000002U)                 /*!< Bit 1 */
12792 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos           (6U)
12793 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk           (0x1UL << SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos) /*!< 0x00000040 */
12794 #define SYSCFG_CFGR1_TIM1_ITR3_RMP               SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk /*!< Timer 1 ITR3 selection */
12795 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos          (7U)
12796 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk          (0x1UL << SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos) /*!< 0x00000080 */
12797 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP              SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk /*!< DAC1 Trigger1 remap */
12798 #define SYSCFG_CFGR1_DMA_RMP_Pos                 (11U)
12799 #define SYSCFG_CFGR1_DMA_RMP_Msk                 (0x1FUL << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x0000F800 */
12800 #define SYSCFG_CFGR1_DMA_RMP                     SYSCFG_CFGR1_DMA_RMP_Msk      /*!< DMA remap mask */
12801 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos           (11U)
12802 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk           (0x1UL << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */
12803 #define SYSCFG_CFGR1_TIM16_DMA_RMP               SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */
12804 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos           (12U)
12805 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk           (0x1UL << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */
12806 #define SYSCFG_CFGR1_TIM17_DMA_RMP               SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */
12807 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos     (13U)
12808 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk     (0x1UL << SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos) /*!< 0x00002000 */
12809 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP         SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk /*!< Timer 6 / DAC1 Ch1 DMA remap */
12810 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos     (14U)
12811 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk     (0x1UL << SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos) /*!< 0x00004000 */
12812 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP         SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk /*!< Timer 7 / DAC1 Ch2 DMA remap */
12813 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Pos         (15U)
12814 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Msk         (0x1UL << SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Pos) /*!< 0x00008000 */
12815 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP             SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Msk /*!< DAC2 CH1 DMA remap */
12816 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos             (16U)
12817 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
12818 #define SYSCFG_CFGR1_I2C_PB6_FMP                 SYSCFG_CFGR1_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
12819 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos             (17U)
12820 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
12821 #define SYSCFG_CFGR1_I2C_PB7_FMP                 SYSCFG_CFGR1_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
12822 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos             (18U)
12823 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
12824 #define SYSCFG_CFGR1_I2C_PB8_FMP                 SYSCFG_CFGR1_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
12825 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos             (19U)
12826 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
12827 #define SYSCFG_CFGR1_I2C_PB9_FMP                 SYSCFG_CFGR1_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
12828 #define SYSCFG_CFGR1_I2C1_FMP_Pos                (20U)
12829 #define SYSCFG_CFGR1_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
12830 #define SYSCFG_CFGR1_I2C1_FMP                    SYSCFG_CFGR1_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
12831 #define SYSCFG_CFGR1_ENCODER_MODE_Pos            (22U)
12832 #define SYSCFG_CFGR1_ENCODER_MODE_Msk            (0x3UL << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00C00000 */
12833 #define SYSCFG_CFGR1_ENCODER_MODE                SYSCFG_CFGR1_ENCODER_MODE_Msk /*!< Encoder Mode */
12834 #define SYSCFG_CFGR1_ENCODER_MODE_0              (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00400000 */
12835 #define SYSCFG_CFGR1_ENCODER_MODE_1              (0x2UL << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00800000 */
12836 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos       (22U)
12837 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk       (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos) /*!< 0x00400000 */
12838 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2           SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
12839 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos       (23U)
12840 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk       (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos) /*!< 0x00800000 */
12841 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3           SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
12842 #define SYSCFG_CFGR1_FPU_IE_Pos                  (26U)
12843 #define SYSCFG_CFGR1_FPU_IE_Msk                  (0x3FUL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0xFC000000 */
12844 #define SYSCFG_CFGR1_FPU_IE                      SYSCFG_CFGR1_FPU_IE_Msk       /*!< Floating Point Unit Interrupt Enable */
12845 #define SYSCFG_CFGR1_FPU_IE_0                    (0x01UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x04000000 */
12846 #define SYSCFG_CFGR1_FPU_IE_1                    (0x02UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x08000000 */
12847 #define SYSCFG_CFGR1_FPU_IE_2                    (0x04UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x10000000 */
12848 #define SYSCFG_CFGR1_FPU_IE_3                    (0x08UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x20000000 */
12849 #define SYSCFG_CFGR1_FPU_IE_4                    (0x10UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x40000000 */
12850 #define SYSCFG_CFGR1_FPU_IE_5                    (0x20UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x80000000 */
12851 
12852 /*****************  Bit definition for SYSCFG_RCR register  *******************/
12853 #define SYSCFG_RCR_PAGE0_Pos                     (0U)
12854 #define SYSCFG_RCR_PAGE0_Msk                     (0x1UL << SYSCFG_RCR_PAGE0_Pos) /*!< 0x00000001 */
12855 #define SYSCFG_RCR_PAGE0                         SYSCFG_RCR_PAGE0_Msk          /*!< ICODE SRAM Write protection page 0 */
12856 #define SYSCFG_RCR_PAGE1_Pos                     (1U)
12857 #define SYSCFG_RCR_PAGE1_Msk                     (0x1UL << SYSCFG_RCR_PAGE1_Pos) /*!< 0x00000002 */
12858 #define SYSCFG_RCR_PAGE1                         SYSCFG_RCR_PAGE1_Msk          /*!< ICODE SRAM Write protection page 1 */
12859 #define SYSCFG_RCR_PAGE2_Pos                     (2U)
12860 #define SYSCFG_RCR_PAGE2_Msk                     (0x1UL << SYSCFG_RCR_PAGE2_Pos) /*!< 0x00000004 */
12861 #define SYSCFG_RCR_PAGE2                         SYSCFG_RCR_PAGE2_Msk          /*!< ICODE SRAM Write protection page 2 */
12862 #define SYSCFG_RCR_PAGE3_Pos                     (3U)
12863 #define SYSCFG_RCR_PAGE3_Msk                     (0x1UL << SYSCFG_RCR_PAGE3_Pos) /*!< 0x00000008 */
12864 #define SYSCFG_RCR_PAGE3                         SYSCFG_RCR_PAGE3_Msk          /*!< ICODE SRAM Write protection page 3 */
12865 
12866 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
12867 #define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)
12868 #define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
12869 #define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
12870 #define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)
12871 #define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
12872 #define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
12873 #define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)
12874 #define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
12875 #define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
12876 #define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)
12877 #define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
12878 #define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
12879 
12880 /*!<*
12881   * @brief  EXTI0 configuration
12882   */
12883 #define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
12884 #define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
12885 #define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
12886 #define SYSCFG_EXTICR1_EXTI0_PD                  (0x00000003U)                 /*!< PD[0] pin */
12887 #define SYSCFG_EXTICR1_EXTI0_PE                  (0x00000004U)                 /*!< PE[0] pin */
12888 #define SYSCFG_EXTICR1_EXTI0_PF                  (0x00000005U)                 /*!< PF[0] pin */
12889 
12890 /*!<*
12891   * @brief  EXTI1 configuration
12892   */
12893 #define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
12894 #define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
12895 #define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
12896 #define SYSCFG_EXTICR1_EXTI1_PD                  (0x00000030U)                 /*!< PD[1] pin */
12897 #define SYSCFG_EXTICR1_EXTI1_PE                  (0x00000040U)                 /*!< PE[1] pin */
12898 #define SYSCFG_EXTICR1_EXTI1_PF                  (0x00000050U)                 /*!< PF[1] pin */
12899 
12900 /*!<*
12901   * @brief  EXTI2 configuration
12902   */
12903 #define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
12904 #define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
12905 #define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
12906 #define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
12907 #define SYSCFG_EXTICR1_EXTI2_PE                  (0x00000400U)                 /*!< PE[2] pin */
12908 #define SYSCFG_EXTICR1_EXTI2_PF                  (0x00000500U)                 /*!< PF[2] pin */
12909 
12910 /*!<*
12911   * @brief  EXTI3 configuration
12912   */
12913 #define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
12914 #define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
12915 #define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
12916 #define SYSCFG_EXTICR1_EXTI3_PD                  (0x00003000U)                 /*!< PD[3] pin */
12917 #define SYSCFG_EXTICR1_EXTI3_PE                  (0x00004000U)                 /*!< PE[3] pin */
12918 
12919 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
12920 #define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)
12921 #define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
12922 #define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
12923 #define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)
12924 #define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
12925 #define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
12926 #define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)
12927 #define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
12928 #define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
12929 #define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)
12930 #define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
12931 #define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
12932 
12933 /*!<*
12934   * @brief  EXTI4 configuration
12935   */
12936 #define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
12937 #define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
12938 #define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
12939 #define SYSCFG_EXTICR2_EXTI4_PD                  (0x00000003U)                 /*!< PD[4] pin */
12940 #define SYSCFG_EXTICR2_EXTI4_PE                  (0x00000004U)                 /*!< PE[4] pin */
12941 #define SYSCFG_EXTICR2_EXTI4_PF                  (0x00000005U)                 /*!< PF[4] pin */
12942 
12943 /*!<*
12944   * @brief  EXTI5 configuration
12945   */
12946 #define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
12947 #define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
12948 #define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
12949 #define SYSCFG_EXTICR2_EXTI5_PD                  (0x00000030U)                 /*!< PD[5] pin */
12950 #define SYSCFG_EXTICR2_EXTI5_PE                  (0x00000040U)                 /*!< PE[5] pin */
12951 #define SYSCFG_EXTICR2_EXTI5_PF                  (0x00000050U)                 /*!< PF[5] pin */
12952 
12953 /*!<*
12954   * @brief  EXTI6 configuration
12955   */
12956 #define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
12957 #define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
12958 #define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
12959 #define SYSCFG_EXTICR2_EXTI6_PD                  (0x00000300U)                 /*!< PD[6] pin */
12960 #define SYSCFG_EXTICR2_EXTI6_PE                  (0x00000400U)                 /*!< PE[6] pin */
12961 #define SYSCFG_EXTICR2_EXTI6_PF                  (0x00000500U)                 /*!< PF[6] pin */
12962 
12963 /*!<*
12964   * @brief  EXTI7 configuration
12965   */
12966 #define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
12967 #define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
12968 #define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
12969 #define SYSCFG_EXTICR2_EXTI7_PD                  (0x00003000U)                 /*!< PD[7] pin */
12970 #define SYSCFG_EXTICR2_EXTI7_PE                  (0x00004000U)                 /*!< PE[7] pin */
12971 
12972 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
12973 #define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)
12974 #define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
12975 #define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
12976 #define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)
12977 #define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
12978 #define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
12979 #define SYSCFG_EXTICR3_EXTI10_Pos                (8U)
12980 #define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
12981 #define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
12982 #define SYSCFG_EXTICR3_EXTI11_Pos                (12U)
12983 #define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
12984 #define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
12985 
12986 /*!<*
12987   * @brief  EXTI8 configuration
12988   */
12989 #define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
12990 #define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
12991 #define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
12992 #define SYSCFG_EXTICR3_EXTI8_PD                  (0x00000003U)                 /*!< PD[8] pin */
12993 #define SYSCFG_EXTICR3_EXTI8_PE                  (0x00000004U)                 /*!< PE[8] pin */
12994 
12995 /*!<*
12996   * @brief  EXTI9 configuration
12997   */
12998 #define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
12999 #define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
13000 #define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
13001 #define SYSCFG_EXTICR3_EXTI9_PD                  (0x00000030U)                 /*!< PD[9] pin */
13002 #define SYSCFG_EXTICR3_EXTI9_PE                  (0x00000040U)                 /*!< PE[9] pin */
13003 #define SYSCFG_EXTICR3_EXTI9_PF                  (0x00000050U)                 /*!< PF[9] pin */
13004 
13005 /*!<*
13006   * @brief  EXTI10 configuration
13007   */
13008 #define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
13009 #define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
13010 #define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
13011 #define SYSCFG_EXTICR3_EXTI10_PD                 (0x00000300U)                 /*!< PD[10] pin */
13012 #define SYSCFG_EXTICR3_EXTI10_PE                 (0x00000400U)                 /*!< PE[10] pin */
13013 #define SYSCFG_EXTICR3_EXTI10_PF                 (0x00000500U)                 /*!< PF[10] pin */
13014 
13015 /*!<*
13016   * @brief  EXTI11 configuration
13017   */
13018 #define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
13019 #define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
13020 #define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
13021 #define SYSCFG_EXTICR3_EXTI11_PD                 (0x00003000U)                 /*!< PD[11] pin */
13022 #define SYSCFG_EXTICR3_EXTI11_PE                 (0x00004000U)                 /*!< PE[11] pin */
13023 
13024 /*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
13025 #define SYSCFG_EXTICR4_EXTI12_Pos                (0U)
13026 #define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
13027 #define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
13028 #define SYSCFG_EXTICR4_EXTI13_Pos                (4U)
13029 #define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
13030 #define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
13031 #define SYSCFG_EXTICR4_EXTI14_Pos                (8U)
13032 #define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
13033 #define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
13034 #define SYSCFG_EXTICR4_EXTI15_Pos                (12U)
13035 #define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
13036 #define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
13037 
13038 /*!<*
13039   * @brief  EXTI12 configuration
13040   */
13041 #define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
13042 #define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
13043 #define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
13044 #define SYSCFG_EXTICR4_EXTI12_PD                 (0x00000003U)                 /*!< PD[12] pin */
13045 #define SYSCFG_EXTICR4_EXTI12_PE                 (0x00000004U)                 /*!< PE[12] pin */
13046 
13047 /*!<*
13048   * @brief  EXTI13 configuration
13049   */
13050 #define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
13051 #define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
13052 #define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
13053 #define SYSCFG_EXTICR4_EXTI13_PD                 (0x00000030U)                 /*!< PD[13] pin */
13054 #define SYSCFG_EXTICR4_EXTI13_PE                 (0x00000040U)                 /*!< PE[13] pin */
13055 
13056 /*!<*
13057   * @brief  EXTI14 configuration
13058   */
13059 #define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
13060 #define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
13061 #define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
13062 #define SYSCFG_EXTICR4_EXTI14_PD                 (0x00000300U)                 /*!< PD[14] pin */
13063 #define SYSCFG_EXTICR4_EXTI14_PE                 (0x00000400U)                 /*!< PE[14] pin */
13064 
13065 /*!<*
13066   * @brief  EXTI15 configuration
13067   */
13068 #define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
13069 #define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
13070 #define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
13071 #define SYSCFG_EXTICR4_EXTI15_PD                 (0x00003000U)                 /*!< PD[15] pin */
13072 #define SYSCFG_EXTICR4_EXTI15_PE                 (0x00004000U)                 /*!< PE[15] pin */
13073 
13074 /*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
13075 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos             (0U)
13076 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk             (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
13077 #define SYSCFG_CFGR2_LOCKUP_LOCK                 SYSCFG_CFGR2_LOCKUP_LOCK_Msk  /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
13078 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos        (1U)
13079 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk        (0x1UL << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
13080 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK            SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
13081 #define SYSCFG_CFGR2_PVD_LOCK_Pos                (2U)
13082 #define SYSCFG_CFGR2_PVD_LOCK_Msk                (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
13083 #define SYSCFG_CFGR2_PVD_LOCK                    SYSCFG_CFGR2_PVD_LOCK_Msk     /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
13084 #define SYSCFG_CFGR2_BYP_ADDR_PAR_Pos            (4U)
13085 #define SYSCFG_CFGR2_BYP_ADDR_PAR_Msk            (0x1UL << SYSCFG_CFGR2_BYP_ADDR_PAR_Pos) /*!< 0x00000010 */
13086 #define SYSCFG_CFGR2_BYP_ADDR_PAR                SYSCFG_CFGR2_BYP_ADDR_PAR_Msk /*!< Disables the adddress parity check on RAM */
13087 #define SYSCFG_CFGR2_SRAM_PE_Pos                 (8U)
13088 #define SYSCFG_CFGR2_SRAM_PE_Msk                 (0x1UL << SYSCFG_CFGR2_SRAM_PE_Pos) /*!< 0x00000100 */
13089 #define SYSCFG_CFGR2_SRAM_PE                     SYSCFG_CFGR2_SRAM_PE_Msk      /*!< SRAM Parity error flag */
13090 
13091 /*****************  Bit definition for SYSCFG_CFGR3 register  *****************/
13092 #define SYSCFG_CFGR3_DMA_RMP_Pos                 (0U)
13093 #define SYSCFG_CFGR3_DMA_RMP_Msk                 (0x3FFUL << SYSCFG_CFGR3_DMA_RMP_Pos) /*!< 0x000003FF */
13094 #define SYSCFG_CFGR3_DMA_RMP                     SYSCFG_CFGR3_DMA_RMP_Msk      /*!< DMA remap mask */
13095 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos         (0U)
13096 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Msk         (0x3UL << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos) /*!< 0x00000003 */
13097 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP             SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Msk /*!< SPI1 RX DMA remap */
13098 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0           (0x1UL << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos) /*!< 0x00000001 */
13099 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1           (0x2UL << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos) /*!< 0x00000002 */
13100 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos         (2U)
13101 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Msk         (0x3UL << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos) /*!< 0x0000000C */
13102 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP             SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Msk /*!< SPI1 TX DMA remap */
13103 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0           (0x1UL << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos) /*!< 0x00000004 */
13104 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1           (0x2UL << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos) /*!< 0x00000008 */
13105 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos         (4U)
13106 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Msk         (0x3UL << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos) /*!< 0x00000030 */
13107 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP             SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Msk /*!< I2C1 RX DMA remap */
13108 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0           (0x1UL << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos) /*!< 0x00000010 */
13109 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1           (0x2UL << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos) /*!< 0x00000020 */
13110 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos         (6U)
13111 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Msk         (0x3UL << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos) /*!< 0x000000C0 */
13112 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP             SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Msk /*!< I2C1 RX DMA remap */
13113 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0           (0x1UL << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos) /*!< 0x00000040 */
13114 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1           (0x2UL << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos) /*!< 0x00000080 */
13115 #define SYSCFG_CFGR3_ADC2_DMA_RMP_Pos            (8U)
13116 #define SYSCFG_CFGR3_ADC2_DMA_RMP_Msk            (0x3UL << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000300 */
13117 #define SYSCFG_CFGR3_ADC2_DMA_RMP                SYSCFG_CFGR3_ADC2_DMA_RMP_Msk /*!< ADC2 DMA remap */
13118 #define SYSCFG_CFGR3_ADC2_DMA_RMP_0              (0x1UL << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000100 */
13119 #define SYSCFG_CFGR3_ADC2_DMA_RMP_1              (0x2UL << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000200 */
13120 #define SYSCFG_CFGR3_TRIGGER_RMP_Pos             (16U)
13121 #define SYSCFG_CFGR3_TRIGGER_RMP_Msk             (0x3UL << SYSCFG_CFGR3_TRIGGER_RMP_Pos) /*!< 0x00030000 */
13122 #define SYSCFG_CFGR3_TRIGGER_RMP                 SYSCFG_CFGR3_TRIGGER_RMP_Msk  /*!< Trigger remap mask */
13123 #define SYSCFG_CFGR3_DAC1_TRG3_RMP_Pos           (16U)
13124 #define SYSCFG_CFGR3_DAC1_TRG3_RMP_Msk           (0x1UL << SYSCFG_CFGR3_DAC1_TRG3_RMP_Pos) /*!< 0x00010000 */
13125 #define SYSCFG_CFGR3_DAC1_TRG3_RMP               SYSCFG_CFGR3_DAC1_TRG3_RMP_Msk /*!< DAC1 TRG3 remap */
13126 #define SYSCFG_CFGR3_DAC1_TRG5_RMP_Pos           (17U)
13127 #define SYSCFG_CFGR3_DAC1_TRG5_RMP_Msk           (0x1UL << SYSCFG_CFGR3_DAC1_TRG5_RMP_Pos) /*!< 0x00020000 */
13128 #define SYSCFG_CFGR3_DAC1_TRG5_RMP               SYSCFG_CFGR3_DAC1_TRG5_RMP_Msk /*!< DAC1 TRG5 remap */
13129 
13130 /******************************************************************************/
13131 /*                                                                            */
13132 /*                                    TIM                                     */
13133 /*                                                                            */
13134 /******************************************************************************/
13135 /*******************  Bit definition for TIM_CR1 register  ********************/
13136 #define TIM_CR1_CEN_Pos           (0U)
13137 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
13138 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
13139 #define TIM_CR1_UDIS_Pos          (1U)
13140 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
13141 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
13142 #define TIM_CR1_URS_Pos           (2U)
13143 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
13144 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
13145 #define TIM_CR1_OPM_Pos           (3U)
13146 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
13147 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
13148 #define TIM_CR1_DIR_Pos           (4U)
13149 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
13150 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
13151 
13152 #define TIM_CR1_CMS_Pos           (5U)
13153 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
13154 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
13155 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
13156 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
13157 
13158 #define TIM_CR1_ARPE_Pos          (7U)
13159 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
13160 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
13161 
13162 #define TIM_CR1_CKD_Pos           (8U)
13163 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
13164 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
13165 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
13166 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
13167 
13168 #define TIM_CR1_UIFREMAP_Pos      (11U)
13169 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)               /*!< 0x00000800 */
13170 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
13171 
13172 /*******************  Bit definition for TIM_CR2 register  ********************/
13173 #define TIM_CR2_CCPC_Pos          (0U)
13174 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
13175 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
13176 #define TIM_CR2_CCUS_Pos          (2U)
13177 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
13178 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
13179 #define TIM_CR2_CCDS_Pos          (3U)
13180 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
13181 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
13182 
13183 #define TIM_CR2_MMS_Pos           (4U)
13184 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
13185 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
13186 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
13187 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
13188 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
13189 
13190 #define TIM_CR2_TI1S_Pos          (7U)
13191 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
13192 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
13193 #define TIM_CR2_OIS1_Pos          (8U)
13194 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
13195 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
13196 #define TIM_CR2_OIS1N_Pos         (9U)
13197 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
13198 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
13199 #define TIM_CR2_OIS2_Pos          (10U)
13200 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
13201 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
13202 #define TIM_CR2_OIS2N_Pos         (11U)
13203 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
13204 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
13205 #define TIM_CR2_OIS3_Pos          (12U)
13206 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
13207 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
13208 #define TIM_CR2_OIS3N_Pos         (13U)
13209 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
13210 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
13211 #define TIM_CR2_OIS4_Pos          (14U)
13212 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
13213 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
13214 
13215 #define TIM_CR2_OIS5_Pos          (16U)
13216 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                   /*!< 0x00010000 */
13217 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
13218 #define TIM_CR2_OIS6_Pos          (18U)
13219 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                   /*!< 0x00040000 */
13220 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
13221 
13222 #define TIM_CR2_MMS2_Pos          (20U)
13223 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                   /*!< 0x00F00000 */
13224 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
13225 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
13226 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
13227 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
13228 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
13229 
13230 /*******************  Bit definition for TIM_SMCR register  *******************/
13231 #define TIM_SMCR_SMS_Pos          (0U)
13232 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010007 */
13233 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
13234 #define TIM_SMCR_SMS_0            (0x00000001U)                                /*!<Bit 0 */
13235 #define TIM_SMCR_SMS_1            (0x00000002U)                                /*!<Bit 1 */
13236 #define TIM_SMCR_SMS_2            (0x00000004U)                                /*!<Bit 2 */
13237 #define TIM_SMCR_SMS_3            (0x00010000U)                                /*!<Bit 3 */
13238 
13239 #define TIM_SMCR_OCCS_Pos         (3U)
13240 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
13241 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
13242 
13243 #define TIM_SMCR_TS_Pos           (4U)
13244 #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
13245 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
13246 #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
13247 #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
13248 #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
13249 
13250 #define TIM_SMCR_MSM_Pos          (7U)
13251 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
13252 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
13253 
13254 #define TIM_SMCR_ETF_Pos          (8U)
13255 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
13256 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
13257 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
13258 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
13259 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
13260 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
13261 
13262 #define TIM_SMCR_ETPS_Pos         (12U)
13263 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
13264 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
13265 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
13266 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
13267 
13268 #define TIM_SMCR_ECE_Pos          (14U)
13269 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
13270 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
13271 #define TIM_SMCR_ETP_Pos          (15U)
13272 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
13273 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
13274 
13275 /*******************  Bit definition for TIM_DIER register  *******************/
13276 #define TIM_DIER_UIE_Pos          (0U)
13277 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
13278 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
13279 #define TIM_DIER_CC1IE_Pos        (1U)
13280 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
13281 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
13282 #define TIM_DIER_CC2IE_Pos        (2U)
13283 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
13284 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
13285 #define TIM_DIER_CC3IE_Pos        (3U)
13286 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
13287 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
13288 #define TIM_DIER_CC4IE_Pos        (4U)
13289 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
13290 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
13291 #define TIM_DIER_COMIE_Pos        (5U)
13292 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
13293 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
13294 #define TIM_DIER_TIE_Pos          (6U)
13295 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
13296 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
13297 #define TIM_DIER_BIE_Pos          (7U)
13298 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
13299 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
13300 #define TIM_DIER_UDE_Pos          (8U)
13301 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
13302 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
13303 #define TIM_DIER_CC1DE_Pos        (9U)
13304 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
13305 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
13306 #define TIM_DIER_CC2DE_Pos        (10U)
13307 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
13308 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
13309 #define TIM_DIER_CC3DE_Pos        (11U)
13310 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
13311 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
13312 #define TIM_DIER_CC4DE_Pos        (12U)
13313 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
13314 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
13315 #define TIM_DIER_COMDE_Pos        (13U)
13316 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
13317 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
13318 #define TIM_DIER_TDE_Pos          (14U)
13319 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
13320 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
13321 
13322 /********************  Bit definition for TIM_SR register  ********************/
13323 #define TIM_SR_UIF_Pos            (0U)
13324 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
13325 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
13326 #define TIM_SR_CC1IF_Pos          (1U)
13327 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
13328 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
13329 #define TIM_SR_CC2IF_Pos          (2U)
13330 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
13331 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
13332 #define TIM_SR_CC3IF_Pos          (3U)
13333 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
13334 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
13335 #define TIM_SR_CC4IF_Pos          (4U)
13336 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
13337 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
13338 #define TIM_SR_COMIF_Pos          (5U)
13339 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
13340 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
13341 #define TIM_SR_TIF_Pos            (6U)
13342 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
13343 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
13344 #define TIM_SR_BIF_Pos            (7U)
13345 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
13346 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
13347 #define TIM_SR_B2IF_Pos           (8U)
13348 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                    /*!< 0x00000100 */
13349 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */
13350 #define TIM_SR_CC1OF_Pos          (9U)
13351 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
13352 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
13353 #define TIM_SR_CC2OF_Pos          (10U)
13354 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
13355 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
13356 #define TIM_SR_CC3OF_Pos          (11U)
13357 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
13358 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
13359 #define TIM_SR_CC4OF_Pos          (12U)
13360 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
13361 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
13362 #define TIM_SR_CC5IF_Pos          (16U)
13363 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                   /*!< 0x00010000 */
13364 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
13365 #define TIM_SR_CC6IF_Pos          (17U)
13366 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                   /*!< 0x00020000 */
13367 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
13368 
13369 /*******************  Bit definition for TIM_EGR register  ********************/
13370 #define TIM_EGR_UG_Pos            (0U)
13371 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
13372 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
13373 #define TIM_EGR_CC1G_Pos          (1U)
13374 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
13375 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
13376 #define TIM_EGR_CC2G_Pos          (2U)
13377 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
13378 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
13379 #define TIM_EGR_CC3G_Pos          (3U)
13380 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
13381 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
13382 #define TIM_EGR_CC4G_Pos          (4U)
13383 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
13384 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
13385 #define TIM_EGR_COMG_Pos          (5U)
13386 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
13387 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
13388 #define TIM_EGR_TG_Pos            (6U)
13389 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
13390 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
13391 #define TIM_EGR_BG_Pos            (7U)
13392 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
13393 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
13394 #define TIM_EGR_B2G_Pos           (8U)
13395 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                    /*!< 0x00000100 */
13396 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */
13397 
13398 /******************  Bit definition for TIM_CCMR1 register  *******************/
13399 #define TIM_CCMR1_CC1S_Pos        (0U)
13400 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
13401 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
13402 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
13403 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
13404 
13405 #define TIM_CCMR1_OC1FE_Pos       (2U)
13406 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
13407 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
13408 #define TIM_CCMR1_OC1PE_Pos       (3U)
13409 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
13410 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
13411 
13412 #define TIM_CCMR1_OC1M_Pos        (4U)
13413 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010070 */
13414 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
13415 #define TIM_CCMR1_OC1M_0          (0x00000010U)                                /*!<Bit 0 */
13416 #define TIM_CCMR1_OC1M_1          (0x00000020U)                                /*!<Bit 1 */
13417 #define TIM_CCMR1_OC1M_2          (0x00000040U)                                /*!<Bit 2 */
13418 #define TIM_CCMR1_OC1M_3          (0x00010000U)                                /*!<Bit 3 */
13419 
13420 #define TIM_CCMR1_OC1CE_Pos       (7U)
13421 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
13422 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
13423 
13424 #define TIM_CCMR1_CC2S_Pos        (8U)
13425 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
13426 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
13427 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
13428 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
13429 
13430 #define TIM_CCMR1_OC2FE_Pos       (10U)
13431 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
13432 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
13433 #define TIM_CCMR1_OC2PE_Pos       (11U)
13434 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
13435 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
13436 
13437 #define TIM_CCMR1_OC2M_Pos        (12U)
13438 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01007000 */
13439 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
13440 #define TIM_CCMR1_OC2M_0          (0x00001000U)                                /*!<Bit 0 */
13441 #define TIM_CCMR1_OC2M_1          (0x00002000U)                                /*!<Bit 1 */
13442 #define TIM_CCMR1_OC2M_2          (0x00004000U)                                /*!<Bit 2 */
13443 #define TIM_CCMR1_OC2M_3          (0x01000000U)                                /*!<Bit 3 */
13444 
13445 #define TIM_CCMR1_OC2CE_Pos       (15U)
13446 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
13447 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
13448 
13449 /*----------------------------------------------------------------------------*/
13450 
13451 #define TIM_CCMR1_IC1PSC_Pos      (2U)
13452 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
13453 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
13454 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
13455 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
13456 
13457 #define TIM_CCMR1_IC1F_Pos        (4U)
13458 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
13459 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
13460 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
13461 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
13462 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
13463 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
13464 
13465 #define TIM_CCMR1_IC2PSC_Pos      (10U)
13466 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
13467 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
13468 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
13469 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
13470 
13471 #define TIM_CCMR1_IC2F_Pos        (12U)
13472 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
13473 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
13474 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
13475 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
13476 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
13477 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
13478 
13479 /******************  Bit definition for TIM_CCMR2 register  *******************/
13480 #define TIM_CCMR2_CC3S_Pos        (0U)
13481 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
13482 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
13483 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
13484 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
13485 
13486 #define TIM_CCMR2_OC3FE_Pos       (2U)
13487 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
13488 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
13489 #define TIM_CCMR2_OC3PE_Pos       (3U)
13490 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
13491 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
13492 
13493 #define TIM_CCMR2_OC3M_Pos        (4U)
13494 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010070 */
13495 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
13496 #define TIM_CCMR2_OC3M_0          (0x00000010U)                                /*!<Bit 0 */
13497 #define TIM_CCMR2_OC3M_1          (0x00000020U)                                /*!<Bit 1 */
13498 #define TIM_CCMR2_OC3M_2          (0x00000040U)                                /*!<Bit 2 */
13499 #define TIM_CCMR2_OC3M_3          (0x00010000U)                                /*!<Bit 3 */
13500 
13501 #define TIM_CCMR2_OC3CE_Pos       (7U)
13502 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
13503 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
13504 
13505 #define TIM_CCMR2_CC4S_Pos        (8U)
13506 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
13507 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
13508 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
13509 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
13510 
13511 #define TIM_CCMR2_OC4FE_Pos       (10U)
13512 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
13513 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
13514 #define TIM_CCMR2_OC4PE_Pos       (11U)
13515 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
13516 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
13517 
13518 #define TIM_CCMR2_OC4M_Pos        (12U)
13519 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01007000 */
13520 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
13521 #define TIM_CCMR2_OC4M_0          (0x00001000U)                                /*!<Bit 0 */
13522 #define TIM_CCMR2_OC4M_1          (0x00002000U)                                /*!<Bit 1 */
13523 #define TIM_CCMR2_OC4M_2          (0x00004000U)                                /*!<Bit 2 */
13524 #define TIM_CCMR2_OC4M_3          (0x01000000U)                                /*!<Bit 3 */
13525 
13526 #define TIM_CCMR2_OC4CE_Pos       (15U)
13527 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
13528 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
13529 
13530 /*----------------------------------------------------------------------------*/
13531 
13532 #define TIM_CCMR2_IC3PSC_Pos      (2U)
13533 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
13534 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
13535 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
13536 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
13537 
13538 #define TIM_CCMR2_IC3F_Pos        (4U)
13539 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
13540 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
13541 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
13542 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
13543 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
13544 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
13545 
13546 #define TIM_CCMR2_IC4PSC_Pos      (10U)
13547 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
13548 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
13549 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
13550 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
13551 
13552 #define TIM_CCMR2_IC4F_Pos        (12U)
13553 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
13554 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
13555 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
13556 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
13557 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
13558 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
13559 
13560 /*******************  Bit definition for TIM_CCER register  *******************/
13561 #define TIM_CCER_CC1E_Pos         (0U)
13562 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
13563 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
13564 #define TIM_CCER_CC1P_Pos         (1U)
13565 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
13566 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
13567 #define TIM_CCER_CC1NE_Pos        (2U)
13568 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
13569 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
13570 #define TIM_CCER_CC1NP_Pos        (3U)
13571 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
13572 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
13573 #define TIM_CCER_CC2E_Pos         (4U)
13574 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
13575 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
13576 #define TIM_CCER_CC2P_Pos         (5U)
13577 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
13578 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
13579 #define TIM_CCER_CC2NE_Pos        (6U)
13580 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
13581 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
13582 #define TIM_CCER_CC2NP_Pos        (7U)
13583 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
13584 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
13585 #define TIM_CCER_CC3E_Pos         (8U)
13586 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
13587 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
13588 #define TIM_CCER_CC3P_Pos         (9U)
13589 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
13590 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
13591 #define TIM_CCER_CC3NE_Pos        (10U)
13592 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
13593 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
13594 #define TIM_CCER_CC3NP_Pos        (11U)
13595 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
13596 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
13597 #define TIM_CCER_CC4E_Pos         (12U)
13598 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
13599 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
13600 #define TIM_CCER_CC4P_Pos         (13U)
13601 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
13602 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
13603 #define TIM_CCER_CC4NP_Pos        (15U)
13604 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
13605 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
13606 #define TIM_CCER_CC5E_Pos         (16U)
13607 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                  /*!< 0x00010000 */
13608 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
13609 #define TIM_CCER_CC5P_Pos         (17U)
13610 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                  /*!< 0x00020000 */
13611 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
13612 #define TIM_CCER_CC6E_Pos         (20U)
13613 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                  /*!< 0x00100000 */
13614 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
13615 #define TIM_CCER_CC6P_Pos         (21U)
13616 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                  /*!< 0x00200000 */
13617 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
13618 
13619 /*******************  Bit definition for TIM_CNT register  ********************/
13620 #define TIM_CNT_CNT_Pos           (0U)
13621 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
13622 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
13623 #define TIM_CNT_UIFCPY_Pos        (31U)
13624 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                 /*!< 0x80000000 */
13625 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */
13626 
13627 /*******************  Bit definition for TIM_PSC register  ********************/
13628 #define TIM_PSC_PSC_Pos           (0U)
13629 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
13630 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
13631 
13632 /*******************  Bit definition for TIM_ARR register  ********************/
13633 #define TIM_ARR_ARR_Pos           (0U)
13634 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
13635 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
13636 
13637 /*******************  Bit definition for TIM_RCR register  ********************/
13638 #define TIM_RCR_REP_Pos           (0U)
13639 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                 /*!< 0x0000FFFF */
13640 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
13641 
13642 /*******************  Bit definition for TIM_CCR1 register  *******************/
13643 #define TIM_CCR1_CCR1_Pos         (0U)
13644 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
13645 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
13646 
13647 /*******************  Bit definition for TIM_CCR2 register  *******************/
13648 #define TIM_CCR2_CCR2_Pos         (0U)
13649 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
13650 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
13651 
13652 /*******************  Bit definition for TIM_CCR3 register  *******************/
13653 #define TIM_CCR3_CCR3_Pos         (0U)
13654 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
13655 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
13656 
13657 /*******************  Bit definition for TIM_CCR4 register  *******************/
13658 #define TIM_CCR4_CCR4_Pos         (0U)
13659 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
13660 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
13661 
13662 /*******************  Bit definition for TIM_CCR5 register  *******************/
13663 #define TIM_CCR5_CCR5_Pos         (0U)
13664 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)           /*!< 0xFFFFFFFF */
13665 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
13666 #define TIM_CCR5_GC5C1_Pos        (29U)
13667 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                 /*!< 0x20000000 */
13668 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
13669 #define TIM_CCR5_GC5C2_Pos        (30U)
13670 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                 /*!< 0x40000000 */
13671 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
13672 #define TIM_CCR5_GC5C3_Pos        (31U)
13673 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                 /*!< 0x80000000 */
13674 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
13675 
13676 /*******************  Bit definition for TIM_CCR6 register  *******************/
13677 #define TIM_CCR6_CCR6_Pos         (0U)
13678 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)               /*!< 0x0000FFFF */
13679 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
13680 
13681 /*******************  Bit definition for TIM_BDTR register  *******************/
13682 #define TIM_BDTR_DTG_Pos          (0U)
13683 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
13684 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
13685 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
13686 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
13687 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
13688 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
13689 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
13690 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
13691 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
13692 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
13693 
13694 #define TIM_BDTR_LOCK_Pos         (8U)
13695 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
13696 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
13697 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
13698 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
13699 
13700 #define TIM_BDTR_OSSI_Pos         (10U)
13701 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
13702 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
13703 #define TIM_BDTR_OSSR_Pos         (11U)
13704 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
13705 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
13706 #define TIM_BDTR_BKE_Pos          (12U)
13707 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
13708 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */
13709 #define TIM_BDTR_BKP_Pos          (13U)
13710 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
13711 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */
13712 #define TIM_BDTR_AOE_Pos          (14U)
13713 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
13714 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
13715 #define TIM_BDTR_MOE_Pos          (15U)
13716 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
13717 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
13718 
13719 #define TIM_BDTR_BKF_Pos          (16U)
13720 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                   /*!< 0x000F0000 */
13721 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */
13722 #define TIM_BDTR_BK2F_Pos         (20U)
13723 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                  /*!< 0x00F00000 */
13724 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */
13725 
13726 #define TIM_BDTR_BK2E_Pos         (24U)
13727 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                  /*!< 0x01000000 */
13728 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */
13729 #define TIM_BDTR_BK2P_Pos         (25U)
13730 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                  /*!< 0x02000000 */
13731 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
13732 
13733 /*******************  Bit definition for TIM_DCR register  ********************/
13734 #define TIM_DCR_DBA_Pos           (0U)
13735 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
13736 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
13737 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
13738 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
13739 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
13740 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
13741 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
13742 
13743 #define TIM_DCR_DBL_Pos           (8U)
13744 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
13745 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
13746 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
13747 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
13748 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
13749 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
13750 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
13751 
13752 /*******************  Bit definition for TIM_DMAR register  *******************/
13753 #define TIM_DMAR_DMAB_Pos         (0U)
13754 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
13755 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
13756 
13757 /*******************  Bit definition for TIM16_OR register  *********************/
13758 #define TIM16_OR_TI1_RMP_Pos      (0U)
13759 #define TIM16_OR_TI1_RMP_Msk      (0x3UL << TIM16_OR_TI1_RMP_Pos)               /*!< 0x00000003 */
13760 #define TIM16_OR_TI1_RMP          TIM16_OR_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
13761 #define TIM16_OR_TI1_RMP_0        (0x1UL << TIM16_OR_TI1_RMP_Pos)               /*!< 0x00000001 */
13762 #define TIM16_OR_TI1_RMP_1        (0x2UL << TIM16_OR_TI1_RMP_Pos)               /*!< 0x00000002 */
13763 
13764 /*******************  Bit definition for TIM1_OR register  *********************/
13765 #define TIM1_OR_ETR_RMP_Pos      (0U)
13766 #define TIM1_OR_ETR_RMP_Msk      (0xFUL << TIM1_OR_ETR_RMP_Pos)                 /*!< 0x0000000F */
13767 #define TIM1_OR_ETR_RMP          TIM1_OR_ETR_RMP_Msk                           /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
13768 #define TIM1_OR_ETR_RMP_0        (0x1UL << TIM1_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
13769 #define TIM1_OR_ETR_RMP_1        (0x2UL << TIM1_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
13770 #define TIM1_OR_ETR_RMP_2        (0x4UL << TIM1_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
13771 #define TIM1_OR_ETR_RMP_3        (0x8UL << TIM1_OR_ETR_RMP_Pos)                 /*!< 0x00000008 */
13772 
13773 /******************  Bit definition for TIM_CCMR3 register  *******************/
13774 #define TIM_CCMR3_OC5FE_Pos       (2U)
13775 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)                /*!< 0x00000004 */
13776 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
13777 #define TIM_CCMR3_OC5PE_Pos       (3U)
13778 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)                /*!< 0x00000008 */
13779 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
13780 
13781 #define TIM_CCMR3_OC5M_Pos        (4U)
13782 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010070 */
13783 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
13784 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */
13785 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */
13786 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */
13787 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
13788 
13789 #define TIM_CCMR3_OC5CE_Pos       (7U)
13790 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)                /*!< 0x00000080 */
13791 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
13792 
13793 #define TIM_CCMR3_OC6FE_Pos       (10U)
13794 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)                /*!< 0x00000400 */
13795 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
13796 #define TIM_CCMR3_OC6PE_Pos       (11U)
13797 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)                /*!< 0x00000800 */
13798 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
13799 
13800 #define TIM_CCMR3_OC6M_Pos        (12U)
13801 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01007000 */
13802 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
13803 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */
13804 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */
13805 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */
13806 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
13807 
13808 #define TIM_CCMR3_OC6CE_Pos       (15U)
13809 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)                /*!< 0x00008000 */
13810 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
13811 
13812 /******************************************************************************/
13813 /*                                                                            */
13814 /*                          Touch Sensing Controller (TSC)                    */
13815 /*                                                                            */
13816 /******************************************************************************/
13817 /*******************  Bit definition for TSC_CR register  *********************/
13818 #define TSC_CR_TSCE_Pos          (0U)
13819 #define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
13820 #define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
13821 #define TSC_CR_START_Pos         (1U)
13822 #define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                    /*!< 0x00000002 */
13823 #define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
13824 #define TSC_CR_AM_Pos            (2U)
13825 #define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
13826 #define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
13827 #define TSC_CR_SYNCPOL_Pos       (3U)
13828 #define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
13829 #define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
13830 #define TSC_CR_IODEF_Pos         (4U)
13831 #define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
13832 #define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
13833 
13834 #define TSC_CR_MCV_Pos           (5U)
13835 #define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
13836 #define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
13837 #define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
13838 #define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
13839 #define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
13840 
13841 #define TSC_CR_PGPSC_Pos         (12U)
13842 #define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
13843 #define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
13844 #define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
13845 #define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
13846 #define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
13847 
13848 #define TSC_CR_SSPSC_Pos         (15U)
13849 #define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
13850 #define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
13851 #define TSC_CR_SSE_Pos           (16U)
13852 #define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
13853 #define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
13854 
13855 #define TSC_CR_SSD_Pos           (17U)
13856 #define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
13857 #define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
13858 #define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
13859 #define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
13860 #define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
13861 #define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
13862 #define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
13863 #define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
13864 #define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
13865 
13866 #define TSC_CR_CTPL_Pos          (24U)
13867 #define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
13868 #define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
13869 #define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
13870 #define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
13871 #define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
13872 #define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
13873 
13874 #define TSC_CR_CTPH_Pos          (28U)
13875 #define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
13876 #define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
13877 #define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
13878 #define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
13879 #define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
13880 #define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
13881 
13882 /*******************  Bit definition for TSC_IER register  ********************/
13883 #define TSC_IER_EOAIE_Pos        (0U)
13884 #define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
13885 #define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
13886 #define TSC_IER_MCEIE_Pos        (1U)
13887 #define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
13888 #define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
13889 
13890 /*******************  Bit definition for TSC_ICR register  ********************/
13891 #define TSC_ICR_EOAIC_Pos        (0U)
13892 #define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
13893 #define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
13894 #define TSC_ICR_MCEIC_Pos        (1U)
13895 #define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
13896 #define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
13897 
13898 /*******************  Bit definition for TSC_ISR register  ********************/
13899 #define TSC_ISR_EOAF_Pos         (0U)
13900 #define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
13901 #define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
13902 #define TSC_ISR_MCEF_Pos         (1U)
13903 #define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
13904 #define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
13905 
13906 /*******************  Bit definition for TSC_IOHCR register  ******************/
13907 #define TSC_IOHCR_G1_IO1_Pos     (0U)
13908 #define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
13909 #define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
13910 #define TSC_IOHCR_G1_IO2_Pos     (1U)
13911 #define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
13912 #define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
13913 #define TSC_IOHCR_G1_IO3_Pos     (2U)
13914 #define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
13915 #define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
13916 #define TSC_IOHCR_G1_IO4_Pos     (3U)
13917 #define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
13918 #define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
13919 #define TSC_IOHCR_G2_IO1_Pos     (4U)
13920 #define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
13921 #define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
13922 #define TSC_IOHCR_G2_IO2_Pos     (5U)
13923 #define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
13924 #define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
13925 #define TSC_IOHCR_G2_IO3_Pos     (6U)
13926 #define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
13927 #define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
13928 #define TSC_IOHCR_G2_IO4_Pos     (7U)
13929 #define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
13930 #define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
13931 #define TSC_IOHCR_G3_IO1_Pos     (8U)
13932 #define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
13933 #define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
13934 #define TSC_IOHCR_G3_IO2_Pos     (9U)
13935 #define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
13936 #define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
13937 #define TSC_IOHCR_G3_IO3_Pos     (10U)
13938 #define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
13939 #define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
13940 #define TSC_IOHCR_G3_IO4_Pos     (11U)
13941 #define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
13942 #define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
13943 #define TSC_IOHCR_G4_IO1_Pos     (12U)
13944 #define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
13945 #define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
13946 #define TSC_IOHCR_G4_IO2_Pos     (13U)
13947 #define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
13948 #define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
13949 #define TSC_IOHCR_G4_IO3_Pos     (14U)
13950 #define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
13951 #define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
13952 #define TSC_IOHCR_G4_IO4_Pos     (15U)
13953 #define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
13954 #define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
13955 #define TSC_IOHCR_G5_IO1_Pos     (16U)
13956 #define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
13957 #define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
13958 #define TSC_IOHCR_G5_IO2_Pos     (17U)
13959 #define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
13960 #define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
13961 #define TSC_IOHCR_G5_IO3_Pos     (18U)
13962 #define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
13963 #define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
13964 #define TSC_IOHCR_G5_IO4_Pos     (19U)
13965 #define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
13966 #define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
13967 #define TSC_IOHCR_G6_IO1_Pos     (20U)
13968 #define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
13969 #define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
13970 #define TSC_IOHCR_G6_IO2_Pos     (21U)
13971 #define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
13972 #define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
13973 #define TSC_IOHCR_G6_IO3_Pos     (22U)
13974 #define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
13975 #define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
13976 #define TSC_IOHCR_G6_IO4_Pos     (23U)
13977 #define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
13978 #define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
13979 #define TSC_IOHCR_G7_IO1_Pos     (24U)
13980 #define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
13981 #define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
13982 #define TSC_IOHCR_G7_IO2_Pos     (25U)
13983 #define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
13984 #define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
13985 #define TSC_IOHCR_G7_IO3_Pos     (26U)
13986 #define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
13987 #define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
13988 #define TSC_IOHCR_G7_IO4_Pos     (27U)
13989 #define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
13990 #define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
13991 #define TSC_IOHCR_G8_IO1_Pos     (28U)
13992 #define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
13993 #define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
13994 #define TSC_IOHCR_G8_IO2_Pos     (29U)
13995 #define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
13996 #define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
13997 #define TSC_IOHCR_G8_IO3_Pos     (30U)
13998 #define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
13999 #define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
14000 #define TSC_IOHCR_G8_IO4_Pos     (31U)
14001 #define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
14002 #define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
14003 
14004 /*******************  Bit definition for TSC_IOASCR register  *****************/
14005 #define TSC_IOASCR_G1_IO1_Pos    (0U)
14006 #define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
14007 #define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
14008 #define TSC_IOASCR_G1_IO2_Pos    (1U)
14009 #define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
14010 #define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
14011 #define TSC_IOASCR_G1_IO3_Pos    (2U)
14012 #define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
14013 #define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
14014 #define TSC_IOASCR_G1_IO4_Pos    (3U)
14015 #define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
14016 #define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
14017 #define TSC_IOASCR_G2_IO1_Pos    (4U)
14018 #define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
14019 #define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
14020 #define TSC_IOASCR_G2_IO2_Pos    (5U)
14021 #define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
14022 #define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
14023 #define TSC_IOASCR_G2_IO3_Pos    (6U)
14024 #define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
14025 #define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
14026 #define TSC_IOASCR_G2_IO4_Pos    (7U)
14027 #define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
14028 #define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
14029 #define TSC_IOASCR_G3_IO1_Pos    (8U)
14030 #define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
14031 #define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
14032 #define TSC_IOASCR_G3_IO2_Pos    (9U)
14033 #define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
14034 #define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
14035 #define TSC_IOASCR_G3_IO3_Pos    (10U)
14036 #define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
14037 #define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
14038 #define TSC_IOASCR_G3_IO4_Pos    (11U)
14039 #define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
14040 #define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
14041 #define TSC_IOASCR_G4_IO1_Pos    (12U)
14042 #define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
14043 #define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
14044 #define TSC_IOASCR_G4_IO2_Pos    (13U)
14045 #define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
14046 #define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
14047 #define TSC_IOASCR_G4_IO3_Pos    (14U)
14048 #define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
14049 #define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
14050 #define TSC_IOASCR_G4_IO4_Pos    (15U)
14051 #define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
14052 #define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
14053 #define TSC_IOASCR_G5_IO1_Pos    (16U)
14054 #define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
14055 #define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
14056 #define TSC_IOASCR_G5_IO2_Pos    (17U)
14057 #define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
14058 #define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
14059 #define TSC_IOASCR_G5_IO3_Pos    (18U)
14060 #define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
14061 #define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
14062 #define TSC_IOASCR_G5_IO4_Pos    (19U)
14063 #define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
14064 #define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
14065 #define TSC_IOASCR_G6_IO1_Pos    (20U)
14066 #define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
14067 #define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
14068 #define TSC_IOASCR_G6_IO2_Pos    (21U)
14069 #define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
14070 #define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
14071 #define TSC_IOASCR_G6_IO3_Pos    (22U)
14072 #define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
14073 #define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
14074 #define TSC_IOASCR_G6_IO4_Pos    (23U)
14075 #define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
14076 #define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
14077 #define TSC_IOASCR_G7_IO1_Pos    (24U)
14078 #define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
14079 #define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
14080 #define TSC_IOASCR_G7_IO2_Pos    (25U)
14081 #define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
14082 #define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
14083 #define TSC_IOASCR_G7_IO3_Pos    (26U)
14084 #define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
14085 #define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
14086 #define TSC_IOASCR_G7_IO4_Pos    (27U)
14087 #define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
14088 #define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
14089 #define TSC_IOASCR_G8_IO1_Pos    (28U)
14090 #define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
14091 #define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
14092 #define TSC_IOASCR_G8_IO2_Pos    (29U)
14093 #define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
14094 #define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
14095 #define TSC_IOASCR_G8_IO3_Pos    (30U)
14096 #define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
14097 #define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
14098 #define TSC_IOASCR_G8_IO4_Pos    (31U)
14099 #define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
14100 #define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
14101 
14102 /*******************  Bit definition for TSC_IOSCR register  ******************/
14103 #define TSC_IOSCR_G1_IO1_Pos     (0U)
14104 #define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
14105 #define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
14106 #define TSC_IOSCR_G1_IO2_Pos     (1U)
14107 #define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
14108 #define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
14109 #define TSC_IOSCR_G1_IO3_Pos     (2U)
14110 #define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
14111 #define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
14112 #define TSC_IOSCR_G1_IO4_Pos     (3U)
14113 #define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
14114 #define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
14115 #define TSC_IOSCR_G2_IO1_Pos     (4U)
14116 #define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
14117 #define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
14118 #define TSC_IOSCR_G2_IO2_Pos     (5U)
14119 #define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
14120 #define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
14121 #define TSC_IOSCR_G2_IO3_Pos     (6U)
14122 #define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
14123 #define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
14124 #define TSC_IOSCR_G2_IO4_Pos     (7U)
14125 #define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
14126 #define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
14127 #define TSC_IOSCR_G3_IO1_Pos     (8U)
14128 #define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
14129 #define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
14130 #define TSC_IOSCR_G3_IO2_Pos     (9U)
14131 #define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
14132 #define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
14133 #define TSC_IOSCR_G3_IO3_Pos     (10U)
14134 #define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
14135 #define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
14136 #define TSC_IOSCR_G3_IO4_Pos     (11U)
14137 #define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
14138 #define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
14139 #define TSC_IOSCR_G4_IO1_Pos     (12U)
14140 #define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
14141 #define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
14142 #define TSC_IOSCR_G4_IO2_Pos     (13U)
14143 #define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
14144 #define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
14145 #define TSC_IOSCR_G4_IO3_Pos     (14U)
14146 #define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
14147 #define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
14148 #define TSC_IOSCR_G4_IO4_Pos     (15U)
14149 #define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
14150 #define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
14151 #define TSC_IOSCR_G5_IO1_Pos     (16U)
14152 #define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
14153 #define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
14154 #define TSC_IOSCR_G5_IO2_Pos     (17U)
14155 #define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
14156 #define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
14157 #define TSC_IOSCR_G5_IO3_Pos     (18U)
14158 #define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
14159 #define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
14160 #define TSC_IOSCR_G5_IO4_Pos     (19U)
14161 #define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
14162 #define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
14163 #define TSC_IOSCR_G6_IO1_Pos     (20U)
14164 #define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
14165 #define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
14166 #define TSC_IOSCR_G6_IO2_Pos     (21U)
14167 #define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
14168 #define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
14169 #define TSC_IOSCR_G6_IO3_Pos     (22U)
14170 #define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
14171 #define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
14172 #define TSC_IOSCR_G6_IO4_Pos     (23U)
14173 #define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
14174 #define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
14175 #define TSC_IOSCR_G7_IO1_Pos     (24U)
14176 #define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
14177 #define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
14178 #define TSC_IOSCR_G7_IO2_Pos     (25U)
14179 #define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
14180 #define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
14181 #define TSC_IOSCR_G7_IO3_Pos     (26U)
14182 #define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
14183 #define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
14184 #define TSC_IOSCR_G7_IO4_Pos     (27U)
14185 #define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
14186 #define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
14187 #define TSC_IOSCR_G8_IO1_Pos     (28U)
14188 #define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
14189 #define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
14190 #define TSC_IOSCR_G8_IO2_Pos     (29U)
14191 #define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
14192 #define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
14193 #define TSC_IOSCR_G8_IO3_Pos     (30U)
14194 #define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
14195 #define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
14196 #define TSC_IOSCR_G8_IO4_Pos     (31U)
14197 #define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
14198 #define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
14199 
14200 /*******************  Bit definition for TSC_IOCCR register  ******************/
14201 #define TSC_IOCCR_G1_IO1_Pos     (0U)
14202 #define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
14203 #define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
14204 #define TSC_IOCCR_G1_IO2_Pos     (1U)
14205 #define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
14206 #define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
14207 #define TSC_IOCCR_G1_IO3_Pos     (2U)
14208 #define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
14209 #define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
14210 #define TSC_IOCCR_G1_IO4_Pos     (3U)
14211 #define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
14212 #define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
14213 #define TSC_IOCCR_G2_IO1_Pos     (4U)
14214 #define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
14215 #define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
14216 #define TSC_IOCCR_G2_IO2_Pos     (5U)
14217 #define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
14218 #define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
14219 #define TSC_IOCCR_G2_IO3_Pos     (6U)
14220 #define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
14221 #define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
14222 #define TSC_IOCCR_G2_IO4_Pos     (7U)
14223 #define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
14224 #define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
14225 #define TSC_IOCCR_G3_IO1_Pos     (8U)
14226 #define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
14227 #define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
14228 #define TSC_IOCCR_G3_IO2_Pos     (9U)
14229 #define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
14230 #define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
14231 #define TSC_IOCCR_G3_IO3_Pos     (10U)
14232 #define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
14233 #define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
14234 #define TSC_IOCCR_G3_IO4_Pos     (11U)
14235 #define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
14236 #define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
14237 #define TSC_IOCCR_G4_IO1_Pos     (12U)
14238 #define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
14239 #define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
14240 #define TSC_IOCCR_G4_IO2_Pos     (13U)
14241 #define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
14242 #define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
14243 #define TSC_IOCCR_G4_IO3_Pos     (14U)
14244 #define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
14245 #define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
14246 #define TSC_IOCCR_G4_IO4_Pos     (15U)
14247 #define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
14248 #define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
14249 #define TSC_IOCCR_G5_IO1_Pos     (16U)
14250 #define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
14251 #define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
14252 #define TSC_IOCCR_G5_IO2_Pos     (17U)
14253 #define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
14254 #define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
14255 #define TSC_IOCCR_G5_IO3_Pos     (18U)
14256 #define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
14257 #define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
14258 #define TSC_IOCCR_G5_IO4_Pos     (19U)
14259 #define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
14260 #define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
14261 #define TSC_IOCCR_G6_IO1_Pos     (20U)
14262 #define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
14263 #define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
14264 #define TSC_IOCCR_G6_IO2_Pos     (21U)
14265 #define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
14266 #define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
14267 #define TSC_IOCCR_G6_IO3_Pos     (22U)
14268 #define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
14269 #define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
14270 #define TSC_IOCCR_G6_IO4_Pos     (23U)
14271 #define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
14272 #define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
14273 #define TSC_IOCCR_G7_IO1_Pos     (24U)
14274 #define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
14275 #define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
14276 #define TSC_IOCCR_G7_IO2_Pos     (25U)
14277 #define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
14278 #define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
14279 #define TSC_IOCCR_G7_IO3_Pos     (26U)
14280 #define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
14281 #define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
14282 #define TSC_IOCCR_G7_IO4_Pos     (27U)
14283 #define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
14284 #define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
14285 #define TSC_IOCCR_G8_IO1_Pos     (28U)
14286 #define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
14287 #define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
14288 #define TSC_IOCCR_G8_IO2_Pos     (29U)
14289 #define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
14290 #define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
14291 #define TSC_IOCCR_G8_IO3_Pos     (30U)
14292 #define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
14293 #define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
14294 #define TSC_IOCCR_G8_IO4_Pos     (31U)
14295 #define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
14296 #define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
14297 
14298 /*******************  Bit definition for TSC_IOGCSR register  *****************/
14299 #define TSC_IOGCSR_G1E_Pos       (0U)
14300 #define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
14301 #define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
14302 #define TSC_IOGCSR_G2E_Pos       (1U)
14303 #define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
14304 #define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
14305 #define TSC_IOGCSR_G3E_Pos       (2U)
14306 #define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
14307 #define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
14308 #define TSC_IOGCSR_G4E_Pos       (3U)
14309 #define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
14310 #define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
14311 #define TSC_IOGCSR_G5E_Pos       (4U)
14312 #define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
14313 #define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
14314 #define TSC_IOGCSR_G6E_Pos       (5U)
14315 #define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
14316 #define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
14317 #define TSC_IOGCSR_G7E_Pos       (6U)
14318 #define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
14319 #define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
14320 #define TSC_IOGCSR_G8E_Pos       (7U)
14321 #define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
14322 #define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
14323 #define TSC_IOGCSR_G1S_Pos       (16U)
14324 #define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
14325 #define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
14326 #define TSC_IOGCSR_G2S_Pos       (17U)
14327 #define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
14328 #define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
14329 #define TSC_IOGCSR_G3S_Pos       (18U)
14330 #define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
14331 #define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
14332 #define TSC_IOGCSR_G4S_Pos       (19U)
14333 #define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
14334 #define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
14335 #define TSC_IOGCSR_G5S_Pos       (20U)
14336 #define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
14337 #define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
14338 #define TSC_IOGCSR_G6S_Pos       (21U)
14339 #define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
14340 #define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
14341 #define TSC_IOGCSR_G7S_Pos       (22U)
14342 #define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
14343 #define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
14344 #define TSC_IOGCSR_G8S_Pos       (23U)
14345 #define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
14346 #define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
14347 
14348 /*******************  Bit definition for TSC_IOGXCR register  *****************/
14349 #define TSC_IOGXCR_CNT_Pos       (0U)
14350 #define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
14351 #define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
14352 
14353 /******************************************************************************/
14354 /*                                                                            */
14355 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
14356 /*                                                                            */
14357 /******************************************************************************/
14358 
14359 /*
14360 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
14361 */
14362 
14363 /* Support of 7 bits data length feature */
14364 #define USART_7BITS_SUPPORT
14365 
14366 /******************  Bit definition for USART_CR1 register  *******************/
14367 #define USART_CR1_UE_Pos              (0U)
14368 #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
14369 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
14370 #define USART_CR1_UESM_Pos            (1U)
14371 #define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
14372 #define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
14373 #define USART_CR1_RE_Pos              (2U)
14374 #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
14375 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
14376 #define USART_CR1_TE_Pos              (3U)
14377 #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
14378 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
14379 #define USART_CR1_IDLEIE_Pos          (4U)
14380 #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
14381 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
14382 #define USART_CR1_RXNEIE_Pos          (5U)
14383 #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
14384 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
14385 #define USART_CR1_TCIE_Pos            (6U)
14386 #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
14387 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
14388 #define USART_CR1_TXEIE_Pos           (7U)
14389 #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
14390 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
14391 #define USART_CR1_PEIE_Pos            (8U)
14392 #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
14393 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
14394 #define USART_CR1_PS_Pos              (9U)
14395 #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
14396 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
14397 #define USART_CR1_PCE_Pos             (10U)
14398 #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
14399 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
14400 #define USART_CR1_WAKE_Pos            (11U)
14401 #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
14402 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
14403 #define USART_CR1_M0_Pos              (12U)
14404 #define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
14405 #define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length bit 0 */
14406 #define USART_CR1_MME_Pos             (13U)
14407 #define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
14408 #define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
14409 #define USART_CR1_CMIE_Pos            (14U)
14410 #define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
14411 #define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
14412 #define USART_CR1_OVER8_Pos           (15U)
14413 #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
14414 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
14415 #define USART_CR1_DEDT_Pos            (16U)
14416 #define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
14417 #define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
14418 #define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
14419 #define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
14420 #define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
14421 #define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
14422 #define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
14423 #define USART_CR1_DEAT_Pos            (21U)
14424 #define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
14425 #define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
14426 #define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
14427 #define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
14428 #define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
14429 #define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
14430 #define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
14431 #define USART_CR1_RTOIE_Pos           (26U)
14432 #define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
14433 #define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
14434 #define USART_CR1_EOBIE_Pos           (27U)
14435 #define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
14436 #define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
14437 #define USART_CR1_M1_Pos              (28U)
14438 #define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
14439 #define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length bit 1 */
14440 #define USART_CR1_M_Pos               (12U)
14441 #define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
14442 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!< [M1:M0] Word length */
14443 
14444 /******************  Bit definition for USART_CR2 register  *******************/
14445 #define USART_CR2_ADDM7_Pos           (4U)
14446 #define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
14447 #define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
14448 #define USART_CR2_LBDL_Pos            (5U)
14449 #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
14450 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
14451 #define USART_CR2_LBDIE_Pos           (6U)
14452 #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
14453 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
14454 #define USART_CR2_LBCL_Pos            (8U)
14455 #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
14456 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
14457 #define USART_CR2_CPHA_Pos            (9U)
14458 #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
14459 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
14460 #define USART_CR2_CPOL_Pos            (10U)
14461 #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
14462 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
14463 #define USART_CR2_CLKEN_Pos           (11U)
14464 #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
14465 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
14466 #define USART_CR2_STOP_Pos            (12U)
14467 #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
14468 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
14469 #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
14470 #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
14471 #define USART_CR2_LINEN_Pos           (14U)
14472 #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
14473 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
14474 #define USART_CR2_SWAP_Pos            (15U)
14475 #define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
14476 #define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
14477 #define USART_CR2_RXINV_Pos           (16U)
14478 #define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
14479 #define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
14480 #define USART_CR2_TXINV_Pos           (17U)
14481 #define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
14482 #define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
14483 #define USART_CR2_DATAINV_Pos         (18U)
14484 #define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
14485 #define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
14486 #define USART_CR2_MSBFIRST_Pos        (19U)
14487 #define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
14488 #define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
14489 #define USART_CR2_ABREN_Pos           (20U)
14490 #define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
14491 #define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
14492 #define USART_CR2_ABRMODE_Pos         (21U)
14493 #define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
14494 #define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
14495 #define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
14496 #define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
14497 #define USART_CR2_RTOEN_Pos           (23U)
14498 #define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
14499 #define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
14500 #define USART_CR2_ADD_Pos             (24U)
14501 #define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
14502 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
14503 
14504 /******************  Bit definition for USART_CR3 register  *******************/
14505 #define USART_CR3_EIE_Pos             (0U)
14506 #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
14507 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
14508 #define USART_CR3_IREN_Pos            (1U)
14509 #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
14510 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
14511 #define USART_CR3_IRLP_Pos            (2U)
14512 #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
14513 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
14514 #define USART_CR3_HDSEL_Pos           (3U)
14515 #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
14516 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
14517 #define USART_CR3_NACK_Pos            (4U)
14518 #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
14519 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
14520 #define USART_CR3_SCEN_Pos            (5U)
14521 #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
14522 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
14523 #define USART_CR3_DMAR_Pos            (6U)
14524 #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
14525 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
14526 #define USART_CR3_DMAT_Pos            (7U)
14527 #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
14528 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
14529 #define USART_CR3_RTSE_Pos            (8U)
14530 #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
14531 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
14532 #define USART_CR3_CTSE_Pos            (9U)
14533 #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
14534 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
14535 #define USART_CR3_CTSIE_Pos           (10U)
14536 #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
14537 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
14538 #define USART_CR3_ONEBIT_Pos          (11U)
14539 #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
14540 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
14541 #define USART_CR3_OVRDIS_Pos          (12U)
14542 #define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
14543 #define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
14544 #define USART_CR3_DDRE_Pos            (13U)
14545 #define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
14546 #define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
14547 #define USART_CR3_DEM_Pos             (14U)
14548 #define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
14549 #define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
14550 #define USART_CR3_DEP_Pos             (15U)
14551 #define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
14552 #define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
14553 #define USART_CR3_SCARCNT_Pos         (17U)
14554 #define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
14555 #define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
14556 #define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
14557 #define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
14558 #define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
14559 #define USART_CR3_WUS_Pos             (20U)
14560 #define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
14561 #define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
14562 #define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
14563 #define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
14564 #define USART_CR3_WUFIE_Pos           (22U)
14565 #define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
14566 #define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
14567 
14568 /******************  Bit definition for USART_BRR register  *******************/
14569 #define USART_BRR_DIV_FRACTION_Pos    (0U)
14570 #define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
14571 #define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
14572 #define USART_BRR_DIV_MANTISSA_Pos    (4U)
14573 #define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
14574 #define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
14575 
14576 /******************  Bit definition for USART_GTPR register  ******************/
14577 #define USART_GTPR_PSC_Pos            (0U)
14578 #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
14579 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
14580 #define USART_GTPR_GT_Pos             (8U)
14581 #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
14582 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
14583 
14584 
14585 /*******************  Bit definition for USART_RTOR register  *****************/
14586 #define USART_RTOR_RTO_Pos            (0U)
14587 #define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
14588 #define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
14589 #define USART_RTOR_BLEN_Pos           (24U)
14590 #define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
14591 #define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
14592 
14593 /*******************  Bit definition for USART_RQR register  ******************/
14594 #define USART_RQR_ABRRQ_Pos           (0U)
14595 #define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
14596 #define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
14597 #define USART_RQR_SBKRQ_Pos           (1U)
14598 #define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
14599 #define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
14600 #define USART_RQR_MMRQ_Pos            (2U)
14601 #define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
14602 #define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
14603 #define USART_RQR_RXFRQ_Pos           (3U)
14604 #define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
14605 #define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
14606 #define USART_RQR_TXFRQ_Pos           (4U)
14607 #define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
14608 #define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
14609 
14610 /*******************  Bit definition for USART_ISR register  ******************/
14611 #define USART_ISR_PE_Pos              (0U)
14612 #define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
14613 #define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
14614 #define USART_ISR_FE_Pos              (1U)
14615 #define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
14616 #define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
14617 #define USART_ISR_NE_Pos              (2U)
14618 #define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
14619 #define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
14620 #define USART_ISR_ORE_Pos             (3U)
14621 #define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
14622 #define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
14623 #define USART_ISR_IDLE_Pos            (4U)
14624 #define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
14625 #define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
14626 #define USART_ISR_RXNE_Pos            (5U)
14627 #define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
14628 #define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
14629 #define USART_ISR_TC_Pos              (6U)
14630 #define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
14631 #define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
14632 #define USART_ISR_TXE_Pos             (7U)
14633 #define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
14634 #define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
14635 #define USART_ISR_LBDF_Pos            (8U)
14636 #define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
14637 #define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
14638 #define USART_ISR_CTSIF_Pos           (9U)
14639 #define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
14640 #define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
14641 #define USART_ISR_CTS_Pos             (10U)
14642 #define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
14643 #define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
14644 #define USART_ISR_RTOF_Pos            (11U)
14645 #define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
14646 #define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
14647 #define USART_ISR_EOBF_Pos            (12U)
14648 #define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
14649 #define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
14650 #define USART_ISR_ABRE_Pos            (14U)
14651 #define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
14652 #define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
14653 #define USART_ISR_ABRF_Pos            (15U)
14654 #define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
14655 #define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
14656 #define USART_ISR_BUSY_Pos            (16U)
14657 #define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
14658 #define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
14659 #define USART_ISR_CMF_Pos             (17U)
14660 #define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
14661 #define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
14662 #define USART_ISR_SBKF_Pos            (18U)
14663 #define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
14664 #define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
14665 #define USART_ISR_RWU_Pos             (19U)
14666 #define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
14667 #define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
14668 #define USART_ISR_WUF_Pos             (20U)
14669 #define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
14670 #define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
14671 #define USART_ISR_TEACK_Pos           (21U)
14672 #define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
14673 #define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
14674 #define USART_ISR_REACK_Pos           (22U)
14675 #define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
14676 #define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
14677 
14678 /*******************  Bit definition for USART_ICR register  ******************/
14679 #define USART_ICR_PECF_Pos            (0U)
14680 #define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
14681 #define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
14682 #define USART_ICR_FECF_Pos            (1U)
14683 #define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
14684 #define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
14685 #define USART_ICR_NCF_Pos             (2U)
14686 #define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
14687 #define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
14688 #define USART_ICR_ORECF_Pos           (3U)
14689 #define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
14690 #define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
14691 #define USART_ICR_IDLECF_Pos          (4U)
14692 #define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
14693 #define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
14694 #define USART_ICR_TCCF_Pos            (6U)
14695 #define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
14696 #define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
14697 #define USART_ICR_LBDCF_Pos           (8U)
14698 #define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
14699 #define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
14700 #define USART_ICR_CTSCF_Pos           (9U)
14701 #define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
14702 #define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
14703 #define USART_ICR_RTOCF_Pos           (11U)
14704 #define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
14705 #define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
14706 #define USART_ICR_EOBCF_Pos           (12U)
14707 #define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
14708 #define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
14709 #define USART_ICR_CMCF_Pos            (17U)
14710 #define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
14711 #define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
14712 #define USART_ICR_WUCF_Pos            (20U)
14713 #define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
14714 #define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
14715 
14716 /*******************  Bit definition for USART_RDR register  ******************/
14717 #define USART_RDR_RDR_Pos             (0U)
14718 #define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
14719 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
14720 
14721 /*******************  Bit definition for USART_TDR register  ******************/
14722 #define USART_TDR_TDR_Pos             (0U)
14723 #define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
14724 #define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
14725 
14726 /******************************************************************************/
14727 /*                                                                            */
14728 /*                            Window WATCHDOG                                 */
14729 /*                                                                            */
14730 /******************************************************************************/
14731 /*******************  Bit definition for WWDG_CR register  ********************/
14732 #define WWDG_CR_T_Pos           (0U)
14733 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
14734 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
14735 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
14736 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
14737 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
14738 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
14739 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
14740 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
14741 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
14742 
14743 /* Legacy defines */
14744 #define  WWDG_CR_T0 WWDG_CR_T_0
14745 #define  WWDG_CR_T1 WWDG_CR_T_1
14746 #define  WWDG_CR_T2 WWDG_CR_T_2
14747 #define  WWDG_CR_T3 WWDG_CR_T_3
14748 #define  WWDG_CR_T4 WWDG_CR_T_4
14749 #define  WWDG_CR_T5 WWDG_CR_T_5
14750 #define  WWDG_CR_T6 WWDG_CR_T_6
14751 
14752 #define WWDG_CR_WDGA_Pos        (7U)
14753 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
14754 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
14755 
14756 /*******************  Bit definition for WWDG_CFR register  *******************/
14757 #define WWDG_CFR_W_Pos          (0U)
14758 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
14759 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
14760 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
14761 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
14762 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
14763 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
14764 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
14765 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
14766 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
14767 
14768 /* Legacy defines */
14769 #define  WWDG_CFR_W0 WWDG_CFR_W_0
14770 #define  WWDG_CFR_W1 WWDG_CFR_W_1
14771 #define  WWDG_CFR_W2 WWDG_CFR_W_2
14772 #define  WWDG_CFR_W3 WWDG_CFR_W_3
14773 #define  WWDG_CFR_W4 WWDG_CFR_W_4
14774 #define  WWDG_CFR_W5 WWDG_CFR_W_5
14775 #define  WWDG_CFR_W6 WWDG_CFR_W_6
14776 
14777 #define WWDG_CFR_WDGTB_Pos      (7U)
14778 #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
14779 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
14780 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
14781 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
14782 
14783 /* Legacy defines */
14784 #define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
14785 #define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
14786 
14787 #define WWDG_CFR_EWI_Pos        (9U)
14788 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
14789 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
14790 
14791 /*******************  Bit definition for WWDG_SR register  ********************/
14792 #define WWDG_SR_EWIF_Pos        (0U)
14793 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
14794 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
14795 
14796 /**
14797   * @}
14798   */
14799 
14800  /**
14801   * @}
14802   */
14803 
14804 /** @addtogroup Exported_macros
14805   * @{
14806   */
14807 
14808 /****************************** ADC Instances *********************************/
14809 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
14810                                        ((INSTANCE) == ADC2))
14811 
14812 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
14813 
14814 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
14815 /****************************** CAN Instances *********************************/
14816 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
14817 
14818 /****************************** COMP Instances ********************************/
14819 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
14820                                         ((INSTANCE) == COMP4) || \
14821                                         ((INSTANCE) == COMP6))
14822 
14823 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) (0U)
14824 
14825 /******************** COMP Instances with switch on DAC1 Channel1 output ******/
14826 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) (0U)
14827 
14828 /******************** COMP Instances with window mode capability **************/
14829 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (0U)
14830 
14831 /****************************** CRC Instances *********************************/
14832 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
14833 
14834 /****************************** DAC Instances *********************************/
14835 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
14836                                        ((INSTANCE) == DAC2))
14837 
14838 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
14839     ((((INSTANCE) == DAC1) &&                   \
14840      (((CHANNEL) == DAC_CHANNEL_1) ||          \
14841       ((CHANNEL) == DAC_CHANNEL_2)))           \
14842     ||                                          \
14843     (((INSTANCE) == DAC2) &&                    \
14844      (((CHANNEL) == DAC_CHANNEL_1))))
14845 
14846 /****************************** DMA Instances *********************************/
14847 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
14848                                        ((INSTANCE) == DMA1_Channel2) || \
14849                                        ((INSTANCE) == DMA1_Channel3) || \
14850                                        ((INSTANCE) == DMA1_Channel4) || \
14851                                        ((INSTANCE) == DMA1_Channel5) || \
14852                                        ((INSTANCE) == DMA1_Channel6) || \
14853                                        ((INSTANCE) == DMA1_Channel7))
14854 
14855 /****************************** GPIO Instances ********************************/
14856 #define IS_GPIO_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
14857                                          ((INSTANCE) == GPIOB) || \
14858                                          ((INSTANCE) == GPIOC) || \
14859                                          ((INSTANCE) == GPIOD) || \
14860                                          ((INSTANCE) == GPIOF))
14861 
14862 #define IS_GPIO_AF_INSTANCE(INSTANCE)   (((INSTANCE) == GPIOA) || \
14863                                          ((INSTANCE) == GPIOB) || \
14864                                          ((INSTANCE) == GPIOC) || \
14865                                          ((INSTANCE) == GPIOD) || \
14866                                          ((INSTANCE) == GPIOF))
14867 
14868 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14869                                          ((INSTANCE) == GPIOB) || \
14870                                          ((INSTANCE) == GPIOC) || \
14871                                          ((INSTANCE) == GPIOD) || \
14872                                          ((INSTANCE) == GPIOF))
14873 
14874 /****************************** HRTIM Instances *********************************/
14875 #define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
14876 
14877 /****************************** I2C Instances *********************************/
14878 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
14879 
14880 /****************** I2C Instances : wakeup capability from stop modes *********/
14881 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
14882 
14883 
14884 /****************************** OPAMP Instances *******************************/
14885 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
14886 
14887 /****************************** IWDG Instances ********************************/
14888 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
14889 
14890 /****************************** RTC Instances *********************************/
14891 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
14892 
14893 /****************************** SMBUS Instances *******************************/
14894 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
14895 
14896 /****************************** SPI Instances *********************************/
14897 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
14898 
14899 /******************* TIM Instances : All supported instances ******************/
14900 #define IS_TIM_INSTANCE(INSTANCE)\
14901   (((INSTANCE) == TIM1)    || \
14902    ((INSTANCE) == TIM2)    || \
14903    ((INSTANCE) == TIM3)    || \
14904    ((INSTANCE) == TIM6)    || \
14905    ((INSTANCE) == TIM7)    || \
14906    ((INSTANCE) == TIM15)   || \
14907    ((INSTANCE) == TIM16)   || \
14908    ((INSTANCE) == TIM17))
14909 
14910 /******************* TIM Instances : at least 1 capture/compare channel *******/
14911 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
14912   (((INSTANCE) == TIM1)    || \
14913    ((INSTANCE) == TIM2)    || \
14914    ((INSTANCE) == TIM3)    || \
14915    ((INSTANCE) == TIM15)   || \
14916    ((INSTANCE) == TIM16)   || \
14917    ((INSTANCE) == TIM17))
14918 
14919 /****************** TIM Instances : at least 2 capture/compare channels *******/
14920 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
14921   (((INSTANCE) == TIM1)    || \
14922    ((INSTANCE) == TIM2)    || \
14923    ((INSTANCE) == TIM3)    || \
14924    ((INSTANCE) == TIM15))
14925 
14926 /****************** TIM Instances : at least 3 capture/compare channels *******/
14927 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
14928   (((INSTANCE) == TIM1)    || \
14929    ((INSTANCE) == TIM2)    || \
14930    ((INSTANCE) == TIM3))
14931 
14932 /****************** TIM Instances : at least 4 capture/compare channels *******/
14933 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
14934   (((INSTANCE) == TIM1)    || \
14935    ((INSTANCE) == TIM2)    || \
14936    ((INSTANCE) == TIM3))
14937 
14938 /****************** TIM Instances : at least 5 capture/compare channels *******/
14939 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
14940   (((INSTANCE) == TIM1))
14941 
14942 /****************** TIM Instances : at least 6 capture/compare channels *******/
14943 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
14944   (((INSTANCE) == TIM1))
14945 
14946 /************************** TIM Instances : Advanced-control timers ***********/
14947 
14948 /****************** TIM Instances : Advanced timer instances *******************/
14949 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
14950   ((INSTANCE) == TIM1)
14951 
14952 /****************** TIM Instances : supporting clock selection ****************/
14953 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
14954   (((INSTANCE) == TIM1)    || \
14955    ((INSTANCE) == TIM2)    || \
14956    ((INSTANCE) == TIM3)    || \
14957    ((INSTANCE) == TIM15))
14958 
14959 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
14960 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
14961   (((INSTANCE) == TIM1)    || \
14962    ((INSTANCE) == TIM2)    || \
14963    ((INSTANCE) == TIM3))
14964 
14965 /****************** TIM Instances : supporting external clock mode 2 **********/
14966 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
14967   (((INSTANCE) == TIM1)    || \
14968    ((INSTANCE) == TIM2)    || \
14969    ((INSTANCE) == TIM3))
14970 
14971 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
14972 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
14973   (((INSTANCE) == TIM1)    || \
14974    ((INSTANCE) == TIM2)    || \
14975    ((INSTANCE) == TIM3)    || \
14976    ((INSTANCE) == TIM15))
14977 
14978 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
14979 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
14980   (((INSTANCE) == TIM1)    || \
14981    ((INSTANCE) == TIM2)    || \
14982    ((INSTANCE) == TIM3)    || \
14983    ((INSTANCE) == TIM15))
14984 
14985 /****************** TIM Instances : supporting OCxREF clear *******************/
14986 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
14987   (((INSTANCE) == TIM1)    || \
14988    ((INSTANCE) == TIM2)    || \
14989    ((INSTANCE) == TIM3))
14990 
14991 /****************** TIM Instances : supporting encoder interface **************/
14992 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
14993   (((INSTANCE) == TIM1)    || \
14994    ((INSTANCE) == TIM2)    || \
14995    ((INSTANCE) == TIM3))
14996 
14997 /****************** TIM Instances : supporting Hall interface *****************/
14998 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
14999   (((INSTANCE) == TIM1))
15000 
15001 /**************** TIM Instances : external trigger input available ************/
15002 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
15003                                             ((INSTANCE) == TIM2)  || \
15004                                             ((INSTANCE) == TIM3))
15005 
15006 /****************** TIM Instances : supporting input XOR function *************/
15007 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
15008   (((INSTANCE) == TIM1)    || \
15009    ((INSTANCE) == TIM2)    || \
15010    ((INSTANCE) == TIM3)    || \
15011    ((INSTANCE) == TIM15))
15012 
15013 /****************** TIM Instances : supporting master mode ********************/
15014 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
15015   (((INSTANCE) == TIM1)    || \
15016    ((INSTANCE) == TIM2)    || \
15017    ((INSTANCE) == TIM3)    || \
15018    ((INSTANCE) == TIM6)    || \
15019    ((INSTANCE) == TIM7)    || \
15020    ((INSTANCE) == TIM15))
15021 
15022 /****************** TIM Instances : supporting slave mode *********************/
15023 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
15024   (((INSTANCE) == TIM1)    || \
15025    ((INSTANCE) == TIM2)    || \
15026    ((INSTANCE) == TIM3)    || \
15027    ((INSTANCE) == TIM15))
15028 
15029 /****************** TIM Instances : supporting 32 bits counter ****************/
15030 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
15031     ((INSTANCE) == TIM2)
15032 
15033 /****************** TIM Instances : supporting DMA burst **********************/
15034 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
15035     (((INSTANCE) == TIM1)    || \
15036      ((INSTANCE) == TIM2)    || \
15037    ((INSTANCE) == TIM3)    || \
15038    ((INSTANCE) == TIM15)   || \
15039    ((INSTANCE) == TIM16)   || \
15040      ((INSTANCE) == TIM17))
15041 
15042 /****************** TIM Instances : supporting the break function *************/
15043 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
15044       (((INSTANCE) == TIM1)    || \
15045        ((INSTANCE) == TIM15)   || \
15046        ((INSTANCE) == TIM16)   || \
15047        ((INSTANCE) == TIM17))
15048 
15049 /****************** TIM Instances : supporting input/output channel(s) ********/
15050 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
15051     ((((INSTANCE) == TIM1) &&                   \
15052      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15053       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15054       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15055       ((CHANNEL) == TIM_CHANNEL_4) ||          \
15056       ((CHANNEL) == TIM_CHANNEL_5) ||          \
15057       ((CHANNEL) == TIM_CHANNEL_6)))           \
15058     ||                                         \
15059     (((INSTANCE) == TIM2) &&                   \
15060      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15061       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15062       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15063       ((CHANNEL) == TIM_CHANNEL_4)))           \
15064     ||                                         \
15065     (((INSTANCE) == TIM3) &&                   \
15066      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15067       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15068       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15069       ((CHANNEL) == TIM_CHANNEL_4)))           \
15070     ||                                         \
15071     (((INSTANCE) == TIM15) &&                  \
15072      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15073       ((CHANNEL) == TIM_CHANNEL_2)))           \
15074     ||                                         \
15075     (((INSTANCE) == TIM16) &&                  \
15076      (((CHANNEL) == TIM_CHANNEL_1)))           \
15077     ||                                         \
15078     (((INSTANCE) == TIM17) &&                  \
15079      (((CHANNEL) == TIM_CHANNEL_1))))
15080 
15081 /****************** TIM Instances : supporting complementary output(s) ********/
15082 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15083    ((((INSTANCE) == TIM1) &&                    \
15084      (((CHANNEL) == TIM_CHANNEL_1) ||           \
15085       ((CHANNEL) == TIM_CHANNEL_2) ||           \
15086       ((CHANNEL) == TIM_CHANNEL_3)))            \
15087     ||                                          \
15088     (((INSTANCE) == TIM15) &&                   \
15089       ((CHANNEL) == TIM_CHANNEL_1))             \
15090     ||                                          \
15091     (((INSTANCE) == TIM16) &&                   \
15092      ((CHANNEL) == TIM_CHANNEL_1))              \
15093     ||                                          \
15094     (((INSTANCE) == TIM17) &&                   \
15095      ((CHANNEL) == TIM_CHANNEL_1)))
15096 
15097 /****************** TIM Instances : supporting counting mode selection ********/
15098 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
15099   (((INSTANCE) == TIM1)    || \
15100    ((INSTANCE) == TIM2)    || \
15101    ((INSTANCE) == TIM3))
15102 
15103 /****************** TIM Instances : supporting repetition counter *************/
15104 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
15105   (((INSTANCE) == TIM1)    || \
15106    ((INSTANCE) == TIM15)   || \
15107    ((INSTANCE) == TIM16)   || \
15108    ((INSTANCE) == TIM17))
15109 
15110 /****************** TIM Instances : supporting clock division *****************/
15111 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
15112   (((INSTANCE) == TIM1)    || \
15113    ((INSTANCE) == TIM2)    || \
15114    ((INSTANCE) == TIM3)    || \
15115    ((INSTANCE) == TIM15)   || \
15116    ((INSTANCE) == TIM16)   || \
15117    ((INSTANCE) == TIM17))
15118 
15119 /****************** TIM Instances : supporting 2 break inputs *****************/
15120 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
15121   (((INSTANCE) == TIM1))
15122 
15123 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
15124 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
15125   (((INSTANCE) == TIM1))
15126 
15127 /****************** TIM Instances : supporting DMA generation on Update events*/
15128 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
15129   (((INSTANCE) == TIM1)    || \
15130    ((INSTANCE) == TIM2)    || \
15131    ((INSTANCE) == TIM3)    || \
15132    ((INSTANCE) == TIM6)    || \
15133    ((INSTANCE) == TIM7)    || \
15134    ((INSTANCE) == TIM15)   || \
15135    ((INSTANCE) == TIM16)   || \
15136    ((INSTANCE) == TIM17))
15137 
15138 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */
15139 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
15140   (((INSTANCE) == TIM1)    || \
15141    ((INSTANCE) == TIM2)    || \
15142    ((INSTANCE) == TIM3)    || \
15143    ((INSTANCE) == TIM15)   || \
15144    ((INSTANCE) == TIM16)   || \
15145    ((INSTANCE) == TIM17))
15146 
15147 /****************** TIM Instances : supporting commutation event generation ***/
15148 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
15149   (((INSTANCE) == TIM1)    || \
15150    ((INSTANCE) == TIM15)   || \
15151    ((INSTANCE) == TIM16)   || \
15152    ((INSTANCE) == TIM17))
15153 
15154 /****************** TIM Instances : supporting remapping capability ***********/
15155 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
15156   (((INSTANCE) == TIM1)    || \
15157    ((INSTANCE) == TIM16))
15158 
15159 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
15160 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
15161   (((INSTANCE) == TIM1))
15162 
15163 /****************************** TSC Instances *********************************/
15164 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
15165 
15166 /******************** USART Instances : Synchronous mode **********************/
15167 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15168                                      ((INSTANCE) == USART2) || \
15169                                      ((INSTANCE) == USART3))
15170 
15171 /****************** USART Instances : Auto Baud Rate detection ****************/
15172 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
15173 
15174 /******************** UART Instances : Asynchronous mode **********************/
15175 #define IS_UART_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
15176                                       ((INSTANCE) == USART2) || \
15177                                       ((INSTANCE) == USART3))
15178 
15179 /******************** UART Instances : Half-Duplex mode **********************/
15180 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
15181                                                  ((INSTANCE) == USART2) || \
15182                                                  ((INSTANCE) == USART3))
15183 
15184 /******************** UART Instances : LIN mode **********************/
15185 #define IS_UART_LIN_INSTANCE(INSTANCE)   ((INSTANCE) == USART1)
15186 
15187 /******************** UART Instances : Wake-up from Stop mode **********************/
15188 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   ((INSTANCE) == USART1)
15189 
15190 /****************** UART Instances : Hardware Flow control ********************/
15191 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15192                                            ((INSTANCE) == USART2) || \
15193                                            ((INSTANCE) == USART3))
15194 
15195 /****************** UART Instances : Auto Baud Rate detection *****************/
15196 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
15197 
15198 /****************** UART Instances : Driver Enable ****************************/
15199 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15200                                                   ((INSTANCE) == USART2) || \
15201                                                   ((INSTANCE) == USART3))
15202 
15203 /********************* UART Instances : Smard card mode ***********************/
15204 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
15205 
15206 /*********************** UART Instances : IRDA mode ***************************/
15207 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
15208 
15209 /******************** UART Instances : Support of continuous communication using DMA ****/
15210 #define IS_UART_DMA_INSTANCE(INSTANCE) (1)
15211 /****************************** WWDG Instances ********************************/
15212 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
15213 
15214 /**
15215   * @}
15216   */
15217 
15218 
15219 /******************************************************************************/
15220 /*  For a painless codes migration between the STM32F3xx device product       */
15221 /*  lines, the aliases defined below are put in place to overcome the         */
15222 /*  differences in the interrupt handlers and IRQn definitions.               */
15223 /*  No need to update developed interrupt code when moving across             */
15224 /*  product lines within the same STM32F3 Family                              */
15225 /******************************************************************************/
15226 
15227 /* Aliases for __IRQn */
15228 #define ADC1_IRQn           ADC1_2_IRQn
15229 #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
15230 #define USB_HP_CAN_TX_IRQn  CAN_TX_IRQn
15231 #define COMP_IRQn           COMP2_IRQn
15232 #define COMP1_2_3_IRQn      COMP2_IRQn
15233 #define COMP1_2_IRQn        COMP2_IRQn
15234 #define COMP4_5_6_IRQn      COMP4_6_IRQn
15235 #define I2C3_ER_IRQn        HRTIM1_FLT_IRQn
15236 #define I2C3_EV_IRQn        HRTIM1_TIME_IRQn
15237 #define TIM15_IRQn          TIM1_BRK_TIM15_IRQn
15238 #define TIM18_DAC2_IRQn     TIM1_CC_IRQn
15239 #define TIM17_IRQn          TIM1_TRG_COM_TIM17_IRQn
15240 #define TIM16_IRQn          TIM1_UP_TIM16_IRQn
15241 #define TIM6_DAC_IRQn       TIM6_DAC1_IRQn
15242 #define TIM7_IRQn           TIM7_DAC2_IRQn
15243 
15244 
15245 /* Aliases for __IRQHandler */
15246 #define ADC1_IRQHandler           ADC1_2_IRQHandler
15247 #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
15248 #define USB_HP_CAN_TX_IRQHandler  CAN_TX_IRQHandler
15249 #define COMP_IRQHandler           COMP2_IRQHandler
15250 #define COMP1_2_3_IRQHandler      COMP2_IRQHandler
15251 #define COMP1_2_IRQHandler        COMP2_IRQHandler
15252 #define COMP4_5_6_IRQHandler      COMP4_6_IRQHandler
15253 #define I2C3_ER_IRQHandler        HRTIM1_FLT_IRQHandler
15254 #define I2C3_EV_IRQHandler        HRTIM1_TIME_IRQHandler
15255 #define TIM15_IRQHandler          TIM1_BRK_TIM15_IRQHandler
15256 #define TIM18_DAC2_IRQHandler     TIM1_CC_IRQHandler
15257 #define TIM17_IRQHandler          TIM1_TRG_COM_TIM17_IRQHandler
15258 #define TIM16_IRQHandler          TIM1_UP_TIM16_IRQHandler
15259 #define TIM6_DAC_IRQHandler       TIM6_DAC1_IRQHandler
15260 #define TIM7_IRQHandler           TIM7_DAC2_IRQHandler
15261 
15262 
15263 #ifdef __cplusplus
15264 }
15265 #endif /* __cplusplus */
15266 
15267 #endif /* __STM32F334x8_H */
15268 
15269 /**
15270   * @}
15271   */
15272 
15273   /**
15274   * @}
15275   */
15276 
15277 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
15278