1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_dac.h 4 * @author MCD Application Team 5 * @brief Header file of DAC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H5xx_HAL_DAC_H 21 #define STM32H5xx_HAL_DAC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /** @addtogroup STM32H5xx_HAL_Driver 28 * @{ 29 */ 30 31 /* Includes ------------------------------------------------------------------*/ 32 #include "stm32h5xx_hal_def.h" 33 34 #if defined(DAC1) 35 36 /** @addtogroup DAC 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 42 /** @defgroup DAC_Exported_Types DAC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief HAL State structures definition 48 */ 49 typedef enum 50 { 51 HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ 52 HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ 53 HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ 54 HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ 55 HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ 56 57 } HAL_DAC_StateTypeDef; 58 59 /** 60 * @brief DAC handle Structure definition 61 */ 62 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 63 typedef struct __DAC_HandleTypeDef 64 #else 65 typedef struct 66 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 67 { 68 DAC_TypeDef *Instance; /*!< Register base address */ 69 70 __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ 71 72 HAL_LockTypeDef Lock; /*!< DAC locking object */ 73 74 DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ 75 76 DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ 77 78 __IO uint32_t ErrorCode; /*!< DAC Error code */ 79 80 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 81 void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); 82 void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); 83 void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); 84 void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); 85 86 void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); 87 void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); 88 void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); 89 void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); 90 91 92 void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); 93 void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); 94 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 95 96 } DAC_HandleTypeDef; 97 98 /** 99 * @brief DAC Configuration sample and hold Channel structure definition 100 */ 101 typedef struct 102 { 103 uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel. 104 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 105 This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ 106 107 uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel 108 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 109 This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ 110 111 uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel 112 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 113 This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ 114 } DAC_SampleAndHoldConfTypeDef; 115 116 /** 117 * @brief DAC Configuration regular Channel structure definition 118 */ 119 typedef struct 120 { 121 uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode 122 This parameter can be a value of @ref DAC_HighFrequency */ 123 124 FunctionalState DAC_DMADoubleDataMode; /*!< Specifies if DMA double data mode should be enabled or not for the selected channel. 125 This parameter can be ENABLE or DISABLE */ 126 127 FunctionalState DAC_SignedFormat; /*!< Specifies if signed format should be used or not for the selected channel. 128 This parameter can be ENABLE or DISABLE */ 129 130 uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. 131 This parameter can be a value of @ref DAC_SampleAndHold */ 132 133 uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. 134 This parameter can be a value of @ref DAC_trigger_selection */ 135 136 uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. 137 This parameter can be a value of @ref DAC_output_buffer */ 138 139 uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral. 140 This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ 141 142 uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode 143 This parameter must be a value of @ref DAC_UserTrimming 144 DAC_UserTrimming is either factory or user trimming */ 145 146 uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value 147 i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. 148 This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ 149 DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ 150 } DAC_ChannelConfTypeDef; 151 152 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 153 /** 154 * @brief HAL DAC Callback ID enumeration definition 155 */ 156 typedef enum 157 { 158 HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */ 159 HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ 160 HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ 161 HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ 162 163 HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ 164 HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ 165 HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ 166 HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ 167 168 HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ 169 HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ 170 HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ 171 } HAL_DAC_CallbackIDTypeDef; 172 173 /** 174 * @brief HAL DAC Callback pointer definition 175 */ 176 typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); 177 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 178 179 /** 180 * @} 181 */ 182 183 /* Exported constants --------------------------------------------------------*/ 184 185 /** @defgroup DAC_Exported_Constants DAC Exported Constants 186 * @{ 187 */ 188 189 /** @defgroup DAC_Error_Code DAC Error Code 190 * @{ 191 */ 192 #define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ 193 #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */ 194 #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */ 195 #define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ 196 #define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */ 197 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 198 #define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */ 199 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 200 #define HAL_DAC_ERROR_INVALID_CONFIG 0x20U /*!< Invalid configuration error */ 201 202 /** 203 * @} 204 */ 205 206 /** @defgroup DAC_trigger_selection DAC trigger selection 207 * @{ 208 */ 209 /* Triggers common to all devices of STM32H5 series */ 210 #define DAC_TRIGGER_NONE 0x00000000UL /*!< conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ 211 #define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< conversion started by software trigger for DAC channel */ 212 #define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel. */ 213 #define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ 214 #define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ 215 #define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ 216 #define DAC_TRIGGER_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 CH1 selected as external conversion trigger for DAC channel */ 217 #define DAC_TRIGGER_LPTIM2_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2 CH1 selected as external conversion trigger for DAC channel */ 218 #define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ 219 220 /* Triggers specific to some devices of STM32H5 series */ 221 #if defined(TIM8) 222 /* Devices STM32H563/H573xx */ 223 #define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ 224 #define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ 225 #define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ 226 #define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ 227 228 #else 229 /* Devices STM32H503xx */ 230 #define DAC_TRIGGER_T3_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */ 231 232 #endif /* Devices STM32H563/H573xx or STM32H503xx */ 233 234 /** 235 * @} 236 */ 237 238 /** @defgroup DAC_output_buffer DAC output buffer 239 * @{ 240 */ 241 #define DAC_OUTPUTBUFFER_ENABLE 0x00000000U 242 #define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1) 243 244 /** 245 * @} 246 */ 247 248 /** @defgroup DAC_Channel_selection DAC Channel selection 249 * @{ 250 */ 251 #define DAC_CHANNEL_1 0x00000000U 252 253 #define DAC_CHANNEL_2 0x00000010U 254 255 /** 256 * @} 257 */ 258 259 /** @defgroup DAC_data_alignment DAC data alignment 260 * @{ 261 */ 262 #define DAC_ALIGN_12B_R 0x00000000U 263 #define DAC_ALIGN_12B_L 0x00000004U 264 #define DAC_ALIGN_8B_R 0x00000008U 265 266 /** 267 * @} 268 */ 269 270 /** @defgroup DAC_flags_definition DAC flags definition 271 * @{ 272 */ 273 #define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) 274 275 #define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) 276 277 #define DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY) 278 279 #define DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY) 280 281 282 /** 283 * @} 284 */ 285 286 /** @defgroup DAC_IT_definition DAC IT definition 287 * @{ 288 */ 289 #define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1) 290 291 #define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2) 292 293 294 /** 295 * @} 296 */ 297 298 /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral 299 * @{ 300 */ 301 #define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) 302 #define DAC_CHIPCONNECT_INTERNAL (1UL << 1) 303 #define DAC_CHIPCONNECT_BOTH (1UL << 2) 304 305 /** 306 * @} 307 */ 308 309 /** @defgroup DAC_UserTrimming DAC User Trimming 310 * @{ 311 */ 312 #define DAC_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */ 313 #define DAC_TRIMMING_USER (0x00000001UL) /*!< User trimming */ 314 /** 315 * @} 316 */ 317 318 /** @defgroup DAC_SampleAndHold DAC power mode 319 * @{ 320 */ 321 #define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL) 322 #define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2) 323 324 /** 325 * @} 326 */ 327 /** @defgroup DAC_HighFrequency DAC high frequency interface mode 328 * @{ 329 */ 330 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */ 331 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */ 332 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */ 333 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002UL /*!< High frequency interface mode automatic */ 334 335 /** 336 * @} 337 */ 338 339 /** 340 * @} 341 */ 342 343 /* Delay for DAC channel voltage settling time from DAC channel startup */ 344 /* (transition from disable to enable). */ 345 /* Note: DAC channel startup time depends on board application environment: */ 346 /* impedance connected to DAC channel output. */ 347 /* The delay below is specified under conditions: */ 348 /* - voltage maximum transition (lowest to highest value) */ 349 /* - until voltage reaches final value +-1LSB */ 350 /* - DAC channel output buffer enabled */ 351 /* - load impedance of 5kOhm (min), 50pF (max) */ 352 /* Literal set to maximum value (refer to device datasheet, */ 353 /* parameter "tWAKEUP"). */ 354 /* Unit: us */ 355 #define DAC_DELAY_STARTUP_US (15UL) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ 356 357 /* Exported macro ------------------------------------------------------------*/ 358 359 /** @defgroup DAC_Exported_Macros DAC Exported Macros 360 * @{ 361 */ 362 363 /** @brief Reset DAC handle state. 364 * @param __HANDLE__ specifies the DAC handle. 365 * @retval None 366 */ 367 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 368 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \ 369 (__HANDLE__)->State = HAL_DAC_STATE_RESET; \ 370 (__HANDLE__)->MspInitCallback = NULL; \ 371 (__HANDLE__)->MspDeInitCallback = NULL; \ 372 } while(0) 373 #else 374 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) 375 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 376 377 /** @brief Enable the DAC channel. 378 * @param __HANDLE__ specifies the DAC handle. 379 * @param __DAC_Channel__ specifies the DAC channel 380 * @retval None 381 */ 382 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ 383 ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) 384 385 /** @brief Disable the DAC channel. 386 * @param __HANDLE__ specifies the DAC handle 387 * @param __DAC_Channel__ specifies the DAC channel. 388 * @retval None 389 */ 390 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ 391 ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) 392 393 /** @brief Set DHR12R1 alignment. 394 * @param __ALIGNMENT__ specifies the DAC alignment 395 * @retval None 396 */ 397 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__)) 398 399 400 /** @brief Set DHR12R2 alignment. 401 * @param __ALIGNMENT__ specifies the DAC alignment 402 * @retval None 403 */ 404 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__)) 405 406 407 /** @brief Set DHR12RD alignment. 408 * @param __ALIGNMENT__ specifies the DAC alignment 409 * @retval None 410 */ 411 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__)) 412 413 /** @brief Enable the DAC interrupt. 414 * @param __HANDLE__ specifies the DAC handle 415 * @param __INTERRUPT__ specifies the DAC interrupt. 416 * This parameter can be any combination of the following values: 417 * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt 418 * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt 419 * @retval None 420 */ 421 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) 422 423 /** @brief Disable the DAC interrupt. 424 * @param __HANDLE__ specifies the DAC handle 425 * @param __INTERRUPT__ specifies the DAC interrupt. 426 * This parameter can be any combination of the following values: 427 * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt 428 * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt 429 * @retval None 430 */ 431 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) 432 433 /** @brief Check whether the specified DAC interrupt source is enabled or not. 434 * @param __HANDLE__ DAC handle 435 * @param __INTERRUPT__ DAC interrupt source to check 436 * This parameter can be any combination of the following values: 437 * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt 438 * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt 439 * @retval State of interruption (SET or RESET) 440 */ 441 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ 442 & (__INTERRUPT__)) == (__INTERRUPT__)) 443 444 /** @brief Get the selected DAC's flag status. 445 * @param __HANDLE__ specifies the DAC handle. 446 * @param __FLAG__ specifies the DAC flag to get. 447 * This parameter can be any combination of the following values: 448 * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag 449 * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag 450 * @arg DAC_FLAG_DAC1RDY DAC channel 1 ready status flag 451 * @arg DAC_FLAG_DAC2RDY DAC channel 2 ready status flag 452 * @retval None 453 */ 454 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 455 456 /** @brief Clear the DAC's flag. 457 * @param __HANDLE__ specifies the DAC handle. 458 * @param __FLAG__ specifies the DAC flag to clear. 459 * This parameter can be any combination of the following values: 460 * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag 461 * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag 462 * @retval None 463 */ 464 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) 465 466 /** 467 * @} 468 */ 469 470 /* Private macro -------------------------------------------------------------*/ 471 472 /** @defgroup DAC_Private_Macros DAC Private Macros 473 * @{ 474 */ 475 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ 476 ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) 477 478 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ 479 ((CHANNEL) == DAC_CHANNEL_2)) 480 481 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ 482 ((ALIGN) == DAC_ALIGN_12B_L) || \ 483 ((ALIGN) == DAC_ALIGN_8B_R)) 484 485 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL) 486 487 #define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL) 488 489 /** 490 * @} 491 */ 492 493 /* Include DAC HAL Extended module */ 494 #include "stm32h5xx_hal_dac_ex.h" 495 496 /* Exported functions --------------------------------------------------------*/ 497 498 /** @addtogroup DAC_Exported_Functions 499 * @{ 500 */ 501 502 /** @addtogroup DAC_Exported_Functions_Group1 503 * @{ 504 */ 505 /* Initialization and de-initialization functions *****************************/ 506 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac); 507 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac); 508 void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac); 509 void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); 510 511 /** 512 * @} 513 */ 514 515 /** @addtogroup DAC_Exported_Functions_Group2 516 * @{ 517 */ 518 /* IO operation functions *****************************************************/ 519 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); 520 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); 521 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, 522 uint32_t Alignment); 523 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); 524 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); 525 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); 526 527 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac); 528 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac); 529 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); 530 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); 531 532 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 533 /* DAC callback registering/unregistering */ 534 HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, 535 pDAC_CallbackTypeDef pCallback); 536 HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); 537 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 538 539 /** 540 * @} 541 */ 542 543 /** @addtogroup DAC_Exported_Functions_Group3 544 * @{ 545 */ 546 /* Peripheral Control functions ***********************************************/ 547 uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel); 548 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, 549 const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); 550 /** 551 * @} 552 */ 553 554 /** @addtogroup DAC_Exported_Functions_Group4 555 * @{ 556 */ 557 /* Peripheral State and Error functions ***************************************/ 558 HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac); 559 uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac); 560 561 /** 562 * @} 563 */ 564 565 /** 566 * @} 567 */ 568 569 /** @defgroup DAC_Private_Functions DAC Private Functions 570 * @{ 571 */ 572 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); 573 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); 574 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); 575 /** 576 * @} 577 */ 578 579 /** 580 * @} 581 */ 582 583 #endif /* DAC1 */ 584 585 /** 586 * @} 587 */ 588 589 #ifdef __cplusplus 590 } 591 #endif 592 593 594 #endif /* STM32H5xx_HAL_DAC_H */ 595
