1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_dac.h 4 * @author MCD Application Team 5 * @brief Header file of DAC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32G4xx_HAL_DAC_H 21 #define STM32G4xx_HAL_DAC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /** @addtogroup STM32G4xx_HAL_Driver 28 * @{ 29 */ 30 31 /* Includes ------------------------------------------------------------------*/ 32 #include "stm32g4xx_hal_def.h" 33 34 #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4) 35 36 /** @addtogroup DAC 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 42 /** @defgroup DAC_Exported_Types DAC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief HAL State structures definition 48 */ 49 typedef enum 50 { 51 HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ 52 HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ 53 HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ 54 HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ 55 HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ 56 57 } HAL_DAC_StateTypeDef; 58 59 /** 60 * @brief DAC handle Structure definition 61 */ 62 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 63 typedef struct __DAC_HandleTypeDef 64 #else 65 typedef struct 66 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 67 { 68 DAC_TypeDef *Instance; /*!< Register base address */ 69 70 __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ 71 72 HAL_LockTypeDef Lock; /*!< DAC locking object */ 73 74 DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ 75 76 DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ 77 78 __IO uint32_t ErrorCode; /*!< DAC Error code */ 79 80 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 81 void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); 82 void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); 83 void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); 84 void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); 85 86 void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); 87 void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); 88 void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); 89 void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); 90 91 92 void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); 93 void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); 94 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 95 96 } DAC_HandleTypeDef; 97 98 /** 99 * @brief DAC Configuration sample and hold Channel structure definition 100 */ 101 typedef struct 102 { 103 uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel. 104 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 105 This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ 106 107 uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel 108 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 109 This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ 110 111 uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel 112 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 113 This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ 114 } DAC_SampleAndHoldConfTypeDef; 115 116 /** 117 * @brief DAC Configuration regular Channel structure definition 118 */ 119 typedef struct 120 { 121 uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode 122 This parameter can be a value of @ref DAC_HighFrequency */ 123 124 FunctionalState DAC_DMADoubleDataMode; /*!< Specifies if DMA double data mode should be enabled or not for the selected channel. 125 This parameter can be ENABLE or DISABLE */ 126 127 FunctionalState DAC_SignedFormat; /*!< Specifies if signed format should be used or not for the selected channel. 128 This parameter can be ENABLE or DISABLE */ 129 130 uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. 131 This parameter can be a value of @ref DAC_SampleAndHold */ 132 133 uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. 134 This parameter can be a value of @ref DAC_trigger_selection. 135 Note: In case of sawtooth wave generation, this 136 trigger corresponds to the reset trigger. */ 137 138 uint32_t DAC_Trigger2; /*!< Specifies the external secondary trigger for the selected DAC channel. 139 This parameter can be a value of @ref DAC_trigger_selection. 140 Note: In case of sawtooth wave generation, this 141 trigger corresponds to the step trigger.*/ 142 143 uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. 144 This parameter can be a value of @ref DAC_output_buffer */ 145 146 uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral. 147 This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ 148 149 uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode 150 This parameter must be a value of @ref DAC_UserTrimming 151 DAC_UserTrimming is either factory or user trimming */ 152 153 uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value 154 i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. 155 This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ 156 DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ 157 } DAC_ChannelConfTypeDef; 158 159 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 160 /** 161 * @brief HAL DAC Callback ID enumeration definition 162 */ 163 typedef enum 164 { 165 HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */ 166 HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ 167 HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ 168 HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ 169 170 HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ 171 HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ 172 HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ 173 HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ 174 175 HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ 176 HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ 177 HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ 178 } HAL_DAC_CallbackIDTypeDef; 179 180 /** 181 * @brief HAL DAC Callback pointer definition 182 */ 183 typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); 184 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 185 186 /** 187 * @} 188 */ 189 190 /* Exported constants --------------------------------------------------------*/ 191 192 /** @defgroup DAC_Exported_Constants DAC Exported Constants 193 * @{ 194 */ 195 196 /** @defgroup DAC_Error_Code DAC Error Code 197 * @{ 198 */ 199 #define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ 200 #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */ 201 #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */ 202 #define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ 203 #define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */ 204 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 205 #define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */ 206 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 207 208 /** 209 * @} 210 */ 211 212 /** @defgroup DAC_trigger_selection DAC trigger selection 213 * @{ 214 */ 215 #define DAC_TRIGGER_NONE 0x00000000UL /*!< DAC (all) conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ 216 #define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< DAC (all) conversion started by software trigger for DAC channel */ 217 #define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: TIM1 TRGO selected as external conversion trigger for DAC channel. */ 218 #define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1/2/4: TIM8 TRGO selected as external conversion trigger for DAC channel. Refer to device datasheet for DACx availability. */ 219 #define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): TIM7 TRGO selected as external conversion trigger for DAC channel */ 220 #define DAC_TRIGGER_T15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM15 TRGO selected as external conversion trigger for DAC channel */ 221 #define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): TIM2 TRGO selected as external conversion trigger for DAC channel */ 222 #define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM4 TRGO selected as external conversion trigger for DAC channel */ 223 #define DAC_TRIGGER_EXT_IT9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): EXTI Line9 event selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger */ 224 #define DAC_TRIGGER_EXT_IT10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): EXTI Line10 event selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger */ 225 #define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM6 TRGO selected as external conversion trigger for DAC channel */ 226 #define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< DAC (all): TIM3 TRGO selected as external conversion trigger for DAC channel */ 227 #define DAC_TRIGGER_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ 228 #define DAC_TRIGGER_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ 229 #define DAC_TRIGGER_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ 230 #define DAC_TRIGGER_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ 231 #define DAC_TRIGGER_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ 232 #define DAC_TRIGGER_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ 233 #define DAC_TRIGGER_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ 234 #define DAC_TRIGGER_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ 235 #define DAC_TRIGGER_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ 236 #define DAC_TRIGGER_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ 237 #define DAC_TRIGGER_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ 238 #define DAC_TRIGGER_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ 239 #define DAC_TRIGGER_HRTIM_TRG01 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1&4: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ 240 #define DAC_TRIGGER_HRTIM_TRG02 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC2: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */ 241 #define DAC_TRIGGER_HRTIM_TRG03 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ 242 243 /** 244 * @} 245 */ 246 247 /** @defgroup DAC_output_buffer DAC output buffer 248 * @{ 249 */ 250 #define DAC_OUTPUTBUFFER_ENABLE 0x00000000U 251 #define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1) 252 253 /** 254 * @} 255 */ 256 257 /** @defgroup DAC_Channel_selection DAC Channel selection 258 * @{ 259 */ 260 #define DAC_CHANNEL_1 0x00000000U 261 262 #define DAC_CHANNEL_2 0x00000010U 263 264 /** 265 * @} 266 */ 267 268 /** @defgroup DAC_data_alignment DAC data alignment 269 * @{ 270 */ 271 #define DAC_ALIGN_12B_R 0x00000000U 272 #define DAC_ALIGN_12B_L 0x00000004U 273 #define DAC_ALIGN_8B_R 0x00000008U 274 275 /** 276 * @} 277 */ 278 279 /** @defgroup DAC_flags_definition DAC flags definition 280 * @{ 281 */ 282 #define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) 283 284 #define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) 285 286 #define DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY) 287 288 #define DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY) 289 290 291 /** 292 * @} 293 */ 294 295 /** @defgroup DAC_IT_definition DAC IT definition 296 * @{ 297 */ 298 #define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1) 299 300 #define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2) 301 302 303 /** 304 * @} 305 */ 306 307 /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral 308 * @{ 309 */ 310 #define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) /*!< DAC channel output is connected to an external pin.*/ 311 #define DAC_CHIPCONNECT_INTERNAL (1UL << 1) /*!< DAC channel output is connected to on-chip peripherals (via 312 internal paths) and to an external pin. */ 313 #define DAC_CHIPCONNECT_BOTH (1UL << 2) /*!< DAC channel output is connected to on-chip peripherals (via 314 internal paths) and to an external pin. 315 Note: this connection is not available in mode normal 316 with buffer disabled. */ 317 /** 318 * @} 319 */ 320 321 /** @defgroup DAC_UserTrimming DAC User Trimming 322 * @{ 323 */ 324 #define DAC_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */ 325 #define DAC_TRIMMING_USER (0x00000001UL) /*!< User trimming */ 326 /** 327 * @} 328 */ 329 330 /** @defgroup DAC_SampleAndHold DAC power mode 331 * @{ 332 */ 333 #define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL) 334 #define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2) 335 336 /** 337 * @} 338 */ 339 /** @defgroup DAC_HighFrequency DAC high frequency interface mode 340 * @{ 341 */ 342 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */ 343 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */ 344 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */ 345 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002UL /*!< High frequency interface mode automatic */ 346 347 /** 348 * @} 349 */ 350 351 /** 352 * @} 353 */ 354 355 /* Delay for DAC channel voltage settling time from DAC channel startup */ 356 /* (transition from disable to enable). */ 357 /* Note: DAC channel startup time depends on board application environment: */ 358 /* impedance connected to DAC channel output. */ 359 /* The delay below is specified under conditions: */ 360 /* - voltage maximum transition (lowest to highest value) */ 361 /* - until voltage reaches final value +-1LSB */ 362 /* - DAC channel output buffer enabled */ 363 /* - load impedance of 5kOhm (min), 50pF (max) */ 364 /* Literal set to maximum value (refer to device datasheet, */ 365 /* parameter "tWAKEUP"). */ 366 /* Unit: us */ 367 #define DAC_DELAY_STARTUP_US (15UL) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ 368 369 /* Exported macro ------------------------------------------------------------*/ 370 371 /** @defgroup DAC_Exported_Macros DAC Exported Macros 372 * @{ 373 */ 374 375 /** @brief Reset DAC handle state. 376 * @param __HANDLE__ specifies the DAC handle. 377 * @retval None 378 */ 379 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 380 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \ 381 (__HANDLE__)->State = HAL_DAC_STATE_RESET; \ 382 (__HANDLE__)->MspInitCallback = NULL; \ 383 (__HANDLE__)->MspDeInitCallback = NULL; \ 384 } while(0) 385 #else 386 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) 387 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 388 389 /** @brief Enable the DAC channel. 390 * @param __HANDLE__ specifies the DAC handle. 391 * @param __DAC_Channel__ specifies the DAC channel 392 * @retval None 393 */ 394 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ 395 ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) 396 397 /** @brief Disable the DAC channel. 398 * @param __HANDLE__ specifies the DAC handle 399 * @param __DAC_Channel__ specifies the DAC channel. 400 * @retval None 401 */ 402 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ 403 ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) 404 405 /** @brief Set DHR12R1 alignment. 406 * @param __ALIGNMENT__ specifies the DAC alignment 407 * @retval None 408 */ 409 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__)) 410 411 412 /** @brief Set DHR12R2 alignment. 413 * @param __ALIGNMENT__ specifies the DAC alignment 414 * @retval None 415 */ 416 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__)) 417 418 419 /** @brief Set DHR12RD alignment. 420 * @param __ALIGNMENT__ specifies the DAC alignment 421 * @retval None 422 */ 423 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__)) 424 425 /** @brief Enable the DAC interrupt. 426 * @param __HANDLE__ specifies the DAC handle 427 * @param __INTERRUPT__ specifies the DAC interrupt. 428 * This parameter can be any combination of the following values: 429 * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt 430 * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1) 431 * 432 * (1) On this STM32 series, parameter not available on all instances. 433 * Refer to device datasheet for channels availability. 434 * @retval None 435 */ 436 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) 437 438 /** @brief Disable the DAC interrupt. 439 * @param __HANDLE__ specifies the DAC handle 440 * @param __INTERRUPT__ specifies the DAC interrupt. 441 * This parameter can be any combination of the following values: 442 * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt 443 * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1) 444 * 445 * (1) On this STM32 series, parameter not available on all instances. 446 * Refer to device datasheet for channels availability. 447 * @retval None 448 */ 449 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) 450 451 /** @brief Check whether the specified DAC interrupt source is enabled or not. 452 * @param __HANDLE__ DAC handle 453 * @param __INTERRUPT__ DAC interrupt source to check 454 * This parameter can be any combination of the following values: 455 * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt 456 * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1) 457 * 458 * (1) On this STM32 series, parameter not available on all instances. 459 * Refer to device datasheet for channels availability. 460 * @retval State of interruption (SET or RESET) 461 */ 462 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ 463 & (__INTERRUPT__)) == (__INTERRUPT__)) 464 465 /** @brief Get the selected DAC's flag status. 466 * @param __HANDLE__ specifies the DAC handle. 467 * @param __FLAG__ specifies the DAC flag to get. 468 * This parameter can be any combination of the following values: 469 * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag 470 * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1) 471 * @arg DAC_FLAG_DAC1RDY DAC channel 1 ready status flag 472 * @arg DAC_FLAG_DAC2RDY DAC channel 2 ready status flag (1) 473 * 474 * (1) On this STM32 series, parameter not available on all instances. 475 * Refer to device datasheet for channels availability. 476 * @retval None 477 */ 478 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 479 480 /** @brief Clear the DAC's flag. 481 * @param __HANDLE__ specifies the DAC handle. 482 * @param __FLAG__ specifies the DAC flag to clear. 483 * This parameter can be any combination of the following values: 484 * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag 485 * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1) 486 * 487 * (1) On this STM32 series, parameter not available on all instances. 488 * Refer to device datasheet for channels availability. 489 * @retval None 490 */ 491 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) 492 493 /** 494 * @} 495 */ 496 497 /* Private macro -------------------------------------------------------------*/ 498 499 /** @defgroup DAC_Private_Macros DAC Private Macros 500 * @{ 501 */ 502 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ 503 ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) 504 505 #if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) 506 #define IS_DAC_CHANNEL(DACX, CHANNEL) \ 507 (((DACX) == DAC2) ? \ 508 ((CHANNEL) == DAC_CHANNEL_1) \ 509 : \ 510 (((CHANNEL) == DAC_CHANNEL_1) || \ 511 ((CHANNEL) == DAC_CHANNEL_2))) 512 #elif defined(STM32G411xB) || defined(STM32G411xC) 513 #define IS_DAC_CHANNEL(DACX, CHANNEL) \ 514 (((DACX) == DAC1) ? \ 515 ((CHANNEL) == DAC_CHANNEL_1) \ 516 : \ 517 (((CHANNEL) == DAC_CHANNEL_1) || \ 518 ((CHANNEL) == DAC_CHANNEL_2))) 519 #else 520 #define IS_DAC_CHANNEL(DACX, CHANNEL) \ 521 (((CHANNEL) == DAC_CHANNEL_1) || \ 522 ((CHANNEL) == DAC_CHANNEL_2)) 523 #endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx */ 524 525 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ 526 ((ALIGN) == DAC_ALIGN_12B_L) || \ 527 ((ALIGN) == DAC_ALIGN_8B_R)) 528 529 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL) 530 531 #define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL) 532 533 /** 534 * @} 535 */ 536 537 /* Include DAC HAL Extended module */ 538 #include "stm32g4xx_hal_dac_ex.h" 539 540 /* Exported functions --------------------------------------------------------*/ 541 542 /** @addtogroup DAC_Exported_Functions 543 * @{ 544 */ 545 546 /** @addtogroup DAC_Exported_Functions_Group1 547 * @{ 548 */ 549 /* Initialization and de-initialization functions *****************************/ 550 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac); 551 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac); 552 void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac); 553 void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); 554 555 /** 556 * @} 557 */ 558 559 /** @addtogroup DAC_Exported_Functions_Group2 560 * @{ 561 */ 562 /* IO operation functions *****************************************************/ 563 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); 564 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); 565 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, 566 uint32_t Alignment); 567 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); 568 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); 569 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); 570 571 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac); 572 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac); 573 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); 574 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); 575 576 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 577 /* DAC callback registering/unregistering */ 578 HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, 579 pDAC_CallbackTypeDef pCallback); 580 HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); 581 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 582 583 /** 584 * @} 585 */ 586 587 /** @addtogroup DAC_Exported_Functions_Group3 588 * @{ 589 */ 590 /* Peripheral Control functions ***********************************************/ 591 uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel); 592 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, 593 const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); 594 /** 595 * @} 596 */ 597 598 /** @addtogroup DAC_Exported_Functions_Group4 599 * @{ 600 */ 601 /* Peripheral State and Error functions ***************************************/ 602 HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac); 603 uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac); 604 605 /** 606 * @} 607 */ 608 609 /** 610 * @} 611 */ 612 613 /** @defgroup DAC_Private_Functions DAC Private Functions 614 * @{ 615 */ 616 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); 617 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); 618 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); 619 /** 620 * @} 621 */ 622 623 /** 624 * @} 625 */ 626 627 #endif /* DAC1 || DAC2 || DAC3 || DAC4 */ 628 629 /** 630 * @} 631 */ 632 633 #ifdef __cplusplus 634 } 635 #endif 636 637 638 #endif /* STM32G4xx_HAL_DAC_H */ 639
