1 /* 2 ** ################################################################### 3 ** Processors: LPC845M301JBD48 4 ** LPC845M301JBD64 5 ** LPC845M301JHI33 6 ** LPC845M301JHI48 7 ** 8 ** Compilers: GNU C Compiler 9 ** IAR ANSI C/C++ Compiler for ARM 10 ** Keil ARM C/C++ Compiler 11 ** MCUXpresso Compiler 12 ** 13 ** Reference manual: LPC84x User manual Rev.1.6 8 Dec 2017 14 ** Version: rev. 1.2, 2017-06-08 15 ** Build: b201029 16 ** 17 ** Abstract: 18 ** CMSIS Peripheral Access Layer for LPC845 19 ** 20 ** Copyright 1997-2016 Freescale Semiconductor, Inc. 21 ** Copyright 2016-2020 NXP 22 ** All rights reserved. 23 ** 24 ** SPDX-License-Identifier: BSD-3-Clause 25 ** 26 ** http: www.nxp.com 27 ** mail: support@nxp.com 28 ** 29 ** Revisions: 30 ** - rev. 1.0 (2016-08-12) 31 ** Initial version. 32 ** - rev. 1.1 (2016-11-25) 33 ** Update CANFD and Classic CAN register. 34 ** Add MAC TIMERSTAMP registers. 35 ** - rev. 1.2 (2017-06-08) 36 ** Remove RTC_CTRL_RTC_OSC_BYPASS. 37 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. 38 ** Remove RESET and HALT from SYSCON_AHBCLKDIV. 39 ** 40 ** ################################################################### 41 */ 42 43 /*! 44 * @file LPC845.h 45 * @version 1.2 46 * @date 2017-06-08 47 * @brief CMSIS Peripheral Access Layer for LPC845 48 * 49 * CMSIS Peripheral Access Layer for LPC845 50 */ 51 52 #ifndef _LPC845_H_ 53 #define _LPC845_H_ /**< Symbol preventing repeated inclusion */ 54 55 /** Memory map major version (memory maps with equal major version number are 56 * compatible) */ 57 #define MCU_MEM_MAP_VERSION 0x0100U 58 /** Memory map minor version */ 59 #define MCU_MEM_MAP_VERSION_MINOR 0x0002U 60 61 62 /* ---------------------------------------------------------------------------- 63 -- Interrupt vector numbers 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 68 * @{ 69 */ 70 71 /** Interrupt Number Definitions */ 72 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ 73 74 typedef enum IRQn { 75 /* Auxiliary constants */ 76 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 77 78 /* Core interrupts */ 79 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 80 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ 81 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ 82 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ 83 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ 84 85 /* Device specific interrupts */ 86 SPI0_IRQn = 0, /**< SPI0 interrupt */ 87 SPI1_IRQn = 1, /**< SPI1 interrupt */ 88 DAC0_IRQn = 2, /**< DAC0 interrupt */ 89 USART0_IRQn = 3, /**< USART0 interrupt */ 90 USART1_IRQn = 4, /**< USART1 interrupt */ 91 USART2_IRQn = 5, /**< USART2 interrupt */ 92 Reserved22_IRQn = 6, /**< Reserved interrupt */ 93 I2C1_IRQn = 7, /**< I2C1 interrupt */ 94 I2C0_IRQn = 8, /**< I2C0 interrupt */ 95 SCT0_IRQn = 9, /**< State configurable timer interrupt */ 96 MRT0_IRQn = 10, /**< Multi-rate timer interrupt */ 97 CMP_CAPT_IRQn = 11, /**< Analog comparator interrupt or Capacitive Touch interrupt */ 98 WDT_IRQn = 12, /**< Windowed watchdog timer interrupt */ 99 BOD_IRQn = 13, /**< BOD interrupts */ 100 FLASH_IRQn = 14, /**< flash interrupt */ 101 WKT_IRQn = 15, /**< Self-wake-up timer interrupt */ 102 ADC0_SEQA_IRQn = 16, /**< ADC0 sequence A completion. */ 103 ADC0_SEQB_IRQn = 17, /**< ADC0 sequence B completion. */ 104 ADC0_THCMP_IRQn = 18, /**< ADC0 threshold compare and error. */ 105 ADC0_OVR_IRQn = 19, /**< ADC0 overrun */ 106 DMA0_IRQn = 20, /**< DMA0 interrupt */ 107 I2C2_IRQn = 21, /**< I2C2 interrupt */ 108 I2C3_IRQn = 22, /**< I2C3 interrupt */ 109 CTIMER0_IRQn = 23, /**< Timer interrupt */ 110 PIN_INT0_IRQn = 24, /**< Pin interrupt 0 or pattern match engine slice 0 interrupt */ 111 PIN_INT1_IRQn = 25, /**< Pin interrupt 1 or pattern match engine slice 1 interrupt */ 112 PIN_INT2_IRQn = 26, /**< Pin interrupt 2 or pattern match engine slice 2 interrupt */ 113 PIN_INT3_IRQn = 27, /**< Pin interrupt 3 or pattern match engine slice 3 interrupt */ 114 PIN_INT4_IRQn = 28, /**< Pin interrupt 4 or pattern match engine slice 4 interrupt */ 115 PIN_INT5_DAC1_IRQn = 29, /**< Pin interrupt 5 or pattern match engine slice 5 interrupt or DAC1 interrupt */ 116 PIN_INT6_USART3_IRQn = 30, /**< Pin interrupt 6 or pattern match engine slice 6 interrupt or UART3 interrupt */ 117 PIN_INT7_USART4_IRQn = 31 /**< Pin interrupt 7 or pattern match engine slice 7 interrupt or UART4 interrupt */ 118 } IRQn_Type; 119 120 /*! 121 * @} 122 */ /* end of group Interrupt_vector_numbers */ 123 124 125 /* ---------------------------------------------------------------------------- 126 -- Cortex M0 Core Configuration 127 ---------------------------------------------------------------------------- */ 128 129 /*! 130 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 131 * @{ 132 */ 133 134 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ 135 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 136 #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ 137 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ 138 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 139 140 #include "core_cm0plus.h" /* Core Peripheral Access Layer */ 141 #include "system_LPC845.h" /* Device specific configuration file */ 142 143 /*! 144 * @} 145 */ /* end of group Cortex_Core_Configuration */ 146 147 148 /* ---------------------------------------------------------------------------- 149 -- Mapping Information 150 ---------------------------------------------------------------------------- */ 151 152 /*! 153 * @addtogroup Mapping_Information Mapping Information 154 * @{ 155 */ 156 157 /** Mapping Information */ 158 /*! 159 * @addtogroup dma_request 160 * @{ 161 */ 162 163 /******************************************************************************* 164 * Definitions 165 ******************************************************************************/ 166 167 /*! 168 * @brief Structure for the DMA hardware request 169 * 170 * Defines the structure for the DMA hardware request collections. The user can configure the 171 * hardware request to trigger the DMA transfer accordingly. The index 172 * of the hardware request varies according to the to SoC. 173 */ 174 typedef enum _dma_request_source 175 { 176 kDmaRequestUSART0_RX_DMA = 0U, /**< USART0 RX DMA */ 177 kDmaRequestUSART0_TX_DMA = 1U, /**< USART0 TX DMA */ 178 kDmaRequestUSART1_RX_DMA = 2U, /**< USART1 RX DMA */ 179 kDmaRequestUSART1_TX_DMA = 3U, /**< USART1 TX DMA */ 180 kDmaRequestUSART2_RX_DMA = 4U, /**< USART2 RX DMA */ 181 kDmaRequestUSART2_TX_DMA = 5U, /**< USART2 TX DMA */ 182 kDmaRequestUSART3_RX_DMA = 6U, /**< USART3 RX DMA */ 183 kDmaRequestUSART3_TX_DMA = 7U, /**< USART3 TX DMA */ 184 kDmaRequestUSART4_RX_DMA = 8U, /**< USART4 RX DMA */ 185 kDmaRequestUSART4_TX_DMA = 9U, /**< USART4 TX DMA */ 186 kDmaRequestSPI0_RX_DMA = 10U, /**< SPI0 RX DMA */ 187 kDmaRequestSPI0_TX_DMA = 11U, /**< SPI0 TX DMA */ 188 kDmaRequestSPI1_RX_DMA = 12U, /**< SPI1 RX DMA */ 189 kDmaRequestSPI1_TX_DMA = 13U, /**< SPI1 TX DMA */ 190 kDmaRequestI2C0_SLV_DMA = 14U, /**< I2C0 SLAVE DMA */ 191 kDmaRequestI2C0_MST_DMA = 15U, /**< I2C0 MASTER DMA */ 192 kDmaRequestI2C1_SLV_DMA = 16U, /**< I2C1 SLAVE DMA */ 193 kDmaRequestI2C1_MST_DMA = 17U, /**< I2C1 MASTER DMA */ 194 kDmaRequestI2C2_SLV_DMA = 18U, /**< I2C2 SLAVE DMA */ 195 kDmaRequestI2C2_MST_DMA = 19U, /**< I2C2 MASTER DMA */ 196 kDmaRequestI2C3_SLV_DMA = 20U, /**< I2C3 SLAVE DMA */ 197 kDmaRequestI2C3_MST_DMA = 21U, /**< I2C3 MASTER DMA */ 198 kDmaRequestDAC0_DMAREQ = 22U, /**< DAC0 DMA REQUEST */ 199 kDmaRequestDAC1_DMAREQ = 23U, /**< DAC1 DMA REQUEST */ 200 kDmaRequestCAPT_DMA = 24U, /**< CAPT DMA */ 201 } dma_request_source_t; 202 203 /* @} */ 204 205 206 /*! 207 * @} 208 */ /* end of group Mapping_Information */ 209 210 211 /* ---------------------------------------------------------------------------- 212 -- Device Peripheral Access Layer 213 ---------------------------------------------------------------------------- */ 214 215 /*! 216 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 217 * @{ 218 */ 219 220 221 /* 222 ** Start of section using anonymous unions 223 */ 224 225 #if defined(__ARMCC_VERSION) 226 #if (__ARMCC_VERSION >= 6010050) 227 #pragma clang diagnostic push 228 #else 229 #pragma push 230 #pragma anon_unions 231 #endif 232 #elif defined(__GNUC__) 233 /* anonymous unions are enabled by default */ 234 #elif defined(__IAR_SYSTEMS_ICC__) 235 #pragma language=extended 236 #else 237 #error Not supported compiler type 238 #endif 239 240 /* ---------------------------------------------------------------------------- 241 -- ACOMP Peripheral Access Layer 242 ---------------------------------------------------------------------------- */ 243 244 /*! 245 * @addtogroup ACOMP_Peripheral_Access_Layer ACOMP Peripheral Access Layer 246 * @{ 247 */ 248 249 /** ACOMP - Register Layout Typedef */ 250 typedef struct { 251 __IO uint32_t CTRL; /**< Comparator control register, offset: 0x0 */ 252 __IO uint32_t LAD; /**< Voltage ladder register, offset: 0x4 */ 253 } ACOMP_Type; 254 255 /* ---------------------------------------------------------------------------- 256 -- ACOMP Register Masks 257 ---------------------------------------------------------------------------- */ 258 259 /*! 260 * @addtogroup ACOMP_Register_Masks ACOMP Register Masks 261 * @{ 262 */ 263 264 /*! @name CTRL - Comparator control register */ 265 /*! @{ */ 266 #define ACOMP_CTRL_EDGESEL_MASK (0x18U) 267 #define ACOMP_CTRL_EDGESEL_SHIFT (3U) 268 /*! EDGESEL - This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below): 269 * 0b00..Falling edges 270 * 0b01..Rising edges 271 * 0b10..Both edges 272 * 0b11..Both edges 273 */ 274 #define ACOMP_CTRL_EDGESEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGESEL_SHIFT)) & ACOMP_CTRL_EDGESEL_MASK) 275 #define ACOMP_CTRL_COMPSA_MASK (0x40U) 276 #define ACOMP_CTRL_COMPSA_SHIFT (6U) 277 /*! COMPSA - Comparator output control 278 * 0b0..Comparator output is used directly. 279 * 0b1..Comparator output is synchronized to the bus clock for output to other modules. 280 */ 281 #define ACOMP_CTRL_COMPSA(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSA_SHIFT)) & ACOMP_CTRL_COMPSA_MASK) 282 #define ACOMP_CTRL_COMP_VP_SEL_MASK (0x700U) 283 #define ACOMP_CTRL_COMP_VP_SEL_SHIFT (8U) 284 /*! COMP_VP_SEL - Selects positive voltage input 285 * 0b000..VOLTAGE_LADDER_OUTPUT 286 * 0b001..ACMP_I1 287 * 0b010..ACMP_I2 288 * 0b011..ACMP_I3 289 * 0b100..ACMP_I4 290 * 0b101..ACMP_I5 291 * 0b110..Band gap. Internal reference voltage. 292 * 0b111..DAC0 output 293 */ 294 #define ACOMP_CTRL_COMP_VP_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VP_SEL_SHIFT)) & ACOMP_CTRL_COMP_VP_SEL_MASK) 295 #define ACOMP_CTRL_COMP_VM_SEL_MASK (0x3800U) 296 #define ACOMP_CTRL_COMP_VM_SEL_SHIFT (11U) 297 /*! COMP_VM_SEL - Selects negative voltage input 298 * 0b000..VOLTAGE_LADDER_OUTPUT 299 * 0b001..ACMP_I1 300 * 0b010..ACMP_I2 301 * 0b011..ACMP_I3 302 * 0b100..ACMP_I4 303 * 0b101..ACMP_I5 304 * 0b110..Band gap. Internal reference voltage. 305 * 0b111..DAC0 output 306 */ 307 #define ACOMP_CTRL_COMP_VM_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VM_SEL_SHIFT)) & ACOMP_CTRL_COMP_VM_SEL_MASK) 308 #define ACOMP_CTRL_EDGECLR_MASK (0x100000U) 309 #define ACOMP_CTRL_EDGECLR_SHIFT (20U) 310 /*! EDGECLR - Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, 311 * toggle the EDGECLR bit by first writing a 1 and then a 0. 312 */ 313 #define ACOMP_CTRL_EDGECLR(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGECLR_SHIFT)) & ACOMP_CTRL_EDGECLR_MASK) 314 #define ACOMP_CTRL_COMPSTAT_MASK (0x200000U) 315 #define ACOMP_CTRL_COMPSTAT_SHIFT (21U) 316 /*! COMPSTAT - Comparator status. This bit reflects the state of the comparator output. 317 */ 318 #define ACOMP_CTRL_COMPSTAT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSTAT_SHIFT)) & ACOMP_CTRL_COMPSTAT_MASK) 319 #define ACOMP_CTRL_COMPEDGE_MASK (0x800000U) 320 #define ACOMP_CTRL_COMPEDGE_SHIFT (23U) 321 /*! COMPEDGE - Comparator edge-detect status. 322 */ 323 #define ACOMP_CTRL_COMPEDGE(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPEDGE_SHIFT)) & ACOMP_CTRL_COMPEDGE_MASK) 324 #define ACOMP_CTRL_INTENA_MASK (0x1000000U) 325 #define ACOMP_CTRL_INTENA_SHIFT (24U) 326 /*! INTENA - Must be set to generate interrupts. 327 */ 328 #define ACOMP_CTRL_INTENA(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_INTENA_SHIFT)) & ACOMP_CTRL_INTENA_MASK) 329 #define ACOMP_CTRL_HYS_MASK (0x6000000U) 330 #define ACOMP_CTRL_HYS_SHIFT (25U) 331 /*! HYS - Controls the hysteresis of the comparator. When the comparator is outputting a certain 332 * state, this is the difference between the selected signals, in the opposite direction from the 333 * state being output, that will switch the output. 334 * 0b00..None (the output will switch as the voltages cross) 335 * 0b01..5 mv 336 * 0b10..10 mv 337 * 0b11..20 mv 338 */ 339 #define ACOMP_CTRL_HYS(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_HYS_SHIFT)) & ACOMP_CTRL_HYS_MASK) 340 /*! @} */ 341 342 /*! @name LAD - Voltage ladder register */ 343 /*! @{ */ 344 #define ACOMP_LAD_LADEN_MASK (0x1U) 345 #define ACOMP_LAD_LADEN_SHIFT (0U) 346 /*! LADEN - Voltage ladder enable 347 */ 348 #define ACOMP_LAD_LADEN(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADEN_SHIFT)) & ACOMP_LAD_LADEN_MASK) 349 #define ACOMP_LAD_LADSEL_MASK (0x3EU) 350 #define ACOMP_LAD_LADSEL_SHIFT (1U) 351 /*! LADSEL - Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 352 * = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref 353 */ 354 #define ACOMP_LAD_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADSEL_SHIFT)) & ACOMP_LAD_LADSEL_MASK) 355 #define ACOMP_LAD_LADREF_MASK (0x40U) 356 #define ACOMP_LAD_LADREF_SHIFT (6U) 357 /*! LADREF - Selects the reference voltage Vref for the voltage ladder. 358 * 0b0..Supply pin VDD 359 * 0b1..VDDCMP pin 360 */ 361 #define ACOMP_LAD_LADREF(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADREF_SHIFT)) & ACOMP_LAD_LADREF_MASK) 362 /*! @} */ 363 364 365 /*! 366 * @} 367 */ /* end of group ACOMP_Register_Masks */ 368 369 370 /* ACOMP - Peripheral instance base addresses */ 371 /** Peripheral ACOMP base address */ 372 #define ACOMP_BASE (0x40024000u) 373 /** Peripheral ACOMP base pointer */ 374 #define ACOMP ((ACOMP_Type *)ACOMP_BASE) 375 /** Array initializer of ACOMP peripheral base addresses */ 376 #define ACOMP_BASE_ADDRS { ACOMP_BASE } 377 /** Array initializer of ACOMP peripheral base pointers */ 378 #define ACOMP_BASE_PTRS { ACOMP } 379 /** Interrupt vectors for the ACOMP peripheral type */ 380 #define ACOMP_IRQS { CMP_CAPT_IRQn } 381 382 /*! 383 * @} 384 */ /* end of group ACOMP_Peripheral_Access_Layer */ 385 386 387 /* ---------------------------------------------------------------------------- 388 -- ADC Peripheral Access Layer 389 ---------------------------------------------------------------------------- */ 390 391 /*! 392 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 393 * @{ 394 */ 395 396 /** ADC - Register Layout Typedef */ 397 typedef struct { 398 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */ 399 uint8_t RESERVED_0[4]; 400 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */ 401 __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */ 402 uint8_t RESERVED_1[8]; 403 __I uint32_t DAT[12]; /**< ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N., array offset: 0x20, array step: 0x4 */ 404 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */ 405 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */ 406 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */ 407 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */ 408 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */ 409 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */ 410 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */ 411 __IO uint32_t TRM; /**< ADC Startup register., offset: 0x6C */ 412 } ADC_Type; 413 414 /* ---------------------------------------------------------------------------- 415 -- ADC Register Masks 416 ---------------------------------------------------------------------------- */ 417 418 /*! 419 * @addtogroup ADC_Register_Masks ADC Register Masks 420 * @{ 421 */ 422 423 /*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ 424 /*! @{ */ 425 #define ADC_CTRL_CLKDIV_MASK (0xFFU) 426 #define ADC_CTRL_CLKDIV_SHIFT (0U) 427 /*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce 428 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, 429 * software should program the smallest value in this field that yields this maximum clock rate or 430 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may 431 * be desirable. This field is ignored in the asynchronous operating mode. 432 */ 433 #define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) 434 #define ADC_CTRL_ASYNMODE_MASK (0x100U) 435 #define ADC_CTRL_ASYNMODE_SHIFT (8U) 436 /*! ASYNMODE - Select clock mode. 437 * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in 438 * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to 439 * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. 440 * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC 441 * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger 442 * pulse. 443 * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block. 444 */ 445 #define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK) 446 #define ADC_CTRL_LPWRMODE_MASK (0x400U) 447 #define ADC_CTRL_LPWRMODE_SHIFT (10U) 448 /*! LPWRMODE - The low-power ADC mode 449 * 0b0..The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested. 450 * 0b1..The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions 451 * are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is 452 * enabled. After the required start-up time, the requested conversion will be launched. Once the conversion 453 * completes, the analog-circuitry will again be powered-down provided no further conversions are pending. 454 * Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are 455 * required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30 456 * clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger 457 * event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the 458 * ADC_ENA bit is low. 459 */ 460 #define ADC_CTRL_LPWRMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_LPWRMODE_SHIFT)) & ADC_CTRL_LPWRMODE_MASK) 461 #define ADC_CTRL_CALMODE_MASK (0x40000000U) 462 #define ADC_CTRL_CALMODE_SHIFT (30U) 463 /*! CALMODE - Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be 464 * automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of 465 * this register may be written to concurrently with setting this bit, however once this bit has 466 * been set no further writes to this register are permitted unitl the full calibration cycle has 467 * ended. 468 */ 469 #define ADC_CTRL_CALMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALMODE_SHIFT)) & ADC_CTRL_CALMODE_MASK) 470 /*! @} */ 471 472 /*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ 473 /*! @{ */ 474 #define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) 475 #define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) 476 /*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this 477 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be 478 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 479 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via 480 * software command, ADC conversions will be performed on each enabled channel, in sequence, 481 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) 482 * is LOW. It is allowed to change this field and set bit 31 in the same write. 483 */ 484 #define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) 485 #define ADC_SEQ_CTRL_TRIGGER_MASK (0x7000U) 486 #define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U) 487 /*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion 488 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order 489 * to avoid generating a spurious trigger, it is recommended writing to this field only when 490 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. 491 */ 492 #define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK) 493 #define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U) 494 #define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U) 495 /*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In 496 * order to avoid generating a spurious trigger, it is recommended writing to this field only when 497 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. 498 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input. 499 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input. 500 */ 501 #define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK) 502 #define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U) 503 #define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U) 504 /*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization 505 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a 506 * conversion. There are slightly different criteria for whether or not this bit can be set 507 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): 508 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already 509 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). 510 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system 511 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be 512 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse 513 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and 514 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be 515 * maintained for one system clock period. 516 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled. 517 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled. 518 */ 519 #define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK) 520 #define ADC_SEQ_CTRL_START_MASK (0x4000000U) 521 #define ADC_SEQ_CTRL_START_SHIFT (26U) 522 /*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The 523 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this 524 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a 525 * conversion sequence. It will consequently always read back as a zero. 526 */ 527 #define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK) 528 #define ADC_SEQ_CTRL_BURST_MASK (0x8000000U) 529 #define ADC_SEQ_CTRL_BURST_SHIFT (27U) 530 /*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled 531 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions 532 * can be halted by clearing this bit. The sequence currently in progress will be completed before 533 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared. 534 */ 535 #define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK) 536 #define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U) 537 #define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U) 538 /*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a 539 * single conversion on the next channel in the sequence instead of the default response of 540 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have 541 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled 542 * channel. Interrupt generation will still occur either after each individual conversion or at 543 * the end of the entire sequence, depending on the state of the MODE bit. 544 */ 545 #define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK) 546 #define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U) 547 #define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U) 548 /*! LOWPRIO - Set priority for sequence A. 549 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost. 550 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence 551 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion 552 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume 553 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the 554 * conversion sequence will resume from that point. 555 */ 556 #define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK) 557 #define ADC_SEQ_CTRL_MODE_MASK (0x40000000U) 558 #define ADC_SEQ_CTRL_MODE_SHIFT (30U) 559 /*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence 560 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each 561 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts 562 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which 563 * overrun conditions contribute to an overrun interrupt as described below. 564 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC 565 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The 566 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger 567 * if enabled. 568 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A 569 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in 570 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun 571 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode. 572 */ 573 #define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK) 574 #define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) 575 #define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) 576 /*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be 577 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state 578 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered 579 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care 580 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE 581 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be 582 * triggered immediately upon being enabled. 583 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence 584 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is 585 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel. 586 * 0b1..Enabled. Sequence n is enabled. 587 */ 588 #define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) 589 /*! @} */ 590 591 /* The count of ADC_SEQ_CTRL */ 592 #define ADC_SEQ_CTRL_COUNT (2U) 593 594 /*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ 595 /*! @{ */ 596 #define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) 597 #define ADC_SEQ_GDAT_RESULT_SHIFT (4U) 598 /*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion 599 * performed under conversion sequence associated with this register. The result is a binary 600 * fraction representing the voltage on the currently-selected input channel as it falls within the 601 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less 602 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input 603 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this 604 * result has not yet been read. 605 */ 606 #define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) 607 #define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U) 608 #define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U) 609 /*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or 610 * within the range established by the designated threshold comparison registers (THRn_LOW and 611 * THRn_HIGH). 612 */ 613 #define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK) 614 #define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U) 615 #define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U) 616 /*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a 617 * crossing of the threshold level established by the designated LOW threshold comparison register 618 * (THRn_LOW) and, if so, in what direction the crossing occurred. 619 */ 620 #define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK) 621 #define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U) 622 #define ADC_SEQ_GDAT_CHN_SHIFT (26U) 623 /*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000 624 * identifies channel 0, 0001 channel 1, etc.). 625 */ 626 #define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK) 627 #define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U) 628 #define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U) 629 /*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a 630 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along 631 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun 632 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set 633 * to '0' (and if the overrun interrupt is enabled). 634 */ 635 #define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK) 636 #define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) 637 #define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) 638 /*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded 639 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a 640 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that 641 * sequence is set to 0 (and if the interrupt is enabled). 642 */ 643 #define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) 644 /*! @} */ 645 646 /* The count of ADC_SEQ_GDAT */ 647 #define ADC_SEQ_GDAT_COUNT (2U) 648 649 /*! @name DAT - ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. */ 650 /*! @{ */ 651 #define ADC_DAT_RESULT_MASK (0xFFF0U) 652 #define ADC_DAT_RESULT_SHIFT (4U) 653 /*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed 654 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, 655 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on 656 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that 657 * the voltage on the input was close to, equal to, or greater than that on VREFP. 658 */ 659 #define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) 660 #define ADC_DAT_THCMPRANGE_MASK (0x30000U) 661 #define ADC_DAT_THCMPRANGE_SHIFT (16U) 662 /*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion 663 * was greater than or equal to the value programmed into the designated LOW threshold register 664 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold 665 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value 666 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last 667 * completed conversion was greater than the value programmed into the designated HIGH threshold 668 * register (THRn_HIGH). 0x3 = Reserved. 669 */ 670 #define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK) 671 #define ADC_DAT_THCMPCROSS_MASK (0xC0000U) 672 #define ADC_DAT_THCMPCROSS_SHIFT (18U) 673 /*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The 674 * most recent completed conversion on this channel had the same relationship (above or below) to 675 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the 676 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing 677 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the 678 * previous sample on this channel was above the threshold value established by the designated LOW 679 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward 680 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred 681 * - i.e. the previous sample on this channel was below the threshold value established by the 682 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 683 */ 684 #define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK) 685 #define ADC_DAT_CHANNEL_MASK (0x3C000000U) 686 #define ADC_DAT_CHANNEL_SHIFT (26U) 687 /*! CHANNEL - This field is hard-coded to contain the channel number that this particular register 688 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 689 * register, etc) 690 */ 691 #define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK) 692 #define ADC_DAT_OVERRUN_MASK (0x40000000U) 693 #define ADC_DAT_OVERRUN_SHIFT (30U) 694 /*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and 695 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit 696 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when 697 * the data related to this channel is read from either of the global SEQn_GDAT registers. This 698 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if 699 * the overrun interrupt is enabled. While it is allowed to include the same channels in both 700 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the 701 * data registers associated with any of the channels that are shared between the two sequences. Any 702 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 703 */ 704 #define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK) 705 #define ADC_DAT_DATAVALID_MASK (0x80000000U) 706 #define ADC_DAT_DATAVALID_SHIFT (31U) 707 /*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is 708 * cleared whenever this register is read or when the data related to this channel is read from 709 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in 710 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in 711 * the data registers associated with any of the channels that are shared between the two 712 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 713 */ 714 #define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) 715 /*! @} */ 716 717 /* The count of ADC_DAT */ 718 #define ADC_DAT_COUNT (12U) 719 720 /*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ 721 /*! @{ */ 722 #define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) 723 #define ADC_THR0_LOW_THRLOW_SHIFT (4U) 724 /*! THRLOW - Low threshold value against which ADC results will be compared 725 */ 726 #define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) 727 /*! @} */ 728 729 /*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ 730 /*! @{ */ 731 #define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) 732 #define ADC_THR1_LOW_THRLOW_SHIFT (4U) 733 /*! THRLOW - Low threshold value against which ADC results will be compared 734 */ 735 #define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) 736 /*! @} */ 737 738 /*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ 739 /*! @{ */ 740 #define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) 741 #define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) 742 /*! THRHIGH - High threshold value against which ADC results will be compared 743 */ 744 #define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) 745 /*! @} */ 746 747 /*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ 748 /*! @{ */ 749 #define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) 750 #define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) 751 /*! THRHIGH - High threshold value against which ADC results will be compared 752 */ 753 #define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) 754 /*! @} */ 755 756 /*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ 757 /*! @{ */ 758 #define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) 759 #define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) 760 /*! CH0_THRSEL - Threshold select for channel 0. 761 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers. 762 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers. 763 */ 764 #define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) 765 #define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U) 766 #define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U) 767 /*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0. 768 */ 769 #define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK) 770 #define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U) 771 #define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U) 772 /*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0. 773 */ 774 #define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK) 775 #define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U) 776 #define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U) 777 /*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0. 778 */ 779 #define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK) 780 #define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U) 781 #define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U) 782 /*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0. 783 */ 784 #define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK) 785 #define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U) 786 #define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U) 787 /*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0. 788 */ 789 #define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK) 790 #define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U) 791 #define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U) 792 /*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0. 793 */ 794 #define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK) 795 #define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U) 796 #define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U) 797 /*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0. 798 */ 799 #define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK) 800 #define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U) 801 #define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U) 802 /*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0. 803 */ 804 #define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK) 805 #define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U) 806 #define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U) 807 /*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0. 808 */ 809 #define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK) 810 #define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U) 811 #define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U) 812 /*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0. 813 */ 814 #define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK) 815 #define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) 816 #define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) 817 /*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0. 818 */ 819 #define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) 820 /*! @} */ 821 822 /*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ 823 /*! @{ */ 824 #define ADC_INTEN_SEQA_INTEN_MASK (0x1U) 825 #define ADC_INTEN_SEQA_INTEN_SHIFT (0U) 826 /*! SEQA_INTEN - Sequence A interrupt enable. 827 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled. 828 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of 829 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of 830 * conversions, depending on the MODE bit in the SEQA_CTRL register. 831 */ 832 #define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) 833 #define ADC_INTEN_SEQB_INTEN_MASK (0x2U) 834 #define ADC_INTEN_SEQB_INTEN_SHIFT (1U) 835 /*! SEQB_INTEN - Sequence B interrupt enable. 836 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled. 837 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of 838 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of 839 * conversions, depending on the MODE bit in the SEQB_CTRL register. 840 */ 841 #define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK) 842 #define ADC_INTEN_OVR_INTEN_MASK (0x4U) 843 #define ADC_INTEN_OVR_INTEN_SHIFT (2U) 844 /*! OVR_INTEN - Overrun interrupt enable. 845 * 0b0..Disabled. The overrun interrupt is disabled. 846 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel 847 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular 848 * sequence is 0, then an overrun in the global data register for that sequence will also cause this 849 * interrupt/DMA trigger to be asserted. 850 */ 851 #define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK) 852 #define ADC_INTEN_ADCMPINTEN0_MASK (0x18U) 853 #define ADC_INTEN_ADCMPINTEN0_SHIFT (3U) 854 /*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0. 855 * 0b00..Disabled. 856 * 0b01..Outside threshold. 857 * 0b10..Crossing threshold. 858 * 0b11..Reserved 859 */ 860 #define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK) 861 #define ADC_INTEN_ADCMPINTEN1_MASK (0x60U) 862 #define ADC_INTEN_ADCMPINTEN1_SHIFT (5U) 863 /*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0. 864 */ 865 #define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK) 866 #define ADC_INTEN_ADCMPINTEN2_MASK (0x180U) 867 #define ADC_INTEN_ADCMPINTEN2_SHIFT (7U) 868 /*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0. 869 */ 870 #define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK) 871 #define ADC_INTEN_ADCMPINTEN3_MASK (0x600U) 872 #define ADC_INTEN_ADCMPINTEN3_SHIFT (9U) 873 /*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0. 874 */ 875 #define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK) 876 #define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U) 877 #define ADC_INTEN_ADCMPINTEN4_SHIFT (11U) 878 /*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0. 879 */ 880 #define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK) 881 #define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U) 882 #define ADC_INTEN_ADCMPINTEN5_SHIFT (13U) 883 /*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0. 884 */ 885 #define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK) 886 #define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U) 887 #define ADC_INTEN_ADCMPINTEN6_SHIFT (15U) 888 /*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0. 889 */ 890 #define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK) 891 #define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U) 892 #define ADC_INTEN_ADCMPINTEN7_SHIFT (17U) 893 /*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0. 894 */ 895 #define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK) 896 #define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U) 897 #define ADC_INTEN_ADCMPINTEN8_SHIFT (19U) 898 /*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0. 899 */ 900 #define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK) 901 #define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U) 902 #define ADC_INTEN_ADCMPINTEN9_SHIFT (21U) 903 /*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0. 904 */ 905 #define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK) 906 #define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U) 907 #define ADC_INTEN_ADCMPINTEN10_SHIFT (23U) 908 /*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0. 909 */ 910 #define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK) 911 #define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) 912 #define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) 913 /*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0. 914 */ 915 #define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) 916 /*! @} */ 917 918 /*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ 919 /*! @{ */ 920 #define ADC_FLAGS_THCMP0_MASK (0x1U) 921 #define ADC_FLAGS_THCMP0_SHIFT (0U) 922 /*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or 923 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by 924 * writing a 1. 925 */ 926 #define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) 927 #define ADC_FLAGS_THCMP1_MASK (0x2U) 928 #define ADC_FLAGS_THCMP1_SHIFT (1U) 929 /*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0. 930 */ 931 #define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK) 932 #define ADC_FLAGS_THCMP2_MASK (0x4U) 933 #define ADC_FLAGS_THCMP2_SHIFT (2U) 934 /*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0. 935 */ 936 #define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK) 937 #define ADC_FLAGS_THCMP3_MASK (0x8U) 938 #define ADC_FLAGS_THCMP3_SHIFT (3U) 939 /*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0. 940 */ 941 #define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK) 942 #define ADC_FLAGS_THCMP4_MASK (0x10U) 943 #define ADC_FLAGS_THCMP4_SHIFT (4U) 944 /*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0. 945 */ 946 #define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK) 947 #define ADC_FLAGS_THCMP5_MASK (0x20U) 948 #define ADC_FLAGS_THCMP5_SHIFT (5U) 949 /*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0. 950 */ 951 #define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK) 952 #define ADC_FLAGS_THCMP6_MASK (0x40U) 953 #define ADC_FLAGS_THCMP6_SHIFT (6U) 954 /*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0. 955 */ 956 #define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK) 957 #define ADC_FLAGS_THCMP7_MASK (0x80U) 958 #define ADC_FLAGS_THCMP7_SHIFT (7U) 959 /*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0. 960 */ 961 #define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK) 962 #define ADC_FLAGS_THCMP8_MASK (0x100U) 963 #define ADC_FLAGS_THCMP8_SHIFT (8U) 964 /*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0. 965 */ 966 #define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK) 967 #define ADC_FLAGS_THCMP9_MASK (0x200U) 968 #define ADC_FLAGS_THCMP9_SHIFT (9U) 969 /*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0. 970 */ 971 #define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK) 972 #define ADC_FLAGS_THCMP10_MASK (0x400U) 973 #define ADC_FLAGS_THCMP10_SHIFT (10U) 974 /*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0. 975 */ 976 #define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK) 977 #define ADC_FLAGS_THCMP11_MASK (0x800U) 978 #define ADC_FLAGS_THCMP11_SHIFT (11U) 979 /*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0. 980 */ 981 #define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK) 982 #define ADC_FLAGS_OVERRUN0_MASK (0x1000U) 983 #define ADC_FLAGS_OVERRUN0_SHIFT (12U) 984 /*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0 985 */ 986 #define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK) 987 #define ADC_FLAGS_OVERRUN1_MASK (0x2000U) 988 #define ADC_FLAGS_OVERRUN1_SHIFT (13U) 989 /*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1 990 */ 991 #define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK) 992 #define ADC_FLAGS_OVERRUN2_MASK (0x4000U) 993 #define ADC_FLAGS_OVERRUN2_SHIFT (14U) 994 /*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2 995 */ 996 #define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK) 997 #define ADC_FLAGS_OVERRUN3_MASK (0x8000U) 998 #define ADC_FLAGS_OVERRUN3_SHIFT (15U) 999 /*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3 1000 */ 1001 #define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK) 1002 #define ADC_FLAGS_OVERRUN4_MASK (0x10000U) 1003 #define ADC_FLAGS_OVERRUN4_SHIFT (16U) 1004 /*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4 1005 */ 1006 #define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK) 1007 #define ADC_FLAGS_OVERRUN5_MASK (0x20000U) 1008 #define ADC_FLAGS_OVERRUN5_SHIFT (17U) 1009 /*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5 1010 */ 1011 #define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK) 1012 #define ADC_FLAGS_OVERRUN6_MASK (0x40000U) 1013 #define ADC_FLAGS_OVERRUN6_SHIFT (18U) 1014 /*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6 1015 */ 1016 #define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK) 1017 #define ADC_FLAGS_OVERRUN7_MASK (0x80000U) 1018 #define ADC_FLAGS_OVERRUN7_SHIFT (19U) 1019 /*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7 1020 */ 1021 #define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK) 1022 #define ADC_FLAGS_OVERRUN8_MASK (0x100000U) 1023 #define ADC_FLAGS_OVERRUN8_SHIFT (20U) 1024 /*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8 1025 */ 1026 #define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK) 1027 #define ADC_FLAGS_OVERRUN9_MASK (0x200000U) 1028 #define ADC_FLAGS_OVERRUN9_SHIFT (21U) 1029 /*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9 1030 */ 1031 #define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK) 1032 #define ADC_FLAGS_OVERRUN10_MASK (0x400000U) 1033 #define ADC_FLAGS_OVERRUN10_SHIFT (22U) 1034 /*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10 1035 */ 1036 #define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK) 1037 #define ADC_FLAGS_OVERRUN11_MASK (0x800000U) 1038 #define ADC_FLAGS_OVERRUN11_SHIFT (23U) 1039 /*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11 1040 */ 1041 #define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK) 1042 #define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U) 1043 #define ADC_FLAGS_SEQA_OVR_SHIFT (24U) 1044 /*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register 1045 */ 1046 #define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK) 1047 #define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U) 1048 #define ADC_FLAGS_SEQB_OVR_SHIFT (25U) 1049 /*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register 1050 */ 1051 #define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK) 1052 #define ADC_FLAGS_SEQA_INT_MASK (0x10000000U) 1053 #define ADC_FLAGS_SEQA_INT_SHIFT (28U) 1054 /*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, 1055 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which 1056 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared 1057 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register 1058 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be 1059 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN 1060 * register. 1061 */ 1062 #define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK) 1063 #define ADC_FLAGS_SEQB_INT_MASK (0x20000000U) 1064 #define ADC_FLAGS_SEQB_INT_SHIFT (29U) 1065 /*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, 1066 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which 1067 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared 1068 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register 1069 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be 1070 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN 1071 * register. 1072 */ 1073 #define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK) 1074 #define ADC_FLAGS_THCMP_INT_MASK (0x40000000U) 1075 #define ADC_FLAGS_THCMP_INT_SHIFT (30U) 1076 /*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in 1077 * the lower bits of this register are set to 1 (due to an enabled out-of-range or 1078 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be 1079 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared 1080 * when all of the individual threshold flags are cleared via writing 1s to those bits. 1081 */ 1082 #define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK) 1083 #define ADC_FLAGS_OVR_INT_MASK (0x80000000U) 1084 #define ADC_FLAGS_OVR_INT_SHIFT (31U) 1085 /*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data 1086 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers 1087 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this 1088 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all 1089 * of the individual overrun bits have been cleared via reading the corresponding data registers. 1090 */ 1091 #define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) 1092 /*! @} */ 1093 1094 /*! @name TRM - ADC Startup register. */ 1095 /*! @{ */ 1096 #define ADC_TRM_VRANGE_MASK (0x20U) 1097 #define ADC_TRM_VRANGE_SHIFT (5U) 1098 /*! VRANGE - 1.8V to 3.6V Vdd range: This bit MUST be set to '1' if operation below 2.7V is to be 1099 * used. Failure to set this bit will result in invalid ADC results. Note: This bit will not be 1100 * spec'd on parts that do not support operation below 2.7V 1101 */ 1102 #define ADC_TRM_VRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_TRM_VRANGE_SHIFT)) & ADC_TRM_VRANGE_MASK) 1103 /*! @} */ 1104 1105 1106 /*! 1107 * @} 1108 */ /* end of group ADC_Register_Masks */ 1109 1110 1111 /* ADC - Peripheral instance base addresses */ 1112 /** Peripheral ADC0 base address */ 1113 #define ADC0_BASE (0x4001C000u) 1114 /** Peripheral ADC0 base pointer */ 1115 #define ADC0 ((ADC_Type *)ADC0_BASE) 1116 /** Array initializer of ADC peripheral base addresses */ 1117 #define ADC_BASE_ADDRS { ADC0_BASE } 1118 /** Array initializer of ADC peripheral base pointers */ 1119 #define ADC_BASE_PTRS { ADC0 } 1120 /** Interrupt vectors for the ADC peripheral type */ 1121 #define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn } 1122 #define ADC_THCMP_IRQS { ADC0_THCMP_IRQn } 1123 1124 /*! 1125 * @} 1126 */ /* end of group ADC_Peripheral_Access_Layer */ 1127 1128 1129 /* ---------------------------------------------------------------------------- 1130 -- CAPT Peripheral Access Layer 1131 ---------------------------------------------------------------------------- */ 1132 1133 /*! 1134 * @addtogroup CAPT_Peripheral_Access_Layer CAPT Peripheral Access Layer 1135 * @{ 1136 */ 1137 1138 /** CAPT - Register Layout Typedef */ 1139 typedef struct { 1140 __IO uint32_t CTRL; /**< Configuration and control to setup the functional clock, the rules, and the pin selections and rules., offset: 0x0 */ 1141 __IO uint32_t STATUS; /**< Status from triggers and time-outs including if in a poll now. Some are used for interrupts., offset: 0x4 */ 1142 __IO uint32_t POLL_TCNT; /**< This sets up the polling counter and measurement counter rules., offset: 0x8 */ 1143 uint8_t RESERVED_0[4]; 1144 __IO uint32_t INTENSET; /**< Interrupt enable, offset: 0x10 */ 1145 __IO uint32_t INTENCLR; /**< Interrupt enable clear, offset: 0x14 */ 1146 __I uint32_t INTSTAT; /**< Interrupt status (mask of STATUS and INTEN), offset: 0x18 */ 1147 uint8_t RESERVED_1[4]; 1148 __I uint32_t TOUCH; /**< Last touch event (touch or no-touch) in context., offset: 0x20 */ 1149 uint8_t RESERVED_2[4056]; 1150 __I uint32_t ID; /**< Block ID, offset: 0xFFC */ 1151 } CAPT_Type; 1152 1153 /* ---------------------------------------------------------------------------- 1154 -- CAPT Register Masks 1155 ---------------------------------------------------------------------------- */ 1156 1157 /*! 1158 * @addtogroup CAPT_Register_Masks CAPT Register Masks 1159 * @{ 1160 */ 1161 1162 /*! @name CTRL - Configuration and control to setup the functional clock, the rules, and the pin selections and rules. */ 1163 /*! @{ */ 1164 #define CAPT_CTRL_POLLMODE_MASK (0x3U) 1165 #define CAPT_CTRL_POLLMODE_SHIFT (0U) 1166 /*! POLLMODE - Mode of operation. May only change from 0 to another value. So, if 2 or 3, must be 1167 * changed to 0 1st. Any attempt to go from non-0 to non-0 will result in 0 anyway. 1168 * 0b00..None, inactive. Poll and time counters are turned off. Writing this will reset state and stop any 1169 * collection in progress. Note: this has no effect on STATUS - those must be cleared manually. 1170 * 0b01..Poll now - forces a manual poll to be started immediately, using XPINSEL X pin(s) to activate in the 1171 * integration loop (all pins set together). Self clears - clear is not indication it is done (see STATUS). 1172 * 0b10..Normal polling using poll delay from POLL_TCNT register. This will start with the poll delay (which can be 0). 1173 * 0b11..The CAPT block will operate in low-power mode. This means it will use GPIO as input, use combination 1174 * touch measurements, and assume it is to wake the system. This will use the POLL_TCNT poll delay, and start 1175 * with the delay. 1176 */ 1177 #define CAPT_CTRL_POLLMODE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_POLLMODE_SHIFT)) & CAPT_CTRL_POLLMODE_MASK) 1178 #define CAPT_CTRL_TYPE_MASK (0xCU) 1179 #define CAPT_CTRL_TYPE_SHIFT (2U) 1180 /*! TYPE - Selects type of Touch arrangement to use and so how to handle XPINSEL bits 1181 * 0b00..Normal - all X elements are treated as normal, such as buttons and sliders. 1182 * 0b01..3x3 grid using NXP Complementary measurements. The 1st 9 Xs are assumed to be the 3x3 grid. After that 1183 * would be normal X elements. This will also allow 3x1 and 3x2 Note: Only possible if XMAX in STATUS is >=8 1184 * 0b10..5 Sensors interleaved to act as 3x3 touch area using NXP Complementary measurements. 1st 5 Xs used for 1185 * this, all remaining are treated as normal. Note that if 16 X pins allowed, the 16th will not be usable 1186 * when TYPE=1. (use TYPE=0 and select 1 smaller than 15 ( and any others from 1 smaller than 5 on up in 1187 * XPINSEL). 1188 * 0b11..9 Sensors interleaved to act as 5x5 touch area using NXP Complementary measurements. 1st 9 Xs used for 1189 * this, all remaining are treated as normal. Note: Only possible if XMAX in STATUS is >=8 1190 */ 1191 #define CAPT_CTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_TYPE_SHIFT)) & CAPT_CTRL_TYPE_MASK) 1192 #define CAPT_CTRL_TRIGGER_MASK (0x10U) 1193 #define CAPT_CTRL_TRIGGER_SHIFT (4U) 1194 /*! TRIGGER - This selects what is being used as the trigger 1195 * 0b0..Uses YH GPIO. This is not normally used except in Low-power mode. But, it can be used with POLLNOW to baseline that measurement. 1196 * 0b1..ACMP (if fitted). This assumes the ACMP state is fed in asynchronously and it will sample. 1197 */ 1198 #define CAPT_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_TRIGGER_SHIFT)) & CAPT_CTRL_TRIGGER_MASK) 1199 #define CAPT_CTRL_WAIT_MASK (0x20U) 1200 #define CAPT_CTRL_WAIT_SHIFT (5U) 1201 /*! WAIT - If 0, the block will continue its X based measurements, even if the TOUCH register has 1202 * not been read (and so could OVERRUN). If 1, it will wait until read when a touch (TOUCH's 1203 * ISTOUCH bit is set) before starting the next. This should not normally be needed. 1204 */ 1205 #define CAPT_CTRL_WAIT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_WAIT_SHIFT)) & CAPT_CTRL_WAIT_MASK) 1206 #define CAPT_CTRL_DMA_MASK (0xC0U) 1207 #define CAPT_CTRL_DMA_SHIFT (6U) 1208 /*! DMA - If not 0, will use the DMA to read out touch events from TOUCH register. The values are 1209 * shown below. This may be changed while active. 1210 * 0b00..No DMA. Application will use ISRs to read out data 1211 * 0b01..Trigger DMA on Touch events 1212 * 0b10..Trigger DMA on both Touch and No-Touch events 1213 * 0b11..Trigger DMA on both plus Timeout. 1214 */ 1215 #define CAPT_CTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_DMA_SHIFT)) & CAPT_CTRL_DMA_MASK) 1216 #define CAPT_CTRL_FDIV_MASK (0xF00U) 1217 #define CAPT_CTRL_FDIV_SHIFT (8U) 1218 /*! FDIV - Functional clock divider, or 0 if no divide. The term "clocks" in this spec then refer to 1219 * divided clocks. For a 12MHz input (e.g. FRO 12MHz), this would normally be set to generate a 1220 * 4MHz output (so, 2). For a 1MHz input, it should be 0. Note for internal use: this does not 1221 * produce a 50/50 duty cycle when non even divide. 1222 * 0b0000..No divide 1223 * 0b0001../2 1224 * 0b0010../3 1225 * 0b0011../4 1226 * 0b0100../5 1227 * 0b0101../6 1228 * 0b0111../(FDIV+1) 1229 * 0b1000../(FDIV+1) 1230 * 0b1001../(FDIV+1) 1231 * 0b1010../(FDIV+1) 1232 * 0b1011../(FDIV+1) 1233 * 0b1100../(FDIV+1) 1234 * 0b1101../(FDIV+1) 1235 * 0b1110../(FDIV+1) 1236 * 0b1111../(FDIV+1) 1237 */ 1238 #define CAPT_CTRL_FDIV(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_FDIV_SHIFT)) & CAPT_CTRL_FDIV_MASK) 1239 #define CAPT_CTRL_XPINUSE_MASK (0x3000U) 1240 #define CAPT_CTRL_XPINUSE_SHIFT (12U) 1241 /*! XPINUSE - Controls how X pins selected in XPINSEL are used when not active in the current polling round. 1242 * 0b00..Normal mode. Each inactive X pin is Hi-Z. 1243 * 0b01..Ground mode. Each inactive X pin is Low 1244 */ 1245 #define CAPT_CTRL_XPINUSE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_XPINUSE_SHIFT)) & CAPT_CTRL_XPINUSE_MASK) 1246 #define CAPT_CTRL_INCHANGE_MASK (0x8000U) 1247 #define CAPT_CTRL_INCHANGE_SHIFT (15U) 1248 /*! INCHANGE - If 1, do not attempt to write to this register again. This means the last change has 1249 * not been propagated. This can only happen after changing POLLMODE and DMA. Worse case time 1250 * would be based on divided FCLK. 1251 */ 1252 #define CAPT_CTRL_INCHANGE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_INCHANGE_SHIFT)) & CAPT_CTRL_INCHANGE_MASK) 1253 #define CAPT_CTRL_XPINSEL_MASK (0xFFFF0000U) 1254 #define CAPT_CTRL_XPINSEL_SHIFT (16U) 1255 /*! XPINSEL - Selects which of the X pins are to be used within the allowed pins - see XMAX in 1256 * STATUS. The X pins are mapped via the IOCON (as are the YH and YL pins) to physical pads. So, this 1257 * only selects which are to be used as the X half of the touch element. Note: when polling, 1258 * these are "walked" (active) one at a time. When using POLLNOW, the 1 or more selected are used at 1259 * the same time. Likewise, when in low-power mode, they are used at the same time (or small 1260 * groups). X pads not selected by XPINSEL are kept at High-Z if they are connected to a pad. This 1261 * allows using controlled sets for touch detection based on context. 1262 */ 1263 #define CAPT_CTRL_XPINSEL(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_XPINSEL_SHIFT)) & CAPT_CTRL_XPINSEL_MASK) 1264 /*! @} */ 1265 1266 /*! @name STATUS - Status from triggers and time-outs including if in a poll now. Some are used for interrupts. */ 1267 /*! @{ */ 1268 #define CAPT_STATUS_YESTOUCH_MASK (0x1U) 1269 #define CAPT_STATUS_YESTOUCH_SHIFT (0U) 1270 /*! YESTOUCH - Is 1 if a touch has been detected, including a wakeup from low-power mode. 1271 */ 1272 #define CAPT_STATUS_YESTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_YESTOUCH_SHIFT)) & CAPT_STATUS_YESTOUCH_MASK) 1273 #define CAPT_STATUS_NOTOUCH_MASK (0x2U) 1274 #define CAPT_STATUS_NOTOUCH_SHIFT (1U) 1275 /*! NOTOUCH - Is 1 if a no-touch has been detected (ie. completed an integration cycle and found 1276 * no-touch). This is not set when in low-power mode. 1277 */ 1278 #define CAPT_STATUS_NOTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_NOTOUCH_SHIFT)) & CAPT_STATUS_NOTOUCH_MASK) 1279 #define CAPT_STATUS_POLLDONE_MASK (0x4U) 1280 #define CAPT_STATUS_POLLDONE_SHIFT (2U) 1281 /*! POLLDONE - Is 1 if a poll or POLLNOW is complete. 1282 */ 1283 #define CAPT_STATUS_POLLDONE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_POLLDONE_SHIFT)) & CAPT_STATUS_POLLDONE_MASK) 1284 #define CAPT_STATUS_TIMEOUT_MASK (0x8U) 1285 #define CAPT_STATUS_TIMEOUT_SHIFT (3U) 1286 /*! TIMEOUT - Is 1 if an integration cycle ended with a timeout (should not happen). 1287 */ 1288 #define CAPT_STATUS_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_TIMEOUT_SHIFT)) & CAPT_STATUS_TIMEOUT_MASK) 1289 #define CAPT_STATUS_OVERUN_MASK (0x10U) 1290 #define CAPT_STATUS_OVERUN_SHIFT (4U) 1291 /*! OVERUN - Is 1 if new data was collected before application read out previous ISTOUCH. No-touch 1292 * (ISTOUCH==0) data will be silently overrun. Is not possible if WAIT=1. 1293 */ 1294 #define CAPT_STATUS_OVERUN(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_OVERUN_SHIFT)) & CAPT_STATUS_OVERUN_MASK) 1295 #define CAPT_STATUS_BUSY_MASK (0x100U) 1296 #define CAPT_STATUS_BUSY_SHIFT (8U) 1297 /*! BUSY - In a poll now. 1298 */ 1299 #define CAPT_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_BUSY_SHIFT)) & CAPT_STATUS_BUSY_MASK) 1300 #define CAPT_STATUS_XMAX_MASK (0xF0000U) 1301 #define CAPT_STATUS_XMAX_SHIFT (16U) 1302 /*! XMAX - Indicates the maximum number of X pins allowed 0-relative. So, 15 means there are pins 0 1303 * to 15, or 16 total X pins. INTERNAL note: this may be setup to be written by ROM boot. 1304 */ 1305 #define CAPT_STATUS_XMAX(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_XMAX_SHIFT)) & CAPT_STATUS_XMAX_MASK) 1306 /*! @} */ 1307 1308 /*! @name POLL_TCNT - This sets up the polling counter and measurement counter rules. */ 1309 /*! @{ */ 1310 #define CAPT_POLL_TCNT_TCNT_MASK (0xFFFU) 1311 #define CAPT_POLL_TCNT_TCNT_SHIFT (0U) 1312 /*! TCNT - Sets the threshold between touch and no-touch count. If not used, then the block will 1313 * treat all events as touch or no-touch, depending whether at max or min. This is in terms of 1314 * divided FCLK. If the comparator triggers it is no-touch; if bigger than TCNT counts, it is a touch 1315 * event. 1316 */ 1317 #define CAPT_POLL_TCNT_TCNT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_TCNT_SHIFT)) & CAPT_POLL_TCNT_TCNT_MASK) 1318 #define CAPT_POLL_TCNT_TOUT_MASK (0xF000U) 1319 #define CAPT_POLL_TCNT_TOUT_SHIFT (12U) 1320 /*! TOUT - Time-out count expressed as 1 is smaller than TOUT, allowing for up to 12 bits. Must be 1321 * less than 13. So, for example, 1 is smaller than 12=4096 counts; if TOUT=12, then if 4096 1322 * counts occur without a trigger, it is a time-out. This should be set to be large enough above TCNT 1323 * to prevent timeout invalidly. 1324 */ 1325 #define CAPT_POLL_TCNT_TOUT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_TOUT_SHIFT)) & CAPT_POLL_TCNT_TOUT_MASK) 1326 #define CAPT_POLL_TCNT_POLL_MASK (0xFF0000U) 1327 #define CAPT_POLL_TCNT_POLL_SHIFT (16U) 1328 /*! POLL - Poll counter in (internal) 12-bit counter wraparounds (loosely 1msec), so related to 1329 * divided FCLK. This expresses time delay between measurement cycles (ie. after one set of X 1330 * measurements, time before starting next). This count is used to delay before the next set of 1331 * measurements. Measuring too often wastes power and does not add value since movement of fingers is 1332 * relatively slow. For low power mode, this must allow for the clock being used (e.g. a 1MHz osc) 1333 * so 12 bit count will be potentially much longer. That means, lowering the count to get the 1334 * reasonable delay period. 1335 */ 1336 #define CAPT_POLL_TCNT_POLL(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_POLL_SHIFT)) & CAPT_POLL_TCNT_POLL_MASK) 1337 #define CAPT_POLL_TCNT_MDELAY_MASK (0x3000000U) 1338 #define CAPT_POLL_TCNT_MDELAY_SHIFT (24U) 1339 /*! MDELAY - If not 0, this selects the number of divided FCLKs to wait after entry of measurement 1340 * mode before deciding if has triggered. This gives the ACMP time to react to the transferred 1341 * charge. It is used as 1+(1 smaller than MDELAY), , so between 2 and 8 ticks of the divided FCLK 1342 * added during the measurement. 1343 */ 1344 #define CAPT_POLL_TCNT_MDELAY(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_MDELAY_SHIFT)) & CAPT_POLL_TCNT_MDELAY_MASK) 1345 #define CAPT_POLL_TCNT_RDELAY_MASK (0xC000000U) 1346 #define CAPT_POLL_TCNT_RDELAY_SHIFT (26U) 1347 /*! RDELAY - If not 0, this is the number of divided FCLKs to hold in Step 0 'Reset' state (draining 1348 * capacitance). It is used as (1 is smaller than RDELAY), so between 2 and 8 ticks of the 1349 * divided FCLK added to the 'Reset' state. 1350 */ 1351 #define CAPT_POLL_TCNT_RDELAY(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_RDELAY_SHIFT)) & CAPT_POLL_TCNT_RDELAY_MASK) 1352 #define CAPT_POLL_TCNT_TCHLOW_ER_MASK (0x80000000U) 1353 #define CAPT_POLL_TCNT_TCHLOW_ER_SHIFT (31U) 1354 /*! TCHLOW_ER - If 1, then the touch/no-touch boundary of TCNT is reversed. In a floating system 1355 * (most common), the no-touch case triggers at a lower count vs. touch; this is due to touch 1356 * drawing off charge. In a grounded system, the reverse is true and the touch adds to the charge and 1357 * so touch is a lower count. In a system which can switch between grounded and non-grounded, the 1358 * SW will check for all of the Xs looking like they have been touched and reverse the setting of 1359 * this bit. This should only be changed between polls. 1360 */ 1361 #define CAPT_POLL_TCNT_TCHLOW_ER(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_TCHLOW_ER_SHIFT)) & CAPT_POLL_TCNT_TCHLOW_ER_MASK) 1362 /*! @} */ 1363 1364 /*! @name INTENSET - Interrupt enable */ 1365 /*! @{ */ 1366 #define CAPT_INTENSET_YESTOUCH_MASK (0x1U) 1367 #define CAPT_INTENSET_YESTOUCH_SHIFT (0U) 1368 /*! YESTOUCH - Is 1 if a touch detected should interrupt. This includes wake from low-power mode. 1369 */ 1370 #define CAPT_INTENSET_YESTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENSET_YESTOUCH_SHIFT)) & CAPT_INTENSET_YESTOUCH_MASK) 1371 #define CAPT_INTENSET_NOTOUCH_MASK (0x2U) 1372 #define CAPT_INTENSET_NOTOUCH_SHIFT (1U) 1373 /*! NOTOUCH - Is 1 if a no-touch detected should interrupt 1374 */ 1375 #define CAPT_INTENSET_NOTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENSET_NOTOUCH_SHIFT)) & CAPT_INTENSET_NOTOUCH_MASK) 1376 #define CAPT_INTENSET_POLLDONE_MASK (0x4U) 1377 #define CAPT_INTENSET_POLLDONE_SHIFT (2U) 1378 /*! POLLDONE - Is 1 if a poll or POLLNOW completing should interrupt 1379 */ 1380 #define CAPT_INTENSET_POLLDONE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENSET_POLLDONE_SHIFT)) & CAPT_INTENSET_POLLDONE_MASK) 1381 #define CAPT_INTENSET_TIMEOUT_MASK (0x8U) 1382 #define CAPT_INTENSET_TIMEOUT_SHIFT (3U) 1383 /*! TIMEOUT - Is 1 if an integration cycle ending with timeout should interrupt 1384 */ 1385 #define CAPT_INTENSET_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENSET_TIMEOUT_SHIFT)) & CAPT_INTENSET_TIMEOUT_MASK) 1386 #define CAPT_INTENSET_OVERUN_MASK (0x10U) 1387 #define CAPT_INTENSET_OVERUN_SHIFT (4U) 1388 /*! OVERUN - Is 1 if an overrun should interrupt. 1389 */ 1390 #define CAPT_INTENSET_OVERUN(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENSET_OVERUN_SHIFT)) & CAPT_INTENSET_OVERUN_MASK) 1391 /*! @} */ 1392 1393 /*! @name INTENCLR - Interrupt enable clear */ 1394 /*! @{ */ 1395 #define CAPT_INTENCLR_YESTOUCH_MASK (0x1U) 1396 #define CAPT_INTENCLR_YESTOUCH_SHIFT (0U) 1397 /*! YESTOUCH - clear the touch interrupt 1398 */ 1399 #define CAPT_INTENCLR_YESTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENCLR_YESTOUCH_SHIFT)) & CAPT_INTENCLR_YESTOUCH_MASK) 1400 #define CAPT_INTENCLR_NOTOUCH_MASK (0x2U) 1401 #define CAPT_INTENCLR_NOTOUCH_SHIFT (1U) 1402 /*! NOTOUCH - clear the no-touch interrupt 1403 */ 1404 #define CAPT_INTENCLR_NOTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENCLR_NOTOUCH_SHIFT)) & CAPT_INTENCLR_NOTOUCH_MASK) 1405 #define CAPT_INTENCLR_POLLDONE_MASK (0x4U) 1406 #define CAPT_INTENCLR_POLLDONE_SHIFT (2U) 1407 /*! POLLDONE - clear the poll or POLLNOW completing interrupt 1408 */ 1409 #define CAPT_INTENCLR_POLLDONE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENCLR_POLLDONE_SHIFT)) & CAPT_INTENCLR_POLLDONE_MASK) 1410 #define CAPT_INTENCLR_TIMEOUT_MASK (0x8U) 1411 #define CAPT_INTENCLR_TIMEOUT_SHIFT (3U) 1412 /*! TIMEOUT - clear the timeout interrupt 1413 */ 1414 #define CAPT_INTENCLR_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENCLR_TIMEOUT_SHIFT)) & CAPT_INTENCLR_TIMEOUT_MASK) 1415 #define CAPT_INTENCLR_OVERUN_MASK (0x10U) 1416 #define CAPT_INTENCLR_OVERUN_SHIFT (4U) 1417 /*! OVERUN - clear the overrun interrupt 1418 */ 1419 #define CAPT_INTENCLR_OVERUN(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENCLR_OVERUN_SHIFT)) & CAPT_INTENCLR_OVERUN_MASK) 1420 /*! @} */ 1421 1422 /*! @name INTSTAT - Interrupt status (mask of STATUS and INTEN) */ 1423 /*! @{ */ 1424 #define CAPT_INTSTAT_YESTOUCH_MASK (0x1U) 1425 #define CAPT_INTSTAT_YESTOUCH_SHIFT (0U) 1426 /*! YESTOUCH - the status of touch interrrupt 1427 */ 1428 #define CAPT_INTSTAT_YESTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTSTAT_YESTOUCH_SHIFT)) & CAPT_INTSTAT_YESTOUCH_MASK) 1429 #define CAPT_INTSTAT_NOTOUCH_MASK (0x2U) 1430 #define CAPT_INTSTAT_NOTOUCH_SHIFT (1U) 1431 /*! NOTOUCH - the status of no-touch interrrupt 1432 */ 1433 #define CAPT_INTSTAT_NOTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTSTAT_NOTOUCH_SHIFT)) & CAPT_INTSTAT_NOTOUCH_MASK) 1434 #define CAPT_INTSTAT_POLLDONE_MASK (0x4U) 1435 #define CAPT_INTSTAT_POLLDONE_SHIFT (2U) 1436 /*! POLLDONE - the status of poll or pollnow completing interrupt 1437 */ 1438 #define CAPT_INTSTAT_POLLDONE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTSTAT_POLLDONE_SHIFT)) & CAPT_INTSTAT_POLLDONE_MASK) 1439 #define CAPT_INTSTAT_TIMEOUT_MASK (0x8U) 1440 #define CAPT_INTSTAT_TIMEOUT_SHIFT (3U) 1441 /*! TIMEOUT - the status of timeout interrupt 1442 */ 1443 #define CAPT_INTSTAT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTSTAT_TIMEOUT_SHIFT)) & CAPT_INTSTAT_TIMEOUT_MASK) 1444 #define CAPT_INTSTAT_OVERUN_MASK (0x10U) 1445 #define CAPT_INTSTAT_OVERUN_SHIFT (4U) 1446 /*! OVERUN - the status of overrun interrupt 1447 */ 1448 #define CAPT_INTSTAT_OVERUN(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTSTAT_OVERUN_SHIFT)) & CAPT_INTSTAT_OVERUN_MASK) 1449 /*! @} */ 1450 1451 /*! @name TOUCH - Last touch event (touch or no-touch) in context. */ 1452 /*! @{ */ 1453 #define CAPT_TOUCH_COUNT_MASK (0xFFFU) 1454 #define CAPT_TOUCH_COUNT_SHIFT (0U) 1455 /*! COUNT - Count value reached at trigger. If timeout, will be (1 bigger than TOUT)-1; e.g. if TOUT=12, then 0xFFF. 1456 */ 1457 #define CAPT_TOUCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_COUNT_SHIFT)) & CAPT_TOUCH_COUNT_MASK) 1458 #define CAPT_TOUCH_XVAL_MASK (0xF000U) 1459 #define CAPT_TOUCH_XVAL_SHIFT (12U) 1460 /*! XVAL - Is the X that triggered this, or lowest X if more than one. 1461 */ 1462 #define CAPT_TOUCH_XVAL(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_XVAL_SHIFT)) & CAPT_TOUCH_XVAL_MASK) 1463 #define CAPT_TOUCH_ISTOUCH_MASK (0x10000U) 1464 #define CAPT_TOUCH_ISTOUCH_SHIFT (16U) 1465 /*! ISTOUCH - 1 if is Touch (by count) or 0 if is no-touch. 1466 */ 1467 #define CAPT_TOUCH_ISTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_ISTOUCH_SHIFT)) & CAPT_TOUCH_ISTOUCH_MASK) 1468 #define CAPT_TOUCH_ISTO_MASK (0x20000U) 1469 #define CAPT_TOUCH_ISTO_SHIFT (17U) 1470 /*! ISTO - 1 if is Timeout. 1471 */ 1472 #define CAPT_TOUCH_ISTO(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_ISTO_SHIFT)) & CAPT_TOUCH_ISTO_MASK) 1473 #define CAPT_TOUCH_SEQ_MASK (0xF00000U) 1474 #define CAPT_TOUCH_SEQ_SHIFT (20U) 1475 /*! SEQ - Sequence number - rolling counter of polls. Changes after all selected Xs per poll (so, 0 1476 * for 1st set of Xs, then 1 for next set, etc). 1477 */ 1478 #define CAPT_TOUCH_SEQ(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_SEQ_SHIFT)) & CAPT_TOUCH_SEQ_MASK) 1479 #define CAPT_TOUCH_CHANGE_MASK (0x80000000U) 1480 #define CAPT_TOUCH_CHANGE_SHIFT (31U) 1481 /*! CHANGE - If 1, the rest of the register is 0 because the data is changing. This will only happen 1482 * for 1 cycle and would never happen if using interrupts to read, unless took so long as to 1483 * overrun. 1484 */ 1485 #define CAPT_TOUCH_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_CHANGE_SHIFT)) & CAPT_TOUCH_CHANGE_MASK) 1486 /*! @} */ 1487 1488 /*! @name ID - Block ID */ 1489 /*! @{ */ 1490 #define CAPT_ID_APERTURE_MASK (0xFFU) 1491 #define CAPT_ID_APERTURE_SHIFT (0U) 1492 /*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 is a 4 K aperture. 1493 */ 1494 #define CAPT_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_ID_APERTURE_SHIFT)) & CAPT_ID_APERTURE_MASK) 1495 #define CAPT_ID_MINOR_REV_MASK (0xF00U) 1496 #define CAPT_ID_MINOR_REV_SHIFT (8U) 1497 /*! MINOR_REV - Minor revision of module implementation, starting at 0. Software compatibility is expected between minor revisions. 1498 */ 1499 #define CAPT_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << CAPT_ID_MINOR_REV_SHIFT)) & CAPT_ID_MINOR_REV_MASK) 1500 #define CAPT_ID_MAJOR_REV_MASK (0xF000U) 1501 #define CAPT_ID_MAJOR_REV_SHIFT (12U) 1502 /*! MAJOR_REV - Major revision of module implementation, starting at 0. There may not be software compatibility between major revisions. 1503 */ 1504 #define CAPT_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << CAPT_ID_MAJOR_REV_SHIFT)) & CAPT_ID_MAJOR_REV_MASK) 1505 #define CAPT_ID_ID_MASK (0xFFFF0000U) 1506 #define CAPT_ID_ID_SHIFT (16U) 1507 /*! ID - 1 if is Timeout. 1508 */ 1509 #define CAPT_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << CAPT_ID_ID_SHIFT)) & CAPT_ID_ID_MASK) 1510 /*! @} */ 1511 1512 1513 /*! 1514 * @} 1515 */ /* end of group CAPT_Register_Masks */ 1516 1517 1518 /* CAPT - Peripheral instance base addresses */ 1519 /** Peripheral CAPT base address */ 1520 #define CAPT_BASE (0x40060000u) 1521 /** Peripheral CAPT base pointer */ 1522 #define CAPT ((CAPT_Type *)CAPT_BASE) 1523 /** Array initializer of CAPT peripheral base addresses */ 1524 #define CAPT_BASE_ADDRS { CAPT_BASE } 1525 /** Array initializer of CAPT peripheral base pointers */ 1526 #define CAPT_BASE_PTRS { CAPT } 1527 /** Interrupt vectors for the CAPT peripheral type */ 1528 #define CAPT_IRQS { CMP_CAPT_IRQn } 1529 1530 /*! 1531 * @} 1532 */ /* end of group CAPT_Peripheral_Access_Layer */ 1533 1534 1535 /* ---------------------------------------------------------------------------- 1536 -- CRC Peripheral Access Layer 1537 ---------------------------------------------------------------------------- */ 1538 1539 /*! 1540 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer 1541 * @{ 1542 */ 1543 1544 /** CRC - Register Layout Typedef */ 1545 typedef struct { 1546 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ 1547 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ 1548 union { /* offset: 0x8 */ 1549 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ 1550 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ 1551 }; 1552 } CRC_Type; 1553 1554 /* ---------------------------------------------------------------------------- 1555 -- CRC Register Masks 1556 ---------------------------------------------------------------------------- */ 1557 1558 /*! 1559 * @addtogroup CRC_Register_Masks CRC Register Masks 1560 * @{ 1561 */ 1562 1563 /*! @name MODE - CRC mode register */ 1564 /*! @{ */ 1565 #define CRC_MODE_CRC_POLY_MASK (0x3U) 1566 #define CRC_MODE_CRC_POLY_SHIFT (0U) 1567 /*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial 1568 */ 1569 #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) 1570 #define CRC_MODE_BIT_RVS_WR_MASK (0x4U) 1571 #define CRC_MODE_BIT_RVS_WR_SHIFT (2U) 1572 /*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) 1573 */ 1574 #define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) 1575 #define CRC_MODE_CMPL_WR_MASK (0x8U) 1576 #define CRC_MODE_CMPL_WR_SHIFT (3U) 1577 /*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA 1578 */ 1579 #define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) 1580 #define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) 1581 #define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) 1582 /*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM 1583 */ 1584 #define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) 1585 #define CRC_MODE_CMPL_SUM_MASK (0x20U) 1586 #define CRC_MODE_CMPL_SUM_SHIFT (5U) 1587 /*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM 1588 */ 1589 #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) 1590 /*! @} */ 1591 1592 /*! @name SEED - CRC seed register */ 1593 /*! @{ */ 1594 #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) 1595 #define CRC_SEED_CRC_SEED_SHIFT (0U) 1596 /*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with 1597 * selected bit order and 1's complement pre-processes. A write access to this register will 1598 * overrule the CRC calculation in progresses. 1599 */ 1600 #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) 1601 /*! @} */ 1602 1603 /*! @name SUM - CRC checksum register */ 1604 /*! @{ */ 1605 #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) 1606 #define CRC_SUM_CRC_SUM_SHIFT (0U) 1607 /*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. 1608 */ 1609 #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) 1610 /*! @} */ 1611 1612 /*! @name WR_DATA - CRC data register */ 1613 /*! @{ */ 1614 #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) 1615 #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) 1616 /*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with 1617 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and 1618 * accept back-to-back transactions. 1619 */ 1620 #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) 1621 /*! @} */ 1622 1623 1624 /*! 1625 * @} 1626 */ /* end of group CRC_Register_Masks */ 1627 1628 1629 /* CRC - Peripheral instance base addresses */ 1630 /** Peripheral CRC base address */ 1631 #define CRC_BASE (0x50000000u) 1632 /** Peripheral CRC base pointer */ 1633 #define CRC ((CRC_Type *)CRC_BASE) 1634 /** Array initializer of CRC peripheral base addresses */ 1635 #define CRC_BASE_ADDRS { CRC_BASE } 1636 /** Array initializer of CRC peripheral base pointers */ 1637 #define CRC_BASE_PTRS { CRC } 1638 1639 /*! 1640 * @} 1641 */ /* end of group CRC_Peripheral_Access_Layer */ 1642 1643 1644 /* ---------------------------------------------------------------------------- 1645 -- CTIMER Peripheral Access Layer 1646 ---------------------------------------------------------------------------- */ 1647 1648 /*! 1649 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer 1650 * @{ 1651 */ 1652 1653 /** CTIMER - Register Layout Typedef */ 1654 typedef struct { 1655 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ 1656 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ 1657 __IO uint32_t TC; /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR., offset: 0x8 */ 1658 __IO uint32_t PR; /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC., offset: 0xC */ 1659 __IO uint32_t PC; /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface., offset: 0x10 */ 1660 __IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */ 1661 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ 1662 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ 1663 __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ 1664 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ 1665 uint8_t RESERVED_0[48]; 1666 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ 1667 __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */ 1668 __IO uint32_t MSR[4]; /**< Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero., array offset: 0x78, array step: 0x4 */ 1669 } CTIMER_Type; 1670 1671 /* ---------------------------------------------------------------------------- 1672 -- CTIMER Register Masks 1673 ---------------------------------------------------------------------------- */ 1674 1675 /*! 1676 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks 1677 * @{ 1678 */ 1679 1680 /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ 1681 /*! @{ */ 1682 #define CTIMER_IR_MR0INT_MASK (0x1U) 1683 #define CTIMER_IR_MR0INT_SHIFT (0U) 1684 /*! MR0INT - Interrupt flag for match channel 0. 1685 */ 1686 #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) 1687 #define CTIMER_IR_MR1INT_MASK (0x2U) 1688 #define CTIMER_IR_MR1INT_SHIFT (1U) 1689 /*! MR1INT - Interrupt flag for match channel 1. 1690 */ 1691 #define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) 1692 #define CTIMER_IR_MR2INT_MASK (0x4U) 1693 #define CTIMER_IR_MR2INT_SHIFT (2U) 1694 /*! MR2INT - Interrupt flag for match channel 2. 1695 */ 1696 #define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) 1697 #define CTIMER_IR_MR3INT_MASK (0x8U) 1698 #define CTIMER_IR_MR3INT_SHIFT (3U) 1699 /*! MR3INT - Interrupt flag for match channel 3. 1700 */ 1701 #define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) 1702 #define CTIMER_IR_CR0INT_MASK (0x10U) 1703 #define CTIMER_IR_CR0INT_SHIFT (4U) 1704 /*! CR0INT - Interrupt flag for capture channel 0 event. 1705 */ 1706 #define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) 1707 #define CTIMER_IR_CR1INT_MASK (0x20U) 1708 #define CTIMER_IR_CR1INT_SHIFT (5U) 1709 /*! CR1INT - Interrupt flag for capture channel 1 event. 1710 */ 1711 #define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) 1712 #define CTIMER_IR_CR2INT_MASK (0x40U) 1713 #define CTIMER_IR_CR2INT_SHIFT (6U) 1714 /*! CR2INT - Interrupt flag for capture channel 2 event. 1715 */ 1716 #define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) 1717 #define CTIMER_IR_CR3INT_MASK (0x80U) 1718 #define CTIMER_IR_CR3INT_SHIFT (7U) 1719 /*! CR3INT - Interrupt flag for capture channel 3 event. 1720 */ 1721 #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) 1722 /*! @} */ 1723 1724 /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ 1725 /*! @{ */ 1726 #define CTIMER_TCR_CEN_MASK (0x1U) 1727 #define CTIMER_TCR_CEN_SHIFT (0U) 1728 /*! CEN - Counter enable. 1729 * 0b0..Disabled.The counters are disabled. 1730 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. 1731 */ 1732 #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) 1733 #define CTIMER_TCR_CRST_MASK (0x2U) 1734 #define CTIMER_TCR_CRST_SHIFT (1U) 1735 /*! CRST - Counter reset. 1736 * 0b0..Disabled. Do nothing. 1737 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of 1738 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. 1739 */ 1740 #define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) 1741 /*! @} */ 1742 1743 /*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */ 1744 /*! @{ */ 1745 #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) 1746 #define CTIMER_TC_TCVAL_SHIFT (0U) 1747 /*! TCVAL - Timer counter value. 1748 */ 1749 #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) 1750 /*! @} */ 1751 1752 /*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */ 1753 /*! @{ */ 1754 #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) 1755 #define CTIMER_PR_PRVAL_SHIFT (0U) 1756 /*! PRVAL - Prescale counter value. 1757 */ 1758 #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) 1759 /*! @} */ 1760 1761 /*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ 1762 /*! @{ */ 1763 #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) 1764 #define CTIMER_PC_PCVAL_SHIFT (0U) 1765 /*! PCVAL - Prescale counter value. 1766 */ 1767 #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) 1768 /*! @} */ 1769 1770 /*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ 1771 /*! @{ */ 1772 #define CTIMER_MCR_MR0I_MASK (0x1U) 1773 #define CTIMER_MCR_MR0I_SHIFT (0U) 1774 /*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled. 1775 */ 1776 #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) 1777 #define CTIMER_MCR_MR0R_MASK (0x2U) 1778 #define CTIMER_MCR_MR0R_SHIFT (1U) 1779 /*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled. 1780 */ 1781 #define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) 1782 #define CTIMER_MCR_MR0S_MASK (0x4U) 1783 #define CTIMER_MCR_MR0S_SHIFT (2U) 1784 /*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled. 1785 */ 1786 #define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) 1787 #define CTIMER_MCR_MR1I_MASK (0x8U) 1788 #define CTIMER_MCR_MR1I_SHIFT (3U) 1789 /*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = 1790 * disabled. 1 = enabled. 0 = disabled. 1 = enabled. 1791 */ 1792 #define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) 1793 #define CTIMER_MCR_MR1R_MASK (0x10U) 1794 #define CTIMER_MCR_MR1R_SHIFT (4U) 1795 /*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled. 1796 */ 1797 #define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) 1798 #define CTIMER_MCR_MR1S_MASK (0x20U) 1799 #define CTIMER_MCR_MR1S_SHIFT (5U) 1800 /*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled. 1801 */ 1802 #define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) 1803 #define CTIMER_MCR_MR2I_MASK (0x40U) 1804 #define CTIMER_MCR_MR2I_SHIFT (6U) 1805 /*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled. 1806 */ 1807 #define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) 1808 #define CTIMER_MCR_MR2R_MASK (0x80U) 1809 #define CTIMER_MCR_MR2R_SHIFT (7U) 1810 /*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled. 1811 */ 1812 #define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) 1813 #define CTIMER_MCR_MR2S_MASK (0x100U) 1814 #define CTIMER_MCR_MR2S_SHIFT (8U) 1815 /*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled. 1816 */ 1817 #define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) 1818 #define CTIMER_MCR_MR3I_MASK (0x200U) 1819 #define CTIMER_MCR_MR3I_SHIFT (9U) 1820 /*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled. 1821 */ 1822 #define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) 1823 #define CTIMER_MCR_MR3R_MASK (0x400U) 1824 #define CTIMER_MCR_MR3R_SHIFT (10U) 1825 /*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled. 1826 */ 1827 #define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) 1828 #define CTIMER_MCR_MR3S_MASK (0x800U) 1829 #define CTIMER_MCR_MR3S_SHIFT (11U) 1830 /*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled. 1831 */ 1832 #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) 1833 #define CTIMER_MCR_MR0RL_MASK (0x1000000U) 1834 #define CTIMER_MCR_MR0RL_SHIFT (24U) 1835 /*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero 1836 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. 1837 */ 1838 #define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) 1839 #define CTIMER_MCR_MR1RL_MASK (0x2000000U) 1840 #define CTIMER_MCR_MR1RL_SHIFT (25U) 1841 /*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero 1842 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. 1843 */ 1844 #define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) 1845 #define CTIMER_MCR_MR2RL_MASK (0x4000000U) 1846 #define CTIMER_MCR_MR2RL_SHIFT (26U) 1847 /*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero 1848 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. 1849 */ 1850 #define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) 1851 #define CTIMER_MCR_MR3RL_MASK (0x8000000U) 1852 #define CTIMER_MCR_MR3RL_SHIFT (27U) 1853 /*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero 1854 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. 1855 */ 1856 #define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) 1857 /*! @} */ 1858 1859 /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ 1860 /*! @{ */ 1861 #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) 1862 #define CTIMER_MR_MATCH_SHIFT (0U) 1863 /*! MATCH - Timer counter match value. 1864 */ 1865 #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) 1866 /*! @} */ 1867 1868 /* The count of CTIMER_MR */ 1869 #define CTIMER_MR_COUNT (4U) 1870 1871 /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ 1872 /*! @{ */ 1873 #define CTIMER_CCR_CAP0RE_MASK (0x1U) 1874 #define CTIMER_CCR_CAP0RE_SHIFT (0U) 1875 /*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with 1876 * the contents of TC. 0 = disabled. 1 = enabled. 1877 */ 1878 #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) 1879 #define CTIMER_CCR_CAP0FE_MASK (0x2U) 1880 #define CTIMER_CCR_CAP0FE_SHIFT (1U) 1881 /*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with 1882 * the contents of TC. 0 = disabled. 1 = enabled. 1883 */ 1884 #define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) 1885 #define CTIMER_CCR_CAP0I_MASK (0x4U) 1886 #define CTIMER_CCR_CAP0I_SHIFT (2U) 1887 /*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. 1888 */ 1889 #define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) 1890 #define CTIMER_CCR_CAP1RE_MASK (0x8U) 1891 #define CTIMER_CCR_CAP1RE_SHIFT (3U) 1892 /*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with 1893 * the contents of TC. 0 = disabled. 1 = enabled. 1894 */ 1895 #define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) 1896 #define CTIMER_CCR_CAP1FE_MASK (0x10U) 1897 #define CTIMER_CCR_CAP1FE_SHIFT (4U) 1898 /*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with 1899 * the contents of TC. 0 = disabled. 1 = enabled. 1900 */ 1901 #define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) 1902 #define CTIMER_CCR_CAP1I_MASK (0x20U) 1903 #define CTIMER_CCR_CAP1I_SHIFT (5U) 1904 /*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. 1905 */ 1906 #define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) 1907 #define CTIMER_CCR_CAP2RE_MASK (0x40U) 1908 #define CTIMER_CCR_CAP2RE_SHIFT (6U) 1909 /*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with 1910 * the contents of TC. 0 = disabled. 1 = enabled. 1911 */ 1912 #define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) 1913 #define CTIMER_CCR_CAP2FE_MASK (0x80U) 1914 #define CTIMER_CCR_CAP2FE_SHIFT (7U) 1915 /*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with 1916 * the contents of TC. 0 = disabled. 1 = enabled. 1917 */ 1918 #define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) 1919 #define CTIMER_CCR_CAP2I_MASK (0x100U) 1920 #define CTIMER_CCR_CAP2I_SHIFT (8U) 1921 /*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. 1922 */ 1923 #define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) 1924 #define CTIMER_CCR_CAP3RE_MASK (0x200U) 1925 #define CTIMER_CCR_CAP3RE_SHIFT (9U) 1926 /*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with 1927 * the contents of TC. 0 = disabled. 1 = enabled. 1928 */ 1929 #define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) 1930 #define CTIMER_CCR_CAP3FE_MASK (0x400U) 1931 #define CTIMER_CCR_CAP3FE_SHIFT (10U) 1932 /*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with 1933 * the contents of TC. 0 = disabled. 1 = enabled. 1934 */ 1935 #define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) 1936 #define CTIMER_CCR_CAP3I_MASK (0x800U) 1937 #define CTIMER_CCR_CAP3I_SHIFT (11U) 1938 /*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. 1939 */ 1940 #define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) 1941 /*! @} */ 1942 1943 /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ 1944 /*! @{ */ 1945 #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) 1946 #define CTIMER_CR_CAP_SHIFT (0U) 1947 /*! CAP - Timer counter capture value. 1948 */ 1949 #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) 1950 /*! @} */ 1951 1952 /* The count of CTIMER_CR */ 1953 #define CTIMER_CR_COUNT (4U) 1954 1955 /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ 1956 /*! @{ */ 1957 #define CTIMER_EMR_EM0_MASK (0x1U) 1958 #define CTIMER_EMR_EM0_SHIFT (0U) 1959 /*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output 1960 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, 1961 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if 1962 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1963 */ 1964 #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) 1965 #define CTIMER_EMR_EM1_MASK (0x2U) 1966 #define CTIMER_EMR_EM1_SHIFT (1U) 1967 /*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output 1968 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, 1969 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if 1970 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1971 */ 1972 #define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) 1973 #define CTIMER_EMR_EM2_MASK (0x4U) 1974 #define CTIMER_EMR_EM2_SHIFT (2U) 1975 /*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output 1976 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, 1977 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if 1978 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1979 */ 1980 #define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) 1981 #define CTIMER_EMR_EM3_MASK (0x8U) 1982 #define CTIMER_EMR_EM3_SHIFT (3U) 1983 /*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output 1984 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, 1985 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins 1986 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1987 */ 1988 #define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) 1989 #define CTIMER_EMR_EMC0_MASK (0x30U) 1990 #define CTIMER_EMR_EMC0_SHIFT (4U) 1991 /*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. 1992 * 0b00..Do Nothing. 1993 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). 1994 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). 1995 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 1996 */ 1997 #define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) 1998 #define CTIMER_EMR_EMC1_MASK (0xC0U) 1999 #define CTIMER_EMR_EMC1_SHIFT (6U) 2000 /*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. 2001 * 0b00..Do Nothing. 2002 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). 2003 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). 2004 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 2005 */ 2006 #define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) 2007 #define CTIMER_EMR_EMC2_MASK (0x300U) 2008 #define CTIMER_EMR_EMC2_SHIFT (8U) 2009 /*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. 2010 * 0b00..Do Nothing. 2011 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). 2012 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). 2013 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 2014 */ 2015 #define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) 2016 #define CTIMER_EMR_EMC3_MASK (0xC00U) 2017 #define CTIMER_EMR_EMC3_SHIFT (10U) 2018 /*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. 2019 * 0b00..Do Nothing. 2020 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). 2021 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). 2022 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 2023 */ 2024 #define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) 2025 /*! @} */ 2026 2027 /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ 2028 /*! @{ */ 2029 #define CTIMER_CTCR_CTMODE_MASK (0x3U) 2030 #define CTIMER_CTCR_CTMODE_SHIFT (0U) 2031 /*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment 2032 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC 2033 * is incremented when the Prescale Counter matches the Prescale Register. 2034 * 0b00..Timer Mode. Incremented every rising APB bus clock edge. 2035 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. 2036 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. 2037 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. 2038 */ 2039 #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) 2040 #define CTIMER_CTCR_CINSEL_MASK (0xCU) 2041 #define CTIMER_CTCR_CINSEL_SHIFT (2U) 2042 /*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which 2043 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input 2044 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be 2045 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the 2046 * same timer. 2047 * 0b00..Channel 0. CAPn.0 for CTIMERn 2048 * 0b01..Channel 1. CAPn.1 for CTIMERn 2049 * 0b10..Channel 2. CAPn.2 for CTIMERn 2050 * 0b11..Channel 3. CAPn.3 for CTIMERn 2051 */ 2052 #define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) 2053 #define CTIMER_CTCR_ENCC_MASK (0x10U) 2054 #define CTIMER_CTCR_ENCC_SHIFT (4U) 2055 /*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the 2056 * capture-edge event specified in bits 7:5 occurs. 2057 */ 2058 #define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) 2059 #define CTIMER_CTCR_SELCC_MASK (0xE0U) 2060 #define CTIMER_CTCR_SELCC_SHIFT (5U) 2061 /*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the 2062 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 2063 * 0x3 and 0x6 to 0x7 are reserved. 2064 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 2065 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 2066 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 2067 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 2068 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 2069 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 2070 * 0b110..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 2071 * 0b111..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 2072 */ 2073 #define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) 2074 /*! @} */ 2075 2076 /*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ 2077 /*! @{ */ 2078 #define CTIMER_PWMC_PWMEN0_MASK (0x1U) 2079 #define CTIMER_PWMC_PWMEN0_SHIFT (0U) 2080 /*! PWMEN0 - PWM mode enable for channel0. 2081 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. 2082 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. 2083 */ 2084 #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) 2085 #define CTIMER_PWMC_PWMEN1_MASK (0x2U) 2086 #define CTIMER_PWMC_PWMEN1_SHIFT (1U) 2087 /*! PWMEN1 - PWM mode enable for channel1. 2088 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. 2089 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. 2090 */ 2091 #define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) 2092 #define CTIMER_PWMC_PWMEN2_MASK (0x4U) 2093 #define CTIMER_PWMC_PWMEN2_SHIFT (2U) 2094 /*! PWMEN2 - PWM mode enable for channel2. 2095 * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. 2096 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. 2097 */ 2098 #define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) 2099 #define CTIMER_PWMC_PWMEN3_MASK (0x8U) 2100 #define CTIMER_PWMC_PWMEN3_SHIFT (3U) 2101 /*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. 2102 * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. 2103 * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. 2104 */ 2105 #define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) 2106 /*! @} */ 2107 2108 /*! @name MSR - Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero. */ 2109 /*! @{ */ 2110 #define CTIMER_MSR_MATCH_SHADOW_MASK (0xFFFFFFFFU) 2111 #define CTIMER_MSR_MATCH_SHADOW_SHIFT (0U) 2112 /*! MATCH_SHADOW - Timer counter match value. 2113 */ 2114 #define CTIMER_MSR_MATCH_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK) 2115 /*! @} */ 2116 2117 /* The count of CTIMER_MSR */ 2118 #define CTIMER_MSR_COUNT (4U) 2119 2120 2121 /*! 2122 * @} 2123 */ /* end of group CTIMER_Register_Masks */ 2124 2125 2126 /* CTIMER - Peripheral instance base addresses */ 2127 /** Peripheral CTIMER0 base address */ 2128 #define CTIMER0_BASE (0x40038000u) 2129 /** Peripheral CTIMER0 base pointer */ 2130 #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) 2131 /** Array initializer of CTIMER peripheral base addresses */ 2132 #define CTIMER_BASE_ADDRS { CTIMER0_BASE } 2133 /** Array initializer of CTIMER peripheral base pointers */ 2134 #define CTIMER_BASE_PTRS { CTIMER0 } 2135 /** Interrupt vectors for the CTIMER peripheral type */ 2136 #define CTIMER_IRQS { CTIMER0_IRQn } 2137 2138 /*! 2139 * @} 2140 */ /* end of group CTIMER_Peripheral_Access_Layer */ 2141 2142 2143 /* ---------------------------------------------------------------------------- 2144 -- DAC Peripheral Access Layer 2145 ---------------------------------------------------------------------------- */ 2146 2147 /*! 2148 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer 2149 * @{ 2150 */ 2151 2152 /** DAC - Register Layout Typedef */ 2153 typedef struct { 2154 __IO uint32_t CR; /**< D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit., offset: 0x0 */ 2155 __IO uint32_t CTRL; /**< DAC Control register. This register controls DMA and timer operation., offset: 0x4 */ 2156 __IO uint32_t CNTVAL; /**< DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer., offset: 0x8 */ 2157 } DAC_Type; 2158 2159 /* ---------------------------------------------------------------------------- 2160 -- DAC Register Masks 2161 ---------------------------------------------------------------------------- */ 2162 2163 /*! 2164 * @addtogroup DAC_Register_Masks DAC Register Masks 2165 * @{ 2166 */ 2167 2168 /*! @name CR - D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit. */ 2169 /*! @{ */ 2170 #define DAC_CR_VALUE_MASK (0xFFC0U) 2171 #define DAC_CR_VALUE_SHIFT (6U) 2172 /*! VALUE - After the selected settling time after this field is written with a new VALUE, the 2173 * voltage on the DAC_OUT pin (with respect to VSSA) is VALUE (VREFP - VREFN)/1024 + VREFN. 2174 */ 2175 #define DAC_CR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_VALUE_SHIFT)) & DAC_CR_VALUE_MASK) 2176 #define DAC_CR_BIAS_MASK (0x10000U) 2177 #define DAC_CR_BIAS_SHIFT (16U) 2178 /*! BIAS - The settling time of the DAC 2179 * 0b0..The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz. 2180 * 0b1..The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz. 2181 */ 2182 #define DAC_CR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_BIAS_SHIFT)) & DAC_CR_BIAS_MASK) 2183 /*! @} */ 2184 2185 /*! @name CTRL - DAC Control register. This register controls DMA and timer operation. */ 2186 /*! @{ */ 2187 #define DAC_CTRL_INT_DMA_REQ_MASK (0x1U) 2188 #define DAC_CTRL_INT_DMA_REQ_SHIFT (0U) 2189 /*! INT_DMA_REQ - DMA request 2190 * 0b0..This bit is cleared on any write to the DACR register. 2191 * 0b1..This bit is set by hardware when the timer times out. 2192 */ 2193 #define DAC_CTRL_INT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_INT_DMA_REQ_SHIFT)) & DAC_CTRL_INT_DMA_REQ_MASK) 2194 #define DAC_CTRL_DBLBUF_ENA_MASK (0x2U) 2195 #define DAC_CTRL_DBLBUF_ENA_SHIFT (1U) 2196 /*! DBLBUF_ENA - dacr double buffer 2197 * 0b0..DACR double-buffering is disabled. 2198 * 0b1..When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be 2199 * enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the 2200 * next time-out of the counter. 2201 */ 2202 #define DAC_CTRL_DBLBUF_ENA(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_DBLBUF_ENA_SHIFT)) & DAC_CTRL_DBLBUF_ENA_MASK) 2203 #define DAC_CTRL_CNT_ENA_MASK (0x4U) 2204 #define DAC_CTRL_CNT_ENA_SHIFT (2U) 2205 /*! CNT_ENA - time-out counter operation 2206 * 0b0..Time-out counter operation is disabled. 2207 * 0b1..Time-out counter operation is enabled. 2208 */ 2209 #define DAC_CTRL_CNT_ENA(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_CNT_ENA_SHIFT)) & DAC_CTRL_CNT_ENA_MASK) 2210 #define DAC_CTRL_DMA_ENA_MASK (0x8U) 2211 #define DAC_CTRL_DMA_ENA_SHIFT (3U) 2212 /*! DMA_ENA - DMA access 2213 * 0b0..DMA access is disabled. 2214 * 0b1..DMA Burst Request Input 7 is enabled for the DAC 2215 */ 2216 #define DAC_CTRL_DMA_ENA(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_DMA_ENA_SHIFT)) & DAC_CTRL_DMA_ENA_MASK) 2217 /*! @} */ 2218 2219 /*! @name CNTVAL - DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer. */ 2220 /*! @{ */ 2221 #define DAC_CNTVAL_VALUE_MASK (0xFFFFU) 2222 #define DAC_CNTVAL_VALUE_SHIFT (0U) 2223 /*! VALUE - 16-bit reload value for the DAC interrupt/DMA timer. 2224 */ 2225 #define DAC_CNTVAL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CNTVAL_VALUE_SHIFT)) & DAC_CNTVAL_VALUE_MASK) 2226 /*! @} */ 2227 2228 2229 /*! 2230 * @} 2231 */ /* end of group DAC_Register_Masks */ 2232 2233 2234 /* DAC - Peripheral instance base addresses */ 2235 /** Peripheral DAC0 base address */ 2236 #define DAC0_BASE (0x40014000u) 2237 /** Peripheral DAC0 base pointer */ 2238 #define DAC0 ((DAC_Type *)DAC0_BASE) 2239 /** Peripheral DAC1 base address */ 2240 #define DAC1_BASE (0x40018000u) 2241 /** Peripheral DAC1 base pointer */ 2242 #define DAC1 ((DAC_Type *)DAC1_BASE) 2243 /** Array initializer of DAC peripheral base addresses */ 2244 #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } 2245 /** Array initializer of DAC peripheral base pointers */ 2246 #define DAC_BASE_PTRS { DAC0, DAC1 } 2247 2248 /*! 2249 * @} 2250 */ /* end of group DAC_Peripheral_Access_Layer */ 2251 2252 2253 /* ---------------------------------------------------------------------------- 2254 -- DMA Peripheral Access Layer 2255 ---------------------------------------------------------------------------- */ 2256 2257 /*! 2258 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer 2259 * @{ 2260 */ 2261 2262 /** DMA - Register Layout Typedef */ 2263 typedef struct { 2264 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ 2265 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ 2266 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ 2267 uint8_t RESERVED_0[20]; 2268 struct { /* offset: 0x20, array step: 0x5C */ 2269 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ 2270 uint8_t RESERVED_0[4]; 2271 __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ 2272 uint8_t RESERVED_1[4]; 2273 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ 2274 uint8_t RESERVED_2[4]; 2275 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ 2276 uint8_t RESERVED_3[4]; 2277 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ 2278 uint8_t RESERVED_4[4]; 2279 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ 2280 uint8_t RESERVED_5[4]; 2281 __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ 2282 uint8_t RESERVED_6[4]; 2283 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ 2284 uint8_t RESERVED_7[4]; 2285 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ 2286 uint8_t RESERVED_8[4]; 2287 __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ 2288 uint8_t RESERVED_9[4]; 2289 __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ 2290 uint8_t RESERVED_10[4]; 2291 __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ 2292 } COMMON[1]; 2293 uint8_t RESERVED_1[900]; 2294 struct { /* offset: 0x400, array step: 0x10 */ 2295 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ 2296 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ 2297 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ 2298 uint8_t RESERVED_0[4]; 2299 } CHANNEL[25]; 2300 } DMA_Type; 2301 2302 /* ---------------------------------------------------------------------------- 2303 -- DMA Register Masks 2304 ---------------------------------------------------------------------------- */ 2305 2306 /*! 2307 * @addtogroup DMA_Register_Masks DMA Register Masks 2308 * @{ 2309 */ 2310 2311 /*! @name CTRL - DMA control. */ 2312 /*! @{ */ 2313 #define DMA_CTRL_ENABLE_MASK (0x1U) 2314 #define DMA_CTRL_ENABLE_SHIFT (0U) 2315 /*! ENABLE - DMA controller master enable. 2316 * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when 2317 * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. 2318 * 0b1..Enabled. The DMA controller is enabled. 2319 */ 2320 #define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) 2321 /*! @} */ 2322 2323 /*! @name INTSTAT - Interrupt status. */ 2324 /*! @{ */ 2325 #define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) 2326 #define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) 2327 /*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. 2328 * 0b0..Not pending. No enabled interrupts are pending. 2329 * 0b1..Pending. At least one enabled interrupt is pending. 2330 */ 2331 #define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) 2332 #define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) 2333 #define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) 2334 /*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. 2335 * 0b0..Not pending. No error interrupts are pending. 2336 * 0b1..Pending. At least one error interrupt is pending. 2337 */ 2338 #define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) 2339 /*! @} */ 2340 2341 /*! @name SRAMBASE - SRAM address of the channel configuration table. */ 2342 /*! @{ */ 2343 #define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) 2344 #define DMA_SRAMBASE_OFFSET_SHIFT (9U) 2345 /*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the 2346 * table must begin on a 512 byte boundary. 2347 */ 2348 #define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) 2349 /*! @} */ 2350 2351 /*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ 2352 /*! @{ */ 2353 #define DMA_COMMON_ENABLESET_ENA_MASK (0x1FFFFFFU) 2354 #define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) 2355 /*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = 2356 * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. 2357 */ 2358 #define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) 2359 /*! @} */ 2360 2361 /* The count of DMA_COMMON_ENABLESET */ 2362 #define DMA_COMMON_ENABLESET_COUNT (1U) 2363 2364 /*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ 2365 /*! @{ */ 2366 #define DMA_COMMON_ENABLECLR_CLR_MASK (0x1FFFFFFU) 2367 #define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) 2368 /*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears 2369 * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits 2370 * are reserved. 2371 */ 2372 #define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) 2373 /*! @} */ 2374 2375 /* The count of DMA_COMMON_ENABLECLR */ 2376 #define DMA_COMMON_ENABLECLR_COUNT (1U) 2377 2378 /*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ 2379 /*! @{ */ 2380 #define DMA_COMMON_ACTIVE_ACT_MASK (0x1FFFFFFU) 2381 #define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) 2382 /*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = 2383 * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. 2384 */ 2385 #define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) 2386 /*! @} */ 2387 2388 /* The count of DMA_COMMON_ACTIVE */ 2389 #define DMA_COMMON_ACTIVE_COUNT (1U) 2390 2391 /*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ 2392 /*! @{ */ 2393 #define DMA_COMMON_BUSY_BSY_MASK (0x1FFFFFFU) 2394 #define DMA_COMMON_BUSY_BSY_SHIFT (0U) 2395 /*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = 2396 * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. 2397 */ 2398 #define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) 2399 /*! @} */ 2400 2401 /* The count of DMA_COMMON_BUSY */ 2402 #define DMA_COMMON_BUSY_COUNT (1U) 2403 2404 /*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ 2405 /*! @{ */ 2406 #define DMA_COMMON_ERRINT_ERR_MASK (0x1FFFFFFU) 2407 #define DMA_COMMON_ERRINT_ERR_SHIFT (0U) 2408 /*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of 2409 * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is 2410 * not active. 1 = error interrupt is active. 2411 */ 2412 #define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) 2413 /*! @} */ 2414 2415 /* The count of DMA_COMMON_ERRINT */ 2416 #define DMA_COMMON_ERRINT_COUNT (1U) 2417 2418 /*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ 2419 /*! @{ */ 2420 #define DMA_COMMON_INTENSET_INTEN_MASK (0x1FFFFFFU) 2421 #define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) 2422 /*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The 2423 * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = 2424 * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. 2425 */ 2426 #define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) 2427 /*! @} */ 2428 2429 /* The count of DMA_COMMON_INTENSET */ 2430 #define DMA_COMMON_INTENSET_COUNT (1U) 2431 2432 /*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ 2433 /*! @{ */ 2434 #define DMA_COMMON_INTENCLR_CLR_MASK (0x1FFFFFFU) 2435 #define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) 2436 /*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n 2437 * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are 2438 * reserved. 2439 */ 2440 #define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) 2441 /*! @} */ 2442 2443 /* The count of DMA_COMMON_INTENCLR */ 2444 #define DMA_COMMON_INTENCLR_COUNT (1U) 2445 2446 /*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ 2447 /*! @{ */ 2448 #define DMA_COMMON_INTA_IA_MASK (0x1FFFFFFU) 2449 #define DMA_COMMON_INTA_IA_SHIFT (0U) 2450 /*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of 2451 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel 2452 * interrupt A is not active. 1 = the DMA channel interrupt A is active. 2453 */ 2454 #define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) 2455 /*! @} */ 2456 2457 /* The count of DMA_COMMON_INTA */ 2458 #define DMA_COMMON_INTA_COUNT (1U) 2459 2460 /*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ 2461 /*! @{ */ 2462 #define DMA_COMMON_INTB_IB_MASK (0x1FFFFFFU) 2463 #define DMA_COMMON_INTB_IB_SHIFT (0U) 2464 /*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of 2465 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel 2466 * interrupt B is not active. 1 = the DMA channel interrupt B is active. 2467 */ 2468 #define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) 2469 /*! @} */ 2470 2471 /* The count of DMA_COMMON_INTB */ 2472 #define DMA_COMMON_INTB_COUNT (1U) 2473 2474 /*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ 2475 /*! @{ */ 2476 #define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) 2477 #define DMA_COMMON_SETVALID_SV_SHIFT (0U) 2478 /*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits 2479 * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the 2480 * VALIDPENDING control bit for DMA channel n 2481 */ 2482 #define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) 2483 /*! @} */ 2484 2485 /* The count of DMA_COMMON_SETVALID */ 2486 #define DMA_COMMON_SETVALID_COUNT (1U) 2487 2488 /*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ 2489 /*! @{ */ 2490 #define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) 2491 #define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) 2492 /*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number 2493 * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = 2494 * sets the TRIG bit for DMA channel n. 2495 */ 2496 #define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) 2497 /*! @} */ 2498 2499 /* The count of DMA_COMMON_SETTRIG */ 2500 #define DMA_COMMON_SETTRIG_COUNT (1U) 2501 2502 /*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ 2503 /*! @{ */ 2504 #define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) 2505 #define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) 2506 /*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 2507 * 1 = aborts DMA operations on channel n. 2508 */ 2509 #define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) 2510 /*! @} */ 2511 2512 /* The count of DMA_COMMON_ABORT */ 2513 #define DMA_COMMON_ABORT_COUNT (1U) 2514 2515 /*! @name CHANNEL_CFG - Configuration register for DMA channel . */ 2516 /*! @{ */ 2517 #define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) 2518 #define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) 2519 /*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory 2520 * move, any peripheral DMA request associated with that channel can be disabled to prevent any 2521 * interaction between the peripheral and the DMA controller. 2522 * 0b0..Disabled. Peripheral DMA requests are disabled. 2523 * 0b1..Enabled. Peripheral DMA requests are enabled. 2524 */ 2525 #define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) 2526 #define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) 2527 #define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) 2528 /*! HWTRIGEN - Hardware Triggering Enable for this channel. 2529 * 0b0..Disabled. Hardware triggering is not used. 2530 * 0b1..Enabled. Use hardware triggering. 2531 */ 2532 #define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) 2533 #define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) 2534 #define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) 2535 /*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 2536 * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. 2537 * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. 2538 */ 2539 #define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) 2540 #define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) 2541 #define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) 2542 /*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. 2543 * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. 2544 * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 2545 * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the 2546 * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger 2547 * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the 2548 * current BURSTPOWER length are completed. 2549 */ 2550 #define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) 2551 #define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) 2552 #define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) 2553 /*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 2554 * 0b0..Single transfer. Hardware trigger causes a single transfer. 2555 * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a 2556 * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a 2557 * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is 2558 * complete. 2559 */ 2560 #define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) 2561 #define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) 2562 #define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) 2563 /*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when 2564 * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). 2565 * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many 2566 * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that 2567 * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: 2568 * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 2569 * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The 2570 * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even 2571 * multiple of the burst size. 2572 */ 2573 #define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) 2574 #define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) 2575 #define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) 2576 /*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is 2577 * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this 2578 * could be used to read several sequential registers from a peripheral for each DMA burst, 2579 * reading the same registers again for each burst. 2580 * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. 2581 * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. 2582 */ 2583 #define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) 2584 #define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) 2585 #define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) 2586 /*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is 2587 * 'wrapped', meaning that the destination address range for each burst will be the same. As an 2588 * example, this could be used to write several sequential registers to a peripheral for each DMA 2589 * burst, writing the same registers again for each burst. 2590 * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. 2591 * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. 2592 */ 2593 #define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) 2594 #define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) 2595 #define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) 2596 /*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority 2597 * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 2598 */ 2599 #define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) 2600 /*! @} */ 2601 2602 /* The count of DMA_CHANNEL_CFG */ 2603 #define DMA_CHANNEL_CFG_COUNT (25U) 2604 2605 /*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ 2606 /*! @{ */ 2607 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) 2608 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) 2609 /*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the 2610 * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 2611 * 0b0..No effect. No effect on DMA operation. 2612 * 0b1..Valid pending. 2613 */ 2614 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) 2615 #define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) 2616 #define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) 2617 /*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is 2618 * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2619 * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. 2620 * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. 2621 */ 2622 #define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) 2623 /*! @} */ 2624 2625 /* The count of DMA_CHANNEL_CTLSTAT */ 2626 #define DMA_CHANNEL_CTLSTAT_COUNT (25U) 2627 2628 /*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ 2629 /*! @{ */ 2630 #define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) 2631 #define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) 2632 /*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor 2633 * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 2634 * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. 2635 * 0b1..Valid. The current channel descriptor is considered valid. 2636 */ 2637 #define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) 2638 #define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) 2639 #define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) 2640 /*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current 2641 * descriptor is exhausted. Reloading allows ping-pong and linked transfers. 2642 * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. 2643 * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. 2644 */ 2645 #define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) 2646 #define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) 2647 #define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) 2648 /*! SWTRIG - Software Trigger. 2649 * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by 2650 * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. 2651 * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not 2652 * be used with level triggering when TRIGBURST = 0. 2653 */ 2654 #define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) 2655 #define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) 2656 #define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) 2657 /*! CLRTRIG - Clear Trigger. 2658 * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. 2659 * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted 2660 */ 2661 #define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) 2662 #define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) 2663 #define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) 2664 /*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between 2665 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By 2666 * convention, interrupt A may be used when only one interrupt flag is needed. 2667 * 0b0..No effect. 2668 * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. 2669 */ 2670 #define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) 2671 #define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) 2672 #define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) 2673 /*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between 2674 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By 2675 * convention, interrupt A may be used when only one interrupt flag is needed. 2676 * 0b0..No effect. 2677 * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. 2678 */ 2679 #define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) 2680 #define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) 2681 #define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) 2682 /*! WIDTH - Transfer width used for this DMA channel. 2683 * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). 2684 * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). 2685 * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). 2686 * 0b11..Reserved. Reserved setting, do not use. 2687 */ 2688 #define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) 2689 #define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) 2690 #define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) 2691 /*! SRCINC - Determines whether the source address is incremented for each DMA transfer. 2692 * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. 2693 * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is 2694 * the usual case when the source is memory. 2695 * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. 2696 * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. 2697 */ 2698 #define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) 2699 #define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) 2700 #define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) 2701 /*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. 2702 * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when 2703 * the destination is a peripheral device. 2704 * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. 2705 * This is the usual case when the destination is memory. 2706 * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. 2707 * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. 2708 */ 2709 #define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) 2710 #define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) 2711 #define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) 2712 /*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes 2713 * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller 2714 * uses this bit field during transfer to count down. Hence, it cannot be used by software to read 2715 * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 2716 * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 2717 * 1,024 transfers will be performed. 2718 */ 2719 #define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) 2720 /*! @} */ 2721 2722 /* The count of DMA_CHANNEL_XFERCFG */ 2723 #define DMA_CHANNEL_XFERCFG_COUNT (25U) 2724 2725 2726 /*! 2727 * @} 2728 */ /* end of group DMA_Register_Masks */ 2729 2730 2731 /* DMA - Peripheral instance base addresses */ 2732 /** Peripheral DMA0 base address */ 2733 #define DMA0_BASE (0x50008000u) 2734 /** Peripheral DMA0 base pointer */ 2735 #define DMA0 ((DMA_Type *)DMA0_BASE) 2736 /** Array initializer of DMA peripheral base addresses */ 2737 #define DMA_BASE_ADDRS { DMA0_BASE } 2738 /** Array initializer of DMA peripheral base pointers */ 2739 #define DMA_BASE_PTRS { DMA0 } 2740 /** Interrupt vectors for the DMA peripheral type */ 2741 #define DMA_IRQS { DMA0_IRQn } 2742 2743 /*! 2744 * @} 2745 */ /* end of group DMA_Peripheral_Access_Layer */ 2746 2747 2748 /* ---------------------------------------------------------------------------- 2749 -- FLASH_CTRL Peripheral Access Layer 2750 ---------------------------------------------------------------------------- */ 2751 2752 /*! 2753 * @addtogroup FLASH_CTRL_Peripheral_Access_Layer FLASH_CTRL Peripheral Access Layer 2754 * @{ 2755 */ 2756 2757 /** FLASH_CTRL - Register Layout Typedef */ 2758 typedef struct { 2759 uint8_t RESERVED_0[16]; 2760 __IO uint32_t FLASHCFG; /**< Flash configuration register, offset: 0x10 */ 2761 uint8_t RESERVED_1[12]; 2762 __IO uint32_t FMSSTART; /**< Flash signature start address register, offset: 0x20 */ 2763 __IO uint32_t FMSSTOP; /**< Flash signaure stop address register, offset: 0x24 */ 2764 uint8_t RESERVED_2[4]; 2765 __I uint32_t FMSW0; /**< Flash signature generation result register returns the flash signature produced by the embedded signature generator.., offset: 0x2C */ 2766 uint8_t RESERVED_3[4016]; 2767 __I uint32_t FMSTAT; /**< Flash signature generation status bit, offset: 0xFE0 */ 2768 uint8_t RESERVED_4[4]; 2769 __O uint32_t FMSTATCLR; /**< Clear FLASH signature generation status bit, offset: 0xFE8 */ 2770 } FLASH_CTRL_Type; 2771 2772 /* ---------------------------------------------------------------------------- 2773 -- FLASH_CTRL Register Masks 2774 ---------------------------------------------------------------------------- */ 2775 2776 /*! 2777 * @addtogroup FLASH_CTRL_Register_Masks FLASH_CTRL Register Masks 2778 * @{ 2779 */ 2780 2781 /*! @name FLASHCFG - Flash configuration register */ 2782 /*! @{ */ 2783 #define FLASH_CTRL_FLASHCFG_FLASHTIM_MASK (0x3U) 2784 #define FLASH_CTRL_FLASHCFG_FLASHTIM_SHIFT (0U) 2785 /*! FLASHTIM - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access. 2786 * 0b00..1 system clock flash access time. 2787 * 0b01..2 system clock flash access time. 2788 * 0b10..3 system clock flash access time. 2789 * 0b11..Reserved. 2790 */ 2791 #define FLASH_CTRL_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FLASHCFG_FLASHTIM_SHIFT)) & FLASH_CTRL_FLASHCFG_FLASHTIM_MASK) 2792 /*! @} */ 2793 2794 /*! @name FMSSTART - Flash signature start address register */ 2795 /*! @{ */ 2796 #define FLASH_CTRL_FMSSTART_START_MASK (0x1FFFFU) 2797 #define FLASH_CTRL_FMSSTART_START_SHIFT (0U) 2798 /*! START - Signature generation start address (corresponds to AHB byte address bits[18:2]). 2799 */ 2800 #define FLASH_CTRL_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTART_START_SHIFT)) & FLASH_CTRL_FMSSTART_START_MASK) 2801 /*! @} */ 2802 2803 /*! @name FMSSTOP - Flash signaure stop address register */ 2804 /*! @{ */ 2805 #define FLASH_CTRL_FMSSTOP_STOPA_MASK (0x1FFFFU) 2806 #define FLASH_CTRL_FMSSTOP_STOPA_SHIFT (0U) 2807 /*! STOPA - Stop address for signature generation (the word specified by STOP is included in the 2808 * address range). The address is in units of memory words, not bytes. 2809 */ 2810 #define FLASH_CTRL_FMSSTOP_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTOP_STOPA_SHIFT)) & FLASH_CTRL_FMSSTOP_STOPA_MASK) 2811 #define FLASH_CTRL_FMSSTOP_STRTBIST_MASK (0x80000000U) 2812 #define FLASH_CTRL_FMSSTOP_STRTBIST_SHIFT (31U) 2813 /*! STRTBIST - When this bit is written to 1, signature generation starts. At the end of signature 2814 * generation, this bit is automatically cleared. 2815 */ 2816 #define FLASH_CTRL_FMSSTOP_STRTBIST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTOP_STRTBIST_SHIFT)) & FLASH_CTRL_FMSSTOP_STRTBIST_MASK) 2817 /*! @} */ 2818 2819 /*! @name FMSW0 - Flash signature generation result register returns the flash signature produced by the embedded signature generator.. */ 2820 /*! @{ */ 2821 #define FLASH_CTRL_FMSW0_SIG_MASK (0xFFFFFFFFU) 2822 #define FLASH_CTRL_FMSW0_SIG_SHIFT (0U) 2823 /*! SIG - 32-bit signature. 2824 */ 2825 #define FLASH_CTRL_FMSW0_SIG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSW0_SIG_SHIFT)) & FLASH_CTRL_FMSW0_SIG_MASK) 2826 /*! @} */ 2827 2828 /*! @name FMSTAT - Flash signature generation status bit */ 2829 /*! @{ */ 2830 #define FLASH_CTRL_FMSTAT_SIG_DONE_MASK (0x2U) 2831 #define FLASH_CTRL_FMSTAT_SIG_DONE_SHIFT (1U) 2832 /*! SIG_DONE - This status bit is set at the end of signature computation 2833 */ 2834 #define FLASH_CTRL_FMSTAT_SIG_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSTAT_SIG_DONE_SHIFT)) & FLASH_CTRL_FMSTAT_SIG_DONE_MASK) 2835 /*! @} */ 2836 2837 /*! @name FMSTATCLR - Clear FLASH signature generation status bit */ 2838 /*! @{ */ 2839 #define FLASH_CTRL_FMSTATCLR_SIG_DONE_CLR_MASK (0x2U) 2840 #define FLASH_CTRL_FMSTATCLR_SIG_DONE_CLR_SHIFT (1U) 2841 /*! SIG_DONE_CLR - When the bit is written to 1, the SIGNATURE_DONE bit is cleared. 2842 */ 2843 #define FLASH_CTRL_FMSTATCLR_SIG_DONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSTATCLR_SIG_DONE_CLR_SHIFT)) & FLASH_CTRL_FMSTATCLR_SIG_DONE_CLR_MASK) 2844 /*! @} */ 2845 2846 2847 /*! 2848 * @} 2849 */ /* end of group FLASH_CTRL_Register_Masks */ 2850 2851 2852 /* FLASH_CTRL - Peripheral instance base addresses */ 2853 /** Peripheral FLASH_CTRL base address */ 2854 #define FLASH_CTRL_BASE (0x40040000u) 2855 /** Peripheral FLASH_CTRL base pointer */ 2856 #define FLASH_CTRL ((FLASH_CTRL_Type *)FLASH_CTRL_BASE) 2857 /** Array initializer of FLASH_CTRL peripheral base addresses */ 2858 #define FLASH_CTRL_BASE_ADDRS { FLASH_CTRL_BASE } 2859 /** Array initializer of FLASH_CTRL peripheral base pointers */ 2860 #define FLASH_CTRL_BASE_PTRS { FLASH_CTRL } 2861 /** Interrupt vectors for the FLASH_CTRL peripheral type */ 2862 #define FLASH_CTRL_IRQS { FLASH_IRQn } 2863 2864 /*! 2865 * @} 2866 */ /* end of group FLASH_CTRL_Peripheral_Access_Layer */ 2867 2868 2869 /* ---------------------------------------------------------------------------- 2870 -- GPIO Peripheral Access Layer 2871 ---------------------------------------------------------------------------- */ 2872 2873 /*! 2874 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 2875 * @{ 2876 */ 2877 2878 /** GPIO - Register Layout Typedef */ 2879 typedef struct { 2880 __IO uint8_t B[2][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ 2881 uint8_t RESERVED_0[4032]; 2882 __IO uint32_t W[2][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ 2883 uint8_t RESERVED_1[3840]; 2884 __IO uint32_t DIR[2]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */ 2885 uint8_t RESERVED_2[120]; 2886 __IO uint32_t MASK[2]; /**< Mask register, array offset: 0x2080, array step: 0x4 */ 2887 uint8_t RESERVED_3[120]; 2888 __IO uint32_t PIN[2]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */ 2889 uint8_t RESERVED_4[120]; 2890 __IO uint32_t MPIN[2]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */ 2891 uint8_t RESERVED_5[120]; 2892 __IO uint32_t SET[2]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */ 2893 uint8_t RESERVED_6[120]; 2894 __O uint32_t CLR[2]; /**< Clear port, array offset: 0x2280, array step: 0x4 */ 2895 uint8_t RESERVED_7[120]; 2896 __O uint32_t NOT[2]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */ 2897 uint8_t RESERVED_8[120]; 2898 __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ 2899 uint8_t RESERVED_9[120]; 2900 __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ 2901 uint8_t RESERVED_10[120]; 2902 __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ 2903 } GPIO_Type; 2904 2905 /* ---------------------------------------------------------------------------- 2906 -- GPIO Register Masks 2907 ---------------------------------------------------------------------------- */ 2908 2909 /*! 2910 * @addtogroup GPIO_Register_Masks GPIO Register Masks 2911 * @{ 2912 */ 2913 2914 /*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ 2915 /*! @{ */ 2916 #define GPIO_B_PBYTE_MASK (0x1U) 2917 #define GPIO_B_PBYTE_SHIFT (0U) 2918 /*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, 2919 * except that pins configured as analog I/O always read as 0. One register for each port pin. 2920 * Supported pins depends on the specific device and package. Write: loads the pin's output bit. 2921 * One register for each port pin. Supported pins depends on the specific device and package. 2922 */ 2923 #define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) 2924 /*! @} */ 2925 2926 /* The count of GPIO_B */ 2927 #define GPIO_B_COUNT (2U) 2928 2929 /* The count of GPIO_B */ 2930 #define GPIO_B_COUNT2 (32U) 2931 2932 /*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ 2933 /*! @{ */ 2934 #define GPIO_W_PWORD_MASK (0xFFFFFFFFU) 2935 #define GPIO_W_PWORD_SHIFT (0U) 2936 /*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is 2937 * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be 2938 * read. Writing any value other than 0 will set the output bit. One register for each port pin. 2939 * Supported pins depends on the specific device and package. 2940 */ 2941 #define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) 2942 /*! @} */ 2943 2944 /* The count of GPIO_W */ 2945 #define GPIO_W_COUNT (2U) 2946 2947 /* The count of GPIO_W */ 2948 #define GPIO_W_COUNT2 (32U) 2949 2950 /*! @name DIR - Direction registers */ 2951 /*! @{ */ 2952 #define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) 2953 #define GPIO_DIR_DIRP_SHIFT (0U) 2954 /*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported 2955 * pins depends on the specific device and package. 0 = input. 1 = output. 2956 */ 2957 #define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) 2958 /*! @} */ 2959 2960 /* The count of GPIO_DIR */ 2961 #define GPIO_DIR_COUNT (2U) 2962 2963 /*! @name MASK - Mask register */ 2964 /*! @{ */ 2965 #define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) 2966 #define GPIO_MASK_MASKP_SHIFT (0U) 2967 /*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = 2968 * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = 2969 * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit 2970 * not affected. 2971 */ 2972 #define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) 2973 /*! @} */ 2974 2975 /* The count of GPIO_MASK */ 2976 #define GPIO_MASK_COUNT (2U) 2977 2978 /*! @name PIN - Port pin register */ 2979 /*! @{ */ 2980 #define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) 2981 #define GPIO_PIN_PORT_SHIFT (0U) 2982 /*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported 2983 * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 2984 * 1 = Read: pin is high; write: set output bit. 2985 */ 2986 #define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) 2987 /*! @} */ 2988 2989 /* The count of GPIO_PIN */ 2990 #define GPIO_PIN_COUNT (2U) 2991 2992 /*! @name MPIN - Masked port register */ 2993 /*! @{ */ 2994 #define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) 2995 #define GPIO_MPIN_MPORTP_SHIFT (0U) 2996 /*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 2997 * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK 2998 * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 2999 * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit 3000 * if the corresponding bit in the MASK register is 0. 3001 */ 3002 #define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) 3003 /*! @} */ 3004 3005 /* The count of GPIO_MPIN */ 3006 #define GPIO_MPIN_COUNT (2U) 3007 3008 /*! @name SET - Write: Set register for port Read: output bits for port */ 3009 /*! @{ */ 3010 #define GPIO_SET_SETP_MASK (0xFFFFFFFFU) 3011 #define GPIO_SET_SETP_SHIFT (0U) 3012 /*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 3013 * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output 3014 * bit; write: set output bit. 3015 */ 3016 #define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) 3017 /*! @} */ 3018 3019 /* The count of GPIO_SET */ 3020 #define GPIO_SET_COUNT (2U) 3021 3022 /*! @name CLR - Clear port */ 3023 /*! @{ */ 3024 #define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) 3025 #define GPIO_CLR_CLRP_SHIFT (0U) 3026 /*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the 3027 * specific device and package. 0 = No operation. 1 = Clear output bit. 3028 */ 3029 #define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) 3030 /*! @} */ 3031 3032 /* The count of GPIO_CLR */ 3033 #define GPIO_CLR_COUNT (2U) 3034 3035 /*! @name NOT - Toggle port */ 3036 /*! @{ */ 3037 #define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) 3038 #define GPIO_NOT_NOTP_SHIFT (0U) 3039 /*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the 3040 * specific device and package. 0 = no operation. 1 = Toggle output bit. 3041 */ 3042 #define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) 3043 /*! @} */ 3044 3045 /* The count of GPIO_NOT */ 3046 #define GPIO_NOT_COUNT (2U) 3047 3048 /*! @name DIRSET - Set pin direction bits for port */ 3049 /*! @{ */ 3050 #define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) 3051 #define GPIO_DIRSET_DIRSETP_SHIFT (0U) 3052 /*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 3053 * the specific device and package. 0 = No operation. 1 = Set direction bit. 3054 */ 3055 #define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) 3056 /*! @} */ 3057 3058 /* The count of GPIO_DIRSET */ 3059 #define GPIO_DIRSET_COUNT (2U) 3060 3061 /*! @name DIRCLR - Clear pin direction bits for port */ 3062 /*! @{ */ 3063 #define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) 3064 #define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) 3065 /*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 3066 * the specific device and package. 0 = No operation. 1 = Clear direction bit. 3067 */ 3068 #define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) 3069 /*! @} */ 3070 3071 /* The count of GPIO_DIRCLR */ 3072 #define GPIO_DIRCLR_COUNT (2U) 3073 3074 /*! @name DIRNOT - Toggle pin direction bits for port */ 3075 /*! @{ */ 3076 #define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) 3077 #define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) 3078 /*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends 3079 * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. 3080 */ 3081 #define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) 3082 /*! @} */ 3083 3084 /* The count of GPIO_DIRNOT */ 3085 #define GPIO_DIRNOT_COUNT (2U) 3086 3087 3088 /*! 3089 * @} 3090 */ /* end of group GPIO_Register_Masks */ 3091 3092 3093 /* GPIO - Peripheral instance base addresses */ 3094 /** Peripheral GPIO base address */ 3095 #define GPIO_BASE (0xA0000000u) 3096 /** Peripheral GPIO base pointer */ 3097 #define GPIO ((GPIO_Type *)GPIO_BASE) 3098 /** Array initializer of GPIO peripheral base addresses */ 3099 #define GPIO_BASE_ADDRS { GPIO_BASE } 3100 /** Array initializer of GPIO peripheral base pointers */ 3101 #define GPIO_BASE_PTRS { GPIO } 3102 3103 /*! 3104 * @} 3105 */ /* end of group GPIO_Peripheral_Access_Layer */ 3106 3107 3108 /* ---------------------------------------------------------------------------- 3109 -- I2C Peripheral Access Layer 3110 ---------------------------------------------------------------------------- */ 3111 3112 /*! 3113 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 3114 * @{ 3115 */ 3116 3117 /** I2C - Register Layout Typedef */ 3118 typedef struct { 3119 __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x0 */ 3120 __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x4 */ 3121 __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x8 */ 3122 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0xC */ 3123 __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x10 */ 3124 __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x14 */ 3125 __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x18 */ 3126 uint8_t RESERVED_0[4]; 3127 __IO uint32_t MSTCTL; /**< Master control register., offset: 0x20 */ 3128 __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x24 */ 3129 __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x28 */ 3130 uint8_t RESERVED_1[20]; 3131 __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x40 */ 3132 __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x44 */ 3133 __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x48, array step: 0x4 */ 3134 __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x58 */ 3135 uint8_t RESERVED_2[36]; 3136 __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x80 */ 3137 } I2C_Type; 3138 3139 /* ---------------------------------------------------------------------------- 3140 -- I2C Register Masks 3141 ---------------------------------------------------------------------------- */ 3142 3143 /*! 3144 * @addtogroup I2C_Register_Masks I2C Register Masks 3145 * @{ 3146 */ 3147 3148 /*! @name CFG - Configuration for shared functions. */ 3149 /*! @{ */ 3150 #define I2C_CFG_MSTEN_MASK (0x1U) 3151 #define I2C_CFG_MSTEN_SHIFT (0U) 3152 /*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not 3153 * changed, but the Master function is internally reset. 3154 * 0b0..Disabled. The I2C Master function is disabled. 3155 * 0b1..Enabled. The I2C Master function is enabled. 3156 */ 3157 #define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) 3158 #define I2C_CFG_SLVEN_MASK (0x2U) 3159 #define I2C_CFG_SLVEN_SHIFT (1U) 3160 /*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not 3161 * changed, but the Slave function is internally reset. 3162 * 0b0..Disabled. The I2C slave function is disabled. 3163 * 0b1..Enabled. The I2C slave function is enabled. 3164 */ 3165 #define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) 3166 #define I2C_CFG_MONEN_MASK (0x4U) 3167 #define I2C_CFG_MONEN_SHIFT (2U) 3168 /*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not 3169 * changed, but the Monitor function is internally reset. 3170 * 0b0..Disabled. The I2C Monitor function is disabled. 3171 * 0b1..Enabled. The I2C Monitor function is enabled. 3172 */ 3173 #define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) 3174 #define I2C_CFG_TIMEOUTEN_MASK (0x8U) 3175 #define I2C_CFG_TIMEOUTEN_SHIFT (3U) 3176 /*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. 3177 * 0b0..Disabled. Time-out function is disabled. 3178 * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause 3179 * interrupts if they are enabled. Typically, only one time-out will be used in a system. 3180 */ 3181 #define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) 3182 #define I2C_CFG_MONCLKSTR_MASK (0x10U) 3183 #define I2C_CFG_MONCLKSTR_SHIFT (4U) 3184 /*! MONCLKSTR - Monitor function Clock Stretching. 3185 * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able 3186 * to read data provided by the Monitor function before it is overwritten. This mode may be used when 3187 * non-invasive monitoring is critical. 3188 * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can 3189 * read all incoming data supplied by the Monitor function. 3190 */ 3191 #define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) 3192 /*! @} */ 3193 3194 /*! @name STAT - Status register for Master, Slave, and Monitor functions. */ 3195 /*! @{ */ 3196 #define I2C_STAT_MSTPENDING_MASK (0x1U) 3197 #define I2C_STAT_MSTPENDING_SHIFT (0U) 3198 /*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on 3199 * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what 3200 * type of software service if any the master expects. This flag will cause an interrupt when set 3201 * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling 3202 * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle 3203 * state, and no communication is needed, mask this interrupt. 3204 * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. 3205 * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the 3206 * idle state, it is waiting to receive or transmit data or the NACK bit. 3207 */ 3208 #define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) 3209 #define I2C_STAT_MSTSTATE_MASK (0xEU) 3210 #define I2C_STAT_MSTSTATE_SHIFT (1U) 3211 /*! MSTSTATE - Master State code. The master state code reflects the master state when the 3212 * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field 3213 * indicates a specific required service for the Master function. All other values are reserved. See 3214 * Table 400 for details of state values and appropriate responses. 3215 * 0b000..Idle. The Master function is available to be used for a new transaction. 3216 * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. 3217 * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. 3218 * 0b011..NACK Address. Slave NACKed address. 3219 * 0b100..NACK Data. Slave NACKed transmitted data. 3220 */ 3221 #define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) 3222 #define I2C_STAT_MSTARBLOSS_MASK (0x10U) 3223 #define I2C_STAT_MSTARBLOSS_SHIFT (4U) 3224 /*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to 3225 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 3226 * 0b0..No Arbitration Loss has occurred. 3227 * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master 3228 * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, 3229 * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. 3230 */ 3231 #define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) 3232 #define I2C_STAT_MSTSTSTPERR_MASK (0x40U) 3233 #define I2C_STAT_MSTSTSTPERR_SHIFT (6U) 3234 /*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to 3235 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 3236 * 0b0..No Start/Stop Error has occurred. 3237 * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is 3238 * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an 3239 * idle state, no action is required. A request for a Start could be made, or software could attempt to insure 3240 * that the bus has not stalled. 3241 */ 3242 #define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) 3243 #define I2C_STAT_SLVPENDING_MASK (0x100U) 3244 #define I2C_STAT_SLVPENDING_SHIFT (8U) 3245 /*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue 3246 * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if 3247 * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the 3248 * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is 3249 * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time 3250 * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 3251 * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are 3252 * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must 3253 * also be detected automatically, since the address must be acknowledged before the clock can be 3254 * stretched. 3255 * 0b0..In progress. The Slave function does not currently need service. 3256 * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. 3257 */ 3258 #define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) 3259 #define I2C_STAT_SLVSTATE_MASK (0x600U) 3260 #define I2C_STAT_SLVSTATE_SHIFT (9U) 3261 /*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for 3262 * the Slave function. All other values are reserved. See Table 401 for state values and actions. 3263 * note that the occurrence of some states and how they are handled are affected by DMA mode and 3264 * Automatic Operation modes. 3265 * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. 3266 * 0b01..Slave receive. Received data is available (Slave Receiver mode). 3267 * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). 3268 */ 3269 #define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) 3270 #define I2C_STAT_SLVNOTSTR_MASK (0x800U) 3271 #define I2C_STAT_SLVNOTSTR_SHIFT (11U) 3272 /*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. 3273 * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave 3274 * operation. This read-only flag reflects the slave function status in real time. 3275 * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. 3276 * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or 3277 * Power-down mode could be entered at this time. 3278 */ 3279 #define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) 3280 #define I2C_STAT_SLVIDX_MASK (0x3000U) 3281 #define I2C_STAT_SLVIDX_SHIFT (12U) 3282 /*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been 3283 * selected by receiving an address that matches one of the slave addresses defined by any enabled 3284 * slave address registers, and provides an identification of the address that was matched. It is 3285 * possible that more than one address could be matched, but only one match can be reported here. 3286 * 0b00..Address 0. Slave address 0 was matched. 3287 * 0b01..Address 1. Slave address 1 was matched. 3288 * 0b10..Address 2. Slave address 2 was matched. 3289 * 0b11..Address 3. Slave address 3 was matched. 3290 */ 3291 #define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) 3292 #define I2C_STAT_SLVSEL_MASK (0x4000U) 3293 #define I2C_STAT_SLVSEL_SHIFT (14U) 3294 /*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave 3295 * function to acknowledge the address, or when the address has been automatically acknowledged. 3296 * It is cleared when another address cycle presents an address that does not match an enabled 3297 * address on the Slave function, when slave software decides to NACK a matched address, when 3298 * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of 3299 * Automatic Operation. SLVSEL is not cleared if software NACKs data. 3300 * 0b0..Not selected. The Slave function is not currently selected. 3301 * 0b1..Selected. The Slave function is currently selected. 3302 */ 3303 #define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) 3304 #define I2C_STAT_SLVDESEL_MASK (0x8000U) 3305 #define I2C_STAT_SLVDESEL_SHIFT (15U) 3306 /*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via 3307 * INTENSET. This flag can be cleared by writing a 1 to this bit. 3308 * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently 3309 * selected. That information can be found in the SLVSEL flag. 3310 * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag 3311 * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. 3312 */ 3313 #define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) 3314 #define I2C_STAT_MONRDY_MASK (0x10000U) 3315 #define I2C_STAT_MONRDY_SHIFT (16U) 3316 /*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. 3317 * 0b0..No data. The Monitor function does not currently have data available. 3318 * 0b1..Data waiting. The Monitor function has data waiting to be read. 3319 */ 3320 #define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) 3321 #define I2C_STAT_MONOV_MASK (0x20000U) 3322 #define I2C_STAT_MONOV_SHIFT (17U) 3323 /*! MONOV - Monitor Overflow flag. 3324 * 0b0..No overrun. Monitor data has not overrun. 3325 * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not 3326 * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. 3327 */ 3328 #define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) 3329 #define I2C_STAT_MONACTIVE_MASK (0x40000U) 3330 #define I2C_STAT_MONACTIVE_SHIFT (18U) 3331 /*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to 3332 * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred 3333 * more recently than a bus Stop. 3334 * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. 3335 * 0b1..Active. The Monitor function considers the I2C bus to be active. 3336 */ 3337 #define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) 3338 #define I2C_STAT_MONIDLE_MASK (0x80000U) 3339 #define I2C_STAT_MONIDLE_SHIFT (19U) 3340 /*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change 3341 * from active to inactive. This can be used by software to decide when to process data 3342 * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the 3343 * INTENSET register. The flag can be cleared by writing a 1 to this bit. 3344 * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. 3345 * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. 3346 */ 3347 #define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) 3348 #define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) 3349 #define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) 3350 /*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been 3351 * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock 3352 * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus 3353 * is idle. 3354 * 0b0..No time-out. I2C bus events have not caused a time-out. 3355 * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. 3356 */ 3357 #define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) 3358 #define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) 3359 #define I2C_STAT_SCLTIMEOUT_SHIFT (25U) 3360 /*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the 3361 * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. 3362 * 0b0..No time-out. SCL low time has not caused a time-out. 3363 * 0b1..Time-out. SCL low time has caused a time-out. 3364 */ 3365 #define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) 3366 /*! @} */ 3367 3368 /*! @name INTENSET - Interrupt Enable Set and read register. */ 3369 /*! @{ */ 3370 #define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) 3371 #define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) 3372 /*! MSTPENDINGEN - Master Pending interrupt Enable. 3373 * 0b0..Disabled. The MstPending interrupt is disabled. 3374 * 0b1..Enabled. The MstPending interrupt is enabled. 3375 */ 3376 #define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) 3377 #define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) 3378 #define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) 3379 /*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. 3380 * 0b0..Disabled. The MstArbLoss interrupt is disabled. 3381 * 0b1..Enabled. The MstArbLoss interrupt is enabled. 3382 */ 3383 #define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) 3384 #define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) 3385 #define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) 3386 /*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. 3387 * 0b0..Disabled. The MstStStpErr interrupt is disabled. 3388 * 0b1..Enabled. The MstStStpErr interrupt is enabled. 3389 */ 3390 #define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) 3391 #define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) 3392 #define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) 3393 /*! SLVPENDINGEN - Slave Pending interrupt Enable. 3394 * 0b0..Disabled. The SlvPending interrupt is disabled. 3395 * 0b1..Enabled. The SlvPending interrupt is enabled. 3396 */ 3397 #define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) 3398 #define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) 3399 #define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) 3400 /*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. 3401 * 0b0..Disabled. The SlvNotStr interrupt is disabled. 3402 * 0b1..Enabled. The SlvNotStr interrupt is enabled. 3403 */ 3404 #define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) 3405 #define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) 3406 #define I2C_INTENSET_SLVDESELEN_SHIFT (15U) 3407 /*! SLVDESELEN - Slave Deselect interrupt Enable. 3408 * 0b0..Disabled. The SlvDeSel interrupt is disabled. 3409 * 0b1..Enabled. The SlvDeSel interrupt is enabled. 3410 */ 3411 #define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) 3412 #define I2C_INTENSET_MONRDYEN_MASK (0x10000U) 3413 #define I2C_INTENSET_MONRDYEN_SHIFT (16U) 3414 /*! MONRDYEN - Monitor data Ready interrupt Enable. 3415 * 0b0..Disabled. The MonRdy interrupt is disabled. 3416 * 0b1..Enabled. The MonRdy interrupt is enabled. 3417 */ 3418 #define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) 3419 #define I2C_INTENSET_MONOVEN_MASK (0x20000U) 3420 #define I2C_INTENSET_MONOVEN_SHIFT (17U) 3421 /*! MONOVEN - Monitor Overrun interrupt Enable. 3422 * 0b0..Disabled. The MonOv interrupt is disabled. 3423 * 0b1..Enabled. The MonOv interrupt is enabled. 3424 */ 3425 #define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) 3426 #define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) 3427 #define I2C_INTENSET_MONIDLEEN_SHIFT (19U) 3428 /*! MONIDLEEN - Monitor Idle interrupt Enable. 3429 * 0b0..Disabled. The MonIdle interrupt is disabled. 3430 * 0b1..Enabled. The MonIdle interrupt is enabled. 3431 */ 3432 #define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) 3433 #define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) 3434 #define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) 3435 /*! EVENTTIMEOUTEN - Event time-out interrupt Enable. 3436 * 0b0..Disabled. The Event time-out interrupt is disabled. 3437 * 0b1..Enabled. The Event time-out interrupt is enabled. 3438 */ 3439 #define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) 3440 #define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) 3441 #define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) 3442 /*! SCLTIMEOUTEN - SCL time-out interrupt Enable. 3443 * 0b0..Disabled. The SCL time-out interrupt is disabled. 3444 * 0b1..Enabled. The SCL time-out interrupt is enabled. 3445 */ 3446 #define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) 3447 /*! @} */ 3448 3449 /*! @name INTENCLR - Interrupt Enable Clear register. */ 3450 /*! @{ */ 3451 #define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) 3452 #define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) 3453 /*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding 3454 * bit in the INTENSET register if implemented. 3455 */ 3456 #define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) 3457 #define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) 3458 #define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) 3459 /*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. 3460 */ 3461 #define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) 3462 #define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) 3463 #define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) 3464 /*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. 3465 */ 3466 #define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) 3467 #define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) 3468 #define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) 3469 /*! SLVPENDINGCLR - Slave Pending interrupt clear. 3470 */ 3471 #define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) 3472 #define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) 3473 #define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) 3474 /*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. 3475 */ 3476 #define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) 3477 #define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) 3478 #define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) 3479 /*! SLVDESELCLR - Slave Deselect interrupt clear. 3480 */ 3481 #define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) 3482 #define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) 3483 #define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) 3484 /*! MONRDYCLR - Monitor data Ready interrupt clear. 3485 */ 3486 #define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) 3487 #define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) 3488 #define I2C_INTENCLR_MONOVCLR_SHIFT (17U) 3489 /*! MONOVCLR - Monitor Overrun interrupt clear. 3490 */ 3491 #define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) 3492 #define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) 3493 #define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) 3494 /*! MONIDLECLR - Monitor Idle interrupt clear. 3495 */ 3496 #define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) 3497 #define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) 3498 #define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) 3499 /*! EVENTTIMEOUTCLR - Event time-out interrupt clear. 3500 */ 3501 #define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) 3502 #define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) 3503 #define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) 3504 /*! SCLTIMEOUTCLR - SCL time-out interrupt clear. 3505 */ 3506 #define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) 3507 /*! @} */ 3508 3509 /*! @name TIMEOUT - Time-out value register. */ 3510 /*! @{ */ 3511 #define I2C_TIMEOUT_TOMIN_MASK (0xFU) 3512 #define I2C_TIMEOUT_TOMIN_SHIFT (0U) 3513 /*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum 3514 * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. 3515 */ 3516 #define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) 3517 #define I2C_TIMEOUT_TO_MASK (0xFFF0U) 3518 #define I2C_TIMEOUT_TO_SHIFT (4U) 3519 /*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C 3520 * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, 3521 * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A 3522 * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 3523 * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the 3524 * I2C function clock. 3525 */ 3526 #define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) 3527 /*! @} */ 3528 3529 /*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ 3530 /*! @{ */ 3531 #define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) 3532 #define I2C_CLKDIV_DIVVAL_SHIFT (0U) 3533 /*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that 3534 * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = 3535 * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is 3536 * divided by 65,536 before use. 3537 */ 3538 #define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) 3539 /*! @} */ 3540 3541 /*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ 3542 /*! @{ */ 3543 #define I2C_INTSTAT_MSTPENDING_MASK (0x1U) 3544 #define I2C_INTSTAT_MSTPENDING_SHIFT (0U) 3545 /*! MSTPENDING - Master Pending. 3546 */ 3547 #define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) 3548 #define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) 3549 #define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) 3550 /*! MSTARBLOSS - Master Arbitration Loss flag. 3551 */ 3552 #define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) 3553 #define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) 3554 #define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) 3555 /*! MSTSTSTPERR - Master Start/Stop Error flag. 3556 */ 3557 #define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) 3558 #define I2C_INTSTAT_SLVPENDING_MASK (0x100U) 3559 #define I2C_INTSTAT_SLVPENDING_SHIFT (8U) 3560 /*! SLVPENDING - Slave Pending. 3561 */ 3562 #define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) 3563 #define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) 3564 #define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) 3565 /*! SLVNOTSTR - Slave Not Stretching status. 3566 */ 3567 #define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) 3568 #define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) 3569 #define I2C_INTSTAT_SLVDESEL_SHIFT (15U) 3570 /*! SLVDESEL - Slave Deselected flag. 3571 */ 3572 #define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) 3573 #define I2C_INTSTAT_MONRDY_MASK (0x10000U) 3574 #define I2C_INTSTAT_MONRDY_SHIFT (16U) 3575 /*! MONRDY - Monitor Ready. 3576 */ 3577 #define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) 3578 #define I2C_INTSTAT_MONOV_MASK (0x20000U) 3579 #define I2C_INTSTAT_MONOV_SHIFT (17U) 3580 /*! MONOV - Monitor Overflow flag. 3581 */ 3582 #define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) 3583 #define I2C_INTSTAT_MONIDLE_MASK (0x80000U) 3584 #define I2C_INTSTAT_MONIDLE_SHIFT (19U) 3585 /*! MONIDLE - Monitor Idle flag. 3586 */ 3587 #define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) 3588 #define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) 3589 #define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) 3590 /*! EVENTTIMEOUT - Event time-out Interrupt flag. 3591 */ 3592 #define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) 3593 #define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) 3594 #define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) 3595 /*! SCLTIMEOUT - SCL time-out Interrupt flag. 3596 */ 3597 #define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) 3598 /*! @} */ 3599 3600 /*! @name MSTCTL - Master control register. */ 3601 /*! @{ */ 3602 #define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) 3603 #define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) 3604 /*! MSTCONTINUE - Master Continue. 3605 * 0b0..No effect. 3606 * 0b1..Informs the Master function to continue to the next operation. 3607 */ 3608 #define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) 3609 #define I2C_MSTCTL_MSTSTART_MASK (0x2U) 3610 #define I2C_MSTCTL_MSTSTART_SHIFT (1U) 3611 /*! MSTSTART - Master Start control. 3612 * 0b0..No effect. 3613 * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. 3614 */ 3615 #define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) 3616 #define I2C_MSTCTL_MSTSTOP_MASK (0x4U) 3617 #define I2C_MSTCTL_MSTSTOP_SHIFT (2U) 3618 /*! MSTSTOP - Master Stop control. 3619 * 0b0..No effect. 3620 * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave 3621 * if the master is receiving data from the slave (Master Receiver mode). 3622 */ 3623 #define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) 3624 #define I2C_MSTCTL_MSTDMA_MASK (0x8U) 3625 #define I2C_MSTCTL_MSTDMA_SHIFT (3U) 3626 /*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type 3627 * operations such as Start, address, Stop, and address match must always be done with software, 3628 * typically via an interrupt. Address acknowledgement must also be done by software except when 3629 * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by 3630 * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA 3631 * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is 3632 * read/write. 3633 * 0b0..Disable. No DMA requests are generated for master operation. 3634 * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating 3635 * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. 3636 */ 3637 #define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) 3638 /*! @} */ 3639 3640 /*! @name MSTTIME - Master timing configuration. */ 3641 /*! @{ */ 3642 #define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) 3643 #define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) 3644 /*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this 3645 * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This 3646 * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters 3647 * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. 3648 * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. 3649 * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. 3650 * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. 3651 * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. 3652 * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. 3653 * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. 3654 * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. 3655 * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. 3656 */ 3657 #define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) 3658 #define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) 3659 #define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) 3660 /*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this 3661 * master on SCL. Other masters in a multi-master system could shorten this time. This 3662 * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters 3663 * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. 3664 * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. 3665 * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . 3666 * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. 3667 * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. 3668 * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. 3669 * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. 3670 * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. 3671 * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. 3672 */ 3673 #define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) 3674 /*! @} */ 3675 3676 /*! @name MSTDAT - Combined Master receiver and transmitter data register. */ 3677 /*! @{ */ 3678 #define I2C_MSTDAT_DATA_MASK (0xFFU) 3679 #define I2C_MSTDAT_DATA_SHIFT (0U) 3680 /*! DATA - Master function data register. Read: read the most recently received data for the Master 3681 * function. Write: transmit data using the Master function. 3682 */ 3683 #define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) 3684 /*! @} */ 3685 3686 /*! @name SLVCTL - Slave control register. */ 3687 /*! @{ */ 3688 #define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) 3689 #define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) 3690 /*! SLVCONTINUE - Slave Continue. 3691 * 0b0..No effect. 3692 * 0b1..Informs the Slave function to continue to the next operation. 3693 */ 3694 #define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) 3695 #define I2C_SLVCTL_SLVNACK_MASK (0x2U) 3696 #define I2C_SLVCTL_SLVNACK_SHIFT (1U) 3697 /*! SLVNACK - Slave NACK. 3698 * 0b0..No effect. 3699 * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). 3700 */ 3701 #define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) 3702 #define I2C_SLVCTL_SLVDMA_MASK (0x8U) 3703 #define I2C_SLVCTL_SLVDMA_SHIFT (3U) 3704 /*! SLVDMA - Slave DMA enable. 3705 * 0b0..Disabled. No DMA requests are issued for Slave mode operation. 3706 * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. 3707 */ 3708 #define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) 3709 /*! @} */ 3710 3711 /*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ 3712 /*! @{ */ 3713 #define I2C_SLVDAT_DATA_MASK (0xFFU) 3714 #define I2C_SLVDAT_DATA_SHIFT (0U) 3715 /*! DATA - Slave function data register. Read: read the most recently received data for the Slave 3716 * function. Write: transmit data using the Slave function. 3717 */ 3718 #define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) 3719 /*! @} */ 3720 3721 /*! @name SLVADR - Slave address register. */ 3722 /*! @{ */ 3723 #define I2C_SLVADR_SADISABLE_MASK (0x1U) 3724 #define I2C_SLVADR_SADISABLE_SHIFT (0U) 3725 /*! SADISABLE - Slave Address n Disable. 3726 * 0b0..Enabled. Slave Address n is enabled. 3727 * 0b1..Ignored Slave Address n is ignored. 3728 */ 3729 #define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) 3730 #define I2C_SLVADR_SLVADR_MASK (0xFEU) 3731 #define I2C_SLVADR_SLVADR_SHIFT (1U) 3732 /*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. 3733 */ 3734 #define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) 3735 /*! @} */ 3736 3737 /* The count of I2C_SLVADR */ 3738 #define I2C_SLVADR_COUNT (4U) 3739 3740 /*! @name SLVQUAL0 - Slave Qualification for address 0. */ 3741 /*! @{ */ 3742 #define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) 3743 #define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) 3744 /*! QUALMODE0 - Qualify mode for slave address 0. 3745 * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. 3746 * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. 3747 */ 3748 #define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) 3749 #define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) 3750 #define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) 3751 /*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to 3752 * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is 3753 * set to 1 will cause an automatic match of the corresponding bit of the received address when it 3754 * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for 3755 * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 3756 * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). 3757 */ 3758 #define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) 3759 /*! @} */ 3760 3761 /*! @name MONRXDAT - Monitor receiver data register. */ 3762 /*! @{ */ 3763 #define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) 3764 #define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) 3765 /*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. 3766 */ 3767 #define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) 3768 #define I2C_MONRXDAT_MONSTART_MASK (0x100U) 3769 #define I2C_MONRXDAT_MONSTART_SHIFT (8U) 3770 /*! MONSTART - Monitor Received Start. 3771 * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. 3772 * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. 3773 */ 3774 #define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) 3775 #define I2C_MONRXDAT_MONRESTART_MASK (0x200U) 3776 #define I2C_MONRXDAT_MONRESTART_SHIFT (9U) 3777 /*! MONRESTART - Monitor Received Repeated Start. 3778 * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. 3779 * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. 3780 */ 3781 #define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) 3782 #define I2C_MONRXDAT_MONNACK_MASK (0x400U) 3783 #define I2C_MONRXDAT_MONNACK_SHIFT (10U) 3784 /*! MONNACK - Monitor Received NACK. 3785 * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. 3786 * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. 3787 */ 3788 #define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) 3789 /*! @} */ 3790 3791 3792 /*! 3793 * @} 3794 */ /* end of group I2C_Register_Masks */ 3795 3796 3797 /* I2C - Peripheral instance base addresses */ 3798 /** Peripheral I2C0 base address */ 3799 #define I2C0_BASE (0x40050000u) 3800 /** Peripheral I2C0 base pointer */ 3801 #define I2C0 ((I2C_Type *)I2C0_BASE) 3802 /** Peripheral I2C1 base address */ 3803 #define I2C1_BASE (0x40054000u) 3804 /** Peripheral I2C1 base pointer */ 3805 #define I2C1 ((I2C_Type *)I2C1_BASE) 3806 /** Peripheral I2C2 base address */ 3807 #define I2C2_BASE (0x40030000u) 3808 /** Peripheral I2C2 base pointer */ 3809 #define I2C2 ((I2C_Type *)I2C2_BASE) 3810 /** Peripheral I2C3 base address */ 3811 #define I2C3_BASE (0x40034000u) 3812 /** Peripheral I2C3 base pointer */ 3813 #define I2C3 ((I2C_Type *)I2C3_BASE) 3814 /** Array initializer of I2C peripheral base addresses */ 3815 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE } 3816 /** Array initializer of I2C peripheral base pointers */ 3817 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3 } 3818 /** Interrupt vectors for the I2C peripheral type */ 3819 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn } 3820 3821 /*! 3822 * @} 3823 */ /* end of group I2C_Peripheral_Access_Layer */ 3824 3825 3826 /* ---------------------------------------------------------------------------- 3827 -- INPUTMUX Peripheral Access Layer 3828 ---------------------------------------------------------------------------- */ 3829 3830 /*! 3831 * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer 3832 * @{ 3833 */ 3834 3835 /** INPUTMUX - Register Layout Typedef */ 3836 typedef struct { 3837 __IO uint32_t DMA_INMUX_INMUX[2]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x0, array step: 0x4 */ 3838 uint8_t RESERVED_0[24]; 3839 __IO uint32_t SCT_INMUX[4]; /**< input select register for SCT, array offset: 0x20, array step: 0x4 */ 3840 uint8_t RESERVED_1[16]; 3841 __IO uint32_t DMA_ITRIG_INMUX[25]; /**< Trigger select register for DMA channel, array offset: 0x40, array step: 0x4 */ 3842 } INPUTMUX_Type; 3843 3844 /* ---------------------------------------------------------------------------- 3845 -- INPUTMUX Register Masks 3846 ---------------------------------------------------------------------------- */ 3847 3848 /*! 3849 * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks 3850 * @{ 3851 */ 3852 3853 /*! @name DMA_INMUX_INMUX - DMA output trigger selection to become DMA trigger */ 3854 /*! @{ */ 3855 #define INPUTMUX_DMA_INMUX_INMUX_INP_MASK (0x1FU) 3856 #define INPUTMUX_DMA_INMUX_INMUX_INP_SHIFT (0U) 3857 /*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 24). 3858 */ 3859 #define INPUTMUX_DMA_INMUX_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_INMUX_INMUX_INP_SHIFT)) & INPUTMUX_DMA_INMUX_INMUX_INP_MASK) 3860 /*! @} */ 3861 3862 /* The count of INPUTMUX_DMA_INMUX_INMUX */ 3863 #define INPUTMUX_DMA_INMUX_INMUX_COUNT (2U) 3864 3865 /*! @name SCT_INMUX - input select register for SCT */ 3866 /*! @{ */ 3867 #define INPUTMUX_SCT_INMUX_INP_N_MASK (0xFU) 3868 #define INPUTMUX_SCT_INMUX_INP_N_SHIFT (0U) 3869 /*! INP_N - Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct 3870 * input 2 3= sct gpio input 3 4= adc_thcmp_irq 5 = comparator out 6 = timer ct32b0 match2 3871 * 7=gpio_int_bmatch 8=arm_txev 9=debug_halted 3872 */ 3873 #define INPUTMUX_SCT_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT_INMUX_INP_N_MASK) 3874 /*! @} */ 3875 3876 /* The count of INPUTMUX_SCT_INMUX */ 3877 #define INPUTMUX_SCT_INMUX_COUNT (4U) 3878 3879 /*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */ 3880 /*! @{ */ 3881 #define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0xFU) 3882 #define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U) 3883 /*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A 3884 * interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= 3885 * Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= 3886 * Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output 3887 * trigger mux 0 12 = DMA output trigger mux 1 3888 */ 3889 #define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK) 3890 /*! @} */ 3891 3892 /* The count of INPUTMUX_DMA_ITRIG_INMUX */ 3893 #define INPUTMUX_DMA_ITRIG_INMUX_COUNT (25U) 3894 3895 3896 /*! 3897 * @} 3898 */ /* end of group INPUTMUX_Register_Masks */ 3899 3900 3901 /* INPUTMUX - Peripheral instance base addresses */ 3902 /** Peripheral INPUTMUX base address */ 3903 #define INPUTMUX_BASE (0x4002C000u) 3904 /** Peripheral INPUTMUX base pointer */ 3905 #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) 3906 /** Array initializer of INPUTMUX peripheral base addresses */ 3907 #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } 3908 /** Array initializer of INPUTMUX peripheral base pointers */ 3909 #define INPUTMUX_BASE_PTRS { INPUTMUX } 3910 3911 /*! 3912 * @} 3913 */ /* end of group INPUTMUX_Peripheral_Access_Layer */ 3914 3915 3916 /* ---------------------------------------------------------------------------- 3917 -- IOCON Peripheral Access Layer 3918 ---------------------------------------------------------------------------- */ 3919 3920 /*! 3921 * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer 3922 * @{ 3923 */ 3924 3925 /** IOCON - Register Layout Typedef */ 3926 typedef struct { 3927 __IO uint32_t PIO[56]; /**< Digital I/O control for pins PIO0_17..Digital I/O control for pins PIO1_10, array offset: 0x0, array step: 0x4 */ 3928 } IOCON_Type; 3929 3930 /* ---------------------------------------------------------------------------- 3931 -- IOCON Register Masks 3932 ---------------------------------------------------------------------------- */ 3933 3934 /*! 3935 * @addtogroup IOCON_Register_Masks IOCON Register Masks 3936 * @{ 3937 */ 3938 3939 /*! @name PIO - Digital I/O control for pins PIO0_17..Digital I/O control for pins PIO1_10 */ 3940 /*! @{ */ 3941 #define IOCON_PIO_MODE_MASK (0x18U) 3942 #define IOCON_PIO_MODE_SHIFT (3U) 3943 /*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). 3944 * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). 3945 * 0b01..Pull-down. Pull-down resistor enabled. 3946 * 0b10..Pull-up. Pull-up resistor enabled. 3947 * 0b11..Repeater. Repeater mode. 3948 */ 3949 #define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) 3950 #define IOCON_PIO_HYS_MASK (0x20U) 3951 #define IOCON_PIO_HYS_SHIFT (5U) 3952 /*! HYS - Hysteresis. 3953 * 0b0..Disable 3954 * 0b1..Enable 3955 */ 3956 #define IOCON_PIO_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_HYS_SHIFT)) & IOCON_PIO_HYS_MASK) 3957 #define IOCON_PIO_INV_MASK (0x40U) 3958 #define IOCON_PIO_INV_SHIFT (6U) 3959 /*! INV - Invert input 3960 * 0b0..Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 3961 * 0b1..Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 3962 */ 3963 #define IOCON_PIO_INV(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INV_SHIFT)) & IOCON_PIO_INV_MASK) 3964 #define IOCON_PIO_I2CMODE_MASK (0x300U) 3965 #define IOCON_PIO_I2CMODE_SHIFT (8U) 3966 /*! I2CMODE - Selects I2C mode. 3967 * 0b00..Standard mode/ Fast-mode I2C. 3968 * 0b01..Standard GPIO functionality. Requires external pull-up for GPIO output function. 3969 * 0b10..Fast-mode Plus I2C 3970 * 0b11..Reserved 3971 */ 3972 #define IOCON_PIO_I2CMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CMODE_SHIFT)) & IOCON_PIO_I2CMODE_MASK) 3973 #define IOCON_PIO_OD_MASK (0x400U) 3974 #define IOCON_PIO_OD_SHIFT (10U) 3975 /*! OD - Open-drain mode. 3976 * 0b0..Disable. 3977 * 0b1..Open-drain mode enabled. Remark: This is not a true open-drain mode. 3978 */ 3979 #define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) 3980 #define IOCON_PIO_S_MODE_MASK (0x1800U) 3981 #define IOCON_PIO_S_MODE_SHIFT (11U) 3982 /*! S_MODE - Digital filter sample mode. 3983 * 0b00..Bypass input filter. 3984 * 0b01..1 clock cycle. Input pulses shorter than one filter clock are rejected. 3985 * 0b10..2 clock cycles. Input pulses shorter than two filter clocks are rejected. 3986 * 0b11..3 clock cycles. Input pulses shorter than three filter clocks are rejected. 3987 */ 3988 #define IOCON_PIO_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_S_MODE_SHIFT)) & IOCON_PIO_S_MODE_MASK) 3989 #define IOCON_PIO_CLK_DIV_MASK (0xE000U) 3990 #define IOCON_PIO_CLK_DIV_SHIFT (13U) 3991 /*! CLK_DIV - Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 3992 * 0b000..IOCONCLKDIV0 3993 * 0b001..IOCONCLKDIV1 3994 * 0b010..IOCONCLKDIV2 3995 * 0b011..IOCONCLKDIV3 3996 * 0b100..IOCONCLKDIV4 3997 * 0b101..IOCONCLKDIV5 3998 * 0b110..IOCONCLKDIV6 3999 */ 4000 #define IOCON_PIO_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_CLK_DIV_SHIFT)) & IOCON_PIO_CLK_DIV_MASK) 4001 #define IOCON_PIO_DACMODE_MASK (0x10000U) 4002 #define IOCON_PIO_DACMODE_SHIFT (16U) 4003 /*! DACMODE - DAC mode enable. 4004 * 0b0..Disable. 4005 * 0b1..Enable. 4006 */ 4007 #define IOCON_PIO_DACMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DACMODE_SHIFT)) & IOCON_PIO_DACMODE_MASK) 4008 /*! @} */ 4009 4010 /* The count of IOCON_PIO */ 4011 #define IOCON_PIO_COUNT (56U) 4012 4013 4014 /*! 4015 * @} 4016 */ /* end of group IOCON_Register_Masks */ 4017 4018 4019 /* IOCON - Peripheral instance base addresses */ 4020 /** Peripheral IOCON base address */ 4021 #define IOCON_BASE (0x40044000u) 4022 /** Peripheral IOCON base pointer */ 4023 #define IOCON ((IOCON_Type *)IOCON_BASE) 4024 /** Array initializer of IOCON peripheral base addresses */ 4025 #define IOCON_BASE_ADDRS { IOCON_BASE } 4026 /** Array initializer of IOCON peripheral base pointers */ 4027 #define IOCON_BASE_PTRS { IOCON } 4028 4029 #define IOCON_INDEX_PIO0_17 ( 0) 4030 #define IOCON_INDEX_PIO0_13 ( 1) 4031 #define IOCON_INDEX_PIO0_12 ( 2) 4032 #define IOCON_INDEX_PIO0_5 ( 3) 4033 #define IOCON_INDEX_PIO0_4 ( 4) 4034 #define IOCON_INDEX_PIO0_3 ( 5) 4035 #define IOCON_INDEX_PIO0_2 ( 6) 4036 #define IOCON_INDEX_PIO0_11 ( 7) 4037 #define IOCON_INDEX_PIO0_10 ( 8) 4038 #define IOCON_INDEX_PIO0_16 ( 9) 4039 #define IOCON_INDEX_PIO0_15 (10) 4040 #define IOCON_INDEX_PIO0_1 (11) 4041 #define IOCON_INDEX_PIO0_9 (13) 4042 #define IOCON_INDEX_PIO0_8 (14) 4043 #define IOCON_INDEX_PIO0_7 (15) 4044 #define IOCON_INDEX_PIO0_6 (16) 4045 #define IOCON_INDEX_PIO0_0 (17) 4046 #define IOCON_INDEX_PIO0_14 (18) 4047 #define IOCON_INDEX_PIO0_28 (20) 4048 #define IOCON_INDEX_PIO0_27 (21) 4049 #define IOCON_INDEX_PIO0_26 (22) 4050 #define IOCON_INDEX_PIO0_25 (23) 4051 #define IOCON_INDEX_PIO0_24 (24) 4052 #define IOCON_INDEX_PIO0_23 (25) 4053 #define IOCON_INDEX_PIO0_22 (26) 4054 #define IOCON_INDEX_PIO0_21 (27) 4055 #define IOCON_INDEX_PIO0_20 (28) 4056 #define IOCON_INDEX_PIO0_19 (29) 4057 #define IOCON_INDEX_PIO0_18 (30) 4058 #define IOCON_INDEX_PIO1_8 (31) 4059 #define IOCON_INDEX_PIO1_9 (32) 4060 #define IOCON_INDEX_PIO1_12 (33) 4061 #define IOCON_INDEX_PIO1_13 (34) 4062 #define IOCON_INDEX_PIO0_31 (35) 4063 #define IOCON_INDEX_PIO1_0 (36) 4064 #define IOCON_INDEX_PIO1_1 (37) 4065 #define IOCON_INDEX_PIO1_2 (38) 4066 #define IOCON_INDEX_PIO1_14 (39) 4067 #define IOCON_INDEX_PIO1_15 (40) 4068 #define IOCON_INDEX_PIO1_3 (41) 4069 #define IOCON_INDEX_PIO1_4 (42) 4070 #define IOCON_INDEX_PIO1_5 (43) 4071 #define IOCON_INDEX_PIO1_16 (44) 4072 #define IOCON_INDEX_PIO1_17 (45) 4073 #define IOCON_INDEX_PIO1_6 (46) 4074 #define IOCON_INDEX_PIO1_18 (47) 4075 #define IOCON_INDEX_PIO1_19 (48) 4076 #define IOCON_INDEX_PIO1_7 (49) 4077 #define IOCON_INDEX_PIO0_29 (50) 4078 #define IOCON_INDEX_PIO0_30 (51) 4079 #define IOCON_INDEX_PIO1_20 (52) 4080 #define IOCON_INDEX_PIO1_21 (53) 4081 #define IOCON_INDEX_PIO1_11 (54) 4082 #define IOCON_INDEX_PIO1_10 (55) 4083 4084 4085 /*! 4086 * @} 4087 */ /* end of group IOCON_Peripheral_Access_Layer */ 4088 4089 4090 /* ---------------------------------------------------------------------------- 4091 -- MRT Peripheral Access Layer 4092 ---------------------------------------------------------------------------- */ 4093 4094 /*! 4095 * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer 4096 * @{ 4097 */ 4098 4099 /** MRT - Register Layout Typedef */ 4100 typedef struct { 4101 struct { /* offset: 0x0, array step: 0x10 */ 4102 __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ 4103 __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ 4104 __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ 4105 __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ 4106 } CHANNEL[4]; 4107 uint8_t RESERVED_0[180]; 4108 __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ 4109 __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ 4110 } MRT_Type; 4111 4112 /* ---------------------------------------------------------------------------- 4113 -- MRT Register Masks 4114 ---------------------------------------------------------------------------- */ 4115 4116 /*! 4117 * @addtogroup MRT_Register_Masks MRT Register Masks 4118 * @{ 4119 */ 4120 4121 /*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ 4122 /*! @{ */ 4123 #define MRT_CHANNEL_INTVAL_IVALUE_MASK (0x7FFFFFFFU) 4124 #define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) 4125 /*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT 4126 * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to 4127 * this bit field starts the timer immediately. If the timer is running, writing a zero to this 4128 * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer 4129 * stops at the end of the time interval. 4130 */ 4131 #define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) 4132 #define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) 4133 #define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) 4134 /*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. 4135 * This bit is write-only. Reading this bit always returns 0. 4136 * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the 4137 * time interval if the repeat mode is selected. 4138 * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. 4139 */ 4140 #define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) 4141 /*! @} */ 4142 4143 /* The count of MRT_CHANNEL_INTVAL */ 4144 #define MRT_CHANNEL_INTVAL_COUNT (4U) 4145 4146 /*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ 4147 /*! @{ */ 4148 #define MRT_CHANNEL_TIMER_VALUE_MASK (0x7FFFFFFFU) 4149 #define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) 4150 /*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn 4151 * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval 4152 * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn 4153 * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields 4154 * returns -1 (0x00FF FFFF). 4155 */ 4156 #define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) 4157 /*! @} */ 4158 4159 /* The count of MRT_CHANNEL_TIMER */ 4160 #define MRT_CHANNEL_TIMER_COUNT (4U) 4161 4162 /*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ 4163 /*! @{ */ 4164 #define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) 4165 #define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) 4166 /*! INTEN - Enable the TIMERn interrupt. 4167 * 0b0..Disabled. TIMERn interrupt is disabled. 4168 * 0b1..Enabled. TIMERn interrupt is enabled. 4169 */ 4170 #define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) 4171 #define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) 4172 #define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) 4173 /*! MODE - Selects timer mode. 4174 * 0b00..Repeat interrupt mode. 4175 * 0b01..One-shot interrupt mode. 4176 * 0b10..One-shot stall mode. 4177 * 0b11..Reserved. 4178 */ 4179 #define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) 4180 /*! @} */ 4181 4182 /* The count of MRT_CHANNEL_CTRL */ 4183 #define MRT_CHANNEL_CTRL_COUNT (4U) 4184 4185 /*! @name CHANNEL_STAT - MRT Status register. */ 4186 /*! @{ */ 4187 #define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) 4188 #define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) 4189 /*! INTFLAG - Monitors the interrupt flag. 4190 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. 4191 * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If 4192 * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt 4193 * are raised. Writing a 1 to this bit clears the interrupt request. 4194 */ 4195 #define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) 4196 #define MRT_CHANNEL_STAT_RUN_MASK (0x2U) 4197 #define MRT_CHANNEL_STAT_RUN_SHIFT (1U) 4198 /*! RUN - Indicates the state of TIMERn. This bit is read-only. 4199 * 0b0..Idle state. TIMERn is stopped. 4200 * 0b1..Running. TIMERn is running. 4201 */ 4202 #define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) 4203 /*! @} */ 4204 4205 /* The count of MRT_CHANNEL_STAT */ 4206 #define MRT_CHANNEL_STAT_COUNT (4U) 4207 4208 /*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ 4209 /*! @{ */ 4210 #define MRT_IDLE_CH_CHAN_MASK (0xF0U) 4211 #define MRT_IDLE_CH_CHAN_SHIFT (4U) 4212 /*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is 4213 * positioned such that it can be used as an offset from the MRT base address in order to access 4214 * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See 4215 * text above for more details. 4216 */ 4217 #define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) 4218 /*! @} */ 4219 4220 /*! @name IRQ_FLAG - Global interrupt flag register */ 4221 /*! @{ */ 4222 #define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) 4223 #define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) 4224 /*! GFLAG0 - Monitors the interrupt flag of TIMER0. 4225 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. 4226 * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If 4227 * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global 4228 * interrupt are raised. Writing a 1 to this bit clears the interrupt request. 4229 */ 4230 #define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) 4231 #define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) 4232 #define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) 4233 /*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. 4234 */ 4235 #define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) 4236 #define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) 4237 #define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) 4238 /*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. 4239 */ 4240 #define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) 4241 #define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) 4242 #define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) 4243 /*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. 4244 */ 4245 #define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) 4246 /*! @} */ 4247 4248 4249 /*! 4250 * @} 4251 */ /* end of group MRT_Register_Masks */ 4252 4253 4254 /* MRT - Peripheral instance base addresses */ 4255 /** Peripheral MRT0 base address */ 4256 #define MRT0_BASE (0x40004000u) 4257 /** Peripheral MRT0 base pointer */ 4258 #define MRT0 ((MRT_Type *)MRT0_BASE) 4259 /** Array initializer of MRT peripheral base addresses */ 4260 #define MRT_BASE_ADDRS { MRT0_BASE } 4261 /** Array initializer of MRT peripheral base pointers */ 4262 #define MRT_BASE_PTRS { MRT0 } 4263 /** Interrupt vectors for the MRT peripheral type */ 4264 #define MRT_IRQS { MRT0_IRQn } 4265 4266 /*! 4267 * @} 4268 */ /* end of group MRT_Peripheral_Access_Layer */ 4269 4270 4271 /* ---------------------------------------------------------------------------- 4272 -- MTB Peripheral Access Layer 4273 ---------------------------------------------------------------------------- */ 4274 4275 /*! 4276 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer 4277 * @{ 4278 */ 4279 4280 /** MTB - Register Layout Typedef */ 4281 typedef struct { 4282 __IO uint32_t POSITION; /**< POSITION Register, offset: 0x0 */ 4283 __IO uint32_t MASTER; /**< MASTER Register, offset: 0x4 */ 4284 __IO uint32_t FLOW; /**< FLOW Register, offset: 0x8 */ 4285 __I uint32_t BASE; /**< Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent., offset: 0xC */ 4286 } MTB_Type; 4287 4288 /* ---------------------------------------------------------------------------- 4289 -- MTB Register Masks 4290 ---------------------------------------------------------------------------- */ 4291 4292 /*! 4293 * @addtogroup MTB_Register_Masks MTB Register Masks 4294 * @{ 4295 */ 4296 4297 /*! @name POSITION - POSITION Register */ 4298 /*! @{ */ 4299 #define MTB_POSITION_WRAP_MASK (0x4U) 4300 #define MTB_POSITION_WRAP_SHIFT (2U) 4301 /*! WRAP - This bit is set to 1 automatically when the POINTER value wraps as determined by the 4302 * MASTER.MASK field in the MASTER Trace Control Register. 4303 */ 4304 #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK) 4305 #define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U) 4306 #define MTB_POSITION_POINTER_SHIFT (3U) 4307 /*! POINTER - Trace packet location pointer. Because a packet consists of two words, the POINTER 4308 * field is the location of the first word of a packet. This field contains bits [31:3] of the 4309 * address, in the SRAM, where the next trace packet will be written. The field points to an unused 4310 * location and is automatically incremented. A debug agent can calculate the system address, on 4311 * the AHB-Lite bus, of the SRAM location pointed to by the POSITION register using the following 4312 * equation: system address = BASE + ((P + (2AWIDTH - (BASE MOD 2AWIDTH))) MOD 2AWIDTH). Where P = 4313 * POSITION AND 0xFFFF_FFF8. Where BASE is the BASE register value 4314 */ 4315 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK) 4316 /*! @} */ 4317 4318 /*! @name MASTER - MASTER Register */ 4319 /*! @{ */ 4320 #define MTB_MASTER_MASK_MASK (0x1FU) 4321 #define MTB_MASTER_MASK_SHIFT (0U) 4322 /*! MASK - This value determines the maximum size of the trace buffer in SRAM. It specifies the 4323 * most-significant bit of the POSITION.POINTER field that can be updated by automatic increment. If 4324 * the trace tries to advance past this power of two, the POSITION.WRAP bit is set to 1, the 4325 * POSITION.POINTER[MASK:0] bits are set to zero, and the POSITION.POINTER[AWIDTH-4:MASK+1] bits 4326 * remain unchanged. This field causes the trace packet information to be stored in a circular buffer 4327 * of size 2(MASK+4) bytes, that can be positioned in memory at multiples of this size. Valid 4328 * values of this field are zero to AWIDTH-4. Values greater than the maximum have the same effect 4329 * as the maximum. 4330 */ 4331 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK) 4332 #define MTB_MASTER_TSTARTEN_MASK (0x20U) 4333 #define MTB_MASTER_TSTARTEN_SHIFT (5U) 4334 /*! TSTARTEN - Trace start input enable. If this bit is 1 and the TSTART signal is HIGH, then the EN 4335 * bit is set to 1. Tracing continues until a stop condition occurs. 4336 */ 4337 #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK) 4338 #define MTB_MASTER_TSTOPEN_MASK (0x40U) 4339 #define MTB_MASTER_TSTOPEN_SHIFT (6U) 4340 /*! TSTOPEN - Trace stop input enable. If this bit is 1 and the TSTOP signal is HIGH, then the EN 4341 * bit is set to 0. If a trace packet is being written to memory, the write is completed before 4342 * tracing is stopped. 4343 */ 4344 #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK) 4345 #define MTB_MASTER_SFRWPRIV_MASK (0x80U) 4346 #define MTB_MASTER_SFRWPRIV_SHIFT (7U) 4347 /*! SFRWPRIV - Special Function Register Write Privilege bit. If this bit is 0, then User or 4348 * Privileged AHB-Lite read and write accesses to the Special Function Registers are permitted. If this 4349 * bit is 1, then only Privileged write accesses are permitted and User write accesses are 4350 * ignored. The HPROT[1] signal determines if an access is User or Privileged. 4351 */ 4352 #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK) 4353 #define MTB_MASTER_RAMPRIV_MASK (0x100U) 4354 #define MTB_MASTER_RAMPRIV_SHIFT (8U) 4355 /*! RAMPRIV - SRAM Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write 4356 * accesses to the SRAM are permitted. If this bit is 1, then only Privileged AHB-Lite read and 4357 * write accesses to the SRAM are permitted and User accesses are RAZ/WI. The HPROT[1] signal 4358 * determines if an access is User or Privileged. 4359 */ 4360 #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK) 4361 #define MTB_MASTER_HALTREQ_MASK (0x200U) 4362 #define MTB_MASTER_HALTREQ_SHIFT (9U) 4363 /*! HALTREQ - Halt request bit. This bit is connected to the halt request signal of the trace logic, 4364 * EDBGRQ. When HALTREQ is set to 1, EDBGRQ is asserted if DBGEN is also HIGH. The HALTREQ bit 4365 * can be automatically set to 1 using the FLOW.WATERMARK field. 4366 */ 4367 #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK) 4368 #define MTB_MASTER_EN_MASK (0x80000000U) 4369 #define MTB_MASTER_EN_SHIFT (31U) 4370 /*! EN - Main trace enable bit. When this bit is 1 trace data is written into the SRAM memory 4371 * location addressed by POSITION.POINTER. The POSITION.POINTER value auto increments after the trace 4372 * data packet is written. The EN bit can be automatically set to 0 using the FLOW.WATERMARK field 4373 * and the FLOW.AUTOSTOP bit. The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and 4374 * the TSTART signal is HIGH. The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the 4375 * TSTOP signal is HIGH. 4376 */ 4377 #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK) 4378 /*! @} */ 4379 4380 /*! @name FLOW - FLOW Register */ 4381 /*! @{ */ 4382 #define MTB_FLOW_AUTOSTOP_MASK (0x1U) 4383 #define MTB_FLOW_AUTOSTOP_SHIFT (0U) 4384 /*! AUTOSTOP - If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.EN bit 4385 * is automatically set to 0. This stops tracing. 4386 */ 4387 #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK) 4388 #define MTB_FLOW_AUTOHALT_MASK (0x2U) 4389 #define MTB_FLOW_AUTOHALT_SHIFT (1U) 4390 /*! AUTOHALT - If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.HALTREQ 4391 * bit is automatically set to 1. If the DBGEN signal is HIGH, the MTB asserts this halt request 4392 * to the Cortex-M0+ processor by asserting the EDBGRQ signal. 4393 */ 4394 #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK) 4395 #define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U) 4396 #define MTB_FLOW_WATERMARK_SHIFT (3U) 4397 /*! WATERMARK - WATERMARK value. This field contains an address in the same format as the 4398 * POSITION.POINTER field. When the POSITION.POINTER matches the WATERMARK field value, actions defined by 4399 * the AUTOHALT and AUTOSTOP bits are performed. 4400 */ 4401 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK) 4402 /*! @} */ 4403 4404 /*! @name BASE - Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent. */ 4405 /*! @{ */ 4406 #define MTB_BASE_BASE_MASK (0xFFFFFFFFU) 4407 #define MTB_BASE_BASE_SHIFT (0U) 4408 /*! BASE - The value provided is the value of the SRAMBASEADDR[31:0] signal. 4409 */ 4410 #define MTB_BASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASE_SHIFT)) & MTB_BASE_BASE_MASK) 4411 /*! @} */ 4412 4413 4414 /*! 4415 * @} 4416 */ /* end of group MTB_Register_Masks */ 4417 4418 4419 /* MTB - Peripheral instance base addresses */ 4420 /** Peripheral MTB_SFR base address */ 4421 #define MTB_SFR_BASE (0x5000C000u) 4422 /** Peripheral MTB_SFR base pointer */ 4423 #define MTB_SFR ((MTB_Type *)MTB_SFR_BASE) 4424 /** Array initializer of MTB peripheral base addresses */ 4425 #define MTB_BASE_ADDRS { MTB_SFR_BASE } 4426 /** Array initializer of MTB peripheral base pointers */ 4427 #define MTB_BASE_PTRS { MTB_SFR } 4428 4429 /*! 4430 * @} 4431 */ /* end of group MTB_Peripheral_Access_Layer */ 4432 4433 4434 /* ---------------------------------------------------------------------------- 4435 -- PINT Peripheral Access Layer 4436 ---------------------------------------------------------------------------- */ 4437 4438 /*! 4439 * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer 4440 * @{ 4441 */ 4442 4443 /** PINT - Register Layout Typedef */ 4444 typedef struct { 4445 __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ 4446 __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ 4447 __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ 4448 __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ 4449 __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ 4450 __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ 4451 __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ 4452 __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ 4453 __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ 4454 __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ 4455 __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ 4456 __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ 4457 __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ 4458 } PINT_Type; 4459 4460 /* ---------------------------------------------------------------------------- 4461 -- PINT Register Masks 4462 ---------------------------------------------------------------------------- */ 4463 4464 /*! 4465 * @addtogroup PINT_Register_Masks PINT Register Masks 4466 * @{ 4467 */ 4468 4469 /*! @name ISEL - Pin Interrupt Mode register */ 4470 /*! @{ */ 4471 #define PINT_ISEL_PMODE_MASK (0xFFU) 4472 #define PINT_ISEL_PMODE_SHIFT (0U) 4473 /*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt 4474 * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive 4475 */ 4476 #define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) 4477 /*! @} */ 4478 4479 /*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ 4480 /*! @{ */ 4481 #define PINT_IENR_ENRL_MASK (0xFFU) 4482 #define PINT_IENR_ENRL_SHIFT (0U) 4483 /*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the 4484 * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable 4485 * rising edge or level interrupt. 4486 */ 4487 #define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) 4488 /*! @} */ 4489 4490 /*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ 4491 /*! @{ */ 4492 #define PINT_SIENR_SETENRL_MASK (0xFFU) 4493 #define PINT_SIENR_SETENRL_SHIFT (0U) 4494 /*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n 4495 * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. 4496 */ 4497 #define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) 4498 /*! @} */ 4499 4500 /*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ 4501 /*! @{ */ 4502 #define PINT_CIENR_CENRL_MASK (0xFFU) 4503 #define PINT_CIENR_CENRL_SHIFT (0U) 4504 /*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit 4505 * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level 4506 * interrupt. 4507 */ 4508 #define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) 4509 /*! @} */ 4510 4511 /*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ 4512 /*! @{ */ 4513 #define PINT_IENF_ENAF_MASK (0xFFU) 4514 #define PINT_IENF_ENAF_SHIFT (0U) 4515 /*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. 4516 * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt 4517 * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active 4518 * interrupt level HIGH. 4519 */ 4520 #define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) 4521 /*! @} */ 4522 4523 /*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ 4524 /*! @{ */ 4525 #define PINT_SIENF_SETENAF_MASK (0xFFU) 4526 #define PINT_SIENF_SETENAF_SHIFT (0U) 4527 /*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n 4528 * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable 4529 * falling edge interrupt. 4530 */ 4531 #define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) 4532 /*! @} */ 4533 4534 /*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ 4535 /*! @{ */ 4536 #define PINT_CIENF_CENAF_MASK (0xFFU) 4537 #define PINT_CIENF_CENAF_SHIFT (0U) 4538 /*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n 4539 * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or 4540 * falling edge interrupt disabled. 4541 */ 4542 #define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) 4543 /*! @} */ 4544 4545 /*! @name RISE - Pin interrupt rising edge register */ 4546 /*! @{ */ 4547 #define PINT_RISE_RDET_MASK (0xFFU) 4548 #define PINT_RISE_RDET_SHIFT (0U) 4549 /*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 4550 * 0: No rising edge has been detected on this pin since Reset or the last time a one was written 4551 * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the 4552 * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. 4553 */ 4554 #define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) 4555 /*! @} */ 4556 4557 /*! @name FALL - Pin interrupt falling edge register */ 4558 /*! @{ */ 4559 #define PINT_FALL_FDET_MASK (0xFFU) 4560 #define PINT_FALL_FDET_SHIFT (0U) 4561 /*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 4562 * 0: No falling edge has been detected on this pin since Reset or the last time a one was 4563 * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or 4564 * the last time a one was written to this bit. Write 1: clear falling edge detection for this 4565 * pin. 4566 */ 4567 #define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) 4568 /*! @} */ 4569 4570 /*! @name IST - Pin interrupt status register */ 4571 /*! @{ */ 4572 #define PINT_IST_PSTAT_MASK (0xFFU) 4573 #define PINT_IST_PSTAT_SHIFT (0U) 4574 /*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts 4575 * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for 4576 * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this 4577 * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. 4578 * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). 4579 */ 4580 #define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) 4581 /*! @} */ 4582 4583 /*! @name PMCTRL - Pattern match interrupt control register */ 4584 /*! @{ */ 4585 #define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) 4586 #define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) 4587 /*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. 4588 * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. 4589 * 0b1..Pattern match. Interrupts are driven in response to pattern matches. 4590 */ 4591 #define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) 4592 #define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) 4593 #define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) 4594 /*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. 4595 * 0b0..Disabled. RXEV output to the CPU is disabled. 4596 * 0b1..Enabled. RXEV output to the CPU is enabled. 4597 */ 4598 #define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) 4599 #define PINT_PMCTRL_PMAT_MASK (0xFF000000U) 4600 #define PINT_PMCTRL_PMAT_SHIFT (24U) 4601 /*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field 4602 * indicates that the corresponding product term is matched by the current state of the appropriate 4603 * inputs. 4604 */ 4605 #define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) 4606 /*! @} */ 4607 4608 /*! @name PMSRC - Pattern match interrupt bit-slice source register */ 4609 /*! @{ */ 4610 #define PINT_PMSRC_SRC0_MASK (0x700U) 4611 #define PINT_PMSRC_SRC0_SHIFT (8U) 4612 /*! SRC0 - Selects the input source for bit slice 0 4613 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. 4614 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. 4615 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. 4616 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. 4617 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. 4618 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. 4619 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. 4620 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. 4621 */ 4622 #define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) 4623 #define PINT_PMSRC_SRC1_MASK (0x3800U) 4624 #define PINT_PMSRC_SRC1_SHIFT (11U) 4625 /*! SRC1 - Selects the input source for bit slice 1 4626 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. 4627 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. 4628 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. 4629 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. 4630 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. 4631 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. 4632 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. 4633 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. 4634 */ 4635 #define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) 4636 #define PINT_PMSRC_SRC2_MASK (0x1C000U) 4637 #define PINT_PMSRC_SRC2_SHIFT (14U) 4638 /*! SRC2 - Selects the input source for bit slice 2 4639 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. 4640 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. 4641 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. 4642 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. 4643 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. 4644 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. 4645 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. 4646 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. 4647 */ 4648 #define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) 4649 #define PINT_PMSRC_SRC3_MASK (0xE0000U) 4650 #define PINT_PMSRC_SRC3_SHIFT (17U) 4651 /*! SRC3 - Selects the input source for bit slice 3 4652 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. 4653 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. 4654 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. 4655 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. 4656 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. 4657 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. 4658 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. 4659 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. 4660 */ 4661 #define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) 4662 #define PINT_PMSRC_SRC4_MASK (0x700000U) 4663 #define PINT_PMSRC_SRC4_SHIFT (20U) 4664 /*! SRC4 - Selects the input source for bit slice 4 4665 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. 4666 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. 4667 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. 4668 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. 4669 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. 4670 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. 4671 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. 4672 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. 4673 */ 4674 #define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) 4675 #define PINT_PMSRC_SRC5_MASK (0x3800000U) 4676 #define PINT_PMSRC_SRC5_SHIFT (23U) 4677 /*! SRC5 - Selects the input source for bit slice 5 4678 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. 4679 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. 4680 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. 4681 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. 4682 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. 4683 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. 4684 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. 4685 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. 4686 */ 4687 #define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) 4688 #define PINT_PMSRC_SRC6_MASK (0x1C000000U) 4689 #define PINT_PMSRC_SRC6_SHIFT (26U) 4690 /*! SRC6 - Selects the input source for bit slice 6 4691 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. 4692 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. 4693 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. 4694 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. 4695 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. 4696 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. 4697 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. 4698 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. 4699 */ 4700 #define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) 4701 #define PINT_PMSRC_SRC7_MASK (0xE0000000U) 4702 #define PINT_PMSRC_SRC7_SHIFT (29U) 4703 /*! SRC7 - Selects the input source for bit slice 7 4704 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. 4705 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. 4706 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. 4707 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. 4708 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. 4709 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. 4710 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. 4711 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. 4712 */ 4713 #define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) 4714 /*! @} */ 4715 4716 /*! @name PMCFG - Pattern match interrupt bit slice configuration register */ 4717 /*! @{ */ 4718 #define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) 4719 #define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) 4720 /*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. 4721 * 0b0..No effect. Slice 0 is not an endpoint. 4722 * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. 4723 */ 4724 #define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) 4725 #define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) 4726 #define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) 4727 /*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. 4728 * 0b0..No effect. Slice 1 is not an endpoint. 4729 * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. 4730 */ 4731 #define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) 4732 #define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) 4733 #define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) 4734 /*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. 4735 * 0b0..No effect. Slice 2 is not an endpoint. 4736 * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. 4737 */ 4738 #define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) 4739 #define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) 4740 #define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) 4741 /*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. 4742 * 0b0..No effect. Slice 3 is not an endpoint. 4743 * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. 4744 */ 4745 #define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) 4746 #define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) 4747 #define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) 4748 /*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. 4749 * 0b0..No effect. Slice 4 is not an endpoint. 4750 * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. 4751 */ 4752 #define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) 4753 #define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) 4754 #define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) 4755 /*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. 4756 * 0b0..No effect. Slice 5 is not an endpoint. 4757 * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. 4758 */ 4759 #define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) 4760 #define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) 4761 #define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) 4762 /*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. 4763 * 0b0..No effect. Slice 6 is not an endpoint. 4764 * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. 4765 */ 4766 #define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) 4767 #define PINT_PMCFG_CFG0_MASK (0x700U) 4768 #define PINT_PMCFG_CFG0_SHIFT (8U) 4769 /*! CFG0 - Specifies the match contribution condition for bit slice 0. 4770 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 4771 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 4772 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4773 * PMSRC registers are written to. 4774 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 4775 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4776 * PMSRC registers are written to. 4777 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 4778 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 4779 * cleared when the PMCFG or the PMSRC registers are written to. 4780 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 4781 * 0b101..Low level. Match occurs when there is a low level on the specified input. 4782 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 4783 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 4784 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 4785 * is cleared after one clock cycle. 4786 */ 4787 #define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) 4788 #define PINT_PMCFG_CFG1_MASK (0x3800U) 4789 #define PINT_PMCFG_CFG1_SHIFT (11U) 4790 /*! CFG1 - Specifies the match contribution condition for bit slice 1. 4791 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 4792 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 4793 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4794 * PMSRC registers are written to. 4795 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 4796 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4797 * PMSRC registers are written to. 4798 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 4799 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 4800 * cleared when the PMCFG or the PMSRC registers are written to. 4801 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 4802 * 0b101..Low level. Match occurs when there is a low level on the specified input. 4803 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 4804 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 4805 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 4806 * is cleared after one clock cycle. 4807 */ 4808 #define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) 4809 #define PINT_PMCFG_CFG2_MASK (0x1C000U) 4810 #define PINT_PMCFG_CFG2_SHIFT (14U) 4811 /*! CFG2 - Specifies the match contribution condition for bit slice 2. 4812 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 4813 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 4814 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4815 * PMSRC registers are written to. 4816 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 4817 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4818 * PMSRC registers are written to. 4819 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 4820 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 4821 * cleared when the PMCFG or the PMSRC registers are written to. 4822 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 4823 * 0b101..Low level. Match occurs when there is a low level on the specified input. 4824 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 4825 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 4826 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 4827 * is cleared after one clock cycle. 4828 */ 4829 #define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) 4830 #define PINT_PMCFG_CFG3_MASK (0xE0000U) 4831 #define PINT_PMCFG_CFG3_SHIFT (17U) 4832 /*! CFG3 - Specifies the match contribution condition for bit slice 3. 4833 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 4834 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 4835 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4836 * PMSRC registers are written to. 4837 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 4838 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4839 * PMSRC registers are written to. 4840 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 4841 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 4842 * cleared when the PMCFG or the PMSRC registers are written to. 4843 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 4844 * 0b101..Low level. Match occurs when there is a low level on the specified input. 4845 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 4846 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 4847 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 4848 * is cleared after one clock cycle. 4849 */ 4850 #define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) 4851 #define PINT_PMCFG_CFG4_MASK (0x700000U) 4852 #define PINT_PMCFG_CFG4_SHIFT (20U) 4853 /*! CFG4 - Specifies the match contribution condition for bit slice 4. 4854 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 4855 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 4856 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4857 * PMSRC registers are written to. 4858 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 4859 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4860 * PMSRC registers are written to. 4861 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 4862 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 4863 * cleared when the PMCFG or the PMSRC registers are written to. 4864 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 4865 * 0b101..Low level. Match occurs when there is a low level on the specified input. 4866 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 4867 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 4868 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 4869 * is cleared after one clock cycle. 4870 */ 4871 #define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) 4872 #define PINT_PMCFG_CFG5_MASK (0x3800000U) 4873 #define PINT_PMCFG_CFG5_SHIFT (23U) 4874 /*! CFG5 - Specifies the match contribution condition for bit slice 5. 4875 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 4876 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 4877 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4878 * PMSRC registers are written to. 4879 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 4880 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4881 * PMSRC registers are written to. 4882 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 4883 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 4884 * cleared when the PMCFG or the PMSRC registers are written to. 4885 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 4886 * 0b101..Low level. Match occurs when there is a low level on the specified input. 4887 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 4888 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 4889 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 4890 * is cleared after one clock cycle. 4891 */ 4892 #define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) 4893 #define PINT_PMCFG_CFG6_MASK (0x1C000000U) 4894 #define PINT_PMCFG_CFG6_SHIFT (26U) 4895 /*! CFG6 - Specifies the match contribution condition for bit slice 6. 4896 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 4897 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 4898 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4899 * PMSRC registers are written to. 4900 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 4901 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4902 * PMSRC registers are written to. 4903 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 4904 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 4905 * cleared when the PMCFG or the PMSRC registers are written to. 4906 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 4907 * 0b101..Low level. Match occurs when there is a low level on the specified input. 4908 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 4909 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 4910 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 4911 * is cleared after one clock cycle. 4912 */ 4913 #define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) 4914 #define PINT_PMCFG_CFG7_MASK (0xE0000000U) 4915 #define PINT_PMCFG_CFG7_SHIFT (29U) 4916 /*! CFG7 - Specifies the match contribution condition for bit slice 7. 4917 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 4918 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 4919 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4920 * PMSRC registers are written to. 4921 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 4922 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 4923 * PMSRC registers are written to. 4924 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 4925 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 4926 * cleared when the PMCFG or the PMSRC registers are written to. 4927 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 4928 * 0b101..Low level. Match occurs when there is a low level on the specified input. 4929 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 4930 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 4931 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 4932 * is cleared after one clock cycle. 4933 */ 4934 #define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) 4935 /*! @} */ 4936 4937 4938 /*! 4939 * @} 4940 */ /* end of group PINT_Register_Masks */ 4941 4942 4943 /* PINT - Peripheral instance base addresses */ 4944 /** Peripheral PINT base address */ 4945 #define PINT_BASE (0xA0004000u) 4946 /** Peripheral PINT base pointer */ 4947 #define PINT ((PINT_Type *)PINT_BASE) 4948 /** Array initializer of PINT peripheral base addresses */ 4949 #define PINT_BASE_ADDRS { PINT_BASE } 4950 /** Array initializer of PINT peripheral base pointers */ 4951 #define PINT_BASE_PTRS { PINT } 4952 /** Interrupt vectors for the PINT peripheral type */ 4953 #define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_DAC1_IRQn, PIN_INT6_USART3_IRQn, PIN_INT7_USART4_IRQn } 4954 4955 /*! 4956 * @} 4957 */ /* end of group PINT_Peripheral_Access_Layer */ 4958 4959 4960 /* ---------------------------------------------------------------------------- 4961 -- PMU Peripheral Access Layer 4962 ---------------------------------------------------------------------------- */ 4963 4964 /*! 4965 * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer 4966 * @{ 4967 */ 4968 4969 /** PMU - Register Layout Typedef */ 4970 typedef struct { 4971 __IO uint32_t PCON; /**< Power control register, offset: 0x0 */ 4972 __IO uint32_t GPREG[4]; /**< General purpose register N, array offset: 0x4, array step: 0x4 */ 4973 __IO uint32_t DPDCTRL; /**< Deep power-down control register. Also includes bits for general purpose storage., offset: 0x14 */ 4974 } PMU_Type; 4975 4976 /* ---------------------------------------------------------------------------- 4977 -- PMU Register Masks 4978 ---------------------------------------------------------------------------- */ 4979 4980 /*! 4981 * @addtogroup PMU_Register_Masks PMU Register Masks 4982 * @{ 4983 */ 4984 4985 /*! @name PCON - Power control register */ 4986 /*! @{ */ 4987 #define PMU_PCON_PM_MASK (0x7U) 4988 #define PMU_PCON_PM_SHIFT (0U) 4989 /*! PM - Power mode 4990 * 0b000..Default. The part is in active or sleep mode. 4991 * 0b001..Deep-sleep mode. ARM WFI will enter Deep-sleep mode. 4992 * 0b010..Power-down mode. ARM WFI will enter Power-down mode. 4993 * 0b011..Deep power-down mode. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down). 4994 */ 4995 #define PMU_PCON_PM(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_PM_SHIFT)) & PMU_PCON_PM_MASK) 4996 #define PMU_PCON_NODPD_MASK (0x8U) 4997 #define PMU_PCON_NODPD_SHIFT (3U) 4998 /*! NODPD - A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM 4999 * field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by 5000 * power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode 5001 * is blocked. 5002 */ 5003 #define PMU_PCON_NODPD(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_NODPD_SHIFT)) & PMU_PCON_NODPD_MASK) 5004 #define PMU_PCON_SLEEPFLAG_MASK (0x100U) 5005 #define PMU_PCON_SLEEPFLAG_SHIFT (8U) 5006 /*! SLEEPFLAG - Sleep mode flag 5007 * 0b0..Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect. 5008 * 0b1..Low power mode. Read: Sleep, Deep-sleep or Power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0. 5009 */ 5010 #define PMU_PCON_SLEEPFLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_SLEEPFLAG_SHIFT)) & PMU_PCON_SLEEPFLAG_MASK) 5011 #define PMU_PCON_DPDFLAG_MASK (0x800U) 5012 #define PMU_PCON_DPDFLAG_SHIFT (11U) 5013 /*! DPDFLAG - Deep power-down flag 5014 * 0b0..Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect. 5015 * 0b1..Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag. 5016 */ 5017 #define PMU_PCON_DPDFLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_DPDFLAG_SHIFT)) & PMU_PCON_DPDFLAG_MASK) 5018 /*! @} */ 5019 5020 /*! @name GPREG - General purpose register N */ 5021 /*! @{ */ 5022 #define PMU_GPREG_GPDATA_MASK (0xFFFFFFFFU) 5023 #define PMU_GPREG_GPDATA_SHIFT (0U) 5024 /*! GPDATA - Data retained during Deep power-down mode. 5025 */ 5026 #define PMU_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPREG_GPDATA_SHIFT)) & PMU_GPREG_GPDATA_MASK) 5027 /*! @} */ 5028 5029 /* The count of PMU_GPREG */ 5030 #define PMU_GPREG_COUNT (4U) 5031 5032 /*! @name DPDCTRL - Deep power-down control register. Also includes bits for general purpose storage. */ 5033 /*! @{ */ 5034 #define PMU_DPDCTRL_WAKEUPHYS_MASK (0x1U) 5035 #define PMU_DPDCTRL_WAKEUPHYS_SHIFT (0U) 5036 /*! WAKEUPHYS - WAKEUP pin hysteresis enable 5037 * 0b0..Disabled. Hysteresis for WAKEUP pin disabled. 5038 * 0b1..Enabled. Hysteresis for WAKEUP pin enabled. 5039 */ 5040 #define PMU_DPDCTRL_WAKEUPHYS(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_WAKEUPHYS_SHIFT)) & PMU_DPDCTRL_WAKEUPHYS_MASK) 5041 #define PMU_DPDCTRL_WAKEPAD_DISABLE_MASK (0x2U) 5042 #define PMU_DPDCTRL_WAKEPAD_DISABLE_SHIFT (1U) 5043 /*! WAKEPAD_DISABLE - WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be 5044 * used for other purposes. Remark: Never set this bit if you intend to use a pin to wake up the 5045 * part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer 5046 * is enabled and configured. Remark: Setting this bit is not necessary if Deep power-down mode is 5047 * not used. 5048 * 0b0..Enabled. The wake-up function is enabled on pin PIO0_4. 5049 * 0b1..Disabled. Setting this bit disables the wake-up function on pin PIO0_4. 5050 */ 5051 #define PMU_DPDCTRL_WAKEPAD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_WAKEPAD_DISABLE_SHIFT)) & PMU_DPDCTRL_WAKEPAD_DISABLE_MASK) 5052 #define PMU_DPDCTRL_LPOSCEN_MASK (0x4U) 5053 #define PMU_DPDCTRL_LPOSCEN_SHIFT (2U) 5054 /*! LPOSCEN - Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You 5055 * must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set. Do not enable 5056 * the low-power oscillator if the self wake-up timer is clocked by the divided IRC or the 5057 * external clock input. 5058 * 0b0..Disabled. 5059 * 0b1..Enabled. 5060 */ 5061 #define PMU_DPDCTRL_LPOSCEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_LPOSCEN_SHIFT)) & PMU_DPDCTRL_LPOSCEN_MASK) 5062 #define PMU_DPDCTRL_LPOSCDPDEN_MASK (0x8U) 5063 #define PMU_DPDCTRL_LPOSCDPDEN_SHIFT (3U) 5064 /*! LPOSCDPDEN - causes the low-power oscillator to remain running during Deep power-down mode 5065 * provided that bit 2 in this register is set as well. You must set this bit for the self wake-up 5066 * timer to be able to wake up the part from Deep power-down mode. Remark: Do not set this bit 5067 * unless you use the self wake-up timer with the low-power oscillator clock source to wake up from 5068 * Deep power-down mode. 5069 * 0b0..Disabled. 5070 * 0b1..Enabled. 5071 */ 5072 #define PMU_DPDCTRL_LPOSCDPDEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_LPOSCDPDEN_SHIFT)) & PMU_DPDCTRL_LPOSCDPDEN_MASK) 5073 #define PMU_DPDCTRL_WAKEUPCLKHYS_MASK (0x10U) 5074 #define PMU_DPDCTRL_WAKEUPCLKHYS_SHIFT (4U) 5075 /*! WAKEUPCLKHYS - External clock input for the self wake-up timer WKTCLKIN hysteresis enable. 5076 * 0b0..Disabled. Hysteresis for WAKEUP clock pin disabled. 5077 * 0b1..Enabled. Hysteresis for WAKEUP clock pin enabled. 5078 */ 5079 #define PMU_DPDCTRL_WAKEUPCLKHYS(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_WAKEUPCLKHYS_SHIFT)) & PMU_DPDCTRL_WAKEUPCLKHYS_MASK) 5080 #define PMU_DPDCTRL_WAKECLKPAD_DISABLE_MASK (0x20U) 5081 #define PMU_DPDCTRL_WAKECLKPAD_DISABLE_SHIFT (5U) 5082 /*! WAKECLKPAD_DISABLE - Disable the external clock input for the self-wake-up timer. Setting this 5083 * bit enables the self-wake-up timer clock pin WKTCLKLIN. To minimize power consumption, 5084 * especially in deep power-down mode, disable this clock input when not using the external clock option 5085 * for the self-wake-up timer. 5086 * 0b0..Disabled. Setting this bit disables external clock input on pin PIO0_28. 5087 * 0b1..Enabled. The external clock input for the self wake-up timer is enabled on pin PIO0_28. 5088 */ 5089 #define PMU_DPDCTRL_WAKECLKPAD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_WAKECLKPAD_DISABLE_SHIFT)) & PMU_DPDCTRL_WAKECLKPAD_DISABLE_MASK) 5090 #define PMU_DPDCTRL_RESETHYS_MASK (0x40U) 5091 #define PMU_DPDCTRL_RESETHYS_SHIFT (6U) 5092 /*! RESETHYS - RESET pin hysteresis enable. 5093 * 0b0..Disabled. Hysteresis for RESET pin disabled. 5094 * 0b1..Enabled. Hysteresis for RESET pin enabled. 5095 */ 5096 #define PMU_DPDCTRL_RESETHYS(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_RESETHYS_SHIFT)) & PMU_DPDCTRL_RESETHYS_MASK) 5097 #define PMU_DPDCTRL_RESET_DISABLE_MASK (0x80U) 5098 #define PMU_DPDCTRL_RESET_DISABLE_SHIFT (7U) 5099 /*! RESET_DISABLE - RESET pin disable. Setting this bit disables the reset wake-up function, so the 5100 * pin can be used for other purposes. Remark: Setting this bit is not necessary if deep 5101 * power-down mode is not used. 5102 * 0b0..Enabled. The reset wake-up function is enabled on pin PIO0_5. 5103 * 0b1..Disabled. Setting this bit disables the wake-up function on pin PIO0_5. 5104 */ 5105 #define PMU_DPDCTRL_RESET_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_RESET_DISABLE_SHIFT)) & PMU_DPDCTRL_RESET_DISABLE_MASK) 5106 #define PMU_DPDCTRL_GPDATA_MASK (0xFFFFFF00U) 5107 #define PMU_DPDCTRL_GPDATA_SHIFT (8U) 5108 /*! GPDATA - Data retained during Deep power-down mode. 5109 */ 5110 #define PMU_DPDCTRL_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << PMU_DPDCTRL_GPDATA_SHIFT)) & PMU_DPDCTRL_GPDATA_MASK) 5111 /*! @} */ 5112 5113 5114 /*! 5115 * @} 5116 */ /* end of group PMU_Register_Masks */ 5117 5118 5119 /* PMU - Peripheral instance base addresses */ 5120 /** Peripheral PMU base address */ 5121 #define PMU_BASE (0x40020000u) 5122 /** Peripheral PMU base pointer */ 5123 #define PMU ((PMU_Type *)PMU_BASE) 5124 /** Array initializer of PMU peripheral base addresses */ 5125 #define PMU_BASE_ADDRS { PMU_BASE } 5126 /** Array initializer of PMU peripheral base pointers */ 5127 #define PMU_BASE_PTRS { PMU } 5128 5129 /*! 5130 * @} 5131 */ /* end of group PMU_Peripheral_Access_Layer */ 5132 5133 5134 /* ---------------------------------------------------------------------------- 5135 -- SCT Peripheral Access Layer 5136 ---------------------------------------------------------------------------- */ 5137 5138 /*! 5139 * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer 5140 * @{ 5141 */ 5142 5143 /** SCT - Register Layout Typedef */ 5144 typedef struct { 5145 __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ 5146 union { /* offset: 0x4 */ 5147 struct { /* offset: 0x4 */ 5148 __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ 5149 __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ 5150 } CTRL_ACCESS16BIT; 5151 __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ 5152 }; 5153 union { /* offset: 0x8 */ 5154 struct { /* offset: 0x8 */ 5155 __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ 5156 __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ 5157 } LIMIT_ACCESS16BIT; 5158 __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ 5159 }; 5160 union { /* offset: 0xC */ 5161 struct { /* offset: 0xC */ 5162 __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ 5163 __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ 5164 } HALT_ACCESS16BIT; 5165 __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ 5166 }; 5167 union { /* offset: 0x10 */ 5168 struct { /* offset: 0x10 */ 5169 __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ 5170 __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ 5171 } STOP_ACCESS16BIT; 5172 __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ 5173 }; 5174 union { /* offset: 0x14 */ 5175 struct { /* offset: 0x14 */ 5176 __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ 5177 __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ 5178 } START_ACCESS16BIT; 5179 __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ 5180 }; 5181 uint8_t RESERVED_0[40]; 5182 union { /* offset: 0x40 */ 5183 struct { /* offset: 0x40 */ 5184 __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ 5185 __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ 5186 } COUNT_ACCESS16BIT; 5187 __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ 5188 }; 5189 union { /* offset: 0x44 */ 5190 struct { /* offset: 0x44 */ 5191 __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ 5192 __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ 5193 } STATE_ACCESS16BIT; 5194 __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ 5195 }; 5196 __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ 5197 union { /* offset: 0x4C */ 5198 struct { /* offset: 0x4C */ 5199 __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ 5200 __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ 5201 } REGMODE_ACCESS16BIT; 5202 __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ 5203 }; 5204 __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ 5205 __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ 5206 __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ 5207 __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ 5208 __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ 5209 uint8_t RESERVED_1[140]; 5210 __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ 5211 __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ 5212 __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ 5213 __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ 5214 union { /* offset: 0x100 */ 5215 union { /* offset: 0x100, array step: 0x4 */ 5216 struct { /* offset: 0x100, array step: 0x4 */ 5217 __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ 5218 __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ 5219 } CAP_ACCESS16BIT[8]; 5220 __IO uint32_t CAP[8]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ 5221 }; 5222 union { /* offset: 0x100, array step: 0x4 */ 5223 struct { /* offset: 0x100, array step: 0x4 */ 5224 __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ 5225 __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ 5226 } MATCH_ACCESS16BIT[8]; 5227 __IO uint32_t MATCH[8]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ 5228 }; 5229 }; 5230 uint8_t RESERVED_2[224]; 5231 union { /* offset: 0x200 */ 5232 union { /* offset: 0x200, array step: 0x4 */ 5233 struct { /* offset: 0x200, array step: 0x4 */ 5234 __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ 5235 __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ 5236 } CAPCTRL_ACCESS16BIT[8]; 5237 __IO uint32_t CAPCTRL[8]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ 5238 }; 5239 union { /* offset: 0x200, array step: 0x4 */ 5240 struct { /* offset: 0x200, array step: 0x4 */ 5241 __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ 5242 __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ 5243 } MATCHREL_ACCESS16BIT[8]; 5244 __IO uint32_t MATCHREL[8]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ 5245 }; 5246 }; 5247 uint8_t RESERVED_3[224]; 5248 struct { /* offset: 0x300, array step: 0x8 */ 5249 __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ 5250 __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ 5251 } EV[8]; 5252 uint8_t RESERVED_4[448]; 5253 struct { /* offset: 0x500, array step: 0x8 */ 5254 __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ 5255 __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ 5256 } OUT[7]; 5257 } SCT_Type; 5258 5259 /* ---------------------------------------------------------------------------- 5260 -- SCT Register Masks 5261 ---------------------------------------------------------------------------- */ 5262 5263 /*! 5264 * @addtogroup SCT_Register_Masks SCT Register Masks 5265 * @{ 5266 */ 5267 5268 /*! @name CONFIG - SCT configuration register */ 5269 /*! @{ */ 5270 #define SCT_CONFIG_UNIFY_MASK (0x1U) 5271 #define SCT_CONFIG_UNIFY_SHIFT (0U) 5272 /*! UNIFY - SCT operation 5273 * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. 5274 * 0b1..The SCT operates as a unified 32-bit counter. 5275 */ 5276 #define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) 5277 #define SCT_CONFIG_CLKMODE_MASK (0x6U) 5278 #define SCT_CONFIG_CLKMODE_SHIFT (1U) 5279 /*! CLKMODE - SCT clock mode 5280 * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. 5281 * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are 5282 * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The 5283 * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the 5284 * high-performance, sampled-clock mode. 5285 * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the 5286 * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the 5287 * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. 5288 * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL 5289 * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system 5290 * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than 5291 * the system clock. 5292 */ 5293 #define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) 5294 #define SCT_CONFIG_CKSEL_MASK (0x78U) 5295 #define SCT_CONFIG_CKSEL_SHIFT (3U) 5296 /*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent 5297 * on the CLKMODE bit selection in this register. 5298 * 0b0000..Rising edges on input 0. 5299 * 0b0001..Falling edges on input 0. 5300 * 0b0010..Rising edges on input 1. 5301 * 0b0011..Falling edges on input 1. 5302 * 0b0100..Rising edges on input 2. 5303 * 0b0101..Falling edges on input 2. 5304 * 0b0110..Rising edges on input 3. 5305 * 0b0111..Falling edges on input 3. 5306 */ 5307 #define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) 5308 #define SCT_CONFIG_NORELOAD_L_MASK (0x80U) 5309 #define SCT_CONFIG_NORELOAD_L_SHIFT (7U) 5310 /*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their 5311 * respective reload registers. Setting this bit eliminates the need to write to the reload 5312 * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any 5313 * time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 5314 */ 5315 #define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) 5316 #define SCT_CONFIG_NORELOAD_H_MASK (0x100U) 5317 #define SCT_CONFIG_NORELOAD_H_SHIFT (8U) 5318 /*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their 5319 * respective reload registers. Setting this bit eliminates the need to write to the reload 5320 * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at 5321 * any time. This bit is not used when the UNIFY bit is set. 5322 */ 5323 #define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) 5324 #define SCT_CONFIG_INSYNC_MASK (0x1E00U) 5325 #define SCT_CONFIG_INSYNC_SHIFT (9U) 5326 /*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all 5327 * other bits are reserved. A 1 in one of these bits subjects the corresponding input to 5328 * synchronization to the SCT clock, before it is used to create an event. If an input is known to 5329 * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: 5330 * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input 5331 * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. 5332 * It does not apply to the clock input specified in the CKSEL field. 5333 */ 5334 #define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) 5335 #define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) 5336 #define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) 5337 /*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto 5338 * LIMIT condition without the need to define an associated event. As with any LIMIT event, this 5339 * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change 5340 * the direction of count in bi-directional mode. Software can write to set or clear this bit at 5341 * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 5342 */ 5343 #define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) 5344 #define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) 5345 #define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) 5346 /*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a 5347 * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, 5348 * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to 5349 * change the direction of count in bi-directional mode. Software can write to set or clear this bit 5350 * at any time. This bit is not used when the UNIFY bit is set. 5351 */ 5352 #define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) 5353 /*! @} */ 5354 5355 /*! @name CTRLL - SCT_CTRLL register */ 5356 /*! @{ */ 5357 #define SCT_CTRLL_DOWN_L_MASK (0x1U) 5358 #define SCT_CTRLL_DOWN_L_SHIFT (0U) 5359 /*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit 5360 * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit 5361 * when the counter is counting down and a limit condition occurs or when the counter reaches 0. 5362 */ 5363 #define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) 5364 #define SCT_CTRLL_STOP_L_MASK (0x2U) 5365 #define SCT_CTRLL_STOP_L_SHIFT (1U) 5366 /*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events 5367 * related to the counter can occur. If a designated start event occurs, this bit is cleared and 5368 * counting resumes. 5369 */ 5370 #define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) 5371 #define SCT_CTRLL_HALT_L_MASK (0x4U) 5372 #define SCT_CTRLL_HALT_L_SHIFT (2U) 5373 /*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A 5374 * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to 5375 * remove the halt condition while keeping the SCT in the stop condition (not running) with a 5376 * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, 5377 * only software can clear this bit to restore counter operation. This bit is set on reset. 5378 */ 5379 #define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) 5380 #define SCT_CTRLL_CLRCTR_L_MASK (0x8U) 5381 #define SCT_CTRLL_CLRCTR_L_SHIFT (3U) 5382 /*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. 5383 */ 5384 #define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) 5385 #define SCT_CTRLL_BIDIR_L_MASK (0x10U) 5386 #define SCT_CTRLL_BIDIR_L_SHIFT (4U) 5387 /*! BIDIR_L - L or unified counter direction select 5388 * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. 5389 * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. 5390 */ 5391 #define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) 5392 #define SCT_CTRLL_PRE_L_MASK (0x1FE0U) 5393 #define SCT_CTRLL_PRE_L_SHIFT (5U) 5394 /*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified 5395 * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. 5396 * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 5397 */ 5398 #define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) 5399 /*! @} */ 5400 5401 /*! @name CTRLH - SCT_CTRLH register */ 5402 /*! @{ */ 5403 #define SCT_CTRLH_DOWN_H_MASK (0x1U) 5404 #define SCT_CTRLH_DOWN_H_SHIFT (0U) 5405 /*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the 5406 * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit 5407 * when the counter is counting down and a limit condition occurs or when the counter reaches 0. 5408 */ 5409 #define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) 5410 #define SCT_CTRLH_STOP_H_MASK (0x2U) 5411 #define SCT_CTRLH_STOP_H_SHIFT (1U) 5412 /*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to 5413 * the counter can occur. If such an event matches the mask in the Start register, this bit is 5414 * cleared and counting resumes. 5415 */ 5416 #define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) 5417 #define SCT_CTRLH_HALT_H_MASK (0x4U) 5418 #define SCT_CTRLH_HALT_H_SHIFT (2U) 5419 /*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets 5420 * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the 5421 * halt condition while keeping the SCT in the stop condition (not running) with a single write to 5422 * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit 5423 * can only be cleared by software to restore counter operation. This bit is set on reset. 5424 */ 5425 #define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) 5426 #define SCT_CTRLH_CLRCTR_H_MASK (0x8U) 5427 #define SCT_CTRLH_CLRCTR_H_SHIFT (3U) 5428 /*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. 5429 */ 5430 #define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) 5431 #define SCT_CTRLH_BIDIR_H_MASK (0x10U) 5432 #define SCT_CTRLH_BIDIR_H_SHIFT (4U) 5433 /*! BIDIR_H - Direction select 5434 * 0b0..The H counter counts up to its limit condition, then is cleared to zero. 5435 * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. 5436 */ 5437 #define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) 5438 #define SCT_CTRLH_PRE_H_MASK (0x1FE0U) 5439 #define SCT_CTRLH_PRE_H_SHIFT (5U) 5440 /*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. 5441 * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the 5442 * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 5443 */ 5444 #define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) 5445 /*! @} */ 5446 5447 /*! @name CTRL - SCT control register */ 5448 /*! @{ */ 5449 #define SCT_CTRL_DOWN_L_MASK (0x1U) 5450 #define SCT_CTRL_DOWN_L_SHIFT (0U) 5451 /*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit 5452 * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit 5453 * when the counter is counting down and a limit condition occurs or when the counter reaches 0. 5454 */ 5455 #define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) 5456 #define SCT_CTRL_STOP_L_MASK (0x2U) 5457 #define SCT_CTRL_STOP_L_SHIFT (1U) 5458 /*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events 5459 * related to the counter can occur. If a designated start event occurs, this bit is cleared and 5460 * counting resumes. 5461 */ 5462 #define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) 5463 #define SCT_CTRL_HALT_L_MASK (0x4U) 5464 #define SCT_CTRL_HALT_L_SHIFT (2U) 5465 /*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A 5466 * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to 5467 * remove the halt condition while keeping the SCT in the stop condition (not running) with a 5468 * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, 5469 * only software can clear this bit to restore counter operation. This bit is set on reset. 5470 */ 5471 #define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) 5472 #define SCT_CTRL_CLRCTR_L_MASK (0x8U) 5473 #define SCT_CTRL_CLRCTR_L_SHIFT (3U) 5474 /*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. 5475 */ 5476 #define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) 5477 #define SCT_CTRL_BIDIR_L_MASK (0x10U) 5478 #define SCT_CTRL_BIDIR_L_SHIFT (4U) 5479 /*! BIDIR_L - L or unified counter direction select 5480 * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. 5481 * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. 5482 */ 5483 #define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) 5484 #define SCT_CTRL_PRE_L_MASK (0x1FE0U) 5485 #define SCT_CTRL_PRE_L_SHIFT (5U) 5486 /*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified 5487 * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. 5488 * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 5489 */ 5490 #define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) 5491 #define SCT_CTRL_DOWN_H_MASK (0x10000U) 5492 #define SCT_CTRL_DOWN_H_SHIFT (16U) 5493 /*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the 5494 * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit 5495 * when the counter is counting down and a limit condition occurs or when the counter reaches 0. 5496 */ 5497 #define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) 5498 #define SCT_CTRL_STOP_H_MASK (0x20000U) 5499 #define SCT_CTRL_STOP_H_SHIFT (17U) 5500 /*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to 5501 * the counter can occur. If such an event matches the mask in the Start register, this bit is 5502 * cleared and counting resumes. 5503 */ 5504 #define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) 5505 #define SCT_CTRL_HALT_H_MASK (0x40000U) 5506 #define SCT_CTRL_HALT_H_SHIFT (18U) 5507 /*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets 5508 * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the 5509 * halt condition while keeping the SCT in the stop condition (not running) with a single write to 5510 * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit 5511 * can only be cleared by software to restore counter operation. This bit is set on reset. 5512 */ 5513 #define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) 5514 #define SCT_CTRL_CLRCTR_H_MASK (0x80000U) 5515 #define SCT_CTRL_CLRCTR_H_SHIFT (19U) 5516 /*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. 5517 */ 5518 #define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) 5519 #define SCT_CTRL_BIDIR_H_MASK (0x100000U) 5520 #define SCT_CTRL_BIDIR_H_SHIFT (20U) 5521 /*! BIDIR_H - Direction select 5522 * 0b0..The H counter counts up to its limit condition, then is cleared to zero. 5523 * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. 5524 */ 5525 #define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) 5526 #define SCT_CTRL_PRE_H_MASK (0x1FE00000U) 5527 #define SCT_CTRL_PRE_H_SHIFT (21U) 5528 /*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. 5529 * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the 5530 * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 5531 */ 5532 #define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) 5533 /*! @} */ 5534 5535 /*! @name LIMITL - SCT_LIMITL register */ 5536 /*! @{ */ 5537 #define SCT_LIMITL_LIMITL_MASK (0xFFFFU) 5538 #define SCT_LIMITL_LIMITL_SHIFT (0U) 5539 #define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) 5540 /*! @} */ 5541 5542 /*! @name LIMITH - SCT_LIMITH register */ 5543 /*! @{ */ 5544 #define SCT_LIMITH_LIMITH_MASK (0xFFFFU) 5545 #define SCT_LIMITH_LIMITH_SHIFT (0U) 5546 #define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) 5547 /*! @} */ 5548 5549 /*! @name LIMIT - SCT limit event select register */ 5550 /*! @{ */ 5551 #define SCT_LIMIT_LIMMSK_L_MASK (0xFFU) 5552 #define SCT_LIMIT_LIMMSK_L_SHIFT (0U) 5553 /*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter 5554 * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 5555 */ 5556 #define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) 5557 #define SCT_LIMIT_LIMMSK_H_MASK (0xFF0000U) 5558 #define SCT_LIMIT_LIMMSK_H_SHIFT (16U) 5559 /*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 5560 * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 5561 */ 5562 #define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) 5563 /*! @} */ 5564 5565 /*! @name HALTL - SCT_HALTL register */ 5566 /*! @{ */ 5567 #define SCT_HALTL_HALTL_MASK (0xFFFFU) 5568 #define SCT_HALTL_HALTL_SHIFT (0U) 5569 #define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) 5570 /*! @} */ 5571 5572 /*! @name HALTH - SCT_HALTH register */ 5573 /*! @{ */ 5574 #define SCT_HALTH_HALTH_MASK (0xFFFFU) 5575 #define SCT_HALTH_HALTH_SHIFT (0U) 5576 #define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) 5577 /*! @} */ 5578 5579 /*! @name HALT - SCT halt event select register */ 5580 /*! @{ */ 5581 #define SCT_HALT_HALTMSK_L_MASK (0xFFU) 5582 #define SCT_HALT_HALTMSK_L_SHIFT (0U) 5583 /*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, 5584 * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 5585 */ 5586 #define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) 5587 #define SCT_HALT_HALTMSK_H_MASK (0xFF0000U) 5588 #define SCT_HALT_HALTMSK_H_SHIFT (16U) 5589 /*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, 5590 * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 5591 */ 5592 #define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) 5593 /*! @} */ 5594 5595 /*! @name STOPL - SCT_STOPL register */ 5596 /*! @{ */ 5597 #define SCT_STOPL_STOPL_MASK (0xFFFFU) 5598 #define SCT_STOPL_STOPL_SHIFT (0U) 5599 #define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) 5600 /*! @} */ 5601 5602 /*! @name STOPH - SCT_STOPH register */ 5603 /*! @{ */ 5604 #define SCT_STOPH_STOPH_MASK (0xFFFFU) 5605 #define SCT_STOPH_STOPH_SHIFT (0U) 5606 #define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) 5607 /*! @} */ 5608 5609 /*! @name STOP - SCT stop event select register */ 5610 /*! @{ */ 5611 #define SCT_STOP_STOPMSK_L_MASK (0xFFU) 5612 #define SCT_STOP_STOPMSK_L_SHIFT (0U) 5613 /*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, 5614 * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 5615 */ 5616 #define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) 5617 #define SCT_STOP_STOPMSK_H_MASK (0xFF0000U) 5618 #define SCT_STOP_STOPMSK_H_SHIFT (16U) 5619 /*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, 5620 * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 5621 */ 5622 #define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) 5623 /*! @} */ 5624 5625 /*! @name STARTL - SCT_STARTL register */ 5626 /*! @{ */ 5627 #define SCT_STARTL_STARTL_MASK (0xFFFFU) 5628 #define SCT_STARTL_STARTL_SHIFT (0U) 5629 #define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) 5630 /*! @} */ 5631 5632 /*! @name STARTH - SCT_STARTH register */ 5633 /*! @{ */ 5634 #define SCT_STARTH_STARTH_MASK (0xFFFFU) 5635 #define SCT_STARTH_STARTH_SHIFT (0U) 5636 #define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) 5637 /*! @} */ 5638 5639 /*! @name START - SCT start event select register */ 5640 /*! @{ */ 5641 #define SCT_START_STARTMSK_L_MASK (0xFFU) 5642 #define SCT_START_STARTMSK_L_SHIFT (0U) 5643 /*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 5644 * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 5645 */ 5646 #define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) 5647 #define SCT_START_STARTMSK_H_MASK (0xFF0000U) 5648 #define SCT_START_STARTMSK_H_SHIFT (16U) 5649 /*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 5650 * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 5651 */ 5652 #define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) 5653 /*! @} */ 5654 5655 /*! @name COUNTL - SCT_COUNTL register */ 5656 /*! @{ */ 5657 #define SCT_COUNTL_COUNTL_MASK (0xFFFFU) 5658 #define SCT_COUNTL_COUNTL_SHIFT (0U) 5659 #define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) 5660 /*! @} */ 5661 5662 /*! @name COUNTH - SCT_COUNTH register */ 5663 /*! @{ */ 5664 #define SCT_COUNTH_COUNTH_MASK (0xFFFFU) 5665 #define SCT_COUNTH_COUNTH_SHIFT (0U) 5666 #define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) 5667 /*! @} */ 5668 5669 /*! @name COUNT - SCT counter register */ 5670 /*! @{ */ 5671 #define SCT_COUNT_CTR_L_MASK (0xFFFFU) 5672 #define SCT_COUNT_CTR_L_SHIFT (0U) 5673 /*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write 5674 * the lower 16 bits of the 32-bit unified counter. 5675 */ 5676 #define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) 5677 #define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) 5678 #define SCT_COUNT_CTR_H_SHIFT (16U) 5679 /*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write 5680 * the upper 16 bits of the 32-bit unified counter. 5681 */ 5682 #define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) 5683 /*! @} */ 5684 5685 /*! @name STATEL - SCT_STATEL register */ 5686 /*! @{ */ 5687 #define SCT_STATEL_STATEL_MASK (0xFFFFU) 5688 #define SCT_STATEL_STATEL_SHIFT (0U) 5689 #define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) 5690 /*! @} */ 5691 5692 /*! @name STATEH - SCT_STATEH register */ 5693 /*! @{ */ 5694 #define SCT_STATEH_STATEH_MASK (0xFFFFU) 5695 #define SCT_STATEH_STATEH_SHIFT (0U) 5696 #define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) 5697 /*! @} */ 5698 5699 /*! @name STATE - SCT state register */ 5700 /*! @{ */ 5701 #define SCT_STATE_STATE_L_MASK (0x1FU) 5702 #define SCT_STATE_STATE_L_SHIFT (0U) 5703 /*! STATE_L - State variable. 5704 */ 5705 #define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) 5706 #define SCT_STATE_STATE_H_MASK (0x1F0000U) 5707 #define SCT_STATE_STATE_H_SHIFT (16U) 5708 /*! STATE_H - State variable. 5709 */ 5710 #define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) 5711 /*! @} */ 5712 5713 /*! @name INPUT - SCT input register */ 5714 /*! @{ */ 5715 #define SCT_INPUT_AIN0_MASK (0x1U) 5716 #define SCT_INPUT_AIN0_SHIFT (0U) 5717 /*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. 5718 */ 5719 #define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) 5720 #define SCT_INPUT_AIN1_MASK (0x2U) 5721 #define SCT_INPUT_AIN1_SHIFT (1U) 5722 /*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. 5723 */ 5724 #define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) 5725 #define SCT_INPUT_AIN2_MASK (0x4U) 5726 #define SCT_INPUT_AIN2_SHIFT (2U) 5727 /*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. 5728 */ 5729 #define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) 5730 #define SCT_INPUT_AIN3_MASK (0x8U) 5731 #define SCT_INPUT_AIN3_SHIFT (3U) 5732 /*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. 5733 */ 5734 #define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) 5735 #define SCT_INPUT_AIN4_MASK (0x10U) 5736 #define SCT_INPUT_AIN4_SHIFT (4U) 5737 /*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. 5738 */ 5739 #define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) 5740 #define SCT_INPUT_SIN0_MASK (0x10000U) 5741 #define SCT_INPUT_SIN0_SHIFT (16U) 5742 /*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. 5743 */ 5744 #define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) 5745 #define SCT_INPUT_SIN1_MASK (0x20000U) 5746 #define SCT_INPUT_SIN1_SHIFT (17U) 5747 /*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. 5748 */ 5749 #define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) 5750 #define SCT_INPUT_SIN2_MASK (0x40000U) 5751 #define SCT_INPUT_SIN2_SHIFT (18U) 5752 /*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. 5753 */ 5754 #define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) 5755 #define SCT_INPUT_SIN3_MASK (0x80000U) 5756 #define SCT_INPUT_SIN3_SHIFT (19U) 5757 /*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. 5758 */ 5759 #define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) 5760 #define SCT_INPUT_SIN4_MASK (0x100000U) 5761 #define SCT_INPUT_SIN4_SHIFT (20U) 5762 /*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. 5763 */ 5764 #define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) 5765 /*! @} */ 5766 5767 /*! @name REGMODEL - SCT_REGMODEL register */ 5768 /*! @{ */ 5769 #define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) 5770 #define SCT_REGMODEL_REGMODEL_SHIFT (0U) 5771 #define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) 5772 /*! @} */ 5773 5774 /*! @name REGMODEH - SCT_REGMODEH register */ 5775 /*! @{ */ 5776 #define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) 5777 #define SCT_REGMODEH_REGMODEH_SHIFT (0U) 5778 #define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) 5779 /*! @} */ 5780 5781 /*! @name REGMODE - SCT match/capture mode register */ 5782 /*! @{ */ 5783 #define SCT_REGMODE_REGMOD_L_MASK (0xFFU) 5784 #define SCT_REGMODE_REGMOD_L_SHIFT (0U) 5785 /*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, 5786 * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as 5787 * match register. 1 = register operates as capture register. 5788 */ 5789 #define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) 5790 #define SCT_REGMODE_REGMOD_H_MASK (0xFF0000U) 5791 #define SCT_REGMODE_REGMOD_H_SHIFT (16U) 5792 /*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 5793 * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as 5794 * match registers. 1 = register operates as capture registers. 5795 */ 5796 #define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) 5797 /*! @} */ 5798 5799 /*! @name OUTPUT - SCT output register */ 5800 /*! @{ */ 5801 #define SCT_OUTPUT_OUT_MASK (0x7FU) 5802 #define SCT_OUTPUT_OUT_SHIFT (0U) 5803 /*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the 5804 * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of 5805 * outputs in this SCT. 5806 */ 5807 #define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) 5808 /*! @} */ 5809 5810 /*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ 5811 /*! @{ */ 5812 #define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) 5813 #define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) 5814 /*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. 5815 * 0b00..Set and clear do not depend on the direction of any counter. 5816 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 5817 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 5818 */ 5819 #define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) 5820 #define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) 5821 #define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) 5822 /*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. 5823 * 0b00..Set and clear do not depend on the direction of any counter. 5824 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 5825 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 5826 */ 5827 #define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) 5828 #define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) 5829 #define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) 5830 /*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. 5831 * 0b00..Set and clear do not depend on the direction of any counter. 5832 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 5833 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 5834 */ 5835 #define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) 5836 #define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) 5837 #define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) 5838 /*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. 5839 * 0b00..Set and clear do not depend on the direction of any counter. 5840 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 5841 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 5842 */ 5843 #define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) 5844 #define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) 5845 #define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) 5846 /*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. 5847 * 0b00..Set and clear do not depend on the direction of any counter. 5848 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 5849 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 5850 */ 5851 #define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) 5852 #define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) 5853 #define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) 5854 /*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. 5855 * 0b00..Set and clear do not depend on the direction of any counter. 5856 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 5857 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 5858 */ 5859 #define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) 5860 #define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) 5861 #define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) 5862 /*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. 5863 * 0b00..Set and clear do not depend on the direction of any counter. 5864 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. 5865 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 5866 */ 5867 #define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) 5868 /*! @} */ 5869 5870 /*! @name RES - SCT conflict resolution register */ 5871 /*! @{ */ 5872 #define SCT_RES_O0RES_MASK (0x3U) 5873 #define SCT_RES_O0RES_SHIFT (0U) 5874 /*! O0RES - Effect of simultaneous set and clear on output 0. 5875 * 0b00..No change. 5876 * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). 5877 * 0b10..Clear output (or set based on the SETCLR0 field). 5878 * 0b11..Toggle output. 5879 */ 5880 #define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) 5881 #define SCT_RES_O1RES_MASK (0xCU) 5882 #define SCT_RES_O1RES_SHIFT (2U) 5883 /*! O1RES - Effect of simultaneous set and clear on output 1. 5884 * 0b00..No change. 5885 * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). 5886 * 0b10..Clear output (or set based on the SETCLR1 field). 5887 * 0b11..Toggle output. 5888 */ 5889 #define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) 5890 #define SCT_RES_O2RES_MASK (0x30U) 5891 #define SCT_RES_O2RES_SHIFT (4U) 5892 /*! O2RES - Effect of simultaneous set and clear on output 2. 5893 * 0b00..No change. 5894 * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). 5895 * 0b10..Clear output n (or set based on the SETCLR2 field). 5896 * 0b11..Toggle output. 5897 */ 5898 #define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) 5899 #define SCT_RES_O3RES_MASK (0xC0U) 5900 #define SCT_RES_O3RES_SHIFT (6U) 5901 /*! O3RES - Effect of simultaneous set and clear on output 3. 5902 * 0b00..No change. 5903 * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). 5904 * 0b10..Clear output (or set based on the SETCLR3 field). 5905 * 0b11..Toggle output. 5906 */ 5907 #define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) 5908 #define SCT_RES_O4RES_MASK (0x300U) 5909 #define SCT_RES_O4RES_SHIFT (8U) 5910 /*! O4RES - Effect of simultaneous set and clear on output 4. 5911 * 0b00..No change. 5912 * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). 5913 * 0b10..Clear output (or set based on the SETCLR4 field). 5914 * 0b11..Toggle output. 5915 */ 5916 #define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) 5917 #define SCT_RES_O5RES_MASK (0xC00U) 5918 #define SCT_RES_O5RES_SHIFT (10U) 5919 /*! O5RES - Effect of simultaneous set and clear on output 5. 5920 * 0b00..No change. 5921 * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). 5922 * 0b10..Clear output (or set based on the SETCLR5 field). 5923 * 0b11..Toggle output. 5924 */ 5925 #define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) 5926 #define SCT_RES_O6RES_MASK (0x3000U) 5927 #define SCT_RES_O6RES_SHIFT (12U) 5928 /*! O6RES - Effect of simultaneous set and clear on output 6. 5929 * 0b00..No change. 5930 * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). 5931 * 0b10..Clear output (or set based on the SETCLR6 field). 5932 * 0b11..Toggle output. 5933 */ 5934 #define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) 5935 /*! @} */ 5936 5937 /*! @name DMAREQ0 - SCT DMA request 0 register */ 5938 /*! @{ */ 5939 #define SCT_DMAREQ0_DEV_0_MASK (0x3FU) 5940 #define SCT_DMAREQ0_DEV_0_SHIFT (0U) 5941 /*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, 5942 * etc.). The number of bits = number of events in this SCT. 5943 */ 5944 #define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) 5945 #define SCT_DMAREQ0_DRL0_MASK (0x40000000U) 5946 #define SCT_DMAREQ0_DRL0_SHIFT (30U) 5947 /*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. 5948 */ 5949 #define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) 5950 #define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) 5951 #define SCT_DMAREQ0_DRQ0_SHIFT (31U) 5952 /*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA 5953 * channel is enabled and properly set up, it is unlikely that software will see this flag, it will 5954 * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA 5955 * setup. 5956 */ 5957 #define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) 5958 /*! @} */ 5959 5960 /*! @name DMAREQ1 - SCT DMA request 1 register */ 5961 /*! @{ */ 5962 #define SCT_DMAREQ1_DEV_1_MASK (0x3FU) 5963 #define SCT_DMAREQ1_DEV_1_SHIFT (0U) 5964 /*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, 5965 * etc.). The number of bits = number of events in this SCT. 5966 */ 5967 #define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) 5968 #define SCT_DMAREQ1_DRL1_MASK (0x40000000U) 5969 #define SCT_DMAREQ1_DRL1_SHIFT (30U) 5970 /*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. 5971 */ 5972 #define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) 5973 #define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) 5974 #define SCT_DMAREQ1_DRQ1_SHIFT (31U) 5975 /*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA 5976 * channel is enabled and properly set up, it is unlikely that software will see this flag, it will 5977 * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA 5978 * setup. 5979 */ 5980 #define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) 5981 /*! @} */ 5982 5983 /*! @name EVEN - SCT event interrupt enable register */ 5984 /*! @{ */ 5985 #define SCT_EVEN_IEN_MASK (0xFFU) 5986 #define SCT_EVEN_IEN_SHIFT (0U) 5987 /*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are 5988 * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in 5989 * this SCT. 5990 */ 5991 #define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) 5992 /*! @} */ 5993 5994 /*! @name EVFLAG - SCT event flag register */ 5995 /*! @{ */ 5996 #define SCT_EVFLAG_FLAG_MASK (0xFFU) 5997 #define SCT_EVFLAG_FLAG_SHIFT (0U) 5998 /*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit 5999 * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 6000 */ 6001 #define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) 6002 /*! @} */ 6003 6004 /*! @name CONEN - SCT conflict interrupt enable register */ 6005 /*! @{ */ 6006 #define SCT_CONEN_NCEN_MASK (0x3FU) 6007 #define SCT_CONEN_NCEN_SHIFT (0U) 6008 /*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag 6009 * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of 6010 * outputs in this SCT. 6011 */ 6012 #define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) 6013 /*! @} */ 6014 6015 /*! @name CONFLAG - SCT conflict flag register */ 6016 /*! @{ */ 6017 #define SCT_CONFLAG_NCFLAG_MASK (0x3FU) 6018 #define SCT_CONFLAG_NCFLAG_SHIFT (0U) 6019 /*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was 6020 * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = 6021 * number of outputs in this SCT. 6022 */ 6023 #define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) 6024 #define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) 6025 #define SCT_CONFLAG_BUSERRL_SHIFT (30U) 6026 /*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE 6027 * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write 6028 * to certain L and H registers can be half successful and half unsuccessful. 6029 */ 6030 #define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) 6031 #define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) 6032 #define SCT_CONFLAG_BUSERRH_SHIFT (31U) 6033 /*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or 6034 * the Output register when the H counter was not halted. 6035 */ 6036 #define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) 6037 /*! @} */ 6038 6039 /*! @name CAPL - SCT_CAPL register */ 6040 /*! @{ */ 6041 #define SCT_CAPL_CAPL_MASK (0xFFFFU) 6042 #define SCT_CAPL_CAPL_SHIFT (0U) 6043 #define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) 6044 /*! @} */ 6045 6046 /* The count of SCT_CAPL */ 6047 #define SCT_CAPL_COUNT (8U) 6048 6049 /*! @name CAPH - SCT_CAPH register */ 6050 /*! @{ */ 6051 #define SCT_CAPH_CAPH_MASK (0xFFFFU) 6052 #define SCT_CAPH_CAPH_SHIFT (0U) 6053 #define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) 6054 /*! @} */ 6055 6056 /* The count of SCT_CAPH */ 6057 #define SCT_CAPH_COUNT (8U) 6058 6059 /*! @name CAP - SCT capture register of capture channel */ 6060 /*! @{ */ 6061 #define SCT_CAP_CAPn_L_MASK (0xFFFFU) 6062 #define SCT_CAP_CAPn_L_SHIFT (0U) 6063 /*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. 6064 * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last 6065 * captured. 6066 */ 6067 #define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) 6068 #define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) 6069 #define SCT_CAP_CAPn_H_SHIFT (16U) 6070 /*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. 6071 * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last 6072 * captured. 6073 */ 6074 #define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) 6075 /*! @} */ 6076 6077 /* The count of SCT_CAP */ 6078 #define SCT_CAP_COUNT (8U) 6079 6080 /*! @name MATCHL - SCT_MATCHL register */ 6081 /*! @{ */ 6082 #define SCT_MATCHL_MATCHL_MASK (0xFFFFU) 6083 #define SCT_MATCHL_MATCHL_SHIFT (0U) 6084 #define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) 6085 /*! @} */ 6086 6087 /* The count of SCT_MATCHL */ 6088 #define SCT_MATCHL_COUNT (8U) 6089 6090 /*! @name MATCHH - SCT_MATCHH register */ 6091 /*! @{ */ 6092 #define SCT_MATCHH_MATCHH_MASK (0xFFFFU) 6093 #define SCT_MATCHH_MATCHH_SHIFT (0U) 6094 #define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) 6095 /*! @} */ 6096 6097 /* The count of SCT_MATCHH */ 6098 #define SCT_MATCHH_COUNT (8U) 6099 6100 /*! @name MATCH - SCT match value register of match channels */ 6101 /*! @{ */ 6102 #define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) 6103 #define SCT_MATCH_MATCHn_L_SHIFT (0U) 6104 /*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When 6105 * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified 6106 * counter. 6107 */ 6108 #define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) 6109 #define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) 6110 #define SCT_MATCH_MATCHn_H_SHIFT (16U) 6111 /*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When 6112 * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified 6113 * counter. 6114 */ 6115 #define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) 6116 /*! @} */ 6117 6118 /* The count of SCT_MATCH */ 6119 #define SCT_MATCH_COUNT (8U) 6120 6121 /*! @name CAPCTRLL - SCT_CAPCTRLL register */ 6122 /*! @{ */ 6123 #define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) 6124 #define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) 6125 #define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) 6126 /*! @} */ 6127 6128 /* The count of SCT_CAPCTRLL */ 6129 #define SCT_CAPCTRLL_COUNT (8U) 6130 6131 /*! @name CAPCTRLH - SCT_CAPCTRLH register */ 6132 /*! @{ */ 6133 #define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) 6134 #define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) 6135 #define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) 6136 /*! @} */ 6137 6138 /* The count of SCT_CAPCTRLH */ 6139 #define SCT_CAPCTRLH_COUNT (8U) 6140 6141 /*! @name CAPCTRL - SCT capture control register */ 6142 /*! @{ */ 6143 #define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFU) 6144 #define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) 6145 /*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) 6146 * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of 6147 * match/captures in this SCT. 6148 */ 6149 #define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) 6150 #define SCT_CAPCTRL_CAPCONn_H_MASK (0xFF0000U) 6151 #define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) 6152 /*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 6153 * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 6154 */ 6155 #define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) 6156 /*! @} */ 6157 6158 /* The count of SCT_CAPCTRL */ 6159 #define SCT_CAPCTRL_COUNT (8U) 6160 6161 /*! @name MATCHRELL - SCT_MATCHRELL register */ 6162 /*! @{ */ 6163 #define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) 6164 #define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) 6165 #define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) 6166 /*! @} */ 6167 6168 /* The count of SCT_MATCHRELL */ 6169 #define SCT_MATCHRELL_COUNT (8U) 6170 6171 /*! @name MATCHRELH - SCT_MATCHRELH register */ 6172 /*! @{ */ 6173 #define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) 6174 #define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) 6175 #define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) 6176 /*! @} */ 6177 6178 /* The count of SCT_MATCHRELH */ 6179 #define SCT_MATCHRELH_COUNT (8U) 6180 6181 /*! @name MATCHREL - SCT match reload value register */ 6182 /*! @{ */ 6183 #define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) 6184 #define SCT_MATCHREL_RELOADn_L_SHIFT (0U) 6185 /*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. 6186 * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn 6187 * register. 6188 */ 6189 #define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) 6190 #define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) 6191 #define SCT_MATCHREL_RELOADn_H_SHIFT (16U) 6192 /*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When 6193 * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn 6194 * register. 6195 */ 6196 #define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) 6197 /*! @} */ 6198 6199 /* The count of SCT_MATCHREL */ 6200 #define SCT_MATCHREL_COUNT (8U) 6201 6202 /*! @name EV_STATE - SCT event state register 0 */ 6203 /*! @{ */ 6204 #define SCT_EV_STATE_STATEMSKn_MASK (0xFFU) 6205 #define SCT_EV_STATE_STATEMSKn_SHIFT (0U) 6206 /*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT 6207 * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of 6208 * bits = number of states in this SCT. 6209 */ 6210 #define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) 6211 /*! @} */ 6212 6213 /* The count of SCT_EV_STATE */ 6214 #define SCT_EV_STATE_COUNT (8U) 6215 6216 /*! @name EV_CTRL - SCT event control register 0 */ 6217 /*! @{ */ 6218 #define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) 6219 #define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) 6220 /*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur 6221 * only when the counter selected by the HEVENT bit is running. 6222 */ 6223 #define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) 6224 #define SCT_EV_CTRL_HEVENT_MASK (0x10U) 6225 #define SCT_EV_CTRL_HEVENT_SHIFT (4U) 6226 /*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. 6227 * 0b0..Selects the L state and the L match register selected by MATCHSEL. 6228 * 0b1..Selects the H state and the H match register selected by MATCHSEL. 6229 */ 6230 #define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) 6231 #define SCT_EV_CTRL_OUTSEL_MASK (0x20U) 6232 #define SCT_EV_CTRL_OUTSEL_SHIFT (5U) 6233 /*! OUTSEL - Input/output select 6234 * 0b0..Selects the inputs selected by IOSEL. 6235 * 0b1..Selects the outputs selected by IOSEL. 6236 */ 6237 #define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) 6238 #define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) 6239 #define SCT_EV_CTRL_IOSEL_SHIFT (6U) 6240 /*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not 6241 * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit 6242 * ingredient of every event. 6243 */ 6244 #define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) 6245 #define SCT_EV_CTRL_IOCOND_MASK (0xC00U) 6246 #define SCT_EV_CTRL_IOCOND_SHIFT (10U) 6247 /*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the 6248 * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state 6249 * detection, an input must have a minimum pulse width of at least one SCT clock period . 6250 * 0b00..LOW 6251 * 0b01..Rise 6252 * 0b10..Fall 6253 * 0b11..HIGH 6254 */ 6255 #define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) 6256 #define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) 6257 #define SCT_EV_CTRL_COMBMODE_SHIFT (12U) 6258 /*! COMBMODE - Selects how the specified match and I/O condition are used and combined. 6259 * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. 6260 * 0b01..MATCH. Uses the specified match only. 6261 * 0b10..IO. Uses the specified I/O condition only. 6262 * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. 6263 */ 6264 #define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) 6265 #define SCT_EV_CTRL_STATELD_MASK (0x4000U) 6266 #define SCT_EV_CTRL_STATELD_SHIFT (14U) 6267 /*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this 6268 * event is the highest-numbered event occurring for that state. 6269 * 0b0..STATEV value is added into STATE (the carry-out is ignored). 6270 * 0b1..STATEV value is loaded into STATE. 6271 */ 6272 #define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) 6273 #define SCT_EV_CTRL_STATEV_MASK (0xF8000U) 6274 #define SCT_EV_CTRL_STATEV_SHIFT (15U) 6275 /*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on 6276 * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and 6277 * STATEV are both zero, there is no change to the STATE value. 6278 */ 6279 #define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) 6280 #define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) 6281 #define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) 6282 /*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the 6283 * triggering of this event, then a match is considered to be active whenever the counter value is 6284 * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR 6285 * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active 6286 * during the cycle when the counter is equal to the match value. 6287 */ 6288 #define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) 6289 #define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) 6290 #define SCT_EV_CTRL_DIRECTION_SHIFT (21U) 6291 /*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters 6292 * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. 6293 * 0b00..Direction independent. This event is triggered regardless of the count direction. 6294 * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. 6295 * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. 6296 */ 6297 #define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) 6298 /*! @} */ 6299 6300 /* The count of SCT_EV_CTRL */ 6301 #define SCT_EV_CTRL_COUNT (8U) 6302 6303 /*! @name OUT_SET - SCT output 0 set register */ 6304 /*! @{ */ 6305 #define SCT_OUT_SET_SET_MASK (0xFFU) 6306 #define SCT_OUT_SET_SET_SHIFT (0U) 6307 /*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 6308 * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the 6309 * counter is used in bi-directional mode, it is possible to reverse the action specified by the 6310 * output set and clear registers when counting down, See the OUTPUTCTRL register. 6311 */ 6312 #define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) 6313 /*! @} */ 6314 6315 /* The count of SCT_OUT_SET */ 6316 #define SCT_OUT_SET_COUNT (7U) 6317 6318 /*! @name OUT_CLR - SCT output 0 clear register */ 6319 /*! @{ */ 6320 #define SCT_OUT_CLR_CLR_MASK (0xFFU) 6321 #define SCT_OUT_CLR_CLR_SHIFT (0U) 6322 /*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 6323 * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the 6324 * counter is used in bi-directional mode, it is possible to reverse the action specified by the 6325 * output set and clear registers when counting down, See the OUTPUTCTRL register. 6326 */ 6327 #define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) 6328 /*! @} */ 6329 6330 /* The count of SCT_OUT_CLR */ 6331 #define SCT_OUT_CLR_COUNT (7U) 6332 6333 6334 /*! 6335 * @} 6336 */ /* end of group SCT_Register_Masks */ 6337 6338 6339 /* SCT - Peripheral instance base addresses */ 6340 /** Peripheral SCT0 base address */ 6341 #define SCT0_BASE (0x50004000u) 6342 /** Peripheral SCT0 base pointer */ 6343 #define SCT0 ((SCT_Type *)SCT0_BASE) 6344 /** Array initializer of SCT peripheral base addresses */ 6345 #define SCT_BASE_ADDRS { SCT0_BASE } 6346 /** Array initializer of SCT peripheral base pointers */ 6347 #define SCT_BASE_PTRS { SCT0 } 6348 /** Interrupt vectors for the SCT peripheral type */ 6349 #define SCT_IRQS { SCT0_IRQn } 6350 6351 /*! 6352 * @} 6353 */ /* end of group SCT_Peripheral_Access_Layer */ 6354 6355 6356 /* ---------------------------------------------------------------------------- 6357 -- SPI Peripheral Access Layer 6358 ---------------------------------------------------------------------------- */ 6359 6360 /*! 6361 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 6362 * @{ 6363 */ 6364 6365 /** SPI - Register Layout Typedef */ 6366 typedef struct { 6367 __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x0 */ 6368 __IO uint32_t DLY; /**< SPI Delay register, offset: 0x4 */ 6369 __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position, offset: 0x8 */ 6370 __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ 6371 __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x10 */ 6372 __I uint32_t RXDAT; /**< SPI Receive Data, offset: 0x14 */ 6373 __IO uint32_t TXDATCTL; /**< SPI Transmit Data with Control, offset: 0x18 */ 6374 __IO uint32_t TXDAT; /**< SPI Transmit Data., offset: 0x1C */ 6375 __IO uint32_t TXCTL; /**< SPI Transmit Control, offset: 0x20 */ 6376 __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x24 */ 6377 __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x28 */ 6378 } SPI_Type; 6379 6380 /* ---------------------------------------------------------------------------- 6381 -- SPI Register Masks 6382 ---------------------------------------------------------------------------- */ 6383 6384 /*! 6385 * @addtogroup SPI_Register_Masks SPI Register Masks 6386 * @{ 6387 */ 6388 6389 /*! @name CFG - SPI Configuration register */ 6390 /*! @{ */ 6391 #define SPI_CFG_ENABLE_MASK (0x1U) 6392 #define SPI_CFG_ENABLE_SHIFT (0U) 6393 /*! ENABLE - SPI enable. 6394 * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. 6395 * 0b1..Enabled. The SPI is enabled for operation. 6396 */ 6397 #define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) 6398 #define SPI_CFG_MASTER_MASK (0x4U) 6399 #define SPI_CFG_MASTER_SHIFT (2U) 6400 /*! MASTER - Master mode select. 6401 * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. 6402 * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. 6403 */ 6404 #define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) 6405 #define SPI_CFG_LSBF_MASK (0x8U) 6406 #define SPI_CFG_LSBF_SHIFT (3U) 6407 /*! LSBF - LSB First mode enable. 6408 * 0b0..Standard. Data is transmitted and received in standard MSB first order. 6409 * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). 6410 */ 6411 #define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) 6412 #define SPI_CFG_CPHA_MASK (0x10U) 6413 #define SPI_CFG_CPHA_SHIFT (4U) 6414 /*! CPHA - Clock Phase select. 6415 * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock 6416 * changes away from the rest state). Data is changed on the following edge. 6417 * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock 6418 * changes away from the rest state). Data is captured on the following edge. 6419 */ 6420 #define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) 6421 #define SPI_CFG_CPOL_MASK (0x20U) 6422 #define SPI_CFG_CPOL_SHIFT (5U) 6423 /*! CPOL - Clock Polarity select. 6424 * 0b0..Low. The rest state of the clock (between transfers) is low. 6425 * 0b1..High. The rest state of the clock (between transfers) is high. 6426 */ 6427 #define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) 6428 #define SPI_CFG_LOOP_MASK (0x80U) 6429 #define SPI_CFG_LOOP_SHIFT (7U) 6430 /*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit 6431 * and receive data connected together to allow simple software testing. 6432 * 0b0..Disabled. 6433 * 0b1..Enabled. 6434 */ 6435 #define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) 6436 #define SPI_CFG_SPOL0_MASK (0x100U) 6437 #define SPI_CFG_SPOL0_SHIFT (8U) 6438 /*! SPOL0 - SSEL0 Polarity select. 6439 * 0b0..Low. The SSEL0 pin is active low. 6440 * 0b1..High. The SSEL0 pin is active high. 6441 */ 6442 #define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) 6443 #define SPI_CFG_SPOL1_MASK (0x200U) 6444 #define SPI_CFG_SPOL1_SHIFT (9U) 6445 /*! SPOL1 - SSEL1 Polarity select. 6446 * 0b0..Low. The SSEL1 pin is active low. 6447 * 0b1..High. The SSEL1 pin is active high. 6448 */ 6449 #define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) 6450 #define SPI_CFG_SPOL2_MASK (0x400U) 6451 #define SPI_CFG_SPOL2_SHIFT (10U) 6452 /*! SPOL2 - SSEL2 Polarity select. 6453 * 0b0..Low. The SSEL2 pin is active low. 6454 * 0b1..High. The SSEL2 pin is active high. 6455 */ 6456 #define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) 6457 #define SPI_CFG_SPOL3_MASK (0x800U) 6458 #define SPI_CFG_SPOL3_SHIFT (11U) 6459 /*! SPOL3 - SSEL3 Polarity select. 6460 * 0b0..Low. The SSEL3 pin is active low. 6461 * 0b1..High. The SSEL3 pin is active high. 6462 */ 6463 #define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) 6464 /*! @} */ 6465 6466 /*! @name DLY - SPI Delay register */ 6467 /*! @{ */ 6468 #define SPI_DLY_PRE_DELAY_MASK (0xFU) 6469 #define SPI_DLY_PRE_DELAY_SHIFT (0U) 6470 /*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data 6471 * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This 6472 * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI 6473 * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are 6474 * inserted. 6475 */ 6476 #define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) 6477 #define SPI_DLY_POST_DELAY_MASK (0xF0U) 6478 #define SPI_DLY_POST_DELAY_SHIFT (4U) 6479 /*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL 6480 * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock 6481 * times are inserted. 0xF = 15 SPI clock times are inserted. 6482 */ 6483 #define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) 6484 #define SPI_DLY_FRAME_DELAY_MASK (0xF00U) 6485 #define SPI_DLY_FRAME_DELAY_SHIFT (8U) 6486 /*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current 6487 * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 6488 * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock 6489 * times are inserted. 6490 */ 6491 #define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) 6492 #define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) 6493 #define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) 6494 /*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between 6495 * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 6496 * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that 6497 * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 6498 * SPI clock times. 6499 */ 6500 #define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) 6501 /*! @} */ 6502 6503 /*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position */ 6504 /*! @{ */ 6505 #define SPI_STAT_RXRDY_MASK (0x1U) 6506 #define SPI_STAT_RXRDY_SHIFT (0U) 6507 /*! RXRDY - Receiver Ready flag. When 1, indicates that data is available to be read from the 6508 * receiver buffer. Cleared after a read of the RXDAT register. 6509 */ 6510 #define SPI_STAT_RXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_RXRDY_SHIFT)) & SPI_STAT_RXRDY_MASK) 6511 #define SPI_STAT_TXRDY_MASK (0x2U) 6512 #define SPI_STAT_TXRDY_SHIFT (1U) 6513 /*! TXRDY - Transmitter Ready flag. When 1, this bit indicates that data may be written to the 6514 * transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data 6515 * is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register. 6516 */ 6517 #define SPI_STAT_TXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_TXRDY_SHIFT)) & SPI_STAT_TXRDY_MASK) 6518 #define SPI_STAT_RXOV_MASK (0x4U) 6519 #define SPI_STAT_RXOV_SHIFT (2U) 6520 /*! RXOV - Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This 6521 * flag is set when the beginning of a received character is detected while the receiver buffer 6522 * is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming 6523 * data is lost. Data received by the SPI should be considered undefined if RxOv is set. 6524 */ 6525 #define SPI_STAT_RXOV(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_RXOV_SHIFT)) & SPI_STAT_RXOV_MASK) 6526 #define SPI_STAT_TXUR_MASK (0x8U) 6527 #define SPI_STAT_TXUR_SHIFT (3U) 6528 /*! TXUR - Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). 6529 * In this case, the transmitter must begin sending new data on the next input clock if the 6530 * transmitter is idle. If that data is not available in the transmitter holding register at that 6531 * point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be 6532 * considered undefined if TXUR is set. 6533 */ 6534 #define SPI_STAT_TXUR(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_TXUR_SHIFT)) & SPI_STAT_TXUR_MASK) 6535 #define SPI_STAT_SSA_MASK (0x10U) 6536 #define SPI_STAT_SSA_SHIFT (4U) 6537 /*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from 6538 * deasserted to asserted, in both master and slave modes. This allows determining when the SPI 6539 * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a 6540 * slave mode access begins. This flag is cleared by software. 6541 */ 6542 #define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) 6543 #define SPI_STAT_SSD_MASK (0x20U) 6544 #define SPI_STAT_SSD_SHIFT (5U) 6545 /*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to 6546 * deasserted, in both master and slave modes. This allows determining when the SPI 6547 * transmit/receive functions become idle. This flag is cleared by software. 6548 */ 6549 #define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) 6550 #define SPI_STAT_STALLED_MASK (0x40U) 6551 #define SPI_STAT_STALLED_SHIFT (6U) 6552 /*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. 6553 */ 6554 #define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) 6555 #define SPI_STAT_ENDTRANSFER_MASK (0x80U) 6556 #define SPI_STAT_ENDTRANSFER_SHIFT (7U) 6557 /*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current 6558 * transfer when the transmitter finishes any activity already in progress, as if the EOT flag 6559 * had been set prior to the last transmission. This capability is included to support cases where 6560 * it is not known when transmit data is written that it will be the end of a transfer. The bit 6561 * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end 6562 * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. 6563 */ 6564 #define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) 6565 #define SPI_STAT_MSTIDLE_MASK (0x100U) 6566 #define SPI_STAT_MSTIDLE_SHIFT (8U) 6567 /*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. 6568 * This means that the transmit holding register is empty and the transmitter is not in the 6569 * process of sending data. 6570 */ 6571 #define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) 6572 /*! @} */ 6573 6574 /*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ 6575 /*! @{ */ 6576 #define SPI_INTENSET_RXRDYEN_MASK (0x1U) 6577 #define SPI_INTENSET_RXRDYEN_SHIFT (0U) 6578 /*! RXRDYEN - Determines whether an interrupt occurs when receiver data is available. 6579 * 0b0..No interrupt will be generated when receiver data is available. 6580 * 0b1..An interrupt will be generated when receiver data is available in the RXDAT register. 6581 */ 6582 #define SPI_INTENSET_RXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_RXRDYEN_SHIFT)) & SPI_INTENSET_RXRDYEN_MASK) 6583 #define SPI_INTENSET_TXRDYEN_MASK (0x2U) 6584 #define SPI_INTENSET_TXRDYEN_SHIFT (1U) 6585 /*! TXRDYEN - Determines whether an interrupt occurs when the transmitter holding register is available. 6586 * 0b0..No interrupt will be generated when the transmitter holding register is available. 6587 * 0b1..An interrupt will be generated when data may be written to TXDAT. 6588 */ 6589 #define SPI_INTENSET_TXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_TXRDYEN_SHIFT)) & SPI_INTENSET_TXRDYEN_MASK) 6590 #define SPI_INTENSET_RXOVEN_MASK (0x4U) 6591 #define SPI_INTENSET_RXOVEN_SHIFT (2U) 6592 /*! RXOVEN - Determines whether an interrupt occurs when a receiver overrun occurs. This happens in 6593 * slave mode when there is a need for the receiver to move newly received data to the RXDAT 6594 * register when it is already in use. The interface prevents receiver overrun in Master mode by not 6595 * allowing a new transmission to begin when a receiver overrun would otherwise occur. 6596 * 0b0..No interrupt will be generated when a receiver overrun occurs. 6597 * 0b1..An interrupt will be generated if a receiver overrun occurs. 6598 */ 6599 #define SPI_INTENSET_RXOVEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_RXOVEN_SHIFT)) & SPI_INTENSET_RXOVEN_MASK) 6600 #define SPI_INTENSET_TXUREN_MASK (0x8U) 6601 #define SPI_INTENSET_TXUREN_SHIFT (3U) 6602 /*! TXUREN - Determines whether an interrupt occurs when a transmitter underrun occurs. This happens 6603 * in slave mode when there is a need to transmit data when none is available. 6604 * 0b0..No interrupt will be generated when the transmitter underruns. 6605 * 0b1..An interrupt will be generated if the transmitter underruns. 6606 */ 6607 #define SPI_INTENSET_TXUREN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_TXUREN_SHIFT)) & SPI_INTENSET_TXUREN_MASK) 6608 #define SPI_INTENSET_SSAEN_MASK (0x10U) 6609 #define SPI_INTENSET_SSAEN_SHIFT (4U) 6610 /*! SSAEN - Determines whether an interrupt occurs when the Slave Select is asserted. 6611 * 0b0..No interrupt will be generated when any Slave Select transitions from deasserted to asserted. 6612 * 0b1..An interrupt will be generated when any Slave Select transitions from deasserted to asserted. 6613 */ 6614 #define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) 6615 #define SPI_INTENSET_SSDEN_MASK (0x20U) 6616 #define SPI_INTENSET_SSDEN_SHIFT (5U) 6617 /*! SSDEN - Determines whether an interrupt occurs when the Slave Select is deasserted. 6618 * 0b0..No interrupt will be generated when all asserted Slave Selects transition to deasserted. 6619 * 0b1..An interrupt will be generated when all asserted Slave Selects transition to deasserted. 6620 */ 6621 #define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) 6622 /*! @} */ 6623 6624 /*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ 6625 /*! @{ */ 6626 #define SPI_INTENCLR_RXRDYEN_MASK (0x1U) 6627 #define SPI_INTENCLR_RXRDYEN_SHIFT (0U) 6628 /*! RXRDYEN - Writing 1 clears the corresponding bits in the INTENSET register. 6629 */ 6630 #define SPI_INTENCLR_RXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_RXRDYEN_SHIFT)) & SPI_INTENCLR_RXRDYEN_MASK) 6631 #define SPI_INTENCLR_TXRDYEN_MASK (0x2U) 6632 #define SPI_INTENCLR_TXRDYEN_SHIFT (1U) 6633 /*! TXRDYEN - Writing 1 clears the corresponding bits in the INTENSET register. 6634 */ 6635 #define SPI_INTENCLR_TXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_TXRDYEN_SHIFT)) & SPI_INTENCLR_TXRDYEN_MASK) 6636 #define SPI_INTENCLR_RXOVEN_MASK (0x4U) 6637 #define SPI_INTENCLR_RXOVEN_SHIFT (2U) 6638 /*! RXOVEN - Writing 1 clears the corresponding bits in the INTENSET register. 6639 */ 6640 #define SPI_INTENCLR_RXOVEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_RXOVEN_SHIFT)) & SPI_INTENCLR_RXOVEN_MASK) 6641 #define SPI_INTENCLR_TXUREN_MASK (0x8U) 6642 #define SPI_INTENCLR_TXUREN_SHIFT (3U) 6643 /*! TXUREN - Writing 1 clears the corresponding bits in the INTENSET register. 6644 */ 6645 #define SPI_INTENCLR_TXUREN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_TXUREN_SHIFT)) & SPI_INTENCLR_TXUREN_MASK) 6646 #define SPI_INTENCLR_SSAEN_MASK (0x10U) 6647 #define SPI_INTENCLR_SSAEN_SHIFT (4U) 6648 /*! SSAEN - Writing 1 clears the corresponding bits in the INTENSET register. 6649 */ 6650 #define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) 6651 #define SPI_INTENCLR_SSDEN_MASK (0x20U) 6652 #define SPI_INTENCLR_SSDEN_SHIFT (5U) 6653 /*! SSDEN - Writing 1 clears the corresponding bits in the INTENSET register. 6654 */ 6655 #define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) 6656 /*! @} */ 6657 6658 /*! @name RXDAT - SPI Receive Data */ 6659 /*! @{ */ 6660 #define SPI_RXDAT_RXDAT_MASK (0xFFFFU) 6661 #define SPI_RXDAT_RXDAT_SHIFT (0U) 6662 /*! RXDAT - Receiver Data. This contains the next piece of received data. The number of bits that 6663 * are used depends on the LEN setting in TXCTL / TXDATCTL. 6664 */ 6665 #define SPI_RXDAT_RXDAT(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXDAT_SHIFT)) & SPI_RXDAT_RXDAT_MASK) 6666 #define SPI_RXDAT_RXSSEL0_N_MASK (0x10000U) 6667 #define SPI_RXDAT_RXSSEL0_N_SHIFT (16U) 6668 /*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved 6669 * along with received data. The value will reflect the SSEL0 pin for both master and slave 6670 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 6671 * pin is configured by the related SPOL bit in CFG. 6672 */ 6673 #define SPI_RXDAT_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL0_N_SHIFT)) & SPI_RXDAT_RXSSEL0_N_MASK) 6674 #define SPI_RXDAT_RXSSEL1_N_MASK (0x20000U) 6675 #define SPI_RXDAT_RXSSEL1_N_SHIFT (17U) 6676 /*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved 6677 * along with received data. The value will reflect the SSEL1 pin for both master and slave 6678 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 6679 * pin is configured by the related SPOL bit in CFG. 6680 */ 6681 #define SPI_RXDAT_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL1_N_SHIFT)) & SPI_RXDAT_RXSSEL1_N_MASK) 6682 #define SPI_RXDAT_RXSSEL2_N_MASK (0x40000U) 6683 #define SPI_RXDAT_RXSSEL2_N_SHIFT (18U) 6684 /*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved 6685 * along with received data. The value will reflect the SSEL2 pin for both master and slave 6686 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 6687 * pin is configured by the related SPOL bit in CFG. 6688 */ 6689 #define SPI_RXDAT_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL2_N_SHIFT)) & SPI_RXDAT_RXSSEL2_N_MASK) 6690 #define SPI_RXDAT_RXSSEL3_N_MASK (0x80000U) 6691 #define SPI_RXDAT_RXSSEL3_N_SHIFT (19U) 6692 /*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved 6693 * along with received data. The value will reflect the SSEL3 pin for both master and slave 6694 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 6695 * pin is configured by the related SPOL bit in CFG. 6696 */ 6697 #define SPI_RXDAT_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL3_N_SHIFT)) & SPI_RXDAT_RXSSEL3_N_MASK) 6698 #define SPI_RXDAT_SOT_MASK (0x100000U) 6699 #define SPI_RXDAT_SOT_SHIFT (20U) 6700 /*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went 6701 * from deasserted to asserted (i.e., any previous transfer has ended). This information can be 6702 * used to identify the first piece of data in cases where the transfer length is greater than 16 6703 * bit. 6704 */ 6705 #define SPI_RXDAT_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_SOT_SHIFT)) & SPI_RXDAT_SOT_MASK) 6706 /*! @} */ 6707 6708 /*! @name TXDATCTL - SPI Transmit Data with Control */ 6709 /*! @{ */ 6710 #define SPI_TXDATCTL_TXDAT_MASK (0xFFFFU) 6711 #define SPI_TXDATCTL_TXDAT_SHIFT (0U) 6712 /*! TXDAT - Transmit Data. This field provides from 1 to 16 bits of data to be transmitted. 6713 */ 6714 #define SPI_TXDATCTL_TXDAT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXDAT_SHIFT)) & SPI_TXDATCTL_TXDAT_MASK) 6715 #define SPI_TXDATCTL_TXSSEL0_N_MASK (0x10000U) 6716 #define SPI_TXDATCTL_TXSSEL0_N_SHIFT (16U) 6717 /*! TXSSEL0_N - Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the 6718 * pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in 6719 * the CFG register. 6720 * 0b0..SSEL0 asserted. 6721 * 0b1..SSEL0 not asserted. 6722 */ 6723 #define SPI_TXDATCTL_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXSSEL0_N_SHIFT)) & SPI_TXDATCTL_TXSSEL0_N_MASK) 6724 #define SPI_TXDATCTL_TXSSEL1_N_MASK (0x20000U) 6725 #define SPI_TXDATCTL_TXSSEL1_N_SHIFT (17U) 6726 /*! TXSSEL1_N - Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the 6727 * pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in 6728 * the CFG register. 6729 * 0b0..SSEL1 asserted. 6730 * 0b1..SSEL1 not asserted. 6731 */ 6732 #define SPI_TXDATCTL_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXSSEL1_N_SHIFT)) & SPI_TXDATCTL_TXSSEL1_N_MASK) 6733 #define SPI_TXDATCTL_TXSSEL2_N_MASK (0x40000U) 6734 #define SPI_TXDATCTL_TXSSEL2_N_SHIFT (18U) 6735 /*! TXSSEL2_N - Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the 6736 * pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in 6737 * the CFG register. 6738 * 0b0..SSEL2 asserted. 6739 * 0b1..SSEL2 not asserted. 6740 */ 6741 #define SPI_TXDATCTL_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXSSEL2_N_SHIFT)) & SPI_TXDATCTL_TXSSEL2_N_MASK) 6742 #define SPI_TXDATCTL_TXSSEL3_N_MASK (0x80000U) 6743 #define SPI_TXDATCTL_TXSSEL3_N_SHIFT (19U) 6744 /*! TXSSEL3_N - Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the 6745 * pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in 6746 * the CFG register. 6747 * 0b0..SSEL3 asserted. 6748 * 0b1..SSEL3 not asserted. 6749 */ 6750 #define SPI_TXDATCTL_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXSSEL3_N_SHIFT)) & SPI_TXDATCTL_TXSSEL3_N_MASK) 6751 #define SPI_TXDATCTL_EOT_MASK (0x100000U) 6752 #define SPI_TXDATCTL_EOT_SHIFT (20U) 6753 /*! EOT - End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain 6754 * so for at least the time specified by the Transfer_delay value in the DLY register. 6755 * 0b0..This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. 6756 * 0b1..This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. 6757 */ 6758 #define SPI_TXDATCTL_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_EOT_SHIFT)) & SPI_TXDATCTL_EOT_MASK) 6759 #define SPI_TXDATCTL_EOF_MASK (0x200000U) 6760 #define SPI_TXDATCTL_EOF_SHIFT (21U) 6761 /*! EOF - End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value 6762 * in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY 6763 * value = 0. This control can be used as part of the support for frame lengths greater than 16 6764 * bits. 6765 * 0b0..This piece of data transmitted is not treated as the end of a frame. 6766 * 0b1..This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted. 6767 */ 6768 #define SPI_TXDATCTL_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_EOF_SHIFT)) & SPI_TXDATCTL_EOF_MASK) 6769 #define SPI_TXDATCTL_RXIGNORE_MASK (0x400000U) 6770 #define SPI_TXDATCTL_RXIGNORE_SHIFT (22U) 6771 /*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to 6772 * read unneeded data from the receiver.Setting this bit simplifies the transmit process and can 6773 * be used with the DMA. 6774 * 0b0..Received data must be read in order to allow transmission to progress. In slave mode, an overrun error 6775 * will occur if received data is not read before new data is received. 6776 * 0b1..Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. 6777 */ 6778 #define SPI_TXDATCTL_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_RXIGNORE_SHIFT)) & SPI_TXDATCTL_RXIGNORE_MASK) 6779 #define SPI_TXDATCTL_LEN_MASK (0xF000000U) 6780 #define SPI_TXDATCTL_LEN_SHIFT (24U) 6781 /*! LEN - Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths 6782 * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data 6783 * transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits 6784 * in length. ... 0xF = Data transfer is 16 bits in length. 6785 * 0b0000.. 6786 * 0b0001..Data transfer is 1 bit in length. 6787 * 0b0010..Data transfer is 2 bit in length. 6788 * 0b0011..Data transfer is 3 bit in length. 6789 * 0b0100..Data transfer is 4 bit in length. 6790 * 0b0101..Data transfer is 5 bit in length. 6791 * 0b0110..Data transfer is 6 bit in length. 6792 * 0b0111..Data transfer is 7 bit in length. 6793 * 0b1000..Data transfer is 8 bit in length. 6794 * 0b1001..Data transfer is 9 bit in length. 6795 * 0b1010..Data transfer is 10 bit in length. 6796 * 0b1011..Data transfer is 11 bit in length. 6797 * 0b1100..Data transfer is 12 bit in length. 6798 * 0b1101..Data transfer is 13 bit in length. 6799 * 0b1110..Data transfer is 14 bit in length. 6800 * 0b1111..Data transfer is 15 bit in length. 6801 */ 6802 #define SPI_TXDATCTL_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_LEN_SHIFT)) & SPI_TXDATCTL_LEN_MASK) 6803 /*! @} */ 6804 6805 /*! @name TXDAT - SPI Transmit Data. */ 6806 /*! @{ */ 6807 #define SPI_TXDAT_DATA_MASK (0xFFFFU) 6808 #define SPI_TXDAT_DATA_SHIFT (0U) 6809 /*! DATA - Transmit Data. This field provides from 4 to 16 bits of data to be transmitted. 6810 */ 6811 #define SPI_TXDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDAT_DATA_SHIFT)) & SPI_TXDAT_DATA_MASK) 6812 /*! @} */ 6813 6814 /*! @name TXCTL - SPI Transmit Control */ 6815 /*! @{ */ 6816 #define SPI_TXCTL_TXSSEL0_N_MASK (0x10000U) 6817 #define SPI_TXCTL_TXSSEL0_N_SHIFT (16U) 6818 /*! TXSSEL0_N - Transmit Slave Select 0. 6819 */ 6820 #define SPI_TXCTL_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_TXSSEL0_N_SHIFT)) & SPI_TXCTL_TXSSEL0_N_MASK) 6821 #define SPI_TXCTL_TXSSEL1_N_MASK (0x20000U) 6822 #define SPI_TXCTL_TXSSEL1_N_SHIFT (17U) 6823 /*! TXSSEL1_N - Transmit Slave Select 1. 6824 */ 6825 #define SPI_TXCTL_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_TXSSEL1_N_SHIFT)) & SPI_TXCTL_TXSSEL1_N_MASK) 6826 #define SPI_TXCTL_TXSSEL2_N_MASK (0x40000U) 6827 #define SPI_TXCTL_TXSSEL2_N_SHIFT (18U) 6828 /*! TXSSEL2_N - Transmit Slave Select 2. 6829 */ 6830 #define SPI_TXCTL_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_TXSSEL2_N_SHIFT)) & SPI_TXCTL_TXSSEL2_N_MASK) 6831 #define SPI_TXCTL_TXSSEL3_N_MASK (0x80000U) 6832 #define SPI_TXCTL_TXSSEL3_N_SHIFT (19U) 6833 /*! TXSSEL3_N - Transmit Slave Select 3. 6834 */ 6835 #define SPI_TXCTL_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_TXSSEL3_N_SHIFT)) & SPI_TXCTL_TXSSEL3_N_MASK) 6836 #define SPI_TXCTL_EOT_MASK (0x100000U) 6837 #define SPI_TXCTL_EOT_SHIFT (20U) 6838 /*! EOT - End of Transfer. 6839 */ 6840 #define SPI_TXCTL_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_EOT_SHIFT)) & SPI_TXCTL_EOT_MASK) 6841 #define SPI_TXCTL_EOF_MASK (0x200000U) 6842 #define SPI_TXCTL_EOF_SHIFT (21U) 6843 /*! EOF - End of Frame. 6844 */ 6845 #define SPI_TXCTL_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_EOF_SHIFT)) & SPI_TXCTL_EOF_MASK) 6846 #define SPI_TXCTL_RXIGNORE_MASK (0x400000U) 6847 #define SPI_TXCTL_RXIGNORE_SHIFT (22U) 6848 /*! RXIGNORE - Receive Ignore. 6849 */ 6850 #define SPI_TXCTL_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_RXIGNORE_SHIFT)) & SPI_TXCTL_RXIGNORE_MASK) 6851 #define SPI_TXCTL_LEN_MASK (0xF000000U) 6852 #define SPI_TXCTL_LEN_SHIFT (24U) 6853 /*! LEN - Data transfer Length. 6854 */ 6855 #define SPI_TXCTL_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_LEN_SHIFT)) & SPI_TXCTL_LEN_MASK) 6856 /*! @} */ 6857 6858 /*! @name DIV - SPI clock Divider */ 6859 /*! @{ */ 6860 #define SPI_DIV_DIVVAL_MASK (0xFFFFU) 6861 #define SPI_DIV_DIVVAL_SHIFT (0U) 6862 /*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the 6863 * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, 6864 * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results 6865 * in FCLK/65536. 6866 */ 6867 #define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) 6868 /*! @} */ 6869 6870 /*! @name INTSTAT - SPI Interrupt Status */ 6871 /*! @{ */ 6872 #define SPI_INTSTAT_RXRDY_MASK (0x1U) 6873 #define SPI_INTSTAT_RXRDY_SHIFT (0U) 6874 /*! RXRDY - Receiver Ready flag. 6875 */ 6876 #define SPI_INTSTAT_RXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_RXRDY_SHIFT)) & SPI_INTSTAT_RXRDY_MASK) 6877 #define SPI_INTSTAT_TXRDY_MASK (0x2U) 6878 #define SPI_INTSTAT_TXRDY_SHIFT (1U) 6879 /*! TXRDY - Transmitter Ready flag. 6880 */ 6881 #define SPI_INTSTAT_TXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_TXRDY_SHIFT)) & SPI_INTSTAT_TXRDY_MASK) 6882 #define SPI_INTSTAT_RXOV_MASK (0x4U) 6883 #define SPI_INTSTAT_RXOV_SHIFT (2U) 6884 /*! RXOV - Receiver Overrun interrupt flag. 6885 */ 6886 #define SPI_INTSTAT_RXOV(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_RXOV_SHIFT)) & SPI_INTSTAT_RXOV_MASK) 6887 #define SPI_INTSTAT_TXUR_MASK (0x8U) 6888 #define SPI_INTSTAT_TXUR_SHIFT (3U) 6889 /*! TXUR - Transmitter Underrun interrupt flag. 6890 */ 6891 #define SPI_INTSTAT_TXUR(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_TXUR_SHIFT)) & SPI_INTSTAT_TXUR_MASK) 6892 #define SPI_INTSTAT_SSA_MASK (0x10U) 6893 #define SPI_INTSTAT_SSA_SHIFT (4U) 6894 /*! SSA - Slave Select Assert. 6895 */ 6896 #define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) 6897 #define SPI_INTSTAT_SSD_MASK (0x20U) 6898 #define SPI_INTSTAT_SSD_SHIFT (5U) 6899 /*! SSD - Slave Select Deassert. 6900 */ 6901 #define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) 6902 #define SPI_INTSTAT_MSTIDLE_MASK (0x100U) 6903 #define SPI_INTSTAT_MSTIDLE_SHIFT (8U) 6904 /*! MSTIDLE - Master Idle status flag. 6905 */ 6906 #define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) 6907 /*! @} */ 6908 6909 6910 /*! 6911 * @} 6912 */ /* end of group SPI_Register_Masks */ 6913 6914 6915 /* SPI - Peripheral instance base addresses */ 6916 /** Peripheral SPI0 base address */ 6917 #define SPI0_BASE (0x40058000u) 6918 /** Peripheral SPI0 base pointer */ 6919 #define SPI0 ((SPI_Type *)SPI0_BASE) 6920 /** Peripheral SPI1 base address */ 6921 #define SPI1_BASE (0x4005C000u) 6922 /** Peripheral SPI1 base pointer */ 6923 #define SPI1 ((SPI_Type *)SPI1_BASE) 6924 /** Array initializer of SPI peripheral base addresses */ 6925 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } 6926 /** Array initializer of SPI peripheral base pointers */ 6927 #define SPI_BASE_PTRS { SPI0, SPI1 } 6928 /** Interrupt vectors for the SPI peripheral type */ 6929 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } 6930 6931 /*! 6932 * @} 6933 */ /* end of group SPI_Peripheral_Access_Layer */ 6934 6935 6936 /* ---------------------------------------------------------------------------- 6937 -- SWM Peripheral Access Layer 6938 ---------------------------------------------------------------------------- */ 6939 6940 /*! 6941 * @addtogroup SWM_Peripheral_Access_Layer SWM Peripheral Access Layer 6942 * @{ 6943 */ 6944 6945 /** SWM - Register Layout Typedef */ 6946 typedef struct { 6947 union { /* offset: 0x0 */ 6948 struct { /* offset: 0x0 */ 6949 __IO uint32_t PINASSIGN0; /**< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS., offset: 0x0 */ 6950 __IO uint32_t PINASSIGN1; /**< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_RTS., offset: 0x4 */ 6951 __IO uint32_t PINASSIGN2; /**< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK, U2_TXD, U2_RXD., offset: 0x8 */ 6952 __IO uint32_t PINASSIGN3; /**< Pin assign register 3. Assign movable function U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK., offset: 0xC */ 6953 __IO uint32_t PINASSIGN4; /**< Pin assign register 4. Assign movable functions SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1., offset: 0x10 */ 6954 __IO uint32_t PINASSIGN5; /**< Pin assign register 5. Assign movable functions SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI, offset: 0x14 */ 6955 __IO uint32_t PINASSIGN6; /**< Pin assign register 6. Assign movable functions SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0., offset: 0x18 */ 6956 __IO uint32_t PINASSIGN7; /**< Pin assign register 7. Assign movable functions SCT_IN1, SCT_IN2, SCT_IN3, SCT_OUT0., offset: 0x1C */ 6957 __IO uint32_t PINASSIGN8; /**< Pin assign register 8. Assign movable functions SCT_OUT1, SCT_OUT2, SCT_OUT3, SCT_OUT4., offset: 0x20 */ 6958 __IO uint32_t PINASSIGN9; /**< Pin assign register 9. Assign movable functions SCT_OUT5, SCT_OUT6, I2C1_SDA, I2C1_SCL., offset: 0x24 */ 6959 __IO uint32_t PINASSIGN10; /**< Pin assign register 10. Assign movable functions I2C2_SDA, I2C2_SCL, I2C3_SDA, I2C3_SCL., offset: 0x28 */ 6960 __IO uint32_t PINASSIGN11; /**< Pin assign register 11. Assign movable functions COMP0_OUT, CLKOUT, GPIOINT_BMATCH, UART3_TXD, offset: 0x2C */ 6961 __IO uint32_t PINASSIGN12; /**< Pin assign register 12. Assign movable functions UART3_RXD, UART3_SCLK, UART4_TXD, UART4_RXD., offset: 0x30 */ 6962 __IO uint32_t PINASSIGN13; /**< Pin assign register 13. Assign movable functions UART4_SCLK, T0_MAT0, T0_MAT1, T0_MAT2., offset: 0x34 */ 6963 __IO uint32_t PINASSIGN14; /**< Pin assign register 14. Assign movable functions T0_MAT3, T0_CAP0, T0_CAP1, T0_CAP2., offset: 0x38 */ 6964 } PINASSIGN; 6965 __IO uint32_t PINASSIGN_DATA[15]; /**< Pin assign register, array offset: 0x0, array step: 0x4 */ 6966 }; 6967 uint8_t RESERVED_0[388]; 6968 __IO uint32_t PINENABLE0; /**< Pin enable register 0. Enables fixed-pin functions ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, VDDCMP and so on., offset: 0x1C0 */ 6969 __IO uint32_t PINENABLE1; /**< Pin enable register 1. Enables fixed-pin functions CAPT_X4, CAPT_X5, CAPT_X6, CAPT_X7, CAPT_X8, CAPT_X4, CAPT_YL and CAPT_YH., offset: 0x1C4 */ 6970 } SWM_Type; 6971 6972 /* ---------------------------------------------------------------------------- 6973 -- SWM Register Masks 6974 ---------------------------------------------------------------------------- */ 6975 6976 /*! 6977 * @addtogroup SWM_Register_Masks SWM Register Masks 6978 * @{ 6979 */ 6980 6981 /*! @name PINASSIGN0 - Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS. */ 6982 /*! @{ */ 6983 #define SWM_PINASSIGN0_U0_TXD_O_MASK (0xFFU) 6984 #define SWM_PINASSIGN0_U0_TXD_O_SHIFT (0U) 6985 /*! U0_TXD_O - U0_TXD function assignment. The value is the pin number to be assigned to this 6986 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 6987 * to PIO1_21(=0x35) . 6988 */ 6989 #define SWM_PINASSIGN0_U0_TXD_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_TXD_O_SHIFT)) & SWM_PINASSIGN0_U0_TXD_O_MASK) 6990 #define SWM_PINASSIGN0_U0_RXD_I_MASK (0xFF00U) 6991 #define SWM_PINASSIGN0_U0_RXD_I_SHIFT (8U) 6992 /*! U0_RXD_I - U0_RXD function assignment. The value is the pin number to be assigned to this 6993 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 6994 * to PIO1_21(=0x35). 6995 */ 6996 #define SWM_PINASSIGN0_U0_RXD_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_RXD_I_SHIFT)) & SWM_PINASSIGN0_U0_RXD_I_MASK) 6997 #define SWM_PINASSIGN0_U0_RTS_O_MASK (0xFF0000U) 6998 #define SWM_PINASSIGN0_U0_RTS_O_SHIFT (16U) 6999 /*! U0_RTS_O - U0_RTS function assignment. The value is the pin number to be assigned to this 7000 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7001 * to PIO1_21(=0x35). 7002 */ 7003 #define SWM_PINASSIGN0_U0_RTS_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_RTS_O_SHIFT)) & SWM_PINASSIGN0_U0_RTS_O_MASK) 7004 #define SWM_PINASSIGN0_U0_CTS_I_MASK (0xFF000000U) 7005 #define SWM_PINASSIGN0_U0_CTS_I_SHIFT (24U) 7006 /*! U0_CTS_I - U0_CTS function assignment. The value is the pin number to be assigned to this 7007 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7008 * to PIO1_21(=0x35). 7009 */ 7010 #define SWM_PINASSIGN0_U0_CTS_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_CTS_I_SHIFT)) & SWM_PINASSIGN0_U0_CTS_I_MASK) 7011 /*! @} */ 7012 7013 /*! @name PINASSIGN1 - Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_RTS. */ 7014 /*! @{ */ 7015 #define SWM_PINASSIGN1_U0_SCLK_IO_MASK (0xFFU) 7016 #define SWM_PINASSIGN1_U0_SCLK_IO_SHIFT (0U) 7017 /*! U0_SCLK_IO - U0_SCLK function assignment. The value is the pin number to be assigned to this 7018 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7019 * (=0x20) to PIO1_21(=0x35). 7020 */ 7021 #define SWM_PINASSIGN1_U0_SCLK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U0_SCLK_IO_SHIFT)) & SWM_PINASSIGN1_U0_SCLK_IO_MASK) 7022 #define SWM_PINASSIGN1_U1_TXD_O_MASK (0xFF00U) 7023 #define SWM_PINASSIGN1_U1_TXD_O_SHIFT (8U) 7024 /*! U1_TXD_O - U1_TXD function assignment. The value is the pin number to be assigned to this 7025 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7026 * to PIO1_21(=0x35). 7027 */ 7028 #define SWM_PINASSIGN1_U1_TXD_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U1_TXD_O_SHIFT)) & SWM_PINASSIGN1_U1_TXD_O_MASK) 7029 #define SWM_PINASSIGN1_U1_RXD_I_MASK (0xFF0000U) 7030 #define SWM_PINASSIGN1_U1_RXD_I_SHIFT (16U) 7031 /*! U1_RXD_I - U1_RXD function assignment. The value is the pin number to be assigned to this 7032 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7033 * to PIO1_21(=0x35). 7034 */ 7035 #define SWM_PINASSIGN1_U1_RXD_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U1_RXD_I_SHIFT)) & SWM_PINASSIGN1_U1_RXD_I_MASK) 7036 #define SWM_PINASSIGN1_U1_RTS_O_MASK (0xFF000000U) 7037 #define SWM_PINASSIGN1_U1_RTS_O_SHIFT (24U) 7038 /*! U1_RTS_O - U1_RTS function assignment. The value is the pin number to be assigned to this 7039 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7040 * to PIO1_21(=0x35). 7041 */ 7042 #define SWM_PINASSIGN1_U1_RTS_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U1_RTS_O_SHIFT)) & SWM_PINASSIGN1_U1_RTS_O_MASK) 7043 /*! @} */ 7044 7045 /*! @name PINASSIGN2 - Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK, U2_TXD, U2_RXD. */ 7046 /*! @{ */ 7047 #define SWM_PINASSIGN2_U1_CTS_I_MASK (0xFFU) 7048 #define SWM_PINASSIGN2_U1_CTS_I_SHIFT (0U) 7049 /*! U1_CTS_I - U1_CTS function assignment. The value is the pin number to be assigned to this 7050 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7051 * to PIO1_21(=0x35). 7052 */ 7053 #define SWM_PINASSIGN2_U1_CTS_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_U1_CTS_I_SHIFT)) & SWM_PINASSIGN2_U1_CTS_I_MASK) 7054 #define SWM_PINASSIGN2_U1_SCLK_IO_MASK (0xFF00U) 7055 #define SWM_PINASSIGN2_U1_SCLK_IO_SHIFT (8U) 7056 /*! U1_SCLK_IO - U1_SCLK function assignment. The value is the pin number to be assigned to this 7057 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7058 * (=0x20) to PIO1_21(=0x35). 7059 */ 7060 #define SWM_PINASSIGN2_U1_SCLK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_U1_SCLK_IO_SHIFT)) & SWM_PINASSIGN2_U1_SCLK_IO_MASK) 7061 #define SWM_PINASSIGN2_U2_TXD_O_MASK (0xFF0000U) 7062 #define SWM_PINASSIGN2_U2_TXD_O_SHIFT (16U) 7063 /*! U2_TXD_O - U2_TXD function assignment. The value is the pin number to be assigned to this 7064 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7065 * to PIO1_21(=0x35). 7066 */ 7067 #define SWM_PINASSIGN2_U2_TXD_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_U2_TXD_O_SHIFT)) & SWM_PINASSIGN2_U2_TXD_O_MASK) 7068 #define SWM_PINASSIGN2_U2_RXD_I_MASK (0xFF000000U) 7069 #define SWM_PINASSIGN2_U2_RXD_I_SHIFT (24U) 7070 /*! U2_RXD_I - U2_RXD function assignment. The value is the pin number to be assigned to this 7071 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7072 * to PIO1_21(=0x35). 7073 */ 7074 #define SWM_PINASSIGN2_U2_RXD_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_U2_RXD_I_SHIFT)) & SWM_PINASSIGN2_U2_RXD_I_MASK) 7075 /*! @} */ 7076 7077 /*! @name PINASSIGN3 - Pin assign register 3. Assign movable function U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK. */ 7078 /*! @{ */ 7079 #define SWM_PINASSIGN3_U2_RTS_O_MASK (0xFFU) 7080 #define SWM_PINASSIGN3_U2_RTS_O_SHIFT (0U) 7081 /*! U2_RTS_O - U2_RTS function assignment. The value is the pin number to be assigned to this 7082 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7083 * to PIO1_21(=0x35). 7084 */ 7085 #define SWM_PINASSIGN3_U2_RTS_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_U2_RTS_O_SHIFT)) & SWM_PINASSIGN3_U2_RTS_O_MASK) 7086 #define SWM_PINASSIGN3_U2_CTS_I_MASK (0xFF00U) 7087 #define SWM_PINASSIGN3_U2_CTS_I_SHIFT (8U) 7088 /*! U2_CTS_I - U2_CTS function assignment. The value is the pin number to be assigned to this 7089 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7090 * to PIO1_21(=0x35). 7091 */ 7092 #define SWM_PINASSIGN3_U2_CTS_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_U2_CTS_I_SHIFT)) & SWM_PINASSIGN3_U2_CTS_I_MASK) 7093 #define SWM_PINASSIGN3_U2_SCLK_IO_MASK (0xFF0000U) 7094 #define SWM_PINASSIGN3_U2_SCLK_IO_SHIFT (16U) 7095 /*! U2_SCLK_IO - U2_SCLK function assignment. The value is the pin number to be assigned to this 7096 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7097 * (=0x20) to PIO1_21(=0x35). 7098 */ 7099 #define SWM_PINASSIGN3_U2_SCLK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_U2_SCLK_IO_SHIFT)) & SWM_PINASSIGN3_U2_SCLK_IO_MASK) 7100 #define SWM_PINASSIGN3_SPI0_SCK_IO_MASK (0xFF000000U) 7101 #define SWM_PINASSIGN3_SPI0_SCK_IO_SHIFT (24U) 7102 /*! SPI0_SCK_IO - SPI0_SCK function assignment. The value is the pin number to be assigned to this 7103 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7104 * (=0x20) to PIO1_21(=0x35). 7105 */ 7106 #define SWM_PINASSIGN3_SPI0_SCK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_SPI0_SCK_IO_SHIFT)) & SWM_PINASSIGN3_SPI0_SCK_IO_MASK) 7107 /*! @} */ 7108 7109 /*! @name PINASSIGN4 - Pin assign register 4. Assign movable functions SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1. */ 7110 /*! @{ */ 7111 #define SWM_PINASSIGN4_SPI0_MOSI_IO_MASK (0xFFU) 7112 #define SWM_PINASSIGN4_SPI0_MOSI_IO_SHIFT (0U) 7113 /*! SPI0_MOSI_IO - SPI0_MOSI function assignment. The value is the pin number to be assigned to this 7114 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7115 * (=0x20) to PIO1_21(=0x35). 7116 */ 7117 #define SWM_PINASSIGN4_SPI0_MOSI_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_SPI0_MOSI_IO_SHIFT)) & SWM_PINASSIGN4_SPI0_MOSI_IO_MASK) 7118 #define SWM_PINASSIGN4_SPI0_MISO_IO_MASK (0xFF00U) 7119 #define SWM_PINASSIGN4_SPI0_MISO_IO_SHIFT (8U) 7120 /*! SPI0_MISO_IO - SPI0_MISIO function assignment. The value is the pin number to be assigned to 7121 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7122 * (=0x20) to PIO1_21(=0x35). 7123 */ 7124 #define SWM_PINASSIGN4_SPI0_MISO_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_SPI0_MISO_IO_SHIFT)) & SWM_PINASSIGN4_SPI0_MISO_IO_MASK) 7125 #define SWM_PINASSIGN4_SPI0_SSEL0_IO_MASK (0xFF0000U) 7126 #define SWM_PINASSIGN4_SPI0_SSEL0_IO_SHIFT (16U) 7127 /*! SPI0_SSEL0_IO - SPI0_SSEL0 function assignment. The value is the pin number to be assigned to 7128 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from 7129 * PIO1_0 (=0x20) to PIO1_21(=0x35). 7130 */ 7131 #define SWM_PINASSIGN4_SPI0_SSEL0_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_SPI0_SSEL0_IO_SHIFT)) & SWM_PINASSIGN4_SPI0_SSEL0_IO_MASK) 7132 #define SWM_PINASSIGN4_SPI0_SSEL1_IO_MASK (0xFF000000U) 7133 #define SWM_PINASSIGN4_SPI0_SSEL1_IO_SHIFT (24U) 7134 /*! SPI0_SSEL1_IO - SPI0_SSEL1 function assignment. The value is the pin number to be assigned to 7135 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from 7136 * PIO1_0 (=0x20) to PIO1_21(=0x35). 7137 */ 7138 #define SWM_PINASSIGN4_SPI0_SSEL1_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_SPI0_SSEL1_IO_SHIFT)) & SWM_PINASSIGN4_SPI0_SSEL1_IO_MASK) 7139 /*! @} */ 7140 7141 /*! @name PINASSIGN5 - Pin assign register 5. Assign movable functions SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI */ 7142 /*! @{ */ 7143 #define SWM_PINASSIGN5_SPI0_SSEL2_IO_MASK (0xFFU) 7144 #define SWM_PINASSIGN5_SPI0_SSEL2_IO_SHIFT (0U) 7145 /*! SPI0_SSEL2_IO - SPI0_SSEL2 function assignment. The value is the pin number to be assigned to 7146 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from 7147 * PIO1_0 (=0x20) to PIO1_21(=0x35). 7148 */ 7149 #define SWM_PINASSIGN5_SPI0_SSEL2_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI0_SSEL2_IO_SHIFT)) & SWM_PINASSIGN5_SPI0_SSEL2_IO_MASK) 7150 #define SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK (0xFF00U) 7151 #define SWM_PINASSIGN5_SPI0_SSEL3_IO_SHIFT (8U) 7152 /*! SPI0_SSEL3_IO - SPI0_SSEL3 function assignment. The value is the pin number to be assigned to 7153 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from 7154 * PIO1_0 (=0x20) to PIO1_21(=0x35). 7155 */ 7156 #define SWM_PINASSIGN5_SPI0_SSEL3_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI0_SSEL3_IO_SHIFT)) & SWM_PINASSIGN5_SPI0_SSEL3_IO_MASK) 7157 #define SWM_PINASSIGN5_SPI1_SCK_IO_MASK (0xFF0000U) 7158 #define SWM_PINASSIGN5_SPI1_SCK_IO_SHIFT (16U) 7159 /*! SPI1_SCK_IO - SPI1_SCK function assignment. The value is the pin number to be assigned to this 7160 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7161 * (=0x20) to PIO1_21(=0x35). 7162 */ 7163 #define SWM_PINASSIGN5_SPI1_SCK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI1_SCK_IO_SHIFT)) & SWM_PINASSIGN5_SPI1_SCK_IO_MASK) 7164 #define SWM_PINASSIGN5_SPI1_MOSI_IO_MASK (0xFF000000U) 7165 #define SWM_PINASSIGN5_SPI1_MOSI_IO_SHIFT (24U) 7166 /*! SPI1_MOSI_IO - SPI1_MOSI function assignment. The value is the pin number to be assigned to this 7167 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7168 * (=0x20) to PIO1_21(=0x35). 7169 */ 7170 #define SWM_PINASSIGN5_SPI1_MOSI_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_SPI1_MOSI_IO_SHIFT)) & SWM_PINASSIGN5_SPI1_MOSI_IO_MASK) 7171 /*! @} */ 7172 7173 /*! @name PINASSIGN6 - Pin assign register 6. Assign movable functions SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0. */ 7174 /*! @{ */ 7175 #define SWM_PINASSIGN6_SPI1_MISO_IO_MASK (0xFFU) 7176 #define SWM_PINASSIGN6_SPI1_MISO_IO_SHIFT (0U) 7177 /*! SPI1_MISO_IO - SPI1_MISO function assignment. The value is the pin number to be assigned to this 7178 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7179 * (=0x20) to PIO1_21(=0x35). 7180 */ 7181 #define SWM_PINASSIGN6_SPI1_MISO_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_SPI1_MISO_IO_SHIFT)) & SWM_PINASSIGN6_SPI1_MISO_IO_MASK) 7182 #define SWM_PINASSIGN6_SPI1_SSEL0_IO_MASK (0xFF00U) 7183 #define SWM_PINASSIGN6_SPI1_SSEL0_IO_SHIFT (8U) 7184 /*! SPI1_SSEL0_IO - SPI1_SSEL0 function assignment. The value is the pin number to be assigned to 7185 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from 7186 * PIO1_0 (=0x20) to PIO1_21(=0x35). 7187 */ 7188 #define SWM_PINASSIGN6_SPI1_SSEL0_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_SPI1_SSEL0_IO_SHIFT)) & SWM_PINASSIGN6_SPI1_SSEL0_IO_MASK) 7189 #define SWM_PINASSIGN6_SPI1_SSEL1_IO_MASK (0xFF0000U) 7190 #define SWM_PINASSIGN6_SPI1_SSEL1_IO_SHIFT (16U) 7191 /*! SPI1_SSEL1_IO - SPI1_SSEL1 function assignment. The value is the pin number to be assigned to 7192 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from 7193 * PIO1_0 (=0x20) to PIO1_21(=0x35). 7194 */ 7195 #define SWM_PINASSIGN6_SPI1_SSEL1_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_SPI1_SSEL1_IO_SHIFT)) & SWM_PINASSIGN6_SPI1_SSEL1_IO_MASK) 7196 #define SWM_PINASSIGN6_SCT0_GPIO_IN_A_I_MASK (0xFF000000U) 7197 #define SWM_PINASSIGN6_SCT0_GPIO_IN_A_I_SHIFT (24U) 7198 /*! SCT0_GPIO_IN_A_I - SCT0_GPIO_IN_A function assignment. The value is the pin number to be 7199 * assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and 7200 * from PIO1_0 (=0x20) to PIO1_21(=0x35). 7201 */ 7202 #define SWM_PINASSIGN6_SCT0_GPIO_IN_A_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_SCT0_GPIO_IN_A_I_SHIFT)) & SWM_PINASSIGN6_SCT0_GPIO_IN_A_I_MASK) 7203 /*! @} */ 7204 7205 /*! @name PINASSIGN7 - Pin assign register 7. Assign movable functions SCT_IN1, SCT_IN2, SCT_IN3, SCT_OUT0. */ 7206 /*! @{ */ 7207 #define SWM_PINASSIGN7_SCT0_GPIO_IN_B_I_MASK (0xFFU) 7208 #define SWM_PINASSIGN7_SCT0_GPIO_IN_B_I_SHIFT (0U) 7209 /*! SCT0_GPIO_IN_B_I - SCT0_GPIO_IN_B function assignment. The value is the pin number to be 7210 * assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and 7211 * from PIO1_0 (=0x20) to PIO1_21(=0x35). 7212 */ 7213 #define SWM_PINASSIGN7_SCT0_GPIO_IN_B_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_SCT0_GPIO_IN_B_I_SHIFT)) & SWM_PINASSIGN7_SCT0_GPIO_IN_B_I_MASK) 7214 #define SWM_PINASSIGN7_SCT0_GPIO_IN_C_I_MASK (0xFF00U) 7215 #define SWM_PINASSIGN7_SCT0_GPIO_IN_C_I_SHIFT (8U) 7216 /*! SCT0_GPIO_IN_C_I - SCT0_GPIO_IN_C function assignment. The value is the pin number to be 7217 * assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and 7218 * from PIO1_0 (=0x20) to PIO1_21(=0x35). 7219 */ 7220 #define SWM_PINASSIGN7_SCT0_GPIO_IN_C_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_SCT0_GPIO_IN_C_I_SHIFT)) & SWM_PINASSIGN7_SCT0_GPIO_IN_C_I_MASK) 7221 #define SWM_PINASSIGN7_SCT0_GPIO_IN_D_I_MASK (0xFF0000U) 7222 #define SWM_PINASSIGN7_SCT0_GPIO_IN_D_I_SHIFT (16U) 7223 /*! SCT0_GPIO_IN_D_I - SCT0_GPIO_IN_D function assignment. The value is the pin number to be 7224 * assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and 7225 * from PIO1_0 (=0x20) to PIO1_21(=0x35). 7226 */ 7227 #define SWM_PINASSIGN7_SCT0_GPIO_IN_D_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_SCT0_GPIO_IN_D_I_SHIFT)) & SWM_PINASSIGN7_SCT0_GPIO_IN_D_I_MASK) 7228 #define SWM_PINASSIGN7_SCT_OUT0_O_MASK (0xFF000000U) 7229 #define SWM_PINASSIGN7_SCT_OUT0_O_SHIFT (24U) 7230 /*! SCT_OUT0_O - SCT_OUT0 function assignment. The value is the pin number to be assigned to this 7231 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7232 * (=0x20) to PIO1_21(=0x35). 7233 */ 7234 #define SWM_PINASSIGN7_SCT_OUT0_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_SCT_OUT0_O_SHIFT)) & SWM_PINASSIGN7_SCT_OUT0_O_MASK) 7235 /*! @} */ 7236 7237 /*! @name PINASSIGN8 - Pin assign register 8. Assign movable functions SCT_OUT1, SCT_OUT2, SCT_OUT3, SCT_OUT4. */ 7238 /*! @{ */ 7239 #define SWM_PINASSIGN8_SCT_OUT1_O_MASK (0xFFU) 7240 #define SWM_PINASSIGN8_SCT_OUT1_O_SHIFT (0U) 7241 /*! SCT_OUT1_O - SCT_OUT1 function assignment. The value is the pin number to be assigned to this 7242 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7243 * (=0x20) to PIO1_21(=0x35). 7244 */ 7245 #define SWM_PINASSIGN8_SCT_OUT1_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_SCT_OUT1_O_SHIFT)) & SWM_PINASSIGN8_SCT_OUT1_O_MASK) 7246 #define SWM_PINASSIGN8_SCT_OUT2_O_MASK (0xFF00U) 7247 #define SWM_PINASSIGN8_SCT_OUT2_O_SHIFT (8U) 7248 /*! SCT_OUT2_O - SCT_OUT2 function assignment. The value is the pin number to be assigned to this 7249 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7250 * (=0x20) to PIO1_21(=0x35). 7251 */ 7252 #define SWM_PINASSIGN8_SCT_OUT2_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_SCT_OUT2_O_SHIFT)) & SWM_PINASSIGN8_SCT_OUT2_O_MASK) 7253 #define SWM_PINASSIGN8_SCT_OUT3_O_MASK (0xFF0000U) 7254 #define SWM_PINASSIGN8_SCT_OUT3_O_SHIFT (16U) 7255 /*! SCT_OUT3_O - SCT_OUT3 function assignment. The value is the pin number to be assigned to this 7256 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7257 * (=0x20) to PIO1_21(=0x35). 7258 */ 7259 #define SWM_PINASSIGN8_SCT_OUT3_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_SCT_OUT3_O_SHIFT)) & SWM_PINASSIGN8_SCT_OUT3_O_MASK) 7260 #define SWM_PINASSIGN8_SCT_OUT4_O_MASK (0xFF000000U) 7261 #define SWM_PINASSIGN8_SCT_OUT4_O_SHIFT (24U) 7262 /*! SCT_OUT4_O - SCT_OUT4 function assignment. The value is the pin number to be assigned to this 7263 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7264 * (=0x20) to PIO1_21(=0x35). 7265 */ 7266 #define SWM_PINASSIGN8_SCT_OUT4_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_SCT_OUT4_O_SHIFT)) & SWM_PINASSIGN8_SCT_OUT4_O_MASK) 7267 /*! @} */ 7268 7269 /*! @name PINASSIGN9 - Pin assign register 9. Assign movable functions SCT_OUT5, SCT_OUT6, I2C1_SDA, I2C1_SCL. */ 7270 /*! @{ */ 7271 #define SWM_PINASSIGN9_SCT_OUT5_O_MASK (0xFFU) 7272 #define SWM_PINASSIGN9_SCT_OUT5_O_SHIFT (0U) 7273 /*! SCT_OUT5_O - SCT_OUT5 function assignment. The value is the pin number to be assigned to this 7274 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7275 * (=0x20) to PIO1_21(=0x35). 7276 */ 7277 #define SWM_PINASSIGN9_SCT_OUT5_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN9_SCT_OUT5_O_SHIFT)) & SWM_PINASSIGN9_SCT_OUT5_O_MASK) 7278 #define SWM_PINASSIGN9_SCT_OUT6_O_MASK (0xFF00U) 7279 #define SWM_PINASSIGN9_SCT_OUT6_O_SHIFT (8U) 7280 /*! SCT_OUT6_O - SCT_OUT6 function assignment. The value is the pin number to be assigned to this 7281 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7282 * (=0x20) to PIO1_21(=0x35). 7283 */ 7284 #define SWM_PINASSIGN9_SCT_OUT6_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN9_SCT_OUT6_O_SHIFT)) & SWM_PINASSIGN9_SCT_OUT6_O_MASK) 7285 #define SWM_PINASSIGN9_I2C1_SDA_IO_MASK (0xFF0000U) 7286 #define SWM_PINASSIGN9_I2C1_SDA_IO_SHIFT (16U) 7287 /*! I2C1_SDA_IO - I2C1_SDA function assignment. The value is the pin number to be assigned to this 7288 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7289 * (=0x20) to PIO1_21(=0x35). 7290 */ 7291 #define SWM_PINASSIGN9_I2C1_SDA_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN9_I2C1_SDA_IO_SHIFT)) & SWM_PINASSIGN9_I2C1_SDA_IO_MASK) 7292 #define SWM_PINASSIGN9_I2C1_SCL_IO_MASK (0xFF000000U) 7293 #define SWM_PINASSIGN9_I2C1_SCL_IO_SHIFT (24U) 7294 /*! I2C1_SCL_IO - I2C1_SCL function assignment. The value is the pin number to be assigned to this 7295 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7296 * (=0x20) to PIO1_21(=0x35). 7297 */ 7298 #define SWM_PINASSIGN9_I2C1_SCL_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN9_I2C1_SCL_IO_SHIFT)) & SWM_PINASSIGN9_I2C1_SCL_IO_MASK) 7299 /*! @} */ 7300 7301 /*! @name PINASSIGN10 - Pin assign register 10. Assign movable functions I2C2_SDA, I2C2_SCL, I2C3_SDA, I2C3_SCL. */ 7302 /*! @{ */ 7303 #define SWM_PINASSIGN10_I2C2_SDA_IO_MASK (0xFFU) 7304 #define SWM_PINASSIGN10_I2C2_SDA_IO_SHIFT (0U) 7305 /*! I2C2_SDA_IO - I2C1_SDA function assignment. The value is the pin number to be assigned to this 7306 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7307 * (=0x20) to PIO1_21(=0x35). 7308 */ 7309 #define SWM_PINASSIGN10_I2C2_SDA_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN10_I2C2_SDA_IO_SHIFT)) & SWM_PINASSIGN10_I2C2_SDA_IO_MASK) 7310 #define SWM_PINASSIGN10_I2C2_SCL_IO_MASK (0xFF00U) 7311 #define SWM_PINASSIGN10_I2C2_SCL_IO_SHIFT (8U) 7312 /*! I2C2_SCL_IO - I2C1_SCL function assignment. The value is the pin number to be assigned to this 7313 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7314 * (=0x20) to PIO1_21(=0x35). 7315 */ 7316 #define SWM_PINASSIGN10_I2C2_SCL_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN10_I2C2_SCL_IO_SHIFT)) & SWM_PINASSIGN10_I2C2_SCL_IO_MASK) 7317 #define SWM_PINASSIGN10_I2C3_SDA_IO_MASK (0xFF0000U) 7318 #define SWM_PINASSIGN10_I2C3_SDA_IO_SHIFT (16U) 7319 /*! I2C3_SDA_IO - I2C3_SDA function assignment. The value is the pin number to be assigned to this 7320 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7321 * (=0x20) to PIO1_21(=0x35). 7322 */ 7323 #define SWM_PINASSIGN10_I2C3_SDA_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN10_I2C3_SDA_IO_SHIFT)) & SWM_PINASSIGN10_I2C3_SDA_IO_MASK) 7324 #define SWM_PINASSIGN10_I2C3_SCL_IO_MASK (0xFF000000U) 7325 #define SWM_PINASSIGN10_I2C3_SCL_IO_SHIFT (24U) 7326 /*! I2C3_SCL_IO - I2C3_SCL function assignment. The value is the pin number to be assigned to this 7327 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7328 * (=0x20) to PIO1_21(=0x35). 7329 */ 7330 #define SWM_PINASSIGN10_I2C3_SCL_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN10_I2C3_SCL_IO_SHIFT)) & SWM_PINASSIGN10_I2C3_SCL_IO_MASK) 7331 /*! @} */ 7332 7333 /*! @name PINASSIGN11 - Pin assign register 11. Assign movable functions COMP0_OUT, CLKOUT, GPIOINT_BMATCH, UART3_TXD */ 7334 /*! @{ */ 7335 #define SWM_PINASSIGN11_COMP0_OUT_O_MASK (0xFFU) 7336 #define SWM_PINASSIGN11_COMP0_OUT_O_SHIFT (0U) 7337 /*! COMP0_OUT_O - COMP0_OUT function assignment. The value is the pin number to be assigned to this 7338 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7339 * (=0x20) to PIO1_21(=0x35). 7340 */ 7341 #define SWM_PINASSIGN11_COMP0_OUT_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN11_COMP0_OUT_O_SHIFT)) & SWM_PINASSIGN11_COMP0_OUT_O_MASK) 7342 #define SWM_PINASSIGN11_CLKOUT_O_MASK (0xFF00U) 7343 #define SWM_PINASSIGN11_CLKOUT_O_SHIFT (8U) 7344 /*! CLKOUT_O - CLKOUT function assignment. The value is the pin number to be assigned to this 7345 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7346 * to PIO1_21(=0x35). 7347 */ 7348 #define SWM_PINASSIGN11_CLKOUT_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN11_CLKOUT_O_SHIFT)) & SWM_PINASSIGN11_CLKOUT_O_MASK) 7349 #define SWM_PINASSIGN11_GPIO_INT_BMAT_O_MASK (0xFF0000U) 7350 #define SWM_PINASSIGN11_GPIO_INT_BMAT_O_SHIFT (16U) 7351 /*! GPIO_INT_BMAT_O - GPIO_INT_BMAT function assignment. The value is the pin number to be assigned 7352 * to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from 7353 * PIO1_0 (=0x20) to PIO1_21(=0x35). 7354 */ 7355 #define SWM_PINASSIGN11_GPIO_INT_BMAT_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN11_GPIO_INT_BMAT_O_SHIFT)) & SWM_PINASSIGN11_GPIO_INT_BMAT_O_MASK) 7356 #define SWM_PINASSIGN11_UART3_TXD_MASK (0xFF000000U) 7357 #define SWM_PINASSIGN11_UART3_TXD_SHIFT (24U) 7358 /*! UART3_TXD - UART3_TXD function assignment. The value is the pin number to be assigned to this 7359 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7360 * (=0x20) to PIO1_21(=0x35). 7361 */ 7362 #define SWM_PINASSIGN11_UART3_TXD(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN11_UART3_TXD_SHIFT)) & SWM_PINASSIGN11_UART3_TXD_MASK) 7363 /*! @} */ 7364 7365 /*! @name PINASSIGN12 - Pin assign register 12. Assign movable functions UART3_RXD, UART3_SCLK, UART4_TXD, UART4_RXD. */ 7366 /*! @{ */ 7367 #define SWM_PINASSIGN12_UART3_RXD_MASK (0xFFU) 7368 #define SWM_PINASSIGN12_UART3_RXD_SHIFT (0U) 7369 /*! UART3_RXD - UART3_RXD function assignment. The value is the pin number to be assigned to this 7370 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7371 * (=0x20) to PIO1_21(=0x35). 7372 */ 7373 #define SWM_PINASSIGN12_UART3_RXD(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN12_UART3_RXD_SHIFT)) & SWM_PINASSIGN12_UART3_RXD_MASK) 7374 #define SWM_PINASSIGN12_UART3_SCLK_MASK (0xFF00U) 7375 #define SWM_PINASSIGN12_UART3_SCLK_SHIFT (8U) 7376 /*! UART3_SCLK - UART3_SCLK function assignment. The value is the pin number to be assigned to this 7377 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7378 * (=0x20) to PIO1_21(=0x35). 7379 */ 7380 #define SWM_PINASSIGN12_UART3_SCLK(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN12_UART3_SCLK_SHIFT)) & SWM_PINASSIGN12_UART3_SCLK_MASK) 7381 #define SWM_PINASSIGN12_UART4_TXD_MASK (0xFF0000U) 7382 #define SWM_PINASSIGN12_UART4_TXD_SHIFT (16U) 7383 /*! UART4_TXD - UART4_TXD function assignment. The value is the pin number to be assigned to this 7384 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7385 * (=0x20) to PIO1_21(=0x35). 7386 */ 7387 #define SWM_PINASSIGN12_UART4_TXD(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN12_UART4_TXD_SHIFT)) & SWM_PINASSIGN12_UART4_TXD_MASK) 7388 #define SWM_PINASSIGN12_UART4_RXD_MASK (0xFF000000U) 7389 #define SWM_PINASSIGN12_UART4_RXD_SHIFT (24U) 7390 /*! UART4_RXD - UART4_TXD function assignment. The value is the pin number to be assigned to this 7391 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7392 * (=0x20) to PIO1_21(=0x35). 7393 */ 7394 #define SWM_PINASSIGN12_UART4_RXD(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN12_UART4_RXD_SHIFT)) & SWM_PINASSIGN12_UART4_RXD_MASK) 7395 /*! @} */ 7396 7397 /*! @name PINASSIGN13 - Pin assign register 13. Assign movable functions UART4_SCLK, T0_MAT0, T0_MAT1, T0_MAT2. */ 7398 /*! @{ */ 7399 #define SWM_PINASSIGN13_UART4_SCLK_MASK (0xFFU) 7400 #define SWM_PINASSIGN13_UART4_SCLK_SHIFT (0U) 7401 /*! UART4_SCLK - UART4_SCLK function assignment. The value is the pin number to be assigned to this 7402 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 7403 * (=0x20) to PIO1_21(=0x35). 7404 */ 7405 #define SWM_PINASSIGN13_UART4_SCLK(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN13_UART4_SCLK_SHIFT)) & SWM_PINASSIGN13_UART4_SCLK_MASK) 7406 #define SWM_PINASSIGN13_T0_MAT0_MASK (0xFF00U) 7407 #define SWM_PINASSIGN13_T0_MAT0_SHIFT (8U) 7408 /*! T0_MAT0 - T0_MAT0 function assignment. The value is the pin number to be assigned to this 7409 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7410 * to PIO1_21(=0x35). 7411 */ 7412 #define SWM_PINASSIGN13_T0_MAT0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN13_T0_MAT0_SHIFT)) & SWM_PINASSIGN13_T0_MAT0_MASK) 7413 #define SWM_PINASSIGN13_T0_MAT1_MASK (0xFF0000U) 7414 #define SWM_PINASSIGN13_T0_MAT1_SHIFT (16U) 7415 /*! T0_MAT1 - T0_MAT1 function assignment. The value is the pin number to be assigned to this 7416 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7417 * to PIO1_21(=0x35). 7418 */ 7419 #define SWM_PINASSIGN13_T0_MAT1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN13_T0_MAT1_SHIFT)) & SWM_PINASSIGN13_T0_MAT1_MASK) 7420 #define SWM_PINASSIGN13_T0_MAT2_MASK (0xFF000000U) 7421 #define SWM_PINASSIGN13_T0_MAT2_SHIFT (24U) 7422 /*! T0_MAT2 - T0_MAT2 function assignment. The value is the pin number to be assigned to this 7423 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7424 * to PIO1_21(=0x35). 7425 */ 7426 #define SWM_PINASSIGN13_T0_MAT2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN13_T0_MAT2_SHIFT)) & SWM_PINASSIGN13_T0_MAT2_MASK) 7427 /*! @} */ 7428 7429 /*! @name PINASSIGN14 - Pin assign register 14. Assign movable functions T0_MAT3, T0_CAP0, T0_CAP1, T0_CAP2. */ 7430 /*! @{ */ 7431 #define SWM_PINASSIGN14_T0_MAT3_MASK (0xFFU) 7432 #define SWM_PINASSIGN14_T0_MAT3_SHIFT (0U) 7433 /*! T0_MAT3 - T0_MAT3 function assignment. The value is the pin number to be assigned to this 7434 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7435 * to PIO1_21(=0x35). 7436 */ 7437 #define SWM_PINASSIGN14_T0_MAT3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN14_T0_MAT3_SHIFT)) & SWM_PINASSIGN14_T0_MAT3_MASK) 7438 #define SWM_PINASSIGN14_T0_CAP0_MASK (0xFF00U) 7439 #define SWM_PINASSIGN14_T0_CAP0_SHIFT (8U) 7440 /*! T0_CAP0 - T0_CAP0 function assignment. The value is the pin number to be assigned to this 7441 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7442 * to PIO1_21(=0x35). 7443 */ 7444 #define SWM_PINASSIGN14_T0_CAP0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN14_T0_CAP0_SHIFT)) & SWM_PINASSIGN14_T0_CAP0_MASK) 7445 #define SWM_PINASSIGN14_T0_CAP1_MASK (0xFF0000U) 7446 #define SWM_PINASSIGN14_T0_CAP1_SHIFT (16U) 7447 /*! T0_CAP1 - T0_CAP1 function assignment. The value is the pin number to be assigned to this 7448 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7449 * to PIO1_21(=0x35). 7450 */ 7451 #define SWM_PINASSIGN14_T0_CAP1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN14_T0_CAP1_SHIFT)) & SWM_PINASSIGN14_T0_CAP1_MASK) 7452 #define SWM_PINASSIGN14_T0_CAP2_MASK (0xFF000000U) 7453 #define SWM_PINASSIGN14_T0_CAP2_SHIFT (24U) 7454 /*! T0_CAP2 - T0_CAP2 function assignment. The value is the pin number to be assigned to this 7455 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7456 * to PIO1_21(=0x35). 7457 */ 7458 #define SWM_PINASSIGN14_T0_CAP2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN14_T0_CAP2_SHIFT)) & SWM_PINASSIGN14_T0_CAP2_MASK) 7459 /*! @} */ 7460 7461 /*! @name PINASSIGN_DATA - Pin assign register */ 7462 /*! @{ */ 7463 #define SWM_PINASSIGN_DATA_DATA0_MASK (0xFFU) 7464 #define SWM_PINASSIGN_DATA_DATA0_SHIFT (0U) 7465 /*! DATA0 - T0_MAT3 function assignment. The value is the pin number to be assigned to this 7466 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7467 * to PIO1_21(=0x35). 7468 */ 7469 #define SWM_PINASSIGN_DATA_DATA0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_DATA0_SHIFT)) & SWM_PINASSIGN_DATA_DATA0_MASK) 7470 #define SWM_PINASSIGN_DATA_DATA1_MASK (0xFF00U) 7471 #define SWM_PINASSIGN_DATA_DATA1_SHIFT (8U) 7472 /*! DATA1 - T0_CAP0 function assignment. The value is the pin number to be assigned to this 7473 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7474 * to PIO1_21(=0x35). 7475 */ 7476 #define SWM_PINASSIGN_DATA_DATA1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_DATA1_SHIFT)) & SWM_PINASSIGN_DATA_DATA1_MASK) 7477 #define SWM_PINASSIGN_DATA_DATA2_MASK (0xFF0000U) 7478 #define SWM_PINASSIGN_DATA_DATA2_SHIFT (16U) 7479 /*! DATA2 - T0_CAP1 function assignment. The value is the pin number to be assigned to this 7480 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7481 * to PIO1_21(=0x35). 7482 */ 7483 #define SWM_PINASSIGN_DATA_DATA2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_DATA2_SHIFT)) & SWM_PINASSIGN_DATA_DATA2_MASK) 7484 #define SWM_PINASSIGN_DATA_DATA3_MASK (0xFF000000U) 7485 #define SWM_PINASSIGN_DATA_DATA3_SHIFT (24U) 7486 /*! DATA3 - T0_CAP2 function assignment. The value is the pin number to be assigned to this 7487 * function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) 7488 * to PIO1_21(=0x35). 7489 */ 7490 #define SWM_PINASSIGN_DATA_DATA3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_DATA3_SHIFT)) & SWM_PINASSIGN_DATA_DATA3_MASK) 7491 /*! @} */ 7492 7493 /* The count of SWM_PINASSIGN_DATA */ 7494 #define SWM_PINASSIGN_DATA_COUNT (15U) 7495 7496 /*! @name PINENABLE0 - Pin enable register 0. Enables fixed-pin functions ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, VDDCMP and so on. */ 7497 /*! @{ */ 7498 #define SWM_PINENABLE0_ACMP_I1_MASK (0x1U) 7499 #define SWM_PINENABLE0_ACMP_I1_SHIFT (0U) 7500 /*! ACMP_I1 - ACMP_I1 function select. 7501 * 0b0..ACMP_I1 enabled on pin PIO0_00. 7502 * 0b1..ACMP_I1 disabled. 7503 */ 7504 #define SWM_PINENABLE0_ACMP_I1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I1_SHIFT)) & SWM_PINENABLE0_ACMP_I1_MASK) 7505 #define SWM_PINENABLE0_ACMP_I2_MASK (0x2U) 7506 #define SWM_PINENABLE0_ACMP_I2_SHIFT (1U) 7507 /*! ACMP_I2 - ACMP_I2 function select. 7508 * 0b0..ACMP_I2 enabled on pin PIO0_1. 7509 * 0b1..ACMP_I2 disabled. 7510 */ 7511 #define SWM_PINENABLE0_ACMP_I2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I2_SHIFT)) & SWM_PINENABLE0_ACMP_I2_MASK) 7512 #define SWM_PINENABLE0_ACMP_I3_MASK (0x4U) 7513 #define SWM_PINENABLE0_ACMP_I3_SHIFT (2U) 7514 /*! ACMP_I3 - ACMP_I3 function select. 7515 * 0b0..ACMP_I3 enabled on pin PIO0_14. 7516 * 0b1..ACMP_I3 disabled. 7517 */ 7518 #define SWM_PINENABLE0_ACMP_I3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I3_SHIFT)) & SWM_PINENABLE0_ACMP_I3_MASK) 7519 #define SWM_PINENABLE0_ACMP_I4_MASK (0x8U) 7520 #define SWM_PINENABLE0_ACMP_I4_SHIFT (3U) 7521 /*! ACMP_I4 - ACMP_I4 function select. 7522 * 0b0..ACMP_I4 enabled on pin PIO0_23. 7523 * 0b1..ACMP_I4 disabled. 7524 */ 7525 #define SWM_PINENABLE0_ACMP_I4(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I4_SHIFT)) & SWM_PINENABLE0_ACMP_I4_MASK) 7526 #define SWM_PINENABLE0_ACMP_I5_MASK (0x10U) 7527 #define SWM_PINENABLE0_ACMP_I5_SHIFT (4U) 7528 /*! ACMP_I5 - ACMP_I5 function select. 7529 * 0b0..ACMP_I5 enabled on pin PIO0_30. 7530 * 0b1..ACMP_I5 disabled. 7531 */ 7532 #define SWM_PINENABLE0_ACMP_I5(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I5_SHIFT)) & SWM_PINENABLE0_ACMP_I5_MASK) 7533 #define SWM_PINENABLE0_SWCLK_MASK (0x20U) 7534 #define SWM_PINENABLE0_SWCLK_SHIFT (5U) 7535 /*! SWCLK - SWCLK function select. 7536 * 0b0..SWCLK enabled on pin PIO0_3. 7537 * 0b1..SWCLK disabled. 7538 */ 7539 #define SWM_PINENABLE0_SWCLK(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_SWCLK_SHIFT)) & SWM_PINENABLE0_SWCLK_MASK) 7540 #define SWM_PINENABLE0_SWDIO_MASK (0x40U) 7541 #define SWM_PINENABLE0_SWDIO_SHIFT (6U) 7542 /*! SWDIO - SWDIO function select. 7543 * 0b0..SWDIO enabled on pin PIO0_2. 7544 * 0b1..SWDIO disabled. 7545 */ 7546 #define SWM_PINENABLE0_SWDIO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_SWDIO_SHIFT)) & SWM_PINENABLE0_SWDIO_MASK) 7547 #define SWM_PINENABLE0_XTALIN_MASK (0x80U) 7548 #define SWM_PINENABLE0_XTALIN_SHIFT (7U) 7549 /*! XTALIN - XTALIN function select. 7550 * 0b0..XTALIN enabled on pin PIO0_8. 7551 * 0b1..XTALIN disabled. 7552 */ 7553 #define SWM_PINENABLE0_XTALIN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_XTALIN_SHIFT)) & SWM_PINENABLE0_XTALIN_MASK) 7554 #define SWM_PINENABLE0_XTALOUT_MASK (0x100U) 7555 #define SWM_PINENABLE0_XTALOUT_SHIFT (8U) 7556 /*! XTALOUT - XTALOUT function select. 7557 * 0b0..XTALOUT enabled on pin PIO0_9. 7558 * 0b1..XTALOUT disabled. 7559 */ 7560 #define SWM_PINENABLE0_XTALOUT(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_XTALOUT_SHIFT)) & SWM_PINENABLE0_XTALOUT_MASK) 7561 #define SWM_PINENABLE0_RESETN_MASK (0x200U) 7562 #define SWM_PINENABLE0_RESETN_SHIFT (9U) 7563 /*! RESETN - RESETN function select. 7564 * 0b0..RESETN enabled on pin PIO0_5. 7565 * 0b1..RESETN disabled. 7566 */ 7567 #define SWM_PINENABLE0_RESETN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_RESETN_SHIFT)) & SWM_PINENABLE0_RESETN_MASK) 7568 #define SWM_PINENABLE0_CLKIN_MASK (0x400U) 7569 #define SWM_PINENABLE0_CLKIN_SHIFT (10U) 7570 /*! CLKIN - CLKIN function select. 7571 * 0b0..CLKIN enabled on pin PIO0_1. 7572 * 0b1..CLKIN disabled. 7573 */ 7574 #define SWM_PINENABLE0_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_CLKIN_SHIFT)) & SWM_PINENABLE0_CLKIN_MASK) 7575 #define SWM_PINENABLE0_VDDCMP_MASK (0x800U) 7576 #define SWM_PINENABLE0_VDDCMP_SHIFT (11U) 7577 /*! VDDCMP - VDDCMP function select. 7578 * 0b0..VDDCMP enabled on pin PIO0_6. 7579 * 0b1..VDDCMP disabled. 7580 */ 7581 #define SWM_PINENABLE0_VDDCMP(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_VDDCMP_SHIFT)) & SWM_PINENABLE0_VDDCMP_MASK) 7582 #define SWM_PINENABLE0_I2C0_SDA_MASK (0x1000U) 7583 #define SWM_PINENABLE0_I2C0_SDA_SHIFT (12U) 7584 /*! I2C0_SDA - I2C0_SDA function select. 7585 * 0b0..I2C0_SDA enabled on pin PIO0_11. 7586 * 0b1..I2C0_SDA disabled. 7587 */ 7588 #define SWM_PINENABLE0_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_I2C0_SDA_SHIFT)) & SWM_PINENABLE0_I2C0_SDA_MASK) 7589 #define SWM_PINENABLE0_I2C0_SCL_MASK (0x2000U) 7590 #define SWM_PINENABLE0_I2C0_SCL_SHIFT (13U) 7591 /*! I2C0_SCL - I2C0_SCL function select. 7592 * 0b0..I2C0_SCL enabled on pin PIO0_10. 7593 * 0b1..I2C0_SCL disabled. 7594 */ 7595 #define SWM_PINENABLE0_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_I2C0_SCL_SHIFT)) & SWM_PINENABLE0_I2C0_SCL_MASK) 7596 #define SWM_PINENABLE0_ADC_0_MASK (0x4000U) 7597 #define SWM_PINENABLE0_ADC_0_SHIFT (14U) 7598 /*! ADC_0 - ADC_0 function select. 7599 * 0b0..ADC_0 enabled on pin PIO0_7. 7600 * 0b1..ADC_0 disabled. 7601 */ 7602 #define SWM_PINENABLE0_ADC_0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_0_SHIFT)) & SWM_PINENABLE0_ADC_0_MASK) 7603 #define SWM_PINENABLE0_ADC_1_MASK (0x8000U) 7604 #define SWM_PINENABLE0_ADC_1_SHIFT (15U) 7605 /*! ADC_1 - ADC_1 function select. 7606 * 0b0..ADC_1 enabled on pin PIO0_6. 7607 * 0b1..ADC_1 disabled. 7608 */ 7609 #define SWM_PINENABLE0_ADC_1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_1_SHIFT)) & SWM_PINENABLE0_ADC_1_MASK) 7610 #define SWM_PINENABLE0_ADC_2_MASK (0x10000U) 7611 #define SWM_PINENABLE0_ADC_2_SHIFT (16U) 7612 /*! ADC_2 - ADC_2 function select. 7613 * 0b0..ADC_2 enabled on pin PIO0_14. 7614 * 0b1..ADC_2 disabled. 7615 */ 7616 #define SWM_PINENABLE0_ADC_2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_2_SHIFT)) & SWM_PINENABLE0_ADC_2_MASK) 7617 #define SWM_PINENABLE0_ADC_3_MASK (0x20000U) 7618 #define SWM_PINENABLE0_ADC_3_SHIFT (17U) 7619 /*! ADC_3 - ADC_3 function select. 7620 * 0b0..ADC_3 enabled on pin PIO0_23. 7621 * 0b1..ADC_3 disabled. 7622 */ 7623 #define SWM_PINENABLE0_ADC_3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_3_SHIFT)) & SWM_PINENABLE0_ADC_3_MASK) 7624 #define SWM_PINENABLE0_ADC_4_MASK (0x40000U) 7625 #define SWM_PINENABLE0_ADC_4_SHIFT (18U) 7626 /*! ADC_4 - ADC_4 function select. 7627 * 0b0..ADC_4 enabled on pin PIO0_22. 7628 * 0b1..ADC_4 disabled. 7629 */ 7630 #define SWM_PINENABLE0_ADC_4(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_4_SHIFT)) & SWM_PINENABLE0_ADC_4_MASK) 7631 #define SWM_PINENABLE0_ADC_5_MASK (0x80000U) 7632 #define SWM_PINENABLE0_ADC_5_SHIFT (19U) 7633 /*! ADC_5 - ADC_5 function select. 7634 * 0b0..ADC_5 enabled on pin PIO0_21. 7635 * 0b1..ADC_5 disabled. 7636 */ 7637 #define SWM_PINENABLE0_ADC_5(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_5_SHIFT)) & SWM_PINENABLE0_ADC_5_MASK) 7638 #define SWM_PINENABLE0_ADC_6_MASK (0x100000U) 7639 #define SWM_PINENABLE0_ADC_6_SHIFT (20U) 7640 /*! ADC_6 - ADC_6 function select. 7641 * 0b0..ADC_6 enabled on pin PIO0_20. 7642 * 0b1..ADC_6 disabled. 7643 */ 7644 #define SWM_PINENABLE0_ADC_6(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_6_SHIFT)) & SWM_PINENABLE0_ADC_6_MASK) 7645 #define SWM_PINENABLE0_ADC_7_MASK (0x200000U) 7646 #define SWM_PINENABLE0_ADC_7_SHIFT (21U) 7647 /*! ADC_7 - ADC_7 function select. 7648 * 0b0..ADC_7 enabled on pin PIO0_19. 7649 * 0b1..ADC_7 disabled. 7650 */ 7651 #define SWM_PINENABLE0_ADC_7(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_7_SHIFT)) & SWM_PINENABLE0_ADC_7_MASK) 7652 #define SWM_PINENABLE0_ADC_8_MASK (0x400000U) 7653 #define SWM_PINENABLE0_ADC_8_SHIFT (22U) 7654 /*! ADC_8 - ADC_8 function select. 7655 * 0b0..ADC_8 enabled on pin PIO0_18. 7656 * 0b1..ADC_8 disabled. 7657 */ 7658 #define SWM_PINENABLE0_ADC_8(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_8_SHIFT)) & SWM_PINENABLE0_ADC_8_MASK) 7659 #define SWM_PINENABLE0_ADC_9_MASK (0x800000U) 7660 #define SWM_PINENABLE0_ADC_9_SHIFT (23U) 7661 /*! ADC_9 - ADC_9 function select. 7662 * 0b0..ADC_9 enabled on pin PIO0_17. 7663 * 0b1..ADC_9 disabled. 7664 */ 7665 #define SWM_PINENABLE0_ADC_9(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_9_SHIFT)) & SWM_PINENABLE0_ADC_9_MASK) 7666 #define SWM_PINENABLE0_ADC_10_MASK (0x1000000U) 7667 #define SWM_PINENABLE0_ADC_10_SHIFT (24U) 7668 /*! ADC_10 - ADC_10 function select. 7669 * 0b0..ADC_10 enabled on pin PIO0_13. 7670 * 0b1..ADC_10 disabled. 7671 */ 7672 #define SWM_PINENABLE0_ADC_10(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_10_SHIFT)) & SWM_PINENABLE0_ADC_10_MASK) 7673 #define SWM_PINENABLE0_ADC_11_MASK (0x2000000U) 7674 #define SWM_PINENABLE0_ADC_11_SHIFT (25U) 7675 /*! ADC_11 - ADC_11 function select. 7676 * 0b0..ADC_11 enabled on pin PIO0_4. 7677 * 0b1..ADC_11 disabled. 7678 */ 7679 #define SWM_PINENABLE0_ADC_11(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_11_SHIFT)) & SWM_PINENABLE0_ADC_11_MASK) 7680 #define SWM_PINENABLE0_DACOUT0_MASK (0x4000000U) 7681 #define SWM_PINENABLE0_DACOUT0_SHIFT (26U) 7682 /*! DACOUT0 - DACOUT0 function select. 7683 * 0b0..DACOUT0 enabled on pin PIO0_17. 7684 * 0b1..DACOUT0 disabled. 7685 */ 7686 #define SWM_PINENABLE0_DACOUT0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_DACOUT0_SHIFT)) & SWM_PINENABLE0_DACOUT0_MASK) 7687 #define SWM_PINENABLE0_DACOUT1_MASK (0x8000000U) 7688 #define SWM_PINENABLE0_DACOUT1_SHIFT (27U) 7689 /*! DACOUT1 - DACOUT1 function select. 7690 * 0b0..DACOUT1 enabled on pin PIO0_29. 7691 * 0b1..DACOUT1 disabled. 7692 */ 7693 #define SWM_PINENABLE0_DACOUT1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_DACOUT1_SHIFT)) & SWM_PINENABLE0_DACOUT1_MASK) 7694 #define SWM_PINENABLE0_CAPT_X0_MASK (0x10000000U) 7695 #define SWM_PINENABLE0_CAPT_X0_SHIFT (28U) 7696 /*! CAPT_X0 - CAPT_X0 function select. 7697 * 0b0..CAPT_X0 enabled on pin PIO0_31. 7698 * 0b1..CAPT_X0 disabled. 7699 */ 7700 #define SWM_PINENABLE0_CAPT_X0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_CAPT_X0_SHIFT)) & SWM_PINENABLE0_CAPT_X0_MASK) 7701 #define SWM_PINENABLE0_CAPT_X1_MASK (0x20000000U) 7702 #define SWM_PINENABLE0_CAPT_X1_SHIFT (29U) 7703 /*! CAPT_X1 - CAPT_X1 function select. 7704 * 0b0..CAPT_X1 enabled on pin PIO1_0. 7705 * 0b1..CAPT_X1 disabled. 7706 */ 7707 #define SWM_PINENABLE0_CAPT_X1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_CAPT_X1_SHIFT)) & SWM_PINENABLE0_CAPT_X1_MASK) 7708 #define SWM_PINENABLE0_CAPT_X2_MASK (0x40000000U) 7709 #define SWM_PINENABLE0_CAPT_X2_SHIFT (30U) 7710 /*! CAPT_X2 - CAPT_X2 function select. 7711 * 0b0..CAPT_X2 enabled on pin PIO1_1. 7712 * 0b1..CAPT_X2 disabled. 7713 */ 7714 #define SWM_PINENABLE0_CAPT_X2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_CAPT_X2_SHIFT)) & SWM_PINENABLE0_CAPT_X2_MASK) 7715 #define SWM_PINENABLE0_CAPT_X3_MASK (0x80000000U) 7716 #define SWM_PINENABLE0_CAPT_X3_SHIFT (31U) 7717 /*! CAPT_X3 - CAPT_X3 function select. 7718 * 0b0..CAPT_X3 enabled on pin PIO1_2. 7719 * 0b1..CAPT_X3 disabled. 7720 */ 7721 #define SWM_PINENABLE0_CAPT_X3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_CAPT_X3_SHIFT)) & SWM_PINENABLE0_CAPT_X3_MASK) 7722 /*! @} */ 7723 7724 /*! @name PINENABLE1 - Pin enable register 1. Enables fixed-pin functions CAPT_X4, CAPT_X5, CAPT_X6, CAPT_X7, CAPT_X8, CAPT_X4, CAPT_YL and CAPT_YH. */ 7725 /*! @{ */ 7726 #define SWM_PINENABLE1_CAPT_X4_MASK (0x1U) 7727 #define SWM_PINENABLE1_CAPT_X4_SHIFT (0U) 7728 /*! CAPT_X4 - CAPT_X4 function select. 7729 * 0b0..CAPT_X4 enabled on pin PIO1_3. 7730 * 0b1..CAPT_X4 disabled. 7731 */ 7732 #define SWM_PINENABLE1_CAPT_X4(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE1_CAPT_X4_SHIFT)) & SWM_PINENABLE1_CAPT_X4_MASK) 7733 #define SWM_PINENABLE1_CAPT_X5_MASK (0x2U) 7734 #define SWM_PINENABLE1_CAPT_X5_SHIFT (1U) 7735 /*! CAPT_X5 - CAPT_X5 function select. 7736 * 0b0..CAPT_X5 enabled on pin PIO1_4. 7737 * 0b1..CAPT_X5 disabled. 7738 */ 7739 #define SWM_PINENABLE1_CAPT_X5(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE1_CAPT_X5_SHIFT)) & SWM_PINENABLE1_CAPT_X5_MASK) 7740 #define SWM_PINENABLE1_CAPT_X6_MASK (0x4U) 7741 #define SWM_PINENABLE1_CAPT_X6_SHIFT (2U) 7742 /*! CAPT_X6 - CAPT_X6 function select. 7743 * 0b0..CAPT_X6 enabled on pin PIO1_5. 7744 * 0b1..CAPT_X6 disabled. 7745 */ 7746 #define SWM_PINENABLE1_CAPT_X6(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE1_CAPT_X6_SHIFT)) & SWM_PINENABLE1_CAPT_X6_MASK) 7747 #define SWM_PINENABLE1_CAPT_X7_MASK (0x8U) 7748 #define SWM_PINENABLE1_CAPT_X7_SHIFT (3U) 7749 /*! CAPT_X7 - CAPT_X7 function select. 7750 * 0b0..CAPT_X7 enabled on pin PIO1_6. 7751 * 0b1..CAPT_X7 disabled. 7752 */ 7753 #define SWM_PINENABLE1_CAPT_X7(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE1_CAPT_X7_SHIFT)) & SWM_PINENABLE1_CAPT_X7_MASK) 7754 #define SWM_PINENABLE1_CAPT_X8_MASK (0x10U) 7755 #define SWM_PINENABLE1_CAPT_X8_SHIFT (4U) 7756 /*! CAPT_X8 - CAPT_X8 function select. 7757 * 0b0..CAPT_X8 enabled on pin PIO1_7. 7758 * 0b1..CAPT_X8 disabled. 7759 */ 7760 #define SWM_PINENABLE1_CAPT_X8(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE1_CAPT_X8_SHIFT)) & SWM_PINENABLE1_CAPT_X8_MASK) 7761 #define SWM_PINENABLE1_CAPT_YL_MASK (0x20U) 7762 #define SWM_PINENABLE1_CAPT_YL_SHIFT (5U) 7763 /*! CAPT_YL - CAPT_YL function select. 7764 * 0b0..CAPT_YL enabled on pin PIO1_8. 7765 * 0b1..CAPT_YL disabled. 7766 */ 7767 #define SWM_PINENABLE1_CAPT_YL(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE1_CAPT_YL_SHIFT)) & SWM_PINENABLE1_CAPT_YL_MASK) 7768 #define SWM_PINENABLE1_CAPT_YH_MASK (0x40U) 7769 #define SWM_PINENABLE1_CAPT_YH_SHIFT (6U) 7770 /*! CAPT_YH - CAPT_YH function select. 7771 * 0b0..CAPT_YH enabled on pin PIO1_9. 7772 * 0b1..CAPT_YH disabled. 7773 */ 7774 #define SWM_PINENABLE1_CAPT_YH(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE1_CAPT_YH_SHIFT)) & SWM_PINENABLE1_CAPT_YH_MASK) 7775 /*! @} */ 7776 7777 7778 /*! 7779 * @} 7780 */ /* end of group SWM_Register_Masks */ 7781 7782 7783 /* SWM - Peripheral instance base addresses */ 7784 /** Peripheral SWM0 base address */ 7785 #define SWM0_BASE (0x4000C000u) 7786 /** Peripheral SWM0 base pointer */ 7787 #define SWM0 ((SWM_Type *)SWM0_BASE) 7788 /** Array initializer of SWM peripheral base addresses */ 7789 #define SWM_BASE_ADDRS { SWM0_BASE } 7790 /** Array initializer of SWM peripheral base pointers */ 7791 #define SWM_BASE_PTRS { SWM0 } 7792 7793 /*! 7794 * @} 7795 */ /* end of group SWM_Peripheral_Access_Layer */ 7796 7797 7798 /* ---------------------------------------------------------------------------- 7799 -- SYSCON Peripheral Access Layer 7800 ---------------------------------------------------------------------------- */ 7801 7802 /*! 7803 * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer 7804 * @{ 7805 */ 7806 7807 /** SYSCON - Register Layout Typedef */ 7808 typedef struct { 7809 __IO uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */ 7810 uint8_t RESERVED_0[4]; 7811 __IO uint32_t SYSPLLCTRL; /**< PLL control, offset: 0x8 */ 7812 __I uint32_t SYSPLLSTAT; /**< PLL status, offset: 0xC */ 7813 uint8_t RESERVED_1[16]; 7814 __IO uint32_t SYSOSCCTRL; /**< system oscillator control, offset: 0x20 */ 7815 __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x24 */ 7816 __IO uint32_t FROOSCCTRL; /**< FRO oscillator control, offset: 0x28 */ 7817 uint8_t RESERVED_2[4]; 7818 __IO uint32_t FRODIRECTCLKUEN; /**< FRO direct clock source update enable register, offset: 0x30 */ 7819 uint8_t RESERVED_3[4]; 7820 __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x38 */ 7821 uint8_t RESERVED_4[4]; 7822 __IO uint32_t SYSPLLCLKSEL; /**< System PLL clock source select register, offset: 0x40 */ 7823 __IO uint32_t SYSPLLCLKUEN; /**< System PLL clock source update enable register, offset: 0x44 */ 7824 __IO uint32_t MAINCLKPLLSEL; /**< Main clock source select register, offset: 0x48 */ 7825 __IO uint32_t MAINCLKPLLUEN; /**< Main clock source update enable register, offset: 0x4C */ 7826 __IO uint32_t MAINCLKSEL; /**< Main clock source select register, offset: 0x50 */ 7827 __IO uint32_t MAINCLKUEN; /**< Main clock source update enable register, offset: 0x54 */ 7828 __IO uint32_t SYSAHBCLKDIV; /**< System clock divider register, offset: 0x58 */ 7829 uint8_t RESERVED_5[4]; 7830 __IO uint32_t CAPTCLKSEL; /**< CAPT clock source select register, offset: 0x60 */ 7831 __IO uint32_t ADCCLKSEL; /**< ADC clock source select register, offset: 0x64 */ 7832 __IO uint32_t ADCCLKDIV; /**< ADC clock divider register, offset: 0x68 */ 7833 __IO uint32_t SCTCLKSEL; /**< SCT clock source select register, offset: 0x6C */ 7834 __IO uint32_t SCTCLKDIV; /**< SCT clock divider register, offset: 0x70 */ 7835 __IO uint32_t EXTCLKSEL; /**< external clock source select register, offset: 0x74 */ 7836 uint8_t RESERVED_6[8]; 7837 __IO uint32_t SYSAHBCLKCTRL0; /**< System clock group 0 control register, offset: 0x80 */ 7838 __IO uint32_t SYSAHBCLKCTRL1; /**< System clock group 1 control register, offset: 0x84 */ 7839 __IO uint32_t PRESETCTRL0; /**< Peripheral reset group 0 control register, offset: 0x88 */ 7840 __IO uint32_t PRESETCTRL1; /**< Peripheral reset group 1 control register, offset: 0x8C */ 7841 __IO uint32_t FCLKSEL[11]; /**< peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register., array offset: 0x90, array step: 0x4 */ 7842 uint8_t RESERVED_7[20]; 7843 struct { /* offset: 0xD0, array step: 0x10 */ 7844 __IO uint32_t FRGDIV; /**< fractional generator N divider value register, array offset: 0xD0, array step: 0x10 */ 7845 __IO uint32_t FRGMULT; /**< fractional generator N multiplier value register, array offset: 0xD4, array step: 0x10 */ 7846 __IO uint32_t FRGCLKSEL; /**< FRG N clock source select register, array offset: 0xD8, array step: 0x10 */ 7847 uint8_t RESERVED_0[4]; 7848 } FRG[2]; 7849 __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select register, offset: 0xF0 */ 7850 __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider registers, offset: 0xF4 */ 7851 uint8_t RESERVED_8[4]; 7852 __IO uint32_t EXTTRACECMD; /**< External trace buffer command register, offset: 0xFC */ 7853 __I uint32_t PIOPORCAP[2]; /**< POR captured PIO N status register(PIO0 has 32 PIOs, PIO1 has 22 PIOs), array offset: 0x100, array step: 0x4 */ 7854 uint8_t RESERVED_9[44]; 7855 __IO uint32_t IOCONCLKDIV6; /**< Peripheral clock 6 to the IOCON block for programmable glitch filter, offset: 0x134 */ 7856 __IO uint32_t IOCONCLKDIV5; /**< Peripheral clock 6 to the IOCON block for programmable glitch filter, offset: 0x138 */ 7857 __IO uint32_t IOCONCLKDIV4; /**< Peripheral clock 4 to the IOCON block for programmable glitch filter, offset: 0x13C */ 7858 __IO uint32_t IOCONCLKDIV3; /**< Peripheral clock 3 to the IOCON block for programmable glitch filter, offset: 0x140 */ 7859 __IO uint32_t IOCONCLKDIV2; /**< Peripheral clock 2 to the IOCON block for programmable glitch filter, offset: 0x144 */ 7860 __IO uint32_t IOCONCLKDIV1; /**< Peripheral clock 1 to the IOCON block for programmable glitch filter, offset: 0x148 */ 7861 __IO uint32_t IOCONCLKDIV0; /**< Peripheral clock 0 to the IOCON block for programmable glitch filter, offset: 0x14C */ 7862 __IO uint32_t BODCTRL; /**< BOD control register, offset: 0x150 */ 7863 __IO uint32_t SYSTCKCAL; /**< System tick timer calibration register, offset: 0x154 */ 7864 uint8_t RESERVED_10[24]; 7865 __IO uint32_t IRQLATENCY; /**< IRQ latency register, offset: 0x170 */ 7866 __IO uint32_t NMISRC; /**< NMI source selection register, offset: 0x174 */ 7867 __IO uint32_t PINTSEL[8]; /**< Pin interrupt select registers N, array offset: 0x178, array step: 0x4 */ 7868 uint8_t RESERVED_11[108]; 7869 __IO uint32_t STARTERP0; /**< Start logic 0 pin wake-up enable register 0, offset: 0x204 */ 7870 uint8_t RESERVED_12[12]; 7871 __IO uint32_t STARTERP1; /**< Start logic 0 pin wake-up enable register 1, offset: 0x214 */ 7872 uint8_t RESERVED_13[24]; 7873 __IO uint32_t PDSLEEPCFG; /**< Deep-sleep configuration register, offset: 0x230 */ 7874 __IO uint32_t PDAWAKECFG; /**< Wake-up configuration register, offset: 0x234 */ 7875 __IO uint32_t PDRUNCFG; /**< Power configuration register, offset: 0x238 */ 7876 uint8_t RESERVED_14[444]; 7877 __I uint32_t DEVICE_ID; /**< Part ID register, offset: 0x3F8 */ 7878 } SYSCON_Type; 7879 7880 /* ---------------------------------------------------------------------------- 7881 -- SYSCON Register Masks 7882 ---------------------------------------------------------------------------- */ 7883 7884 /*! 7885 * @addtogroup SYSCON_Register_Masks SYSCON Register Masks 7886 * @{ 7887 */ 7888 7889 /*! @name SYSMEMREMAP - System Remap register */ 7890 /*! @{ */ 7891 #define SYSCON_SYSMEMREMAP_MAP_MASK (0x3U) 7892 #define SYSCON_SYSMEMREMAP_MAP_SHIFT (0U) 7893 /*! MAP - System memory remap. Value 0x3 is reserved. 7894 * 0b00..Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. 7895 * 0b01..User RAM Mode. Interrupt vectors are re-mapped to Static RAM. 7896 * 0b10..User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. 7897 */ 7898 #define SYSCON_SYSMEMREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSMEMREMAP_MAP_SHIFT)) & SYSCON_SYSMEMREMAP_MAP_MASK) 7899 /*! @} */ 7900 7901 /*! @name SYSPLLCTRL - PLL control */ 7902 /*! @{ */ 7903 #define SYSCON_SYSPLLCTRL_MSEL_MASK (0x1FU) 7904 #define SYSCON_SYSPLLCTRL_MSEL_SHIFT (0U) 7905 /*! MSEL - Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: 7906 * Division ratio M = 1 to 11111: Division ratio M = 32 7907 */ 7908 #define SYSCON_SYSPLLCTRL_MSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_MSEL_SHIFT)) & SYSCON_SYSPLLCTRL_MSEL_MASK) 7909 #define SYSCON_SYSPLLCTRL_PSEL_MASK (0x60U) 7910 #define SYSCON_SYSPLLCTRL_PSEL_SHIFT (5U) 7911 /*! PSEL - Post divider ratio P. The division ratio is 2 x P. 7912 * 0b00..P = 1 7913 * 0b01..P = 2 7914 * 0b10..P = 4 7915 * 0b11..P = 8 7916 */ 7917 #define SYSCON_SYSPLLCTRL_PSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_PSEL_SHIFT)) & SYSCON_SYSPLLCTRL_PSEL_MASK) 7918 /*! @} */ 7919 7920 /*! @name SYSPLLSTAT - PLL status */ 7921 /*! @{ */ 7922 #define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U) 7923 #define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U) 7924 /*! LOCK - PLL0 lock indicator 7925 */ 7926 #define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK) 7927 /*! @} */ 7928 7929 /*! @name SYSOSCCTRL - system oscillator control */ 7930 /*! @{ */ 7931 #define SYSCON_SYSOSCCTRL_BYPASS_MASK (0x1U) 7932 #define SYSCON_SYSOSCCTRL_BYPASS_SHIFT (0U) 7933 /*! BYPASS - oscillator (Xtal) Test Mode input (Active High) 7934 */ 7935 #define SYSCON_SYSOSCCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_BYPASS_SHIFT)) & SYSCON_SYSOSCCTRL_BYPASS_MASK) 7936 #define SYSCON_SYSOSCCTRL_FREQRANGE_MASK (0x2U) 7937 #define SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT (1U) 7938 /*! FREQRANGE - oscillator low / high transconductance selection input (Active High) 1-20MHz '0' : 15-50MHz '1' 7939 */ 7940 #define SYSCON_SYSOSCCTRL_FREQRANGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT)) & SYSCON_SYSOSCCTRL_FREQRANGE_MASK) 7941 /*! @} */ 7942 7943 /*! @name WDTOSCCTRL - Watchdog oscillator control */ 7944 /*! @{ */ 7945 #define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU) 7946 #define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U) 7947 /*! DIVSEL - Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + 7948 * DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64 7949 */ 7950 #define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK) 7951 #define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x1E0U) 7952 #define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U) 7953 /*! FREQSEL - Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when 7954 * watchdog oscillator is running 0x1 = 0.6 MHz 0x2 = 1.05 MHz 0x3 = 1.4 MHz 0x4 = 1.75 MHz 0x5 7955 * = 2.1 MHz 0x6 = 2.4 MHz 0x7 = 2.7 MHz 0x8 = 3.0 MHz 0x9 = 3.25 MHz 0xA = 3.5 MHz 0xB = 3.75 7956 * MHz 0xC = 4.0 MHz 0xD = 4.2 MHz 0xE = 4.4 MHz 0xF = 4.6 MHz 7957 */ 7958 #define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK) 7959 /*! @} */ 7960 7961 /*! @name FROOSCCTRL - FRO oscillator control */ 7962 /*! @{ */ 7963 #define SYSCON_FROOSCCTRL_FRO_DIRECT_MASK (0x20000U) 7964 #define SYSCON_FROOSCCTRL_FRO_DIRECT_SHIFT (17U) 7965 /*! FRO_DIRECT - fro direct clock select 7966 * 0b0..fro clock is divider by 2 or 16,depend on FAIM slow boot value 7967 * 0b1..fro clock is direct from FRO oscillator 7968 */ 7969 #define SYSCON_FROOSCCTRL_FRO_DIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROOSCCTRL_FRO_DIRECT_SHIFT)) & SYSCON_FROOSCCTRL_FRO_DIRECT_MASK) 7970 /*! @} */ 7971 7972 /*! @name FRODIRECTCLKUEN - FRO direct clock source update enable register */ 7973 /*! @{ */ 7974 #define SYSCON_FRODIRECTCLKUEN_ENA_MASK (0x1U) 7975 #define SYSCON_FRODIRECTCLKUEN_ENA_SHIFT (0U) 7976 /*! ENA - Enable fro clock source update 7977 * 0b0..no change 7978 * 0b1..update clock source 7979 */ 7980 #define SYSCON_FRODIRECTCLKUEN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRODIRECTCLKUEN_ENA_SHIFT)) & SYSCON_FRODIRECTCLKUEN_ENA_MASK) 7981 /*! @} */ 7982 7983 /*! @name SYSRSTSTAT - System reset status register */ 7984 /*! @{ */ 7985 #define SYSCON_SYSRSTSTAT_POR_MASK (0x1U) 7986 #define SYSCON_SYSRSTSTAT_POR_SHIFT (0U) 7987 /*! POR - POR reset status 7988 * 0b0..No POR detected 7989 * 0b1..POR detected. Writing a one clears this reset. 7990 */ 7991 #define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK) 7992 #define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U) 7993 #define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U) 7994 /*! EXTRST - Status of the external RESET pin. External reset status. 7995 * 0b0..No reset event detected. 7996 * 0b1..Reset detected. Writing a one clears this reset. 7997 */ 7998 #define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK) 7999 #define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U) 8000 #define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U) 8001 /*! WDT - Status of the Watchdog reset 8002 * 0b0..No WDT reset detected 8003 * 0b1..WDT reset detected. Writing a one clears this reset. 8004 */ 8005 #define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK) 8006 #define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U) 8007 #define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U) 8008 /*! BOD - Status of the Brown-out detect reset 8009 * 0b0..No BOD reset detected 8010 * 0b1..BOD reset detected. Writing a one clears this reset. 8011 */ 8012 #define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK) 8013 #define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U) 8014 #define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U) 8015 /*! SYSRST - Status of the software system reset 8016 * 0b0..No System reset detected 8017 * 0b1..System reset detected. Writing a one clears this reset. 8018 */ 8019 #define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK) 8020 /*! @} */ 8021 8022 /*! @name SYSPLLCLKSEL - System PLL clock source select register */ 8023 /*! @{ */ 8024 #define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x3U) 8025 #define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U) 8026 /*! SEL - System PLL clock source 8027 * 0b00..FRO 8028 * 0b01..External clock 8029 * 0b10..Watchdog oscillator 8030 * 0b11..FRO DIV 8031 */ 8032 #define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK) 8033 /*! @} */ 8034 8035 /*! @name SYSPLLCLKUEN - System PLL clock source update enable register */ 8036 /*! @{ */ 8037 #define SYSCON_SYSPLLCLKUEN_ENA_MASK (0x1U) 8038 #define SYSCON_SYSPLLCLKUEN_ENA_SHIFT (0U) 8039 /*! ENA - Enable system PLL clock source update 8040 * 0b0..no change 8041 * 0b1..update clock source 8042 */ 8043 #define SYSCON_SYSPLLCLKUEN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKUEN_ENA_SHIFT)) & SYSCON_SYSPLLCLKUEN_ENA_MASK) 8044 /*! @} */ 8045 8046 /*! @name MAINCLKPLLSEL - Main clock source select register */ 8047 /*! @{ */ 8048 #define SYSCON_MAINCLKPLLSEL_SEL_MASK (0x3U) 8049 #define SYSCON_MAINCLKPLLSEL_SEL_SHIFT (0U) 8050 /*! SEL - System PLL clock source 8051 * 0b00..main_clk_pre_pll 8052 * 0b01..sys pll 8053 * 0b10..none 8054 * 0b11..none 8055 */ 8056 #define SYSCON_MAINCLKPLLSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKPLLSEL_SEL_SHIFT)) & SYSCON_MAINCLKPLLSEL_SEL_MASK) 8057 /*! @} */ 8058 8059 /*! @name MAINCLKPLLUEN - Main clock source update enable register */ 8060 /*! @{ */ 8061 #define SYSCON_MAINCLKPLLUEN_ENA_MASK (0x1U) 8062 #define SYSCON_MAINCLKPLLUEN_ENA_SHIFT (0U) 8063 /*! ENA - Enable main clock source update 8064 * 0b0..no change 8065 * 0b1..update clock source 8066 */ 8067 #define SYSCON_MAINCLKPLLUEN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKPLLUEN_ENA_SHIFT)) & SYSCON_MAINCLKPLLUEN_ENA_MASK) 8068 /*! @} */ 8069 8070 /*! @name MAINCLKSEL - Main clock source select register */ 8071 /*! @{ */ 8072 #define SYSCON_MAINCLKSEL_SEL_MASK (0x3U) 8073 #define SYSCON_MAINCLKSEL_SEL_SHIFT (0U) 8074 /*! SEL - System PLL clock source 8075 * 0b00..FRO 8076 * 0b01..External clock 8077 * 0b10..Watchdog oscillator 8078 * 0b11..FRO_DIV 8079 */ 8080 #define SYSCON_MAINCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSEL_SEL_SHIFT)) & SYSCON_MAINCLKSEL_SEL_MASK) 8081 /*! @} */ 8082 8083 /*! @name MAINCLKUEN - Main clock source update enable register */ 8084 /*! @{ */ 8085 #define SYSCON_MAINCLKUEN_ENA_MASK (0x1U) 8086 #define SYSCON_MAINCLKUEN_ENA_SHIFT (0U) 8087 /*! ENA - Enable main clock source update 8088 * 0b0..no change 8089 * 0b1..update clock source 8090 */ 8091 #define SYSCON_MAINCLKUEN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKUEN_ENA_SHIFT)) & SYSCON_MAINCLKUEN_ENA_MASK) 8092 /*! @} */ 8093 8094 /*! @name SYSAHBCLKDIV - System clock divider register */ 8095 /*! @{ */ 8096 #define SYSCON_SYSAHBCLKDIV_DIV_MASK (0xFFU) 8097 #define SYSCON_SYSAHBCLKDIV_DIV_SHIFT (0U) 8098 /*! DIV - System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. 8099 */ 8100 #define SYSCON_SYSAHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKDIV_DIV_SHIFT)) & SYSCON_SYSAHBCLKDIV_DIV_MASK) 8101 /*! @} */ 8102 8103 /*! @name CAPTCLKSEL - CAPT clock source select register */ 8104 /*! @{ */ 8105 #define SYSCON_CAPTCLKSEL_SEL_MASK (0x7U) 8106 #define SYSCON_CAPTCLKSEL_SEL_SHIFT (0U) 8107 /*! SEL - Clock source for CAPT clock 8108 * 0b000..FRO 8109 * 0b001..main clock 8110 * 0b010..sys pll 8111 * 0b011..FRO_DIV 8112 * 0b100..Watchdog oscillator 8113 * 0b101..None 8114 * 0b110..None 8115 * 0b111..None 8116 */ 8117 #define SYSCON_CAPTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAPTCLKSEL_SEL_SHIFT)) & SYSCON_CAPTCLKSEL_SEL_MASK) 8118 /*! @} */ 8119 8120 /*! @name ADCCLKSEL - ADC clock source select register */ 8121 /*! @{ */ 8122 #define SYSCON_ADCCLKSEL_SEL_MASK (0x3U) 8123 #define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) 8124 /*! SEL - Clock source for ADC clock 8125 * 0b00..FRO 8126 * 0b01..sys pll 8127 * 0b10..none 8128 * 0b11..none 8129 */ 8130 #define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) 8131 /*! @} */ 8132 8133 /*! @name ADCCLKDIV - ADC clock divider register */ 8134 /*! @{ */ 8135 #define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU) 8136 #define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) 8137 /*! DIV - ADC clock divider values 0: ADC clock disabled. 1: Divide by 1. to 255: Divide by 255. 8138 */ 8139 #define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) 8140 /*! @} */ 8141 8142 /*! @name SCTCLKSEL - SCT clock source select register */ 8143 /*! @{ */ 8144 #define SYSCON_SCTCLKSEL_SEL_MASK (0x3U) 8145 #define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) 8146 /*! SEL - Clock source for SCT clock 8147 * 0b00..FRO 8148 * 0b01..main clock 8149 * 0b10..sys pll 8150 * 0b11..none 8151 */ 8152 #define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) 8153 /*! @} */ 8154 8155 /*! @name SCTCLKDIV - SCT clock divider register */ 8156 /*! @{ */ 8157 #define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) 8158 #define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) 8159 /*! DIV - SCT clock divider values 0: SCT clock disabled. 1: Divide by 1. to 255: Divide by 255. 8160 */ 8161 #define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) 8162 /*! @} */ 8163 8164 /*! @name EXTCLKSEL - external clock source select register */ 8165 /*! @{ */ 8166 #define SYSCON_EXTCLKSEL_SEL_MASK (0x1U) 8167 #define SYSCON_EXTCLKSEL_SEL_SHIFT (0U) 8168 /*! SEL - Clock source for external clock 8169 * 0b0..System oscillator 8170 * 0b1..Clk_in 8171 */ 8172 #define SYSCON_EXTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EXTCLKSEL_SEL_SHIFT)) & SYSCON_EXTCLKSEL_SEL_MASK) 8173 /*! @} */ 8174 8175 /*! @name SYSAHBCLKCTRL0 - System clock group 0 control register */ 8176 /*! @{ */ 8177 #define SYSCON_SYSAHBCLKCTRL0_SYS_MASK (0x1U) 8178 #define SYSCON_SYSAHBCLKCTRL0_SYS_SHIFT (0U) 8179 /*! SYS - Enables the clock for the AHB, the APB bridge, the Cortex-M0+ core clocks, SYSCON, and the 8180 * PMU. This bit is read only and always reads as 1. 8181 */ 8182 #define SYSCON_SYSAHBCLKCTRL0_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_SYS_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_SYS_MASK) 8183 #define SYSCON_SYSAHBCLKCTRL0_ROM_MASK (0x2U) 8184 #define SYSCON_SYSAHBCLKCTRL0_ROM_SHIFT (1U) 8185 /*! ROM - Enables clock for ROM. 8186 * 0b0..disable 8187 * 0b1..enable 8188 */ 8189 #define SYSCON_SYSAHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_ROM_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_ROM_MASK) 8190 #define SYSCON_SYSAHBCLKCTRL0_RAM0_1_MASK (0x4U) 8191 #define SYSCON_SYSAHBCLKCTRL0_RAM0_1_SHIFT (2U) 8192 /*! RAM0_1 - Enables clock for SRAM0 and SRAM1. 8193 * 0b0..disable 8194 * 0b1..enable 8195 */ 8196 #define SYSCON_SYSAHBCLKCTRL0_RAM0_1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_RAM0_1_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_RAM0_1_MASK) 8197 #define SYSCON_SYSAHBCLKCTRL0_FLASH_MASK (0x10U) 8198 #define SYSCON_SYSAHBCLKCTRL0_FLASH_SHIFT (4U) 8199 /*! FLASH - Enables clock for flash. 8200 * 0b0..disable 8201 * 0b1..enable 8202 */ 8203 #define SYSCON_SYSAHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_FLASH_MASK) 8204 #define SYSCON_SYSAHBCLKCTRL0_I2C0_MASK (0x20U) 8205 #define SYSCON_SYSAHBCLKCTRL0_I2C0_SHIFT (5U) 8206 /*! I2C0 - Enables clock for I2C0. 8207 * 0b0..disable 8208 * 0b1..enable 8209 */ 8210 #define SYSCON_SYSAHBCLKCTRL0_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_I2C0_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_I2C0_MASK) 8211 #define SYSCON_SYSAHBCLKCTRL0_GPIO0_MASK (0x40U) 8212 #define SYSCON_SYSAHBCLKCTRL0_GPIO0_SHIFT (6U) 8213 /*! GPIO0 - Enables clock for GPIO0 port registers. 8214 * 0b0..disable 8215 * 0b1..enable 8216 */ 8217 #define SYSCON_SYSAHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_GPIO0_MASK) 8218 #define SYSCON_SYSAHBCLKCTRL0_SWM_MASK (0x80U) 8219 #define SYSCON_SYSAHBCLKCTRL0_SWM_SHIFT (7U) 8220 /*! SWM - Enables clock for switch matrix. 8221 * 0b0..disable 8222 * 0b1..enable 8223 */ 8224 #define SYSCON_SYSAHBCLKCTRL0_SWM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_SWM_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_SWM_MASK) 8225 #define SYSCON_SYSAHBCLKCTRL0_SCT_MASK (0x100U) 8226 #define SYSCON_SYSAHBCLKCTRL0_SCT_SHIFT (8U) 8227 /*! SCT - Enables clock for state configurable timer SCTimer/PWM. 8228 * 0b0..disable 8229 * 0b1..enable 8230 */ 8231 #define SYSCON_SYSAHBCLKCTRL0_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_SCT_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_SCT_MASK) 8232 #define SYSCON_SYSAHBCLKCTRL0_WKT_MASK (0x200U) 8233 #define SYSCON_SYSAHBCLKCTRL0_WKT_SHIFT (9U) 8234 /*! WKT - Enables clock for self-wake-up timer. 8235 * 0b0..disable 8236 * 0b1..enable 8237 */ 8238 #define SYSCON_SYSAHBCLKCTRL0_WKT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_WKT_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_WKT_MASK) 8239 #define SYSCON_SYSAHBCLKCTRL0_MRT_MASK (0x400U) 8240 #define SYSCON_SYSAHBCLKCTRL0_MRT_SHIFT (10U) 8241 /*! MRT - Enables clock for multi-rate timer. 8242 * 0b0..disable 8243 * 0b1..enable 8244 */ 8245 #define SYSCON_SYSAHBCLKCTRL0_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_MRT_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_MRT_MASK) 8246 #define SYSCON_SYSAHBCLKCTRL0_SPI0_MASK (0x800U) 8247 #define SYSCON_SYSAHBCLKCTRL0_SPI0_SHIFT (11U) 8248 /*! SPI0 - Enables clock for SPI0. 8249 * 0b0..disable 8250 * 0b1..enable 8251 */ 8252 #define SYSCON_SYSAHBCLKCTRL0_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_SPI0_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_SPI0_MASK) 8253 #define SYSCON_SYSAHBCLKCTRL0_SPI1_MASK (0x1000U) 8254 #define SYSCON_SYSAHBCLKCTRL0_SPI1_SHIFT (12U) 8255 /*! SPI1 - Enables clock for SPI1. 8256 * 0b0..disable 8257 * 0b1..enable 8258 */ 8259 #define SYSCON_SYSAHBCLKCTRL0_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_SPI1_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_SPI1_MASK) 8260 #define SYSCON_SYSAHBCLKCTRL0_CRC_MASK (0x2000U) 8261 #define SYSCON_SYSAHBCLKCTRL0_CRC_SHIFT (13U) 8262 /*! CRC - Enables clock for CRC. 8263 * 0b0..disable 8264 * 0b1..enable 8265 */ 8266 #define SYSCON_SYSAHBCLKCTRL0_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_CRC_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_CRC_MASK) 8267 #define SYSCON_SYSAHBCLKCTRL0_UART0_MASK (0x4000U) 8268 #define SYSCON_SYSAHBCLKCTRL0_UART0_SHIFT (14U) 8269 /*! UART0 - Enables clock for UART0. 8270 * 0b0..disable 8271 * 0b1..enable 8272 */ 8273 #define SYSCON_SYSAHBCLKCTRL0_UART0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_UART0_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_UART0_MASK) 8274 #define SYSCON_SYSAHBCLKCTRL0_UART1_MASK (0x8000U) 8275 #define SYSCON_SYSAHBCLKCTRL0_UART1_SHIFT (15U) 8276 /*! UART1 - Enables clock for UART1. 8277 * 0b0..disable 8278 * 0b1..enable 8279 */ 8280 #define SYSCON_SYSAHBCLKCTRL0_UART1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_UART1_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_UART1_MASK) 8281 #define SYSCON_SYSAHBCLKCTRL0_UART2_MASK (0x10000U) 8282 #define SYSCON_SYSAHBCLKCTRL0_UART2_SHIFT (16U) 8283 /*! UART2 - Enables clock for UART2. 8284 * 0b0..disable 8285 * 0b1..enable 8286 */ 8287 #define SYSCON_SYSAHBCLKCTRL0_UART2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_UART2_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_UART2_MASK) 8288 #define SYSCON_SYSAHBCLKCTRL0_WWDT_MASK (0x20000U) 8289 #define SYSCON_SYSAHBCLKCTRL0_WWDT_SHIFT (17U) 8290 /*! WWDT - Enables clock for WWDT. 8291 * 0b0..disable 8292 * 0b1..enable 8293 */ 8294 #define SYSCON_SYSAHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_WWDT_MASK) 8295 #define SYSCON_SYSAHBCLKCTRL0_IOCON_MASK (0x40000U) 8296 #define SYSCON_SYSAHBCLKCTRL0_IOCON_SHIFT (18U) 8297 /*! IOCON - Enables clock for IOCON. 8298 * 0b0..disable 8299 * 0b1..enable 8300 */ 8301 #define SYSCON_SYSAHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_IOCON_MASK) 8302 #define SYSCON_SYSAHBCLKCTRL0_ACMP_MASK (0x80000U) 8303 #define SYSCON_SYSAHBCLKCTRL0_ACMP_SHIFT (19U) 8304 /*! ACMP - Enables clock for analog comparator. 8305 * 0b0..disable 8306 * 0b1..enable 8307 */ 8308 #define SYSCON_SYSAHBCLKCTRL0_ACMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_ACMP_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_ACMP_MASK) 8309 #define SYSCON_SYSAHBCLKCTRL0_GPIO1_MASK (0x100000U) 8310 #define SYSCON_SYSAHBCLKCTRL0_GPIO1_SHIFT (20U) 8311 /*! GPIO1 - Enables clock for GPIO1 port registers. 8312 * 0b0..disable 8313 * 0b1..enable 8314 */ 8315 #define SYSCON_SYSAHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_GPIO1_MASK) 8316 #define SYSCON_SYSAHBCLKCTRL0_I2C1_MASK (0x200000U) 8317 #define SYSCON_SYSAHBCLKCTRL0_I2C1_SHIFT (21U) 8318 /*! I2C1 - Enables clock for I2C1. 8319 * 0b0..disable 8320 * 0b1..enable 8321 */ 8322 #define SYSCON_SYSAHBCLKCTRL0_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_I2C1_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_I2C1_MASK) 8323 #define SYSCON_SYSAHBCLKCTRL0_I2C2_MASK (0x400000U) 8324 #define SYSCON_SYSAHBCLKCTRL0_I2C2_SHIFT (22U) 8325 /*! I2C2 - Enables clock for I2C2. 8326 * 0b0..disable 8327 * 0b1..enable 8328 */ 8329 #define SYSCON_SYSAHBCLKCTRL0_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_I2C2_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_I2C2_MASK) 8330 #define SYSCON_SYSAHBCLKCTRL0_I2C3_MASK (0x800000U) 8331 #define SYSCON_SYSAHBCLKCTRL0_I2C3_SHIFT (23U) 8332 /*! I2C3 - Enables clock for I2C3. 8333 * 0b0..disable 8334 * 0b1..enable 8335 */ 8336 #define SYSCON_SYSAHBCLKCTRL0_I2C3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_I2C3_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_I2C3_MASK) 8337 #define SYSCON_SYSAHBCLKCTRL0_ADC_MASK (0x1000000U) 8338 #define SYSCON_SYSAHBCLKCTRL0_ADC_SHIFT (24U) 8339 /*! ADC - Enables clock for ADC. 8340 * 0b0..disable 8341 * 0b1..enable 8342 */ 8343 #define SYSCON_SYSAHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_ADC_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_ADC_MASK) 8344 #define SYSCON_SYSAHBCLKCTRL0_CTIMER_MASK (0x2000000U) 8345 #define SYSCON_SYSAHBCLKCTRL0_CTIMER_SHIFT (25U) 8346 /*! CTIMER - Enables clock for CTIMER. 8347 * 0b0..disable 8348 * 0b1..enable 8349 */ 8350 #define SYSCON_SYSAHBCLKCTRL0_CTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_CTIMER_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_CTIMER_MASK) 8351 #define SYSCON_SYSAHBCLKCTRL0_MTB_MASK (0x4000000U) 8352 #define SYSCON_SYSAHBCLKCTRL0_MTB_SHIFT (26U) 8353 /*! MTB - Enables clock to micro-trace buffer control registers. Turn on this clock when using the 8354 * micro-trace buffer for debug purposes. 8355 * 0b0..disable 8356 * 0b1..enable 8357 */ 8358 #define SYSCON_SYSAHBCLKCTRL0_MTB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_MTB_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_MTB_MASK) 8359 #define SYSCON_SYSAHBCLKCTRL0_DAC0_MASK (0x8000000U) 8360 #define SYSCON_SYSAHBCLKCTRL0_DAC0_SHIFT (27U) 8361 /*! DAC0 - Enables clock for DAC0. 8362 * 0b0..disable 8363 * 0b1..enable 8364 */ 8365 #define SYSCON_SYSAHBCLKCTRL0_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_DAC0_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_DAC0_MASK) 8366 #define SYSCON_SYSAHBCLKCTRL0_GPIO_INT_MASK (0x10000000U) 8367 #define SYSCON_SYSAHBCLKCTRL0_GPIO_INT_SHIFT (28U) 8368 /*! GPIO_INT - Enable clock for GPIO pin interrupt registers 8369 * 0b0..disable 8370 * 0b1..enable 8371 */ 8372 #define SYSCON_SYSAHBCLKCTRL0_GPIO_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_GPIO_INT_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_GPIO_INT_MASK) 8373 #define SYSCON_SYSAHBCLKCTRL0_DMA_MASK (0x20000000U) 8374 #define SYSCON_SYSAHBCLKCTRL0_DMA_SHIFT (29U) 8375 /*! DMA - Enables clock for DMA. 8376 * 0b0..disable 8377 * 0b1..enable 8378 */ 8379 #define SYSCON_SYSAHBCLKCTRL0_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_DMA_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_DMA_MASK) 8380 #define SYSCON_SYSAHBCLKCTRL0_UART3_MASK (0x40000000U) 8381 #define SYSCON_SYSAHBCLKCTRL0_UART3_SHIFT (30U) 8382 /*! UART3 - Enables clock for UART3. 8383 * 0b0..disable 8384 * 0b1..enable 8385 */ 8386 #define SYSCON_SYSAHBCLKCTRL0_UART3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_UART3_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_UART3_MASK) 8387 #define SYSCON_SYSAHBCLKCTRL0_UART4_MASK (0x80000000U) 8388 #define SYSCON_SYSAHBCLKCTRL0_UART4_SHIFT (31U) 8389 /*! UART4 - Enables clock for UART4. 8390 * 0b0..disable 8391 * 0b1..enable 8392 */ 8393 #define SYSCON_SYSAHBCLKCTRL0_UART4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_UART4_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_UART4_MASK) 8394 /*! @} */ 8395 8396 /*! @name SYSAHBCLKCTRL1 - System clock group 1 control register */ 8397 /*! @{ */ 8398 #define SYSCON_SYSAHBCLKCTRL1_CAPT_MASK (0x1U) 8399 #define SYSCON_SYSAHBCLKCTRL1_CAPT_SHIFT (0U) 8400 /*! CAPT - Enables clock for CAPT. 8401 * 0b0..disable 8402 * 0b1..enable 8403 */ 8404 #define SYSCON_SYSAHBCLKCTRL1_CAPT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL1_CAPT_SHIFT)) & SYSCON_SYSAHBCLKCTRL1_CAPT_MASK) 8405 #define SYSCON_SYSAHBCLKCTRL1_DAC1_MASK (0x2U) 8406 #define SYSCON_SYSAHBCLKCTRL1_DAC1_SHIFT (1U) 8407 /*! DAC1 - Enables clock for DAC1. 8408 * 0b0..disable 8409 * 0b1..enable 8410 */ 8411 #define SYSCON_SYSAHBCLKCTRL1_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL1_DAC1_SHIFT)) & SYSCON_SYSAHBCLKCTRL1_DAC1_MASK) 8412 /*! @} */ 8413 8414 /*! @name PRESETCTRL0 - Peripheral reset group 0 control register */ 8415 /*! @{ */ 8416 #define SYSCON_PRESETCTRL0_FLASH_RST_N_MASK (0x10U) 8417 #define SYSCON_PRESETCTRL0_FLASH_RST_N_SHIFT (4U) 8418 /*! FLASH_RST_N - flash controller reset control 8419 * 0b0..Assert the flash controller reset. 8420 * 0b1..Clear the flash controller reset. 8421 */ 8422 #define SYSCON_PRESETCTRL0_FLASH_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_N_MASK) 8423 #define SYSCON_PRESETCTRL0_I2C0_RST_N_MASK (0x20U) 8424 #define SYSCON_PRESETCTRL0_I2C0_RST_N_SHIFT (5U) 8425 /*! I2C0_RST_N - I2C0 reset control 8426 * 0b0..Assert the I2C0 reset. 8427 * 0b1..Clear the I2C0 reset. 8428 */ 8429 #define SYSCON_PRESETCTRL0_I2C0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_I2C0_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_I2C0_RST_N_MASK) 8430 #define SYSCON_PRESETCTRL0_GPIO0_RST_N_MASK (0x40U) 8431 #define SYSCON_PRESETCTRL0_GPIO0_RST_N_SHIFT (6U) 8432 /*! GPIO0_RST_N - GPIO0 reset control 8433 * 0b0..Assert the GPIO0 reset. 8434 * 0b1..Clear the GPIO0 reset. 8435 */ 8436 #define SYSCON_PRESETCTRL0_GPIO0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_N_MASK) 8437 #define SYSCON_PRESETCTRL0_SWM_RST_N_MASK (0x80U) 8438 #define SYSCON_PRESETCTRL0_SWM_RST_N_SHIFT (7U) 8439 /*! SWM_RST_N - SWM reset control 8440 * 0b0..Assert the SWM reset. 8441 * 0b1..Clear the SWM reset. 8442 */ 8443 #define SYSCON_PRESETCTRL0_SWM_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SWM_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_SWM_RST_N_MASK) 8444 #define SYSCON_PRESETCTRL0_SCT_RST_N_MASK (0x100U) 8445 #define SYSCON_PRESETCTRL0_SCT_RST_N_SHIFT (8U) 8446 /*! SCT_RST_N - SCT reset control 8447 * 0b0..Assert the SCT reset. 8448 * 0b1..Clear the SCT reset. 8449 */ 8450 #define SYSCON_PRESETCTRL0_SCT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SCT_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_SCT_RST_N_MASK) 8451 #define SYSCON_PRESETCTRL0_WKT_RST_N_MASK (0x200U) 8452 #define SYSCON_PRESETCTRL0_WKT_RST_N_SHIFT (9U) 8453 /*! WKT_RST_N - Self-wake-up timer (WKT) reset control 8454 * 0b0..Assert the WKT reset. 8455 * 0b1..Clear the WKT reset. 8456 */ 8457 #define SYSCON_PRESETCTRL0_WKT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WKT_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_WKT_RST_N_MASK) 8458 #define SYSCON_PRESETCTRL0_MRT_RST_N_MASK (0x400U) 8459 #define SYSCON_PRESETCTRL0_MRT_RST_N_SHIFT (10U) 8460 /*! MRT_RST_N - Multi-rate timer (MRT) reset control 8461 * 0b0..Assert the MRT reset. 8462 * 0b1..Clear the MRT reset. 8463 */ 8464 #define SYSCON_PRESETCTRL0_MRT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MRT_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_MRT_RST_N_MASK) 8465 #define SYSCON_PRESETCTRL0_SPI0_RST_N_MASK (0x800U) 8466 #define SYSCON_PRESETCTRL0_SPI0_RST_N_SHIFT (11U) 8467 /*! SPI0_RST_N - SPI0 reset control 8468 * 0b0..Assert the SPI0 reset. 8469 * 0b1..Clear the SPI0 reset. 8470 */ 8471 #define SYSCON_PRESETCTRL0_SPI0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SPI0_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_SPI0_RST_N_MASK) 8472 #define SYSCON_PRESETCTRL0_SPI1_RST_N_MASK (0x1000U) 8473 #define SYSCON_PRESETCTRL0_SPI1_RST_N_SHIFT (12U) 8474 /*! SPI1_RST_N - SPI1 reset control 8475 * 0b0..Assert the SPI1 reset. 8476 * 0b1..Clear the SPI1 reset. 8477 */ 8478 #define SYSCON_PRESETCTRL0_SPI1_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SPI1_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_SPI1_RST_N_MASK) 8479 #define SYSCON_PRESETCTRL0_CRC_RST_N_MASK (0x2000U) 8480 #define SYSCON_PRESETCTRL0_CRC_RST_N_SHIFT (13U) 8481 /*! CRC_RST_N - CRC engine reset control 8482 * 0b0..Assert the CRC reset. 8483 * 0b1..Clear the CRC reset. 8484 */ 8485 #define SYSCON_PRESETCTRL0_CRC_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRC_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_CRC_RST_N_MASK) 8486 #define SYSCON_PRESETCTRL0_UART0_RST_N_MASK (0x4000U) 8487 #define SYSCON_PRESETCTRL0_UART0_RST_N_SHIFT (14U) 8488 /*! UART0_RST_N - UART0 reset control 8489 * 0b0..Assert the UART0 reset. 8490 * 0b1..Clear the UART0 reset. 8491 */ 8492 #define SYSCON_PRESETCTRL0_UART0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_UART0_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_UART0_RST_N_MASK) 8493 #define SYSCON_PRESETCTRL0_UART1_RST_N_MASK (0x8000U) 8494 #define SYSCON_PRESETCTRL0_UART1_RST_N_SHIFT (15U) 8495 /*! UART1_RST_N - UART1 reset control 8496 * 0b0..Assert the UART1 reset. 8497 * 0b1..Clear the UART1 reset. 8498 */ 8499 #define SYSCON_PRESETCTRL0_UART1_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_UART1_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_UART1_RST_N_MASK) 8500 #define SYSCON_PRESETCTRL0_UART2_RST_N_MASK (0x10000U) 8501 #define SYSCON_PRESETCTRL0_UART2_RST_N_SHIFT (16U) 8502 /*! UART2_RST_N - UART2 reset control 8503 * 0b0..Assert the UART2 reset. 8504 * 0b1..Clear the UART2 reset. 8505 */ 8506 #define SYSCON_PRESETCTRL0_UART2_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_UART2_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_UART2_RST_N_MASK) 8507 #define SYSCON_PRESETCTRL0_IOCON_RST_N_MASK (0x40000U) 8508 #define SYSCON_PRESETCTRL0_IOCON_RST_N_SHIFT (18U) 8509 /*! IOCON_RST_N - IOCON reset control 8510 * 0b0..Assert the IOCON reset. 8511 * 0b1..Clear the IOCON reset. 8512 */ 8513 #define SYSCON_PRESETCTRL0_IOCON_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_N_MASK) 8514 #define SYSCON_PRESETCTRL0_ACMP_RST_N_MASK (0x80000U) 8515 #define SYSCON_PRESETCTRL0_ACMP_RST_N_SHIFT (19U) 8516 /*! ACMP_RST_N - Analog comparator reset control 8517 * 0b0..Assert the analog comparator reset. 8518 * 0b1..Clear the analog comparator reset. 8519 */ 8520 #define SYSCON_PRESETCTRL0_ACMP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ACMP_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_ACMP_RST_N_MASK) 8521 #define SYSCON_PRESETCTRL0_GPIO1_RST_N_MASK (0x100000U) 8522 #define SYSCON_PRESETCTRL0_GPIO1_RST_N_SHIFT (20U) 8523 /*! GPIO1_RST_N - GPIO1 reset control 8524 * 0b0..Assert the GPIO1 reset. 8525 * 0b1..Clear the GPIO1 reset. 8526 */ 8527 #define SYSCON_PRESETCTRL0_GPIO1_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_N_MASK) 8528 #define SYSCON_PRESETCTRL0_I2C1_RST_N_MASK (0x200000U) 8529 #define SYSCON_PRESETCTRL0_I2C1_RST_N_SHIFT (21U) 8530 /*! I2C1_RST_N - I2C1 reset control 8531 * 0b0..Assert the I2C1 reset. 8532 * 0b1..Clear the I2C1 reset. 8533 */ 8534 #define SYSCON_PRESETCTRL0_I2C1_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_I2C1_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_I2C1_RST_N_MASK) 8535 #define SYSCON_PRESETCTRL0_I2C2_RST_N_MASK (0x400000U) 8536 #define SYSCON_PRESETCTRL0_I2C2_RST_N_SHIFT (22U) 8537 /*! I2C2_RST_N - I2C2 reset control 8538 * 0b0..Assert the I2C2 reset. 8539 * 0b1..Clear the I2C2 reset. 8540 */ 8541 #define SYSCON_PRESETCTRL0_I2C2_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_I2C2_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_I2C2_RST_N_MASK) 8542 #define SYSCON_PRESETCTRL0_I2C3_RST_N_MASK (0x800000U) 8543 #define SYSCON_PRESETCTRL0_I2C3_RST_N_SHIFT (23U) 8544 /*! I2C3_RST_N - I2C3 reset control 8545 * 0b0..Assert the I2C3 reset. 8546 * 0b1..Clear the I2C3 reset. 8547 */ 8548 #define SYSCON_PRESETCTRL0_I2C3_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_I2C3_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_I2C3_RST_N_MASK) 8549 #define SYSCON_PRESETCTRL0_ADC_RST_N_MASK (0x1000000U) 8550 #define SYSCON_PRESETCTRL0_ADC_RST_N_SHIFT (24U) 8551 /*! ADC_RST_N - ADC reset control 8552 * 0b0..Assert the ADC reset. 8553 * 0b1..Clear the ADC reset. 8554 */ 8555 #define SYSCON_PRESETCTRL0_ADC_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_N_MASK) 8556 #define SYSCON_PRESETCTRL0_CTIMER_RST_N_MASK (0x2000000U) 8557 #define SYSCON_PRESETCTRL0_CTIMER_RST_N_SHIFT (25U) 8558 /*! CTIMER_RST_N - CTIMER reset control 8559 * 0b0..Assert the CTIMER reset. 8560 * 0b1..Clear the CTIMER reset. 8561 */ 8562 #define SYSCON_PRESETCTRL0_CTIMER_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CTIMER_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_CTIMER_RST_N_MASK) 8563 #define SYSCON_PRESETCTRL0_DAC0_RST_N_MASK (0x8000000U) 8564 #define SYSCON_PRESETCTRL0_DAC0_RST_N_SHIFT (27U) 8565 /*! DAC0_RST_N - DAC0 reset control 8566 * 0b0..Assert the DAC0 reset. 8567 * 0b1..Clear the DAC0 reset. 8568 */ 8569 #define SYSCON_PRESETCTRL0_DAC0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DAC0_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_DAC0_RST_N_MASK) 8570 #define SYSCON_PRESETCTRL0_GPIOINT_RST_N_MASK (0x10000000U) 8571 #define SYSCON_PRESETCTRL0_GPIOINT_RST_N_SHIFT (28U) 8572 /*! GPIOINT_RST_N - GPIOINT reset control 8573 * 0b0..Assert the GPIOINT reset. 8574 * 0b1..Clear the GPIOINT reset. 8575 */ 8576 #define SYSCON_PRESETCTRL0_GPIOINT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIOINT_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_GPIOINT_RST_N_MASK) 8577 #define SYSCON_PRESETCTRL0_DMA_RST_N_MASK (0x20000000U) 8578 #define SYSCON_PRESETCTRL0_DMA_RST_N_SHIFT (29U) 8579 /*! DMA_RST_N - DMA reset control 8580 * 0b0..Assert the DMA reset. 8581 * 0b1..Clear the DMA reset. 8582 */ 8583 #define SYSCON_PRESETCTRL0_DMA_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_DMA_RST_N_MASK) 8584 #define SYSCON_PRESETCTRL0_UART3_RST_N_MASK (0x40000000U) 8585 #define SYSCON_PRESETCTRL0_UART3_RST_N_SHIFT (30U) 8586 /*! UART3_RST_N - UART3 reset control 8587 * 0b0..Assert the UART3 reset. 8588 * 0b1..Clear the UART3 reset. 8589 */ 8590 #define SYSCON_PRESETCTRL0_UART3_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_UART3_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_UART3_RST_N_MASK) 8591 #define SYSCON_PRESETCTRL0_UART4_RST_N_MASK (0x80000000U) 8592 #define SYSCON_PRESETCTRL0_UART4_RST_N_SHIFT (31U) 8593 /*! UART4_RST_N - UART4 reset control 8594 * 0b0..Assert the UART4 reset. 8595 * 0b1..Clear the UART4 reset. 8596 */ 8597 #define SYSCON_PRESETCTRL0_UART4_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_UART4_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_UART4_RST_N_MASK) 8598 /*! @} */ 8599 8600 /*! @name PRESETCTRL1 - Peripheral reset group 1 control register */ 8601 /*! @{ */ 8602 #define SYSCON_PRESETCTRL1_CAPT_RST_N_MASK (0x1U) 8603 #define SYSCON_PRESETCTRL1_CAPT_RST_N_SHIFT (0U) 8604 /*! CAPT_RST_N - Capacitive touch reset control 8605 * 0b0..Assert the capacitive touch reset. 8606 * 0b1..Clear the capacitive touch reset. 8607 */ 8608 #define SYSCON_PRESETCTRL1_CAPT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_CAPT_RST_N_SHIFT)) & SYSCON_PRESETCTRL1_CAPT_RST_N_MASK) 8609 #define SYSCON_PRESETCTRL1_DAC1_RST_N_MASK (0x2U) 8610 #define SYSCON_PRESETCTRL1_DAC1_RST_N_SHIFT (1U) 8611 /*! DAC1_RST_N - DAC1 reset control 8612 * 0b0..Assert the DAC1 reset. 8613 * 0b1..Clear the DAC1 reset. 8614 */ 8615 #define SYSCON_PRESETCTRL1_DAC1_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_DAC1_RST_N_SHIFT)) & SYSCON_PRESETCTRL1_DAC1_RST_N_MASK) 8616 #define SYSCON_PRESETCTRL1_FRG0_RST_N_MASK (0x8U) 8617 #define SYSCON_PRESETCTRL1_FRG0_RST_N_SHIFT (3U) 8618 /*! FRG0_RST_N - Fractional baud rate generator 0 reset control 8619 * 0b0..Assert the FRG0 reset. 8620 * 0b1..Clear the FRG0 reset. 8621 */ 8622 #define SYSCON_PRESETCTRL1_FRG0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FRG0_RST_N_SHIFT)) & SYSCON_PRESETCTRL1_FRG0_RST_N_MASK) 8623 #define SYSCON_PRESETCTRL1_FRG1_RST_N_MASK (0x10U) 8624 #define SYSCON_PRESETCTRL1_FRG1_RST_N_SHIFT (4U) 8625 /*! FRG1_RST_N - Fractional baud rate generator 1 reset control 8626 * 0b0..Assert the FRG1 reset. 8627 * 0b1..Clear the FRG1 reset. 8628 */ 8629 #define SYSCON_PRESETCTRL1_FRG1_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FRG1_RST_N_SHIFT)) & SYSCON_PRESETCTRL1_FRG1_RST_N_MASK) 8630 /*! @} */ 8631 8632 /*! @name FCLKSEL - peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register. */ 8633 /*! @{ */ 8634 #define SYSCON_FCLKSEL_SEL_MASK (0x7U) 8635 #define SYSCON_FCLKSEL_SEL_SHIFT (0U) 8636 /*! SEL - Peripheral clock source 8637 * 0b000..FRO 8638 * 0b001..main clock 8639 * 0b010..Frg0clk 8640 * 0b011..Frg1clk 8641 * 0b100..FRO_DIV 8642 * 0b101..none 8643 * 0b110..none 8644 * 0b111..none 8645 */ 8646 #define SYSCON_FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL_SEL_SHIFT)) & SYSCON_FCLKSEL_SEL_MASK) 8647 /*! @} */ 8648 8649 /* The count of SYSCON_FCLKSEL */ 8650 #define SYSCON_FCLKSEL_COUNT (11U) 8651 8652 /*! @name FRG_FRGDIV - fractional generator N divider value register */ 8653 /*! @{ */ 8654 #define SYSCON_FRG_FRGDIV_DIV_MASK (0xFFU) 8655 #define SYSCON_FRG_FRGDIV_DIV_SHIFT (0U) 8656 /*! DIV - Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set 8657 * to 0xFF to use with the fractional baud rate generator. 8658 */ 8659 #define SYSCON_FRG_FRGDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRG_FRGDIV_DIV_SHIFT)) & SYSCON_FRG_FRGDIV_DIV_MASK) 8660 /*! @} */ 8661 8662 /* The count of SYSCON_FRG_FRGDIV */ 8663 #define SYSCON_FRG_FRGDIV_COUNT (2U) 8664 8665 /*! @name FRG_FRGMULT - fractional generator N multiplier value register */ 8666 /*! @{ */ 8667 #define SYSCON_FRG_FRGMULT_MULT_MASK (0xFFU) 8668 #define SYSCON_FRG_FRGMULT_MULT_SHIFT (0U) 8669 /*! MULT - Numerator of the fractional divider. MULT is equal to the programmed value. 8670 */ 8671 #define SYSCON_FRG_FRGMULT_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRG_FRGMULT_MULT_SHIFT)) & SYSCON_FRG_FRGMULT_MULT_MASK) 8672 /*! @} */ 8673 8674 /* The count of SYSCON_FRG_FRGMULT */ 8675 #define SYSCON_FRG_FRGMULT_COUNT (2U) 8676 8677 /*! @name FRG_FRGCLKSEL - FRG N clock source select register */ 8678 /*! @{ */ 8679 #define SYSCON_FRG_FRGCLKSEL_SEL_MASK (0x3U) 8680 #define SYSCON_FRG_FRGCLKSEL_SEL_SHIFT (0U) 8681 /*! SEL - Clock source for frgN_src clock 8682 * 0b00..FRO 8683 * 0b01..main clock 8684 * 0b10..sys pll 8685 * 0b11..None 8686 */ 8687 #define SYSCON_FRG_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRG_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRG_FRGCLKSEL_SEL_MASK) 8688 /*! @} */ 8689 8690 /* The count of SYSCON_FRG_FRGCLKSEL */ 8691 #define SYSCON_FRG_FRGCLKSEL_COUNT (2U) 8692 8693 /*! @name CLKOUTSEL - CLKOUT clock source select register */ 8694 /*! @{ */ 8695 #define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) 8696 #define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) 8697 /*! SEL - CLKOUT clock source 8698 * 0b000..FRO 8699 * 0b001..main clock 8700 * 0b010..sys pll 8701 * 0b011..external clock 8702 * 0b100..Watchdog oscillator 8703 * 0b101..None 8704 * 0b110..None 8705 * 0b111..None 8706 */ 8707 #define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) 8708 /*! @} */ 8709 8710 /*! @name CLKOUTDIV - CLKOUT clock divider registers */ 8711 /*! @{ */ 8712 #define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) 8713 #define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) 8714 /*! DIV - CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255. 8715 */ 8716 #define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) 8717 /*! @} */ 8718 8719 /*! @name EXTTRACECMD - External trace buffer command register */ 8720 /*! @{ */ 8721 #define SYSCON_EXTTRACECMD_START_MASK (0x1U) 8722 #define SYSCON_EXTTRACECMD_START_SHIFT (0U) 8723 /*! START - Trace start command. Writing a one to this bit sets the TSTART signal to the MTB to HIGH 8724 * and starts tracing if the TSTARTEN bit in the MTB master register is set to one as well. 8725 */ 8726 #define SYSCON_EXTTRACECMD_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EXTTRACECMD_START_SHIFT)) & SYSCON_EXTTRACECMD_START_MASK) 8727 #define SYSCON_EXTTRACECMD_STOP_MASK (0x2U) 8728 #define SYSCON_EXTTRACECMD_STOP_SHIFT (1U) 8729 /*! STOP - Trace stop command. Writing a one to this bit sets the TSTOP signal in the MTB to HIGH 8730 * and stops tracing if the TSTOPEN bit in the MTB master register is set to one as well. 8731 */ 8732 #define SYSCON_EXTTRACECMD_STOP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EXTTRACECMD_STOP_SHIFT)) & SYSCON_EXTTRACECMD_STOP_MASK) 8733 /*! @} */ 8734 8735 /*! @name PIOPORCAP - POR captured PIO N status register(PIO0 has 32 PIOs, PIO1 has 22 PIOs) */ 8736 /*! @{ */ 8737 #define SYSCON_PIOPORCAP_PIOSTAT_MASK (0xFFFFFFFFU) 8738 #define SYSCON_PIOPORCAP_PIOSTAT_SHIFT (0U) 8739 /*! PIOSTAT - State of PION_31 through PION_0 at power-on reset 8740 */ 8741 #define SYSCON_PIOPORCAP_PIOSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOSTAT_SHIFT)) & SYSCON_PIOPORCAP_PIOSTAT_MASK) 8742 /*! @} */ 8743 8744 /* The count of SYSCON_PIOPORCAP */ 8745 #define SYSCON_PIOPORCAP_COUNT (2U) 8746 8747 /*! @name IOCONCLKDIV6 - Peripheral clock 6 to the IOCON block for programmable glitch filter */ 8748 /*! @{ */ 8749 #define SYSCON_IOCONCLKDIV6_DIV_MASK (0xFFU) 8750 #define SYSCON_IOCONCLKDIV6_DIV_SHIFT (0U) 8751 /*! DIV - IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 8752 */ 8753 #define SYSCON_IOCONCLKDIV6_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_IOCONCLKDIV6_DIV_SHIFT)) & SYSCON_IOCONCLKDIV6_DIV_MASK) 8754 /*! @} */ 8755 8756 /*! @name IOCONCLKDIV5 - Peripheral clock 6 to the IOCON block for programmable glitch filter */ 8757 /*! @{ */ 8758 #define SYSCON_IOCONCLKDIV5_DIV_MASK (0xFFU) 8759 #define SYSCON_IOCONCLKDIV5_DIV_SHIFT (0U) 8760 /*! DIV - IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 8761 */ 8762 #define SYSCON_IOCONCLKDIV5_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_IOCONCLKDIV5_DIV_SHIFT)) & SYSCON_IOCONCLKDIV5_DIV_MASK) 8763 /*! @} */ 8764 8765 /*! @name IOCONCLKDIV4 - Peripheral clock 4 to the IOCON block for programmable glitch filter */ 8766 /*! @{ */ 8767 #define SYSCON_IOCONCLKDIV4_DIV_MASK (0xFFU) 8768 #define SYSCON_IOCONCLKDIV4_DIV_SHIFT (0U) 8769 /*! DIV - IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 8770 */ 8771 #define SYSCON_IOCONCLKDIV4_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_IOCONCLKDIV4_DIV_SHIFT)) & SYSCON_IOCONCLKDIV4_DIV_MASK) 8772 /*! @} */ 8773 8774 /*! @name IOCONCLKDIV3 - Peripheral clock 3 to the IOCON block for programmable glitch filter */ 8775 /*! @{ */ 8776 #define SYSCON_IOCONCLKDIV3_DIV_MASK (0xFFU) 8777 #define SYSCON_IOCONCLKDIV3_DIV_SHIFT (0U) 8778 /*! DIV - IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 8779 */ 8780 #define SYSCON_IOCONCLKDIV3_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_IOCONCLKDIV3_DIV_SHIFT)) & SYSCON_IOCONCLKDIV3_DIV_MASK) 8781 /*! @} */ 8782 8783 /*! @name IOCONCLKDIV2 - Peripheral clock 2 to the IOCON block for programmable glitch filter */ 8784 /*! @{ */ 8785 #define SYSCON_IOCONCLKDIV2_DIV_MASK (0xFFU) 8786 #define SYSCON_IOCONCLKDIV2_DIV_SHIFT (0U) 8787 /*! DIV - IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 8788 */ 8789 #define SYSCON_IOCONCLKDIV2_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_IOCONCLKDIV2_DIV_SHIFT)) & SYSCON_IOCONCLKDIV2_DIV_MASK) 8790 /*! @} */ 8791 8792 /*! @name IOCONCLKDIV1 - Peripheral clock 1 to the IOCON block for programmable glitch filter */ 8793 /*! @{ */ 8794 #define SYSCON_IOCONCLKDIV1_DIV_MASK (0xFFU) 8795 #define SYSCON_IOCONCLKDIV1_DIV_SHIFT (0U) 8796 /*! DIV - IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 8797 */ 8798 #define SYSCON_IOCONCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_IOCONCLKDIV1_DIV_SHIFT)) & SYSCON_IOCONCLKDIV1_DIV_MASK) 8799 /*! @} */ 8800 8801 /*! @name IOCONCLKDIV0 - Peripheral clock 0 to the IOCON block for programmable glitch filter */ 8802 /*! @{ */ 8803 #define SYSCON_IOCONCLKDIV0_DIV_MASK (0xFFU) 8804 #define SYSCON_IOCONCLKDIV0_DIV_SHIFT (0U) 8805 /*! DIV - IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 8806 */ 8807 #define SYSCON_IOCONCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_IOCONCLKDIV0_DIV_SHIFT)) & SYSCON_IOCONCLKDIV0_DIV_MASK) 8808 /*! @} */ 8809 8810 /*! @name BODCTRL - BOD control register */ 8811 /*! @{ */ 8812 #define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U) 8813 #define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U) 8814 /*! BODRSTLEV - BOD reset level 8815 * 0b00..Reserved 8816 * 0b01..Level 1 8817 * 0b10..Level 2 8818 * 0b11..Level 3 8819 */ 8820 #define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK) 8821 #define SYSCON_BODCTRL_BODINTVAL_MASK (0xCU) 8822 #define SYSCON_BODCTRL_BODINTVAL_SHIFT (2U) 8823 /*! BODINTVAL - BOD interrupt level 8824 * 0b00..Reserved 8825 * 0b01..Level 1 8826 * 0b10..Level 2 8827 * 0b11..Level 3 8828 */ 8829 #define SYSCON_BODCTRL_BODINTVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTVAL_SHIFT)) & SYSCON_BODCTRL_BODINTVAL_MASK) 8830 #define SYSCON_BODCTRL_BODRSTENA_MASK (0x10U) 8831 #define SYSCON_BODCTRL_BODRSTENA_SHIFT (4U) 8832 /*! BODRSTENA - BOD reset enable 8833 * 0b0..Disable reset function. 8834 * 0b1..Enable reset function. 8835 */ 8836 #define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK) 8837 /*! @} */ 8838 8839 /*! @name SYSTCKCAL - System tick timer calibration register */ 8840 /*! @{ */ 8841 #define SYSCON_SYSTCKCAL_CAL_MASK (0x3FFFFFFU) 8842 #define SYSCON_SYSTCKCAL_CAL_SHIFT (0U) 8843 /*! CAL - System tick timer calibration value. 8844 */ 8845 #define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK) 8846 /*! @} */ 8847 8848 /*! @name IRQLATENCY - IRQ latency register */ 8849 /*! @{ */ 8850 #define SYSCON_IRQLATENCY_LATENCY_MASK (0xFFU) 8851 #define SYSCON_IRQLATENCY_LATENCY_SHIFT (0U) 8852 /*! LATENCY - 8-bit latency value. 8853 */ 8854 #define SYSCON_IRQLATENCY_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_IRQLATENCY_LATENCY_SHIFT)) & SYSCON_IRQLATENCY_LATENCY_MASK) 8855 /*! @} */ 8856 8857 /*! @name NMISRC - NMI source selection register */ 8858 /*! @{ */ 8859 #define SYSCON_NMISRC_IRQN_MASK (0x1FU) 8860 #define SYSCON_NMISRC_IRQN_SHIFT (0U) 8861 /*! IRQN - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1 8862 */ 8863 #define SYSCON_NMISRC_IRQN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQN_SHIFT)) & SYSCON_NMISRC_IRQN_MASK) 8864 #define SYSCON_NMISRC_NMIEN_MASK (0x80000000U) 8865 #define SYSCON_NMISRC_NMIEN_SHIFT (31U) 8866 /*! NMIEN - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0. 8867 */ 8868 #define SYSCON_NMISRC_NMIEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIEN_SHIFT)) & SYSCON_NMISRC_NMIEN_MASK) 8869 /*! @} */ 8870 8871 /*! @name PINTSEL - Pin interrupt select registers N */ 8872 /*! @{ */ 8873 #define SYSCON_PINTSEL_INTPIN_MASK (0x3FU) 8874 #define SYSCON_PINTSEL_INTPIN_SHIFT (0U) 8875 /*! INTPIN - Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to 8876 * PIO0_31correspond to numbers 0 to 31 and PIO1_0 to PIO1_31 correspond to numbers 32 to 63). 8877 */ 8878 #define SYSCON_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PINTSEL_INTPIN_SHIFT)) & SYSCON_PINTSEL_INTPIN_MASK) 8879 /*! @} */ 8880 8881 /* The count of SYSCON_PINTSEL */ 8882 #define SYSCON_PINTSEL_COUNT (8U) 8883 8884 /*! @name STARTERP0 - Start logic 0 pin wake-up enable register 0 */ 8885 /*! @{ */ 8886 #define SYSCON_STARTERP0_PINT0_MASK (0x1U) 8887 #define SYSCON_STARTERP0_PINT0_SHIFT (0U) 8888 /*! PINT0 - GPIO pin interrupt 0 wake-up 8889 * 0b0..Disabled 8890 * 0b1..Enabled 8891 */ 8892 #define SYSCON_STARTERP0_PINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT0_SHIFT)) & SYSCON_STARTERP0_PINT0_MASK) 8893 #define SYSCON_STARTERP0_PINT1_MASK (0x2U) 8894 #define SYSCON_STARTERP0_PINT1_SHIFT (1U) 8895 /*! PINT1 - GPIO pin interrupt 1 wake-up 8896 * 0b0..Disabled 8897 * 0b1..Enabled 8898 */ 8899 #define SYSCON_STARTERP0_PINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT1_SHIFT)) & SYSCON_STARTERP0_PINT1_MASK) 8900 #define SYSCON_STARTERP0_PINT2_MASK (0x4U) 8901 #define SYSCON_STARTERP0_PINT2_SHIFT (2U) 8902 /*! PINT2 - GPIO pin interrupt 2 wake-up 8903 * 0b0..Disabled 8904 * 0b1..Enabled 8905 */ 8906 #define SYSCON_STARTERP0_PINT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT2_SHIFT)) & SYSCON_STARTERP0_PINT2_MASK) 8907 #define SYSCON_STARTERP0_PINT3_MASK (0x8U) 8908 #define SYSCON_STARTERP0_PINT3_SHIFT (3U) 8909 /*! PINT3 - GPIO pin interrupt 3 wake-up 8910 * 0b0..Disabled 8911 * 0b1..Enabled 8912 */ 8913 #define SYSCON_STARTERP0_PINT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT3_SHIFT)) & SYSCON_STARTERP0_PINT3_MASK) 8914 #define SYSCON_STARTERP0_PINT4_MASK (0x10U) 8915 #define SYSCON_STARTERP0_PINT4_SHIFT (4U) 8916 /*! PINT4 - GPIO pin interrupt 4 wake-up 8917 * 0b0..Disabled 8918 * 0b1..Enabled 8919 */ 8920 #define SYSCON_STARTERP0_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT4_SHIFT)) & SYSCON_STARTERP0_PINT4_MASK) 8921 #define SYSCON_STARTERP0_PINT5_MASK (0x20U) 8922 #define SYSCON_STARTERP0_PINT5_SHIFT (5U) 8923 /*! PINT5 - GPIO pin interrupt 5 wake-up 8924 * 0b0..Disabled 8925 * 0b1..Enabled 8926 */ 8927 #define SYSCON_STARTERP0_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT5_SHIFT)) & SYSCON_STARTERP0_PINT5_MASK) 8928 #define SYSCON_STARTERP0_PINT6_MASK (0x40U) 8929 #define SYSCON_STARTERP0_PINT6_SHIFT (6U) 8930 /*! PINT6 - GPIO pin interrupt 6 wake-up 8931 * 0b0..Disabled 8932 * 0b1..Enabled 8933 */ 8934 #define SYSCON_STARTERP0_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT6_SHIFT)) & SYSCON_STARTERP0_PINT6_MASK) 8935 #define SYSCON_STARTERP0_PINT7_MASK (0x80U) 8936 #define SYSCON_STARTERP0_PINT7_SHIFT (7U) 8937 /*! PINT7 - GPIO pin interrupt 7 wake-up 8938 * 0b0..Disabled 8939 * 0b1..Enabled 8940 */ 8941 #define SYSCON_STARTERP0_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT7_SHIFT)) & SYSCON_STARTERP0_PINT7_MASK) 8942 /*! @} */ 8943 8944 /*! @name STARTERP1 - Start logic 0 pin wake-up enable register 1 */ 8945 /*! @{ */ 8946 #define SYSCON_STARTERP1_SPI0_MASK (0x1U) 8947 #define SYSCON_STARTERP1_SPI0_SHIFT (0U) 8948 /*! SPI0 - SPI0 interrupt wake-up 8949 * 0b0..Disabled 8950 * 0b1..Enabled 8951 */ 8952 #define SYSCON_STARTERP1_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_SPI0_SHIFT)) & SYSCON_STARTERP1_SPI0_MASK) 8953 #define SYSCON_STARTERP1_SPI1_MASK (0x2U) 8954 #define SYSCON_STARTERP1_SPI1_SHIFT (1U) 8955 /*! SPI1 - SPI1 interrupt wake-up 8956 * 0b0..Disabled 8957 * 0b1..Enabled 8958 */ 8959 #define SYSCON_STARTERP1_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_SPI1_SHIFT)) & SYSCON_STARTERP1_SPI1_MASK) 8960 #define SYSCON_STARTERP1_USART0_MASK (0x8U) 8961 #define SYSCON_STARTERP1_USART0_SHIFT (3U) 8962 /*! USART0 - USART0 interrupt wake-up. Configure USART in synchronous slave mode. 8963 * 0b0..Disabled 8964 * 0b1..Enabled 8965 */ 8966 #define SYSCON_STARTERP1_USART0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_USART0_SHIFT)) & SYSCON_STARTERP1_USART0_MASK) 8967 #define SYSCON_STARTERP1_USART1_MASK (0x10U) 8968 #define SYSCON_STARTERP1_USART1_SHIFT (4U) 8969 /*! USART1 - USART1 interrupt wake-up. Configure USART in synchronous slave mode. 8970 * 0b0..Disabled 8971 * 0b1..Enabled 8972 */ 8973 #define SYSCON_STARTERP1_USART1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_USART1_SHIFT)) & SYSCON_STARTERP1_USART1_MASK) 8974 #define SYSCON_STARTERP1_USART2_MASK (0x20U) 8975 #define SYSCON_STARTERP1_USART2_SHIFT (5U) 8976 /*! USART2 - USART2 interrupt wake-up. Configure USART in synchronous slave mode. 8977 * 0b0..Disabled 8978 * 0b1..Enabled 8979 */ 8980 #define SYSCON_STARTERP1_USART2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_USART2_SHIFT)) & SYSCON_STARTERP1_USART2_MASK) 8981 #define SYSCON_STARTERP1_I2C1_MASK (0x80U) 8982 #define SYSCON_STARTERP1_I2C1_SHIFT (7U) 8983 /*! I2C1 - I2C1 interrupt wake-up. 8984 * 0b0..Disabled 8985 * 0b1..Enabled 8986 */ 8987 #define SYSCON_STARTERP1_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_I2C1_SHIFT)) & SYSCON_STARTERP1_I2C1_MASK) 8988 #define SYSCON_STARTERP1_I2C0_MASK (0x100U) 8989 #define SYSCON_STARTERP1_I2C0_SHIFT (8U) 8990 /*! I2C0 - I2C0 interrupt wake-up. 8991 * 0b0..Disabled 8992 * 0b1..Enabled 8993 */ 8994 #define SYSCON_STARTERP1_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_I2C0_SHIFT)) & SYSCON_STARTERP1_I2C0_MASK) 8995 #define SYSCON_STARTERP1_Cap_Touch_MASK (0x800U) 8996 #define SYSCON_STARTERP1_Cap_Touch_SHIFT (11U) 8997 /*! Cap_Touch - Cap Touch interrupt wake-up. 8998 * 0b0..Disabled 8999 * 0b1..Enabled 9000 */ 9001 #define SYSCON_STARTERP1_Cap_Touch(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_Cap_Touch_SHIFT)) & SYSCON_STARTERP1_Cap_Touch_MASK) 9002 #define SYSCON_STARTERP1_WWDT_MASK (0x1000U) 9003 #define SYSCON_STARTERP1_WWDT_SHIFT (12U) 9004 /*! WWDT - WWDT interrupt wake-up 9005 * 0b0..Disabled 9006 * 0b1..Enabled 9007 */ 9008 #define SYSCON_STARTERP1_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_WWDT_SHIFT)) & SYSCON_STARTERP1_WWDT_MASK) 9009 #define SYSCON_STARTERP1_BOD_MASK (0x2000U) 9010 #define SYSCON_STARTERP1_BOD_SHIFT (13U) 9011 /*! BOD - BOD interrupt wake-up 9012 * 0b0..Disabled 9013 * 0b1..Enabled 9014 */ 9015 #define SYSCON_STARTERP1_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_BOD_SHIFT)) & SYSCON_STARTERP1_BOD_MASK) 9016 #define SYSCON_STARTERP1_WKT_MASK (0x8000U) 9017 #define SYSCON_STARTERP1_WKT_SHIFT (15U) 9018 /*! WKT - Self-wake-up timer interrupt wake-up 9019 * 0b0..Disabled 9020 * 0b1..Enabled 9021 */ 9022 #define SYSCON_STARTERP1_WKT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_WKT_SHIFT)) & SYSCON_STARTERP1_WKT_MASK) 9023 #define SYSCON_STARTERP1_I2C2_MASK (0x200000U) 9024 #define SYSCON_STARTERP1_I2C2_SHIFT (21U) 9025 /*! I2C2 - I2C2 interrupt wake-up 9026 * 0b0..Disabled 9027 * 0b1..Enabled 9028 */ 9029 #define SYSCON_STARTERP1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_I2C2_SHIFT)) & SYSCON_STARTERP1_I2C2_MASK) 9030 #define SYSCON_STARTERP1_I2C3_MASK (0x400000U) 9031 #define SYSCON_STARTERP1_I2C3_SHIFT (22U) 9032 /*! I2C3 - I2C3 interrupt wake-up 9033 * 0b0..Disabled 9034 * 0b1..Enabled 9035 */ 9036 #define SYSCON_STARTERP1_I2C3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_I2C3_SHIFT)) & SYSCON_STARTERP1_I2C3_MASK) 9037 #define SYSCON_STARTERP1_UART3_MASK (0x40000000U) 9038 #define SYSCON_STARTERP1_UART3_SHIFT (30U) 9039 /*! UART3 - UART3 interrupt wake-up 9040 * 0b0..Disabled 9041 * 0b1..Enabled 9042 */ 9043 #define SYSCON_STARTERP1_UART3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_UART3_SHIFT)) & SYSCON_STARTERP1_UART3_MASK) 9044 #define SYSCON_STARTERP1_UART4_MASK (0x80000000U) 9045 #define SYSCON_STARTERP1_UART4_SHIFT (31U) 9046 /*! UART4 - UART4 interrupt wake-up 9047 * 0b0..Disabled 9048 * 0b1..Enabled 9049 */ 9050 #define SYSCON_STARTERP1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_UART4_SHIFT)) & SYSCON_STARTERP1_UART4_MASK) 9051 /*! @} */ 9052 9053 /*! @name PDSLEEPCFG - Deep-sleep configuration register */ 9054 /*! @{ */ 9055 #define SYSCON_PDSLEEPCFG_BOD_PD_MASK (0x8U) 9056 #define SYSCON_PDSLEEPCFG_BOD_PD_SHIFT (3U) 9057 /*! BOD_PD - BOD power-down control for Deep-sleep and Power-down mode 9058 * 0b0..powered 9059 * 0b1..powered down 9060 */ 9061 #define SYSCON_PDSLEEPCFG_BOD_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_BOD_PD_SHIFT)) & SYSCON_PDSLEEPCFG_BOD_PD_MASK) 9062 #define SYSCON_PDSLEEPCFG_WDTOSC_PD_MASK (0x40U) 9063 #define SYSCON_PDSLEEPCFG_WDTOSC_PD_SHIFT (6U) 9064 /*! WDTOSC_PD - Watchdog oscillator power-down control for Deep-sleep and Power-down mode. Changing 9065 * this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In 9066 * this case, the watchdog oscillator is always running. 9067 * 0b0..Disabled 9068 * 0b1..Enabled 9069 */ 9070 #define SYSCON_PDSLEEPCFG_WDTOSC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_WDTOSC_PD_SHIFT)) & SYSCON_PDSLEEPCFG_WDTOSC_PD_MASK) 9071 /*! @} */ 9072 9073 /*! @name PDAWAKECFG - Wake-up configuration register */ 9074 /*! @{ */ 9075 #define SYSCON_PDAWAKECFG_FROOUT_PD_MASK (0x1U) 9076 #define SYSCON_PDAWAKECFG_FROOUT_PD_SHIFT (0U) 9077 /*! FROOUT_PD - FRO oscillator output wake-up configuration 9078 * 0b0..powered 9079 * 0b1..powered down 9080 */ 9081 #define SYSCON_PDAWAKECFG_FROOUT_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_FROOUT_PD_SHIFT)) & SYSCON_PDAWAKECFG_FROOUT_PD_MASK) 9082 #define SYSCON_PDAWAKECFG_FRO_PD_MASK (0x2U) 9083 #define SYSCON_PDAWAKECFG_FRO_PD_SHIFT (1U) 9084 /*! FRO_PD - FRO oscillator power-down wake-up configuration 9085 * 0b0..powered 9086 * 0b1..powered down 9087 */ 9088 #define SYSCON_PDAWAKECFG_FRO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_FRO_PD_SHIFT)) & SYSCON_PDAWAKECFG_FRO_PD_MASK) 9089 #define SYSCON_PDAWAKECFG_FLASH_PD_MASK (0x4U) 9090 #define SYSCON_PDAWAKECFG_FLASH_PD_SHIFT (2U) 9091 /*! FLASH_PD - Flash wake-up configuration 9092 * 0b0..powered 9093 * 0b1..powered down 9094 */ 9095 #define SYSCON_PDAWAKECFG_FLASH_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_FLASH_PD_SHIFT)) & SYSCON_PDAWAKECFG_FLASH_PD_MASK) 9096 #define SYSCON_PDAWAKECFG_BOD_PD_MASK (0x8U) 9097 #define SYSCON_PDAWAKECFG_BOD_PD_SHIFT (3U) 9098 /*! BOD_PD - BOD wake-up configuration 9099 * 0b0..powered 9100 * 0b1..powered down 9101 */ 9102 #define SYSCON_PDAWAKECFG_BOD_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_BOD_PD_SHIFT)) & SYSCON_PDAWAKECFG_BOD_PD_MASK) 9103 #define SYSCON_PDAWAKECFG_ADC_PD_MASK (0x10U) 9104 #define SYSCON_PDAWAKECFG_ADC_PD_SHIFT (4U) 9105 /*! ADC_PD - ADC wake-up configuration 9106 * 0b0..powered 9107 * 0b1..powered down 9108 */ 9109 #define SYSCON_PDAWAKECFG_ADC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_ADC_PD_SHIFT)) & SYSCON_PDAWAKECFG_ADC_PD_MASK) 9110 #define SYSCON_PDAWAKECFG_SYSOSC_PD_MASK (0x20U) 9111 #define SYSCON_PDAWAKECFG_SYSOSC_PD_SHIFT (5U) 9112 /*! SYSOSC_PD - Crystal oscillator wake-up configuration 9113 * 0b0..powered 9114 * 0b1..powered down 9115 */ 9116 #define SYSCON_PDAWAKECFG_SYSOSC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_SYSOSC_PD_SHIFT)) & SYSCON_PDAWAKECFG_SYSOSC_PD_MASK) 9117 #define SYSCON_PDAWAKECFG_WDTOSC_PD_MASK (0x40U) 9118 #define SYSCON_PDAWAKECFG_WDTOSC_PD_SHIFT (6U) 9119 /*! WDTOSC_PD - Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no 9120 * effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog 9121 * oscillator is always running 9122 * 0b0..Disabled 9123 * 0b1..Enabled 9124 */ 9125 #define SYSCON_PDAWAKECFG_WDTOSC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_WDTOSC_PD_SHIFT)) & SYSCON_PDAWAKECFG_WDTOSC_PD_MASK) 9126 #define SYSCON_PDAWAKECFG_SYSPLL_PD_MASK (0x80U) 9127 #define SYSCON_PDAWAKECFG_SYSPLL_PD_SHIFT (7U) 9128 /*! SYSPLL_PD - System PLL wake-up configuration 9129 * 0b0..Disabled 9130 * 0b1..Enabled 9131 */ 9132 #define SYSCON_PDAWAKECFG_SYSPLL_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_SYSPLL_PD_SHIFT)) & SYSCON_PDAWAKECFG_SYSPLL_PD_MASK) 9133 #define SYSCON_PDAWAKECFG_VREF2_PD_MASK (0x400U) 9134 #define SYSCON_PDAWAKECFG_VREF2_PD_SHIFT (10U) 9135 /*! VREF2_PD - VREF2 wake-up configuration 9136 * 0b0..Disabled 9137 * 0b1..Enabled 9138 */ 9139 #define SYSCON_PDAWAKECFG_VREF2_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_VREF2_PD_SHIFT)) & SYSCON_PDAWAKECFG_VREF2_PD_MASK) 9140 #define SYSCON_PDAWAKECFG_DAC0_MASK (0x2000U) 9141 #define SYSCON_PDAWAKECFG_DAC0_SHIFT (13U) 9142 /*! DAC0 - DAC0 wake-up configuration 9143 * 0b0..Disabled 9144 * 0b1..Enabled 9145 */ 9146 #define SYSCON_PDAWAKECFG_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_DAC0_SHIFT)) & SYSCON_PDAWAKECFG_DAC0_MASK) 9147 #define SYSCON_PDAWAKECFG_DAC1_MASK (0x4000U) 9148 #define SYSCON_PDAWAKECFG_DAC1_SHIFT (14U) 9149 /*! DAC1 - DAC1 wake-up configuration 9150 * 0b0..Disabled 9151 * 0b1..Enabled 9152 */ 9153 #define SYSCON_PDAWAKECFG_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_DAC1_SHIFT)) & SYSCON_PDAWAKECFG_DAC1_MASK) 9154 #define SYSCON_PDAWAKECFG_ACMP_MASK (0x8000U) 9155 #define SYSCON_PDAWAKECFG_ACMP_SHIFT (15U) 9156 /*! ACMP - Analog comparator wake-up configuration 9157 * 0b0..Disabled 9158 * 0b1..Enabled 9159 */ 9160 #define SYSCON_PDAWAKECFG_ACMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_ACMP_SHIFT)) & SYSCON_PDAWAKECFG_ACMP_MASK) 9161 /*! @} */ 9162 9163 /*! @name PDRUNCFG - Power configuration register */ 9164 /*! @{ */ 9165 #define SYSCON_PDRUNCFG_FROOUT_PD_MASK (0x1U) 9166 #define SYSCON_PDRUNCFG_FROOUT_PD_SHIFT (0U) 9167 /*! FROOUT_PD - FRO oscillator output wake-up configuration 9168 * 0b0..powered 9169 * 0b1..powered down 9170 */ 9171 #define SYSCON_PDRUNCFG_FROOUT_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_FROOUT_PD_SHIFT)) & SYSCON_PDRUNCFG_FROOUT_PD_MASK) 9172 #define SYSCON_PDRUNCFG_FRO_PD_MASK (0x2U) 9173 #define SYSCON_PDRUNCFG_FRO_PD_SHIFT (1U) 9174 /*! FRO_PD - FRO oscillator power-down wake-up configuration 9175 * 0b0..powered 9176 * 0b1..powered down 9177 */ 9178 #define SYSCON_PDRUNCFG_FRO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_FRO_PD_SHIFT)) & SYSCON_PDRUNCFG_FRO_PD_MASK) 9179 #define SYSCON_PDRUNCFG_FLASH_PD_MASK (0x4U) 9180 #define SYSCON_PDRUNCFG_FLASH_PD_SHIFT (2U) 9181 /*! FLASH_PD - Flash wake-up configuration 9182 * 0b0..powered 9183 * 0b1..powered down 9184 */ 9185 #define SYSCON_PDRUNCFG_FLASH_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_FLASH_PD_SHIFT)) & SYSCON_PDRUNCFG_FLASH_PD_MASK) 9186 #define SYSCON_PDRUNCFG_BOD_PD_MASK (0x8U) 9187 #define SYSCON_PDRUNCFG_BOD_PD_SHIFT (3U) 9188 /*! BOD_PD - BOD wake-up configuration 9189 * 0b0..powered 9190 * 0b1..powered down 9191 */ 9192 #define SYSCON_PDRUNCFG_BOD_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_BOD_PD_SHIFT)) & SYSCON_PDRUNCFG_BOD_PD_MASK) 9193 #define SYSCON_PDRUNCFG_ADC_PD_MASK (0x10U) 9194 #define SYSCON_PDRUNCFG_ADC_PD_SHIFT (4U) 9195 /*! ADC_PD - ADC wake-up configuration 9196 * 0b0..powered 9197 * 0b1..powered down 9198 */ 9199 #define SYSCON_PDRUNCFG_ADC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_ADC_PD_SHIFT)) & SYSCON_PDRUNCFG_ADC_PD_MASK) 9200 #define SYSCON_PDRUNCFG_SYSOSC_PD_MASK (0x20U) 9201 #define SYSCON_PDRUNCFG_SYSOSC_PD_SHIFT (5U) 9202 /*! SYSOSC_PD - Crystal oscillator wake-up configuration 9203 * 0b0..powered 9204 * 0b1..powered down 9205 */ 9206 #define SYSCON_PDRUNCFG_SYSOSC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_SYSOSC_PD_SHIFT)) & SYSCON_PDRUNCFG_SYSOSC_PD_MASK) 9207 #define SYSCON_PDRUNCFG_WDTOSC_PD_MASK (0x40U) 9208 #define SYSCON_PDRUNCFG_WDTOSC_PD_SHIFT (6U) 9209 /*! WDTOSC_PD - Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no 9210 * effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog 9211 * oscillator is always running 9212 * 0b0..Disabled 9213 * 0b1..Enabled 9214 */ 9215 #define SYSCON_PDRUNCFG_WDTOSC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_WDTOSC_PD_SHIFT)) & SYSCON_PDRUNCFG_WDTOSC_PD_MASK) 9216 #define SYSCON_PDRUNCFG_SYSPLL_PD_MASK (0x80U) 9217 #define SYSCON_PDRUNCFG_SYSPLL_PD_SHIFT (7U) 9218 /*! SYSPLL_PD - System PLL wake-up configuration 9219 * 0b0..Disabled 9220 * 0b1..Enabled 9221 */ 9222 #define SYSCON_PDRUNCFG_SYSPLL_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_SYSPLL_PD_SHIFT)) & SYSCON_PDRUNCFG_SYSPLL_PD_MASK) 9223 #define SYSCON_PDRUNCFG_DAC0_MASK (0x2000U) 9224 #define SYSCON_PDRUNCFG_DAC0_SHIFT (13U) 9225 /*! DAC0 - DAC0 wake-up configuration 9226 * 0b0..Disabled 9227 * 0b1..Enabled 9228 */ 9229 #define SYSCON_PDRUNCFG_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_DAC0_SHIFT)) & SYSCON_PDRUNCFG_DAC0_MASK) 9230 #define SYSCON_PDRUNCFG_DAC1_MASK (0x4000U) 9231 #define SYSCON_PDRUNCFG_DAC1_SHIFT (14U) 9232 /*! DAC1 - DAC1 wake-up configuration 9233 * 0b0..Disabled 9234 * 0b1..Enabled 9235 */ 9236 #define SYSCON_PDRUNCFG_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_DAC1_SHIFT)) & SYSCON_PDRUNCFG_DAC1_MASK) 9237 #define SYSCON_PDRUNCFG_ACMP_MASK (0x8000U) 9238 #define SYSCON_PDRUNCFG_ACMP_SHIFT (15U) 9239 /*! ACMP - Analog comparator wake-up configuration 9240 * 0b0..Disabled 9241 * 0b1..Enabled 9242 */ 9243 #define SYSCON_PDRUNCFG_ACMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_ACMP_SHIFT)) & SYSCON_PDRUNCFG_ACMP_MASK) 9244 /*! @} */ 9245 9246 /*! @name DEVICE_ID - Part ID register */ 9247 /*! @{ */ 9248 #define SYSCON_DEVICE_ID_DEVICEID_MASK (0xFFFFFFFFU) 9249 #define SYSCON_DEVICE_ID_DEVICEID_SHIFT (0U) 9250 /*! DEVICEID - Part ID 9251 */ 9252 #define SYSCON_DEVICE_ID_DEVICEID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID_DEVICEID_SHIFT)) & SYSCON_DEVICE_ID_DEVICEID_MASK) 9253 /*! @} */ 9254 9255 9256 /*! 9257 * @} 9258 */ /* end of group SYSCON_Register_Masks */ 9259 9260 9261 /* SYSCON - Peripheral instance base addresses */ 9262 /** Peripheral SYSCON base address */ 9263 #define SYSCON_BASE (0x40048000u) 9264 /** Peripheral SYSCON base pointer */ 9265 #define SYSCON ((SYSCON_Type *)SYSCON_BASE) 9266 /** Array initializer of SYSCON peripheral base addresses */ 9267 #define SYSCON_BASE_ADDRS { SYSCON_BASE } 9268 /** Array initializer of SYSCON peripheral base pointers */ 9269 #define SYSCON_BASE_PTRS { SYSCON } 9270 /** Interrupt vectors for the SYSCON peripheral type */ 9271 #define SYSCON_IRQS { BOD_IRQn } 9272 9273 /*! 9274 * @} 9275 */ /* end of group SYSCON_Peripheral_Access_Layer */ 9276 9277 9278 /* ---------------------------------------------------------------------------- 9279 -- USART Peripheral Access Layer 9280 ---------------------------------------------------------------------------- */ 9281 9282 /*! 9283 * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer 9284 * @{ 9285 */ 9286 9287 /** USART - Register Layout Typedef */ 9288 typedef struct { 9289 __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ 9290 __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ 9291 __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ 9292 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ 9293 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ 9294 __I uint32_t RXDAT; /**< Receiver Data register. Contains the last character received., offset: 0x14 */ 9295 __I uint32_t RXDATSTAT; /**< Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together., offset: 0x18 */ 9296 __IO uint32_t TXDAT; /**< Transmit Data register. Data to be transmitted is written here., offset: 0x1C */ 9297 __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ 9298 __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ 9299 __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ 9300 __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ 9301 } USART_Type; 9302 9303 /* ---------------------------------------------------------------------------- 9304 -- USART Register Masks 9305 ---------------------------------------------------------------------------- */ 9306 9307 /*! 9308 * @addtogroup USART_Register_Masks USART Register Masks 9309 * @{ 9310 */ 9311 9312 /*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ 9313 /*! @{ */ 9314 #define USART_CFG_ENABLE_MASK (0x1U) 9315 #define USART_CFG_ENABLE_SHIFT (0U) 9316 /*! ENABLE - USART Enable. 9317 * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, 9318 * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control 9319 * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the 9320 * transmitter has been reset and is therefore available. 9321 * 0b1..Enabled. The USART is enabled for operation. 9322 */ 9323 #define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) 9324 #define USART_CFG_DATALEN_MASK (0xCU) 9325 #define USART_CFG_DATALEN_SHIFT (2U) 9326 /*! DATALEN - Selects the data size for the USART. 9327 * 0b00..7 bit Data length. 9328 * 0b01..8 bit Data length. 9329 * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. 9330 * 0b11..Reserved. 9331 */ 9332 #define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) 9333 #define USART_CFG_PARITYSEL_MASK (0x30U) 9334 #define USART_CFG_PARITYSEL_SHIFT (4U) 9335 /*! PARITYSEL - Selects what type of parity is used by the USART. 9336 * 0b00..No parity. 9337 * 0b01..Reserved. 9338 * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, 9339 * and the number of 1s in a received character is expected to be even. 9340 * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, 9341 * and the number of 1s in a received character is expected to be odd. 9342 */ 9343 #define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) 9344 #define USART_CFG_STOPLEN_MASK (0x40U) 9345 #define USART_CFG_STOPLEN_SHIFT (6U) 9346 /*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 9347 * 0b0..1 stop bit. 9348 * 0b1..2 stop bits. This setting should only be used for asynchronous communication. 9349 */ 9350 #define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) 9351 #define USART_CFG_CTSEN_MASK (0x200U) 9352 #define USART_CFG_CTSEN_SHIFT (9U) 9353 /*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input 9354 * pin, or from the USART's own RTS if loopback mode is enabled. 9355 * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. 9356 * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. 9357 */ 9358 #define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) 9359 #define USART_CFG_SYNCEN_MASK (0x800U) 9360 #define USART_CFG_SYNCEN_SHIFT (11U) 9361 /*! SYNCEN - Selects synchronous or asynchronous operation. 9362 * 0b0..Asynchronous mode. 9363 * 0b1..Synchronous mode. 9364 */ 9365 #define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) 9366 #define USART_CFG_CLKPOL_MASK (0x1000U) 9367 #define USART_CFG_CLKPOL_SHIFT (12U) 9368 /*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. 9369 * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. 9370 * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. 9371 */ 9372 #define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) 9373 #define USART_CFG_SYNCMST_MASK (0x4000U) 9374 #define USART_CFG_SYNCMST_SHIFT (14U) 9375 /*! SYNCMST - Synchronous mode Master select. 9376 * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. 9377 * 0b1..Master. When synchronous mode is enabled, the USART is a master. 9378 */ 9379 #define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) 9380 #define USART_CFG_LOOP_MASK (0x8000U) 9381 #define USART_CFG_LOOP_SHIFT (15U) 9382 /*! LOOP - Selects data loopback mode. 9383 * 0b0..Normal operation. 9384 * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial 9385 * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD 9386 * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device 9387 * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. 9388 */ 9389 #define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) 9390 #define USART_CFG_OETA_MASK (0x40000U) 9391 #define USART_CFG_OETA_SHIFT (18U) 9392 /*! OETA - Output Enable Turnaround time enable for RS-485 operation. 9393 * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. 9394 * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the 9395 * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins 9396 * before it is deasserted. 9397 */ 9398 #define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) 9399 #define USART_CFG_AUTOADDR_MASK (0x80000U) 9400 #define USART_CFG_AUTOADDR_SHIFT (19U) 9401 /*! AUTOADDR - Automatic Address matching enable. 9402 * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the 9403 * possibility of versatile addressing (e.g. respond to more than one address). 9404 * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in 9405 * the ADDR register as the address to match. 9406 */ 9407 #define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) 9408 #define USART_CFG_OESEL_MASK (0x100000U) 9409 #define USART_CFG_OESEL_SHIFT (20U) 9410 /*! OESEL - Output Enable Select. 9411 * 0b0..Standard. The RTS signal is used as the standard flow control function. 9412 * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. 9413 */ 9414 #define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) 9415 #define USART_CFG_OEPOL_MASK (0x200000U) 9416 #define USART_CFG_OEPOL_SHIFT (21U) 9417 /*! OEPOL - Output Enable Polarity. 9418 * 0b0..Low. If selected by OESEL, the output enable is active low. 9419 * 0b1..High. If selected by OESEL, the output enable is active high. 9420 */ 9421 #define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) 9422 #define USART_CFG_RXPOL_MASK (0x400000U) 9423 #define USART_CFG_RXPOL_SHIFT (22U) 9424 /*! RXPOL - Receive data polarity. 9425 * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start 9426 * bit is 0, data is not inverted, and the stop bit is 1. 9427 * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 9428 * 0, start bit is 1, data is inverted, and the stop bit is 0. 9429 */ 9430 #define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) 9431 #define USART_CFG_TXPOL_MASK (0x800000U) 9432 #define USART_CFG_TXPOL_SHIFT (23U) 9433 /*! TXPOL - Transmit data polarity. 9434 * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 9435 * 0, data is not inverted, and the stop bit is 1. 9436 * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value 9437 * is 0, start bit is 1, data is inverted, and the stop bit is 0. 9438 */ 9439 #define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) 9440 /*! @} */ 9441 9442 /*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ 9443 /*! @{ */ 9444 #define USART_CTL_TXBRKEN_MASK (0x2U) 9445 #define USART_CTL_TXBRKEN_SHIFT (1U) 9446 /*! TXBRKEN - Break Enable. 9447 * 0b0..Normal operation. 9448 * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit 9449 * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the 9450 * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled 9451 * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. 9452 */ 9453 #define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) 9454 #define USART_CTL_ADDRDET_MASK (0x4U) 9455 #define USART_CTL_ADDRDET_SHIFT (2U) 9456 /*! ADDRDET - Enable address detect mode. 9457 * 0b0..Disabled. The USART presents all incoming data. 9458 * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data 9459 * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, 9460 * generating a received data interrupt. Software can then check the data to see if this is an address that 9461 * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled 9462 * normally. 9463 */ 9464 #define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) 9465 #define USART_CTL_TXDIS_MASK (0x40U) 9466 #define USART_CTL_TXDIS_SHIFT (6U) 9467 /*! TXDIS - Transmit Disable. 9468 * 0b0..Not disabled. USART transmitter is not disabled. 9469 * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This 9470 * feature can be used to facilitate software flow control. 9471 */ 9472 #define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) 9473 #define USART_CTL_CC_MASK (0x100U) 9474 #define USART_CTL_CC_SHIFT (8U) 9475 /*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. 9476 * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to 9477 * complete a character that is being received. 9478 * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on 9479 * Un_RxD independently from transmission on Un_TXD). 9480 */ 9481 #define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) 9482 #define USART_CTL_CLRCCONRX_MASK (0x200U) 9483 #define USART_CTL_CLRCCONRX_SHIFT (9U) 9484 /*! CLRCCONRX - Clear Continuous Clock. 9485 * 0b0..No effect. No effect on the CC bit. 9486 * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. 9487 */ 9488 #define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) 9489 #define USART_CTL_AUTOBAUD_MASK (0x10000U) 9490 #define USART_CTL_AUTOBAUD_SHIFT (16U) 9491 /*! AUTOBAUD - Autobaud enable. 9492 * 0b0..Disabled. USART is in normal operating mode. 9493 * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The 9494 * first start bit of RX is measured and used the update the BRG register to match the received data rate. 9495 * AUTOBAUD is cleared once this process is complete, or if there is an AERR. 9496 */ 9497 #define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) 9498 /*! @} */ 9499 9500 /*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ 9501 /*! @{ */ 9502 #define USART_STAT_RXRDY_MASK (0x1U) 9503 #define USART_STAT_RXRDY_SHIFT (0U) 9504 /*! RXRDY - Receiver Ready flag. When 1, indicates that data is available to be read from the 9505 * receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers. 9506 */ 9507 #define USART_STAT_RXRDY(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXRDY_SHIFT)) & USART_STAT_RXRDY_MASK) 9508 #define USART_STAT_RXIDLE_MASK (0x2U) 9509 #define USART_STAT_RXIDLE_SHIFT (1U) 9510 /*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of 9511 * receiving data. When 1, indicates that the receiver is not currently in the process of receiving 9512 * data. 9513 */ 9514 #define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) 9515 #define USART_STAT_TXRDY_MASK (0x4U) 9516 #define USART_STAT_TXRDY_SHIFT (2U) 9517 /*! TXRDY - Transmitter Ready flag. When 1, this bit indicates that data may be written to the 9518 * transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data 9519 * is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift 9520 * register. 9521 */ 9522 #define USART_STAT_TXRDY(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXRDY_SHIFT)) & USART_STAT_TXRDY_MASK) 9523 #define USART_STAT_TXIDLE_MASK (0x8U) 9524 #define USART_STAT_TXIDLE_SHIFT (3U) 9525 /*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of 9526 * sending data.When 1, indicate that the transmitter is not currently in the process of sending 9527 * data. 9528 */ 9529 #define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) 9530 #define USART_STAT_CTS_MASK (0x10U) 9531 #define USART_STAT_CTS_SHIFT (4U) 9532 /*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the 9533 * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode 9534 * is enabled. 9535 */ 9536 #define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) 9537 #define USART_STAT_DELTACTS_MASK (0x20U) 9538 #define USART_STAT_DELTACTS_SHIFT (5U) 9539 /*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. 9540 */ 9541 #define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) 9542 #define USART_STAT_TXDISSTAT_MASK (0x40U) 9543 #define USART_STAT_TXDISSTAT_SHIFT (6U) 9544 /*! TXDISSTAT - Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART 9545 * transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1). 9546 */ 9547 #define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) 9548 #define USART_STAT_OVERRUNINT_MASK (0x100U) 9549 #define USART_STAT_OVERRUNINT_SHIFT (8U) 9550 /*! OVERRUNINT - Overrun Error interrupt flag. This flag is set when a new character is received 9551 * while the receiver buffer is still in use. If this occurs, the newly received character in the 9552 * shift register is lost. 9553 */ 9554 #define USART_STAT_OVERRUNINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_OVERRUNINT_SHIFT)) & USART_STAT_OVERRUNINT_MASK) 9555 #define USART_STAT_RXBRK_MASK (0x400U) 9556 #define USART_STAT_RXBRK_SHIFT (10U) 9557 /*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection 9558 * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also 9559 * be set when this condition occurs because the stop bit(s) for the character would be missing. 9560 * RXBRK is cleared when the Un_RXD pin goes high. 9561 */ 9562 #define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) 9563 #define USART_STAT_DELTARXBRK_MASK (0x800U) 9564 #define USART_STAT_DELTARXBRK_SHIFT (11U) 9565 /*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs.Cleared by software. 9566 */ 9567 #define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) 9568 #define USART_STAT_START_MASK (0x1000U) 9569 #define USART_STAT_START_SHIFT (12U) 9570 /*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily 9571 * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. 9572 * Cleared by software. 9573 */ 9574 #define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) 9575 #define USART_STAT_FRAMERRINT_MASK (0x2000U) 9576 #define USART_STAT_FRAMERRINT_SHIFT (13U) 9577 /*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a 9578 * missing stop bit at the expected location. This could be an indication of a baud rate or 9579 * configuration mismatch with the transmitting source. 9580 */ 9581 #define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) 9582 #define USART_STAT_PARITYERRINT_MASK (0x4000U) 9583 #define USART_STAT_PARITYERRINT_SHIFT (14U) 9584 /*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. 9585 */ 9586 #define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) 9587 #define USART_STAT_RXNOISEINT_MASK (0x8000U) 9588 #define USART_STAT_RXNOISEINT_SHIFT (15U) 9589 /*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to 9590 * determine the value of each received data bit, except in synchronous mode. This acts as a 9591 * noise filter if one sample disagrees. This flag is set when a received data bit contains one 9592 * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or 9593 * loss of synchronization during data reception. 9594 */ 9595 #define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) 9596 #define USART_STAT_ABERR_MASK (0x10000U) 9597 #define USART_STAT_ABERR_SHIFT (16U) 9598 /*! ABERR - Autobaud Error. An autobaud error can occur if the BRG counts to its limit before the 9599 * end of the start bit that is being measured, essentially an autobaud time-out. 9600 */ 9601 #define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) 9602 /*! @} */ 9603 9604 /*! @name INTENSET - Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ 9605 /*! @{ */ 9606 #define USART_INTENSET_RXRDYEN_MASK (0x1U) 9607 #define USART_INTENSET_RXRDYEN_SHIFT (0U) 9608 /*! RXRDYEN - When 1, enables an interrupt when there is a received character available to be read from the RXDAT register. 9609 */ 9610 #define USART_INTENSET_RXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXRDYEN_SHIFT)) & USART_INTENSET_RXRDYEN_MASK) 9611 #define USART_INTENSET_TXRDYEN_MASK (0x4U) 9612 #define USART_INTENSET_TXRDYEN_SHIFT (2U) 9613 /*! TXRDYEN - When 1, enables an interrupt when the TXDAT register is available to take another character to transmit. 9614 */ 9615 #define USART_INTENSET_TXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXRDYEN_SHIFT)) & USART_INTENSET_TXRDYEN_MASK) 9616 #define USART_INTENSET_TXIDLEEN_MASK (0x8U) 9617 #define USART_INTENSET_TXIDLEEN_SHIFT (3U) 9618 /*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). 9619 */ 9620 #define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) 9621 #define USART_INTENSET_DELTACTSEN_MASK (0x20U) 9622 #define USART_INTENSET_DELTACTSEN_SHIFT (5U) 9623 /*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. 9624 */ 9625 #define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) 9626 #define USART_INTENSET_TXDISEN_MASK (0x40U) 9627 #define USART_INTENSET_TXDISEN_SHIFT (6U) 9628 /*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by 9629 * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. 9630 */ 9631 #define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) 9632 #define USART_INTENSET_OVERRUNEN_MASK (0x100U) 9633 #define USART_INTENSET_OVERRUNEN_SHIFT (8U) 9634 /*! OVERRUNEN - When 1, enables an interrupt when an overrun error occurred. 9635 */ 9636 #define USART_INTENSET_OVERRUNEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_OVERRUNEN_SHIFT)) & USART_INTENSET_OVERRUNEN_MASK) 9637 #define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) 9638 #define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) 9639 /*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection 9640 * of a received break condition (break condition asserted or deasserted). 9641 */ 9642 #define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) 9643 #define USART_INTENSET_STARTEN_MASK (0x1000U) 9644 #define USART_INTENSET_STARTEN_SHIFT (12U) 9645 /*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. 9646 */ 9647 #define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) 9648 #define USART_INTENSET_FRAMERREN_MASK (0x2000U) 9649 #define USART_INTENSET_FRAMERREN_SHIFT (13U) 9650 /*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. 9651 */ 9652 #define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) 9653 #define USART_INTENSET_PARITYERREN_MASK (0x4000U) 9654 #define USART_INTENSET_PARITYERREN_SHIFT (14U) 9655 /*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. 9656 */ 9657 #define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) 9658 #define USART_INTENSET_RXNOISEEN_MASK (0x8000U) 9659 #define USART_INTENSET_RXNOISEEN_SHIFT (15U) 9660 /*! RXNOISEEN - When 1, enables an interrupt when noise is detected. 9661 */ 9662 #define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) 9663 #define USART_INTENSET_ABERREN_MASK (0x10000U) 9664 #define USART_INTENSET_ABERREN_SHIFT (16U) 9665 /*! ABERREN - When 1, enables an interrupt when an autobaud error occurs. 9666 */ 9667 #define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) 9668 /*! @} */ 9669 9670 /*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ 9671 /*! @{ */ 9672 #define USART_INTENCLR_RXRDYCLR_MASK (0x1U) 9673 #define USART_INTENCLR_RXRDYCLR_SHIFT (0U) 9674 /*! RXRDYCLR - Writing 1 clears the corresponding bit in the INTENSET register. 9675 */ 9676 #define USART_INTENCLR_RXRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXRDYCLR_SHIFT)) & USART_INTENCLR_RXRDYCLR_MASK) 9677 #define USART_INTENCLR_TXRDYCLR_MASK (0x4U) 9678 #define USART_INTENCLR_TXRDYCLR_SHIFT (2U) 9679 /*! TXRDYCLR - Writing 1 clears the corresponding bit in the INTENSET register. 9680 */ 9681 #define USART_INTENCLR_TXRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXRDYCLR_SHIFT)) & USART_INTENCLR_TXRDYCLR_MASK) 9682 #define USART_INTENCLR_TXIDLECLR_MASK (0x8U) 9683 #define USART_INTENCLR_TXIDLECLR_SHIFT (3U) 9684 /*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. 9685 */ 9686 #define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) 9687 #define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) 9688 #define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) 9689 /*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. 9690 */ 9691 #define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) 9692 #define USART_INTENCLR_TXDISINTCLR_MASK (0x40U) 9693 #define USART_INTENCLR_TXDISINTCLR_SHIFT (6U) 9694 /*! TXDISINTCLR - Writing 1 clears the corresponding bit in the INTENSET register. 9695 */ 9696 #define USART_INTENCLR_TXDISINTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISINTCLR_SHIFT)) & USART_INTENCLR_TXDISINTCLR_MASK) 9697 #define USART_INTENCLR_OVERRUNCLR_MASK (0x100U) 9698 #define USART_INTENCLR_OVERRUNCLR_SHIFT (8U) 9699 /*! OVERRUNCLR - Writing 1 clears the corresponding bit in the INTENSET register. 9700 */ 9701 #define USART_INTENCLR_OVERRUNCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_OVERRUNCLR_SHIFT)) & USART_INTENCLR_OVERRUNCLR_MASK) 9702 #define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) 9703 #define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) 9704 /*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. 9705 */ 9706 #define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) 9707 #define USART_INTENCLR_STARTCLR_MASK (0x1000U) 9708 #define USART_INTENCLR_STARTCLR_SHIFT (12U) 9709 /*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. 9710 */ 9711 #define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) 9712 #define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) 9713 #define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) 9714 /*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. 9715 */ 9716 #define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) 9717 #define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) 9718 #define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) 9719 /*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. 9720 */ 9721 #define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) 9722 #define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) 9723 #define USART_INTENCLR_RXNOISECLR_SHIFT (15U) 9724 /*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. 9725 */ 9726 #define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) 9727 #define USART_INTENCLR_ABERRCLR_MASK (0x10000U) 9728 #define USART_INTENCLR_ABERRCLR_SHIFT (16U) 9729 /*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. 9730 */ 9731 #define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) 9732 /*! @} */ 9733 9734 /*! @name RXDAT - Receiver Data register. Contains the last character received. */ 9735 /*! @{ */ 9736 #define USART_RXDAT_RXDAT_MASK (0x1FFU) 9737 #define USART_RXDAT_RXDAT_SHIFT (0U) 9738 /*! RXDAT - The USART Receiver Data register contains the next received character. The number of 9739 * bits that are relevant depends on the USART configuration settings. 9740 */ 9741 #define USART_RXDAT_RXDAT(x) (((uint32_t)(((uint32_t)(x)) << USART_RXDAT_RXDAT_SHIFT)) & USART_RXDAT_RXDAT_MASK) 9742 /*! @} */ 9743 9744 /*! @name RXDATSTAT - Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together. */ 9745 /*! @{ */ 9746 #define USART_RXDATSTAT_RXDAT_MASK (0x1FFU) 9747 #define USART_RXDATSTAT_RXDAT_SHIFT (0U) 9748 /*! RXDAT - The USART Receiver Data register contains the next received character. The number of 9749 * bits that are relevant depends on the USART configuration settings. 9750 */ 9751 #define USART_RXDATSTAT_RXDAT(x) (((uint32_t)(((uint32_t)(x)) << USART_RXDATSTAT_RXDAT_SHIFT)) & USART_RXDATSTAT_RXDAT_MASK) 9752 #define USART_RXDATSTAT_FRAMERR_MASK (0x2000U) 9753 #define USART_RXDATSTAT_FRAMERR_SHIFT (13U) 9754 /*! FRAMERR - Framing Error status flag. This bit is valid when there is a character to be read in 9755 * the RXDAT register and reflects the status of that character. This bit will set when the 9756 * character in RXDAT was received with a missing stop bit at the expected location. This could be an 9757 * indication of a baud rate or configuration mismatch with the transmitting source. 9758 */ 9759 #define USART_RXDATSTAT_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_RXDATSTAT_FRAMERR_SHIFT)) & USART_RXDATSTAT_FRAMERR_MASK) 9760 #define USART_RXDATSTAT_PARITYERR_MASK (0x4000U) 9761 #define USART_RXDATSTAT_PARITYERR_SHIFT (14U) 9762 /*! PARITYERR - Parity Error status flag. This bit is valid when there is a character to be read in 9763 * the RXDAT register and reflects the status of that character. This bit will be set when a 9764 * parity error is detected in a received character. 9765 */ 9766 #define USART_RXDATSTAT_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_RXDATSTAT_PARITYERR_SHIFT)) & USART_RXDATSTAT_PARITYERR_MASK) 9767 #define USART_RXDATSTAT_RXNOISE_MASK (0x8000U) 9768 #define USART_RXDATSTAT_RXNOISE_SHIFT (15U) 9769 /*! RXNOISE - Received Noise flag. 9770 */ 9771 #define USART_RXDATSTAT_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_RXDATSTAT_RXNOISE_SHIFT)) & USART_RXDATSTAT_RXNOISE_MASK) 9772 /*! @} */ 9773 9774 /*! @name TXDAT - Transmit Data register. Data to be transmitted is written here. */ 9775 /*! @{ */ 9776 #define USART_TXDAT_TXDAT_MASK (0x1FFU) 9777 #define USART_TXDAT_TXDAT_SHIFT (0U) 9778 /*! TXDAT - Writing to the USART Transmit Data Register causes the data to be transmitted as soon as 9779 * the transmit shift register is available and any conditions for transmitting data are met: 9780 * CTS low (if CTSEN bit = 1), TXDIS bit = 0. 9781 */ 9782 #define USART_TXDAT_TXDAT(x) (((uint32_t)(((uint32_t)(x)) << USART_TXDAT_TXDAT_SHIFT)) & USART_TXDAT_TXDAT_MASK) 9783 /*! @} */ 9784 9785 /*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ 9786 /*! @{ */ 9787 #define USART_BRG_BRGVAL_MASK (0xFFFFU) 9788 #define USART_BRG_BRGVAL_SHIFT (0U) 9789 /*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on 9790 * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is 9791 * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART 9792 * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. 9793 */ 9794 #define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) 9795 /*! @} */ 9796 9797 /*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ 9798 /*! @{ */ 9799 #define USART_INTSTAT_RXRDY_MASK (0x1U) 9800 #define USART_INTSTAT_RXRDY_SHIFT (0U) 9801 /*! RXRDY - Receiver Ready flag. 9802 */ 9803 #define USART_INTSTAT_RXRDY(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXRDY_SHIFT)) & USART_INTSTAT_RXRDY_MASK) 9804 #define USART_INTSTAT_TXRDY_MASK (0x4U) 9805 #define USART_INTSTAT_TXRDY_SHIFT (2U) 9806 /*! TXRDY - Transmitter Ready flag. 9807 */ 9808 #define USART_INTSTAT_TXRDY(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXRDY_SHIFT)) & USART_INTSTAT_TXRDY_MASK) 9809 #define USART_INTSTAT_TXIDLE_MASK (0x8U) 9810 #define USART_INTSTAT_TXIDLE_SHIFT (3U) 9811 /*! TXIDLE - Transmitter idle status. 9812 */ 9813 #define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) 9814 #define USART_INTSTAT_DELTACTS_MASK (0x20U) 9815 #define USART_INTSTAT_DELTACTS_SHIFT (5U) 9816 /*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. 9817 */ 9818 #define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) 9819 #define USART_INTSTAT_TXDISINT_MASK (0x40U) 9820 #define USART_INTSTAT_TXDISINT_SHIFT (6U) 9821 /*! TXDISINT - Transmitter Disabled Interrupt flag. 9822 */ 9823 #define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) 9824 #define USART_INTSTAT_OVERRUNINT_MASK (0x100U) 9825 #define USART_INTSTAT_OVERRUNINT_SHIFT (8U) 9826 /*! OVERRUNINT - Overrun Error interrupt flag. 9827 */ 9828 #define USART_INTSTAT_OVERRUNINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_OVERRUNINT_SHIFT)) & USART_INTSTAT_OVERRUNINT_MASK) 9829 #define USART_INTSTAT_DELTARXBRK_MASK (0x800U) 9830 #define USART_INTSTAT_DELTARXBRK_SHIFT (11U) 9831 /*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. 9832 */ 9833 #define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) 9834 #define USART_INTSTAT_START_MASK (0x1000U) 9835 #define USART_INTSTAT_START_SHIFT (12U) 9836 /*! START - This bit is set when a start is detected on the receiver input. 9837 */ 9838 #define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) 9839 #define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) 9840 #define USART_INTSTAT_FRAMERRINT_SHIFT (13U) 9841 /*! FRAMERRINT - Framing Error interrupt flag. 9842 */ 9843 #define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) 9844 #define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) 9845 #define USART_INTSTAT_PARITYERRINT_SHIFT (14U) 9846 /*! PARITYERRINT - Parity Error interrupt flag. 9847 */ 9848 #define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) 9849 #define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) 9850 #define USART_INTSTAT_RXNOISEINT_SHIFT (15U) 9851 /*! RXNOISEINT - Received Noise interrupt flag. 9852 */ 9853 #define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) 9854 #define USART_INTSTAT_ABERR_MASK (0x10000U) 9855 #define USART_INTSTAT_ABERR_SHIFT (16U) 9856 /*! ABERR - Autobaud Error flag. 9857 */ 9858 #define USART_INTSTAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERR_SHIFT)) & USART_INTSTAT_ABERR_MASK) 9859 /*! @} */ 9860 9861 /*! @name OSR - Oversample selection register for asynchronous communication. */ 9862 /*! @{ */ 9863 #define USART_OSR_OSRVAL_MASK (0xFU) 9864 #define USART_OSR_OSRVAL_SHIFT (0U) 9865 /*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to 9866 * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive 9867 * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. 9868 */ 9869 #define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) 9870 /*! @} */ 9871 9872 /*! @name ADDR - Address register for automatic address matching. */ 9873 /*! @{ */ 9874 #define USART_ADDR_ADDRESS_MASK (0xFFU) 9875 #define USART_ADDR_ADDRESS_SHIFT (0U) 9876 /*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is 9877 * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). 9878 */ 9879 #define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) 9880 /*! @} */ 9881 9882 9883 /*! 9884 * @} 9885 */ /* end of group USART_Register_Masks */ 9886 9887 9888 /* USART - Peripheral instance base addresses */ 9889 /** Peripheral USART0 base address */ 9890 #define USART0_BASE (0x40064000u) 9891 /** Peripheral USART0 base pointer */ 9892 #define USART0 ((USART_Type *)USART0_BASE) 9893 /** Peripheral USART1 base address */ 9894 #define USART1_BASE (0x40068000u) 9895 /** Peripheral USART1 base pointer */ 9896 #define USART1 ((USART_Type *)USART1_BASE) 9897 /** Peripheral USART2 base address */ 9898 #define USART2_BASE (0x4006C000u) 9899 /** Peripheral USART2 base pointer */ 9900 #define USART2 ((USART_Type *)USART2_BASE) 9901 /** Peripheral USART3 base address */ 9902 #define USART3_BASE (0x40070000u) 9903 /** Peripheral USART3 base pointer */ 9904 #define USART3 ((USART_Type *)USART3_BASE) 9905 /** Peripheral USART4 base address */ 9906 #define USART4_BASE (0x40074000u) 9907 /** Peripheral USART4 base pointer */ 9908 #define USART4 ((USART_Type *)USART4_BASE) 9909 /** Array initializer of USART peripheral base addresses */ 9910 #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE } 9911 /** Array initializer of USART peripheral base pointers */ 9912 #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4 } 9913 /** Interrupt vectors for the USART peripheral type */ 9914 #define USART_IRQS { USART0_IRQn, USART1_IRQn, USART2_IRQn, PIN_INT6_USART3_IRQn, PIN_INT7_USART4_IRQn } 9915 9916 /*! 9917 * @} 9918 */ /* end of group USART_Peripheral_Access_Layer */ 9919 9920 9921 /* ---------------------------------------------------------------------------- 9922 -- WKT Peripheral Access Layer 9923 ---------------------------------------------------------------------------- */ 9924 9925 /*! 9926 * @addtogroup WKT_Peripheral_Access_Layer WKT Peripheral Access Layer 9927 * @{ 9928 */ 9929 9930 /** WKT - Register Layout Typedef */ 9931 typedef struct { 9932 __IO uint32_t CTRL; /**< Self wake-up timer control register., offset: 0x0 */ 9933 uint8_t RESERVED_0[8]; 9934 __IO uint32_t COUNT; /**< Counter register., offset: 0xC */ 9935 } WKT_Type; 9936 9937 /* ---------------------------------------------------------------------------- 9938 -- WKT Register Masks 9939 ---------------------------------------------------------------------------- */ 9940 9941 /*! 9942 * @addtogroup WKT_Register_Masks WKT Register Masks 9943 * @{ 9944 */ 9945 9946 /*! @name CTRL - Self wake-up timer control register. */ 9947 /*! @{ */ 9948 #define WKT_CTRL_CLKSEL_MASK (0x1U) 9949 #define WKT_CTRL_CLKSEL_SHIFT (0U) 9950 /*! CLKSEL - Select the self wake-up timer clock source. Remark: This bit only has an effect if the SEL_EXTCLK bit is not set. 9951 * 0b0..Divided FRO clock. This clock runs at 750 kHz and provides time-out periods of up to approximately 95 9952 * minutes in 1.33 us increments. Remark: This clock is not available in not available in Deep-sleep, 9953 * power-down, deep power-down modes. Do not select this option if the timer is to be used to wake up from one of these 9954 * modes. 9955 * 0b1..This is the (nominally) 10 kHz clock and provides time-out periods of up to approximately 119 hours in 9956 * 100 us increments. The accuracy of this clock is limited to +/- 40 % over temperature and processing. 9957 * Remark: This clock is available in all power modes. Prior to use, the low-power oscillator must be enabled. The 9958 * oscillator must also be set to remain active in Deep power-down if needed. 9959 */ 9960 #define WKT_CTRL_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << WKT_CTRL_CLKSEL_SHIFT)) & WKT_CTRL_CLKSEL_MASK) 9961 #define WKT_CTRL_ALARMFLAG_MASK (0x2U) 9962 #define WKT_CTRL_ALARMFLAG_SHIFT (1U) 9963 /*! ALARMFLAG - Wake-up or alarm timer flag. 9964 * 0b0..No time-out. The self wake-up timer has not timed out. Writing a 0 to has no effect. 9965 * 0b1..Time-out. The self wake-up timer has timed out. This flag generates an interrupt request which can wake 9966 * up the part from any reduced power mode including Deep power-down if the clock source is the low power 9967 * oscillator. Writing a 1 clears this status bit. 9968 */ 9969 #define WKT_CTRL_ALARMFLAG(x) (((uint32_t)(((uint32_t)(x)) << WKT_CTRL_ALARMFLAG_SHIFT)) & WKT_CTRL_ALARMFLAG_MASK) 9970 #define WKT_CTRL_CLEARCTR_MASK (0x4U) 9971 #define WKT_CTRL_CLEARCTR_SHIFT (2U) 9972 /*! CLEARCTR - Clears the self wake-up timer. 9973 * 0b0..No effect. Reading this bit always returns 0. 9974 * 0b1..Clear the counter. Counting is halted until a new count value is loaded. 9975 */ 9976 #define WKT_CTRL_CLEARCTR(x) (((uint32_t)(((uint32_t)(x)) << WKT_CTRL_CLEARCTR_SHIFT)) & WKT_CTRL_CLEARCTR_MASK) 9977 #define WKT_CTRL_SEL_EXTCLK_MASK (0x8U) 9978 #define WKT_CTRL_SEL_EXTCLK_SHIFT (3U) 9979 /*! SEL_EXTCLK - Select external or internal clock source for the self wake-up timer. The internal 9980 * clock source is selected by the CLKSEL bit in this register if SET_EXTCLK is set to internal. 9981 * 0b0..Internal. The clock source is the internal clock selected by the CLKSEL bit. 9982 * 0b1..External. The self wake-up timer uses the external WKTCLKIN pin. 9983 */ 9984 #define WKT_CTRL_SEL_EXTCLK(x) (((uint32_t)(((uint32_t)(x)) << WKT_CTRL_SEL_EXTCLK_SHIFT)) & WKT_CTRL_SEL_EXTCLK_MASK) 9985 /*! @} */ 9986 9987 /*! @name COUNT - Counter register. */ 9988 /*! @{ */ 9989 #define WKT_COUNT_VALUE_MASK (0xFFFFFFFFU) 9990 #define WKT_COUNT_VALUE_SHIFT (0U) 9991 /*! VALUE - A write to this register pre-loads start count value into the timer and starts the 9992 * count-down sequence. A read reflects the current value of the timer. 9993 */ 9994 #define WKT_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << WKT_COUNT_VALUE_SHIFT)) & WKT_COUNT_VALUE_MASK) 9995 /*! @} */ 9996 9997 9998 /*! 9999 * @} 10000 */ /* end of group WKT_Register_Masks */ 10001 10002 10003 /* WKT - Peripheral instance base addresses */ 10004 /** Peripheral WKT base address */ 10005 #define WKT_BASE (0x40008000u) 10006 /** Peripheral WKT base pointer */ 10007 #define WKT ((WKT_Type *)WKT_BASE) 10008 /** Array initializer of WKT peripheral base addresses */ 10009 #define WKT_BASE_ADDRS { WKT_BASE } 10010 /** Array initializer of WKT peripheral base pointers */ 10011 #define WKT_BASE_PTRS { WKT } 10012 /** Interrupt vectors for the WKT peripheral type */ 10013 #define WKT_IRQS { WKT_IRQn } 10014 10015 /*! 10016 * @} 10017 */ /* end of group WKT_Peripheral_Access_Layer */ 10018 10019 10020 /* ---------------------------------------------------------------------------- 10021 -- WWDT Peripheral Access Layer 10022 ---------------------------------------------------------------------------- */ 10023 10024 /*! 10025 * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer 10026 * @{ 10027 */ 10028 10029 /** WWDT - Register Layout Typedef */ 10030 typedef struct { 10031 __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ 10032 __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ 10033 __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ 10034 __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ 10035 uint8_t RESERVED_0[4]; 10036 __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ 10037 __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ 10038 } WWDT_Type; 10039 10040 /* ---------------------------------------------------------------------------- 10041 -- WWDT Register Masks 10042 ---------------------------------------------------------------------------- */ 10043 10044 /*! 10045 * @addtogroup WWDT_Register_Masks WWDT Register Masks 10046 * @{ 10047 */ 10048 10049 /*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ 10050 /*! @{ */ 10051 #define WWDT_MOD_WDEN_MASK (0x1U) 10052 #define WWDT_MOD_WDEN_SHIFT (0U) 10053 /*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the 10054 * watchdog timer will run permanently. 10055 * 0b0..Stop. The watchdog timer is stopped. 10056 * 0b1..Run. The watchdog timer is running. 10057 */ 10058 #define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) 10059 #define WWDT_MOD_WDRESET_MASK (0x2U) 10060 #define WWDT_MOD_WDRESET_SHIFT (1U) 10061 /*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. 10062 * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. 10063 * 0b1..Reset. A watchdog time-out will cause a chip reset. 10064 */ 10065 #define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) 10066 #define WWDT_MOD_WDTOF_MASK (0x4U) 10067 #define WWDT_MOD_WDTOF_SHIFT (2U) 10068 /*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by 10069 * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a 10070 * chip reset if WDRESET = 1. 10071 */ 10072 #define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) 10073 #define WWDT_MOD_WDINT_MASK (0x8U) 10074 #define WWDT_MOD_WDINT_SHIFT (3U) 10075 /*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. 10076 * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the 10077 * WARNINT value is equal to the value of the TV register. This can occur if the value of 10078 * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. 10079 */ 10080 #define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) 10081 #define WWDT_MOD_WDPROTECT_MASK (0x10U) 10082 #define WWDT_MOD_WDPROTECT_SHIFT (4U) 10083 /*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. 10084 * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. 10085 * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. 10086 */ 10087 #define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) 10088 #define WWDT_MOD_LOCK_MASK (0x20U) 10089 #define WWDT_MOD_LOCK_SHIFT (5U) 10090 /*! LOCK - Once this bit is set to one and a watchdog feed is performed, disabling or powering down 10091 * the watchdog oscillator is prevented by hardware. This bit can be set once by software and is 10092 * only cleared by any reset. 10093 */ 10094 #define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) 10095 /*! @} */ 10096 10097 /*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ 10098 /*! @{ */ 10099 #define WWDT_TC_COUNT_MASK (0xFFFFFFU) 10100 #define WWDT_TC_COUNT_SHIFT (0U) 10101 /*! COUNT - Watchdog time-out value. 10102 */ 10103 #define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) 10104 /*! @} */ 10105 10106 /*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ 10107 /*! @{ */ 10108 #define WWDT_FEED_FEED_MASK (0xFFU) 10109 #define WWDT_FEED_FEED_SHIFT (0U) 10110 /*! FEED - Feed value should be 0xAA followed by 0x55. 10111 */ 10112 #define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) 10113 /*! @} */ 10114 10115 /*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ 10116 /*! @{ */ 10117 #define WWDT_TV_COUNT_MASK (0xFFFFFFU) 10118 #define WWDT_TV_COUNT_SHIFT (0U) 10119 /*! COUNT - Counter timer value. 10120 */ 10121 #define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) 10122 /*! @} */ 10123 10124 /*! @name WARNINT - Watchdog Warning Interrupt compare value. */ 10125 /*! @{ */ 10126 #define WWDT_WARNINT_WARNINT_MASK (0x3FFU) 10127 #define WWDT_WARNINT_WARNINT_SHIFT (0U) 10128 /*! WARNINT - Watchdog warning interrupt compare value. 10129 */ 10130 #define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) 10131 /*! @} */ 10132 10133 /*! @name WINDOW - Watchdog Window compare value. */ 10134 /*! @{ */ 10135 #define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) 10136 #define WWDT_WINDOW_WINDOW_SHIFT (0U) 10137 /*! WINDOW - Watchdog window value. 10138 */ 10139 #define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) 10140 /*! @} */ 10141 10142 10143 /*! 10144 * @} 10145 */ /* end of group WWDT_Register_Masks */ 10146 10147 10148 /* WWDT - Peripheral instance base addresses */ 10149 /** Peripheral WWDT base address */ 10150 #define WWDT_BASE (0x40000000u) 10151 /** Peripheral WWDT base pointer */ 10152 #define WWDT ((WWDT_Type *)WWDT_BASE) 10153 /** Array initializer of WWDT peripheral base addresses */ 10154 #define WWDT_BASE_ADDRS { WWDT_BASE } 10155 /** Array initializer of WWDT peripheral base pointers */ 10156 #define WWDT_BASE_PTRS { WWDT } 10157 /** Interrupt vectors for the WWDT peripheral type */ 10158 #define WWDT_IRQS { WDT_IRQn } 10159 10160 /*! 10161 * @} 10162 */ /* end of group WWDT_Peripheral_Access_Layer */ 10163 10164 10165 /* 10166 ** End of section using anonymous unions 10167 */ 10168 10169 #if defined(__ARMCC_VERSION) 10170 #if (__ARMCC_VERSION >= 6010050) 10171 #pragma clang diagnostic pop 10172 #else 10173 #pragma pop 10174 #endif 10175 #elif defined(__GNUC__) 10176 /* leave anonymous unions enabled */ 10177 #elif defined(__IAR_SYSTEMS_ICC__) 10178 #pragma language=default 10179 #else 10180 #error Not supported compiler type 10181 #endif 10182 10183 /*! 10184 * @} 10185 */ /* end of group Peripheral_access_layer */ 10186 10187 10188 /* ---------------------------------------------------------------------------- 10189 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 10190 ---------------------------------------------------------------------------- */ 10191 10192 /*! 10193 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 10194 * @{ 10195 */ 10196 10197 #if defined(__ARMCC_VERSION) 10198 #if (__ARMCC_VERSION >= 6010050) 10199 #pragma clang system_header 10200 #endif 10201 #elif defined(__IAR_SYSTEMS_ICC__) 10202 #pragma system_include 10203 #endif 10204 10205 /** 10206 * @brief Mask and left-shift a bit field value for use in a register bit range. 10207 * @param field Name of the register bit field. 10208 * @param value Value of the bit field. 10209 * @return Masked and shifted value. 10210 */ 10211 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) 10212 /** 10213 * @brief Mask and right-shift a register value to extract a bit field value. 10214 * @param field Name of the register bit field. 10215 * @param value Value of the register. 10216 * @return Masked and shifted bit field value. 10217 */ 10218 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) 10219 10220 /*! 10221 * @} 10222 */ /* end of group Bit_Field_Generic_Macros */ 10223 10224 10225 /* ---------------------------------------------------------------------------- 10226 -- SDK Compatibility 10227 ---------------------------------------------------------------------------- */ 10228 10229 /*! 10230 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 10231 * @{ 10232 */ 10233 10234 /* No SDK compatibility issues. */ 10235 10236 /*! 10237 * @} 10238 */ /* end of group SDK_Compatibility_Symbols */ 10239 10240 10241 #endif /* _LPC845_H_ */ 10242 10243
