1 /* 2 * Licensed to the Apache Software Foundation (ASF) under one 3 * or more contributor license agreements. See the NOTICE file 4 * distributed with this work for additional information 5 * regarding copyright ownership. The ASF licenses this file 6 * to you under the Apache License, Version 2.0 (the 7 * "License"); you may not use this file except in compliance 8 * with the License. You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, 13 * software distributed under the License is distributed on an 14 * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 15 * KIND, either express or implied. See the License for the 16 * specific language governing permissions and limitations 17 * under the License. 18 */ 19 20 #ifndef __DA1469X_CONFIG_H_ 21 #define __DA1469X_CONFIG_H_ 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #include <zephyr/irq.h> 28 29 #define MCU_REMAPPED_BASE (0x00000000UL) 30 /* The max. remapped memory size supported. */ 31 #define MCU_REMAPPED_SIZE (0x02000000UL) 32 33 /* 34 * OTP memory base address; should be used when accessed by 35 * peripheral devices (DMA, CRYPTO etc.). 36 */ 37 #define MCU_OTP_M_P_BASE (0x30080000UL) 38 /* The max. supported OTP region size */ 39 #define MCU_OTP_M_P_SIZE (0x00010000UL) 40 41 /* OTP memory base address (not remapped) */ 42 #define MCU_OTP_M_BASE (0x10080000UL) 43 /* The max. supported OTP region size */ 44 #define MCU_OTP_M_SIZE (0x00010000UL) 45 46 #define MCU_ROM_BASE (0x900000UL) 47 #define MCU_ROM_SIZE (0x20000UL) 48 49 /* Actual memory size integrated into SoC */ 50 #define MCU_OTPM_SIZE (4096) 51 #define MCU_OTPM_CS_OFFSET (0x0c00) 52 #define MCU_OTPM_CS_LENGTH (0x0400) 53 54 /* 55 * QSPI Flash memory based address. Accesses are done through the AHB code bus (cached). 56 * The region size available is restricted according to CACHE_FLASH_REG (up to 32MB). 57 */ 58 #define MCU_QSPIF_M_CACHED_BASE (0x16000000UL) 59 #define MCU_QSPIF_M_CACHED_SIZE (0x2000000UL) 60 61 /* 62 * QSPIC Flash memory base address. Accesses are done through the AHB system bus (not cached). 63 * Using this address space the whole Flash memory can be accesed (up to 32MB). 64 */ 65 #define MCU_QSPIF_M_BASE (0x36000000UL) 66 #define MCU_QSPIF_M_SIZE (0x2000000UL) 67 68 /* System RAM base address (not cached) */ 69 #define MCU_SYSRAM_M_BASE (0x20000000UL) 70 #define MCU_SYSRAM_M_SIZE (0x80000UL) 71 72 /* QSPIC2 RAM memory base address */ 73 #define MCU_QSPIR_M_BASE (0x32000000UL) 74 #define MCU_QSPIR_M_SIZE (0x2000000UL) 75 76 77 #define WITHIN_RANGE(_a, _s, _e) (((uint32_t)(_a) >= (uint32_t)(_s)) && ((uint32_t)(_a) < (uint32_t)(_e))) 78 79 /* True if the address provided is within the remapped region. Otherwise, false. */ 80 #define IS_REMAPPED_ADDRESS(_a) WITHIN_RANGE(_a, MCU_REMAPPED_BASE, MCU_REMAPPED_BASE + MCU_REMAPPED_SIZE) 81 82 /* True if the address provided is within the OTP region. Otherwise, false. */ 83 #define IS_OTP_ADDRESS(_a) WITHIN_RANGE(_a, MCU_OTP_M_BASE, MCU_OTP_M_BASE + MCU_OTP_M_SIZE) 84 85 /* True if the address provided is within the remapped OTP region. Otherwise, false. */ 86 #define IS_OTP_P_ADDRESS(_a) WITHIN_RANGE(_a, MCU_OTP_M_P_BASE, MCU_OTP_M_P_BASE + MCU_OTP_M_P_SIZE) 87 88 /* True if the address provided is within the SYSRAM region (no cached). Otherwise, false. */ 89 #define IS_SYSRAM_ADDRESS(_a) WITHIN_RANGE(_a, MCU_SYSRAM_M_BASE, MCU_SYSRAM_M_BASE + MCU_SYSRAM_M_SIZE) 90 91 /* True if the address provided is within the Flash region (not cached). Otherwise, false. */ 92 #define IS_QSPIF_ADDRESS(_a) WITHIN_RANGE(_a, MCU_QSPIF_M_BASE, MCU_QSPIF_M_BASE + MCU_QSPIF_M_SIZE) 93 94 /* True if the address provided is within the Flash region (cached). Otherwise, false. */ 95 #define IS_QSPIF_CACHED_ADDRESS(_a) WITHIN_RANGE(_a, MCU_QSPIF_M_CACHED_BASE, MCU_QSPIF_M_CACHED_BASE + \ 96 MCU_QSPIF_M_CACHED_SIZE) 97 98 /* True if the address provided is within the PSRAM region size. Otherwise, false */ 99 #define IS_QSPIR_ADDRESS(_a) WITHIN_RANGE(_a, MCU_QSPIR_M_BASE, MCU_QSPIR_M_BASE + MCU_QSPIR_M_SIZE) 100 101 #define MCU_TRIMV_GROUP_ID_MAX (18) 102 103 #define MCU_RCX_CAL_REF_CNT (100) 104 105 #define DA1469X_IRQ_DISABLE() irq_lock() 106 #define DA1469X_IRQ_ENABLE(_key) irq_unlock(_key) 107 108 #ifdef __cplusplus 109 } 110 #endif 111 112 #endif /* __DA1469X_CONFIG_H_ */ 113
