1;/**************************************************************************//**
2; * @file     startup_cm0plus.s
3; * @brief    CMSIS Core Device Startup File for
4; *           ARMCM0plus Device
5; * @version  V1.0.0
6; * @date     09. July 2018
7; ******************************************************************************/
8;/*
9; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
10; *
11; * SPDX-License-Identifier: Apache-2.0
12; *
13; * Licensed under the Apache License, Version 2.0 (the License); you may
14; * not use this file except in compliance with the License.
15; * You may obtain a copy of the License at
16; *
17; * www.apache.org/licenses/LICENSE-2.0
18; *
19; * Unless required by applicable law or agreed to in writing, software
20; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22; * See the License for the specific language governing permissions and
23; * limitations under the License.
24; */
25
26;
27; The modules in this file are included in the libraries, and may be replaced
28; by any user-defined modules that define the PUBLIC symbol _program_start or
29; a user defined start symbol.
30; To override the cstartup defined in the library, simply add your modified
31; version to the workbench project.
32;
33; The vector table is normally located at address 0.
34; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
35; The name "__vector_table" has special meaning for C-SPY:
36; it is where the SP start value is found, and the NVIC vector
37; table register (VTOR) is initialized to this address if != 0.
38;
39; Cortex-M version
40;
41
42        MODULE  ?cstartup
43
44
45;************************************************************************
46;* Local definitions
47;************************************************************************
48
49; Set a sufficient startup stack size for correct operation of C startup code (startup.c)
50STARTUP_STACK_SIZE_DOUBLE_WORDS    EQU 32
51
52VTOR                               EQU 0xe000ed08
53
54CPUSS_RAM0_CTL0                    EQU 0x40201300
55CPUSS_RAM1_CTL0                    EQU 0x40201380
56CPUSS_RAM2_CTL0                    EQU 0x402013a0
57
58
59;************************************************************************
60;* Import symbols
61;************************************************************************
62
63        EXTERN  CM0P_CpuIntr2_Handler
64        EXTERN  CM0P_CpuIntr3_Handler
65        EXTERN  CM0P_CpuIntr4_Handler
66        EXTERN  CM0P_CpuIntr5_Handler
67        EXTERN  CM0P_CpuIntr6_Handler
68        EXTERN  CM0P_CpuIntr7_Handler
69        EXTERN  __iar_program_start
70        EXTERN  __iar_data_init3
71        EXTERN  __iar_dynamic_initialization
72        EXTERN  SystemInit
73        EXTERN  CyMain
74
75
76;************************************************************************
77;* Export symbols
78;************************************************************************
79
80        PUBLIC  __vector_table
81        PUBLIC  __vector_table_0x1c
82        PUBLIC  __Vectors
83        PUBLIC  __Vectors_End
84        PUBLIC  __Vectors_Size
85        PUBLIC  __ramVectors
86        PUBLIC  Cy_u32StartupStackStartAddress
87        PUBLIC  Cy_u32StartupStackEndAddress
88
89
90;************************************************************************
91;* Vector Table and RAM Vector Table
92;************************************************************************
93
94        SECTION CSTACK:DATA:NOROOT(3)
95
96        ; align to 256 byte, because CM0_VECTOR_TABLE_BASE register only supports address bits [31:8] (Note: for VTOR a 128-byte alignment would be ok)
97        SECTION .intvec:CODE:ROOT(8)
98        DATA
99
100__vector_table:
101        DCD     sfe(CSTACK)
102        DCD     Reset_Handler
103        DCD     NMI_Handler
104        DCD     HardFault_Handler
105        DCD     0
106        DCD     0
107        DCD     0
108__vector_table_0x1c:
109        DCD     0
110        DCD     0
111        DCD     0
112        DCD     0
113        DCD     SVC_Handler
114        DCD     0
115        DCD     0
116        DCD     PendSV_Handler
117        DCD     SysTick_Handler
118
119        ; External interrupts              PowerMode    Description
120
121        DCD     DefaultInt_Handler           ; DeepSleep    CPU User Interrupt #0 ; updated in RAM vector table with corresponding SROM vector table entry (after ROM-to-RAM copy)
122        DCD     DefaultInt_Handler           ; DeepSleep    CPU User Interrupt #1 ; updated in RAM vector table with corresponding SROM vector table entry (after ROM-to-RAM copy)
123        DCD     CM0P_CpuIntr2_Handler      ; DeepSleep    CPU User Interrupt #2
124        DCD     CM0P_CpuIntr3_Handler      ; DeepSleep    CPU User Interrupt #3
125        DCD     CM0P_CpuIntr4_Handler      ; DeepSleep    CPU User Interrupt #4
126        DCD     CM0P_CpuIntr5_Handler      ; DeepSleep    CPU User Interrupt #5
127        DCD     CM0P_CpuIntr6_Handler      ; DeepSleep    CPU User Interrupt #6
128        DCD     CM0P_CpuIntr7_Handler      ; DeepSleep    CPU User Interrupt #7
129
130        ; These IRQs can only be triggered by SW via NVIC regs
131        DCD     CpuUserInt8_Handler      ; Active       CPU User Interrupt #8
132        DCD     CpuUserInt9_Handler      ; Active       CPU User Interrupt #9
133        DCD     CpuUserInt10_Handler     ; Active       CPU User Interrupt #10
134        DCD     CpuUserInt11_Handler     ; Active       CPU User Interrupt #11
135        DCD     CpuUserInt12_Handler     ; Active       CPU User Interrupt #12
136        DCD     CpuUserInt13_Handler     ; Active       CPU User Interrupt #13
137        DCD     CpuUserInt14_Handler     ; Active       CPU User Interrupt #14
138        DCD     CpuUserInt15_Handler     ; Active       CPU User Interrupt #15
139__Vectors_End:
140
141__Vectors       EQU   __vector_table
142__Vectors_Size  EQU   __Vectors_End - __Vectors
143
144        ; use same alignment like vector table in ROM above (even though VTOR minimum requirement would be 128 bytes if not used in combination with CM0_VECTOR_TABLE_BASE register)
145        SECTION .intvec_ram:DATA:ROOT(8)
146__ramVectors:
147        DS8     __Vectors_Size
148
149
150;************************************************************************
151;* Start-up Code
152;************************************************************************
153
154        THUMB
155        PUBWEAK Reset_Handler
156        SECTION .text:CODE:REORDER:NOROOT(2)
157Reset_Handler:
158
159; Disable global interrupts
160        CPSID   I
161
162; Update Vector Table Offset Register with address of user ROM table
163; (will be updated later to user RAM table address in C startup code)
164        LDR  r0, =__vector_table
165        LDR  r1, =VTOR
166        STR  r0, [r1]
167        DSB
168
169; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core
170; Set CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet
171; Generic code can be used, even if RAMx_CTL0 (x > 0) registers are not implemented in a device
172; or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
173        MOVS r0, #1
174        LSLS r0, r0, #19
175        LDR  r1, =CPUSS_RAM0_CTL0
176        LDR  r2, [r1]
177        ORRS r2, r0
178        STR  r2, [r1]
179        LDR  r1, =CPUSS_RAM1_CTL0
180        LDR  r2, [r1]
181        ORRS r2, r0
182        STR  r2, [r1]
183        LDR  r1, =CPUSS_RAM2_CTL0
184        LDR  r2, [r1]
185        ORRS r2, r0
186        STR  r2, [r1]
187
188; Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 bytes per loop iteration,
189; because the ECC initialization feature uses this generic granularity that will cover any memory (SRAM/TCM) in any TVII device
190; Prerequisite: Stack Pointer (SP) has not been modified (from the vector table init value) by above code (otherwise code must be adapted)
191        MOVS r0, #0 ; clear value
192        MOVS r1, #0 ; clear value
193        LDR  r2, Cy_u32StartupStackStartAddress
194startup_stack_ecc_init_loop:
195        STM  r2!, {r0, r1}
196        CMP  r2, sp
197        BNE  startup_stack_ecc_init_loop
198; Call C startup code (no ANSI C context established yet!)
199        LDR   r0, =SystemInit
200        BLX   r0
201
202        LDR   r0, =CyMain
203        BLX   r0
204
205; Note: Control flow does not necessarily return here.
206; On some tool-chains (e.g. IAR) control flow will never return from
207; the system library.
208Cy_Main_Exited:
209        B    Cy_Main_Exited
210
211;************************************************************************
212;* Literal pool
213;************************************************************************
214
215        ALIGNROM 2
216
217        LTORG
218
219        DATA
220
221        ALIGNROM 2
222
223STARTUP_STACK_SIZE_BYTES    EQU (STARTUP_STACK_SIZE_DOUBLE_WORDS * 8)  ; Multiplication does not work in below data definition directive, so an additional define is created
224
225Cy_u32StartupStackStartAddress:
226        DCD (sfe(CSTACK) - STARTUP_STACK_SIZE_BYTES)
227
228Cy_u32StartupStackEndAddress:
229        DCD (sfe(CSTACK) - 1)
230
231
232
233;************************************************************************
234;* Default and weak implementation of interrupt handlers
235;************************************************************************
236
237
238        PUBWEAK NMI_Handler
239        SECTION .text:CODE:REORDER:NOROOT(2)
240NMI_Handler:
241        B NMI_Handler
242
243;-----------------------------------------
244
245        PUBWEAK Cy_SysLib_FaultHandler
246        SECTION .text:CODE:REORDER:NOROOT(2)
247Cy_SysLib_FaultHandler:
248        B Cy_SysLib_FaultHandler
249
250;-----------------------------------------
251
252        PUBWEAK HardFault_Handler
253        SECTION .text:CODE:REORDER:NOROOT(2)
254HardFault_Handler:
255        IMPORT Cy_SysLib_FaultHandler
256        MOVS r0, #4
257        MOV  r1, lr
258        TST  r0, r1
259        BEQ  L_MSP
260        MRS  r0, PSP
261        B    L_API_call
262L_MSP
263        MRS  r0, MSP
264L_API_call
265        ; Storing LR content for Creator call stack trace
266        PUSH {lr}
267        LDR  r1, =Cy_SysLib_FaultHandler
268        BLX  r1
269
270;-----------------------------------------
271
272        PUBWEAK SVC_Handler
273        SECTION .text:CODE:REORDER:NOROOT(2)
274SVC_Handler:
275        B SVC_Handler
276
277;-----------------------------------------
278
279        PUBWEAK PendSV_Handler
280        SECTION .text:CODE:REORDER:NOROOT(2)
281PendSV_Handler:
282        B PendSV_Handler
283
284;-----------------------------------------
285
286        PUBWEAK SysTick_Handler
287        SECTION .text:CODE:REORDER:NOROOT(2)
288SysTick_Handler:
289        B SysTick_Handler
290
291
292;-----------------------------------------
293
294
295        PUBWEAK DefaultInt_Handler
296        SECTION .text:CODE:REORDER:NOROOT(2)
297DefaultInt_Handler:
298        B DefaultInt_Handler
299
300;-----------------------------------------
301
302        ; External interrupts
303        ; Traveo II CPU User Interrupts 0-7 handlers are defined in the project interrupt mapping file
304        ; Traveo II CPU User Interrupts 8-15 can only be used as SW interrupts and need to be defined by user (weak implementation provided below)
305
306
307        PUBWEAK CpuUserInt8_Handler
308        SECTION .text:CODE:REORDER:NOROOT(2)
309CpuUserInt8_Handler:
310        B CpuUserInt8_Handler
311
312;-----------------------------------------
313
314        PUBWEAK CpuUserInt9_Handler
315        SECTION .text:CODE:REORDER:NOROOT(2)
316CpuUserInt9_Handler:
317        B CpuUserInt9_Handler
318
319;-----------------------------------------
320
321        PUBWEAK CpuUserInt10_Handler
322        SECTION .text:CODE:REORDER:NOROOT(2)
323CpuUserInt10_Handler:
324        B CpuUserInt10_Handler
325
326;-----------------------------------------
327
328        PUBWEAK CpuUserInt11_Handler
329        SECTION .text:CODE:REORDER:NOROOT(2)
330CpuUserInt11_Handler:
331        B CpuUserInt11_Handler
332
333;-----------------------------------------
334
335        PUBWEAK CpuUserInt12_Handler
336        SECTION .text:CODE:REORDER:NOROOT(2)
337CpuUserInt12_Handler:
338        B CpuUserInt12_Handler
339
340;-----------------------------------------
341
342        PUBWEAK CpuUserInt13_Handler
343        SECTION .text:CODE:REORDER:NOROOT(2)
344CpuUserInt13_Handler:
345        B CpuUserInt13_Handler
346
347;-----------------------------------------
348
349        PUBWEAK CpuUserInt14_Handler
350        SECTION .text:CODE:REORDER:NOROOT(2)
351CpuUserInt14_Handler:
352        B CpuUserInt14_Handler
353
354;-----------------------------------------
355
356        PUBWEAK CpuUserInt15_Handler
357        SECTION .text:CODE:REORDER:NOROOT(2)
358CpuUserInt15_Handler:
359        B CpuUserInt15_Handler
360
361;-----------------------------------------
362
363
364;************************************************************************
365;* File end
366;************************************************************************
367
368        END
369
370
371