1 /***************************************************************************//**
2 * \file cy_tcpwm_shiftreg.c
3 * \version 1.70
4 *
5 * \brief
6 * The source file of the tcpwm driver.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2016-2021 Cypress Semiconductor Corporation
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_tcpwm_shiftreg.h"
27
28 #ifdef CY_IP_MXTCPWM
29
30 #if defined(__cplusplus)
31 extern "C" {
32 #endif
33
34 /*******************************************************************************
35 * Function Name: Cy_TCPWM_ShiftReg_Init
36 ****************************************************************************//**
37 *
38 * Initializes the counter in the TCPWM block for the Shift Register operation.
39 *
40 * \param base
41 * The pointer to a TCPWM instance.
42 *
43 * \param cntNum
44 * The Counter instance number in the selected TCPWM.
45 *
46 * \param config
47 * The pointer to a configuration structure. See \ref cy_stc_tcpwm_shiftreg_config_t.
48 *
49 * \return error / status code. See \ref cy_en_tcpwm_status_t.
50 *
51 * \snippet tcpwm/shiftreg/snippet/main.c snippet_Cy_TCPWM_ShiftReg_Init
52 *
53 *******************************************************************************/
Cy_TCPWM_ShiftReg_Init(TCPWM_Type const * base,uint32_t cntNum,cy_stc_tcpwm_shiftreg_config_t const * config)54 cy_en_tcpwm_status_t Cy_TCPWM_ShiftReg_Init(TCPWM_Type const *base, uint32_t cntNum, cy_stc_tcpwm_shiftreg_config_t const *config)
55 {
56 cy_en_tcpwm_status_t status = CY_TCPWM_SUCCESS;
57
58 #if (CY_IP_MXTCPWM_VERSION >= 2U)
59 if ((NULL != base) && (NULL != config))
60 {
61 uint32_t grp = TCPWM_GRP_CNT_GET_GRP(cntNum);
62 bool enabled_bit = _FLD2BOOL(TCPWM_GRP_CNT_V2_CTRL_ENABLED, TCPWM_GRP_CNT_CTRL(base, grp, cntNum));
63
64 TCPWM_GRP_CNT_CTRL(base, grp, cntNum) =
65 (_VAL2FLD(TCPWM_GRP_CNT_V2_CTRL_MODE, CY_TCPWM_MODE_SHIFTREG) |
66 (config->enableCompare0Swap ? TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Msk : 0UL) |
67 _VAL2FLD(TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE,
68 (config->invertShiftRegOut | (config->invertShiftRegOutN << 1U))) |
69 _VAL2FLD(TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE, config->shiftRegOnDisable) |
70 #if defined (CY_IP_MXS40TCPWM)
71 _VAL2FLD(TCPWM_GRP_CNT_V3_CTRL_SWAP_ENABLED, config->buffer_swap_enable) |
72 #endif
73 (enabled_bit ? TCPWM_GRP_CNT_V2_CTRL_ENABLED_Msk : 0UL));
74
75 TCPWM_GRP_CNT_DT(base, grp, cntNum) = _VAL2FLD(TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L, (uint8_t)config->clockPrescaler);
76
77 TCPWM_GRP_CNT_CC0(base, grp, cntNum) = config->compare0;
78 TCPWM_GRP_CNT_CC0_BUFF(base, grp, cntNum) = config->compareBuf0;
79
80 TCPWM_GRP_CNT_PERIOD_BUFF(base, grp, cntNum) = config->tapsEnabled;
81
82 TCPWM_GRP_CNT_TR_IN_SEL0(base, grp, cntNum) =
83 (_VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL, config->serialInput) |
84 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL, config->reloadInput) |
85 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL, config->killInput) |
86 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL, config->shiftInput));
87
88 TCPWM_GRP_CNT_TR_IN_SEL1(base, grp, cntNum) = _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL, config->startInput);
89
90 TCPWM_GRP_CNT_TR_IN_EDGE_SEL(base, grp, cntNum) =
91 (_VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE, config->serialInputMode) |
92 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE, config->reloadInputMode) |
93 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE, config->startInputMode) |
94 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE, config->killInputMode) |
95 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE, config->shiftInputMode));
96
97 TCPWM_GRP_CNT_TR_OUT_SEL(base, grp, cntNum) =
98 (_VAL2FLD(TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0, config->trigger0Event) |
99 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1, config->trigger1Event));
100
101 TCPWM_GRP_CNT_INTR_MASK(base, grp, cntNum) = config->interruptSources;
102
103 if(TCPWM_GRP_CC1(base, grp))
104 {
105 TCPWM_GRP_CNT_CC1(base, grp, cntNum) = config->compare1;
106 TCPWM_GRP_CNT_CC1_BUFF(base, grp, cntNum) = config->compareBuf1;
107
108 TCPWM_GRP_CNT_CTRL(base, grp, cntNum) |=
109 (config->enableCompare1Swap ? TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Msk : 0UL);
110 }
111 }
112 else
113 {
114 status = CY_TCPWM_BAD_PARAM;
115 }
116 #else
117 /* Suppress a compiler warning about unused variables */
118 (void) base;
119 (void) cntNum;
120 (void) config;
121
122 status = CY_TCPWM_UNSUPPORTED_FEATURE;
123 #endif
124 return(status);
125 }
126
127 /*******************************************************************************
128 * Function Name: Cy_TCPWM_ShiftReg_DeInit
129 ****************************************************************************//**
130 *
131 * De-initializes the counter in the TCPWM block, returns register values to
132 * default.
133 *
134 * \param base
135 * The pointer to a TCPWM instance.
136 *
137 * \param cntNum
138 * The Counter instance number in the selected TCPWM.
139 *
140 * \param config
141 * The pointer to a configuration structure. See \ref cy_stc_tcpwm_shiftreg_config_t.
142 *
143 * \snippet tcpwm/shiftreg/snippet/main.c snippet_Cy_TCPWM_ShiftReg_DeInit
144 *
145 *******************************************************************************/
Cy_TCPWM_ShiftReg_DeInit(TCPWM_Type const * base,uint32_t cntNum,cy_stc_tcpwm_shiftreg_config_t const * config)146 void Cy_TCPWM_ShiftReg_DeInit(TCPWM_Type const *base, uint32_t cntNum, cy_stc_tcpwm_shiftreg_config_t const *config)
147 {
148
149 (void) config;
150
151 #if (CY_IP_MXTCPWM_VERSION >= 2U)
152
153 uint32_t grp = TCPWM_GRP_CNT_GET_GRP(cntNum);
154
155 TCPWM_GRP_CNT_CTRL(base, grp, cntNum) = CY_TCPWM_GRP_CNT_CTRL_DEFAULT;
156 TCPWM_GRP_CNT_DT(base, grp, cntNum) = CY_TCPWM_GRP_CNT_DT_DEFAULT;
157 TCPWM_GRP_CNT_COUNTER(base, grp, cntNum) = CY_TCPWM_GRP_CNT_COUNTER_DEFAULT;
158 TCPWM_GRP_CNT_TR_PWM_CTRL(base, grp, cntNum) = CY_TCPWM_GRP_CNT_TR_PWM_CTRL_DEFAULT;
159 TCPWM_GRP_CNT_CC0(base, grp, cntNum) = CY_TCPWM_GRP_CNT_CC0_DEFAULT;
160 TCPWM_GRP_CNT_CC0_BUFF(base, grp, cntNum) = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT;
161 TCPWM_GRP_CNT_CC1(base, grp, cntNum) = CY_TCPWM_GRP_CNT_CC0_DEFAULT;
162 TCPWM_GRP_CNT_CC1_BUFF(base, grp, cntNum) = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT;
163 TCPWM_GRP_CNT_PERIOD(base, grp, cntNum) = CY_TCPWM_GRP_CNT_PERIOD_DEFAULT;
164 TCPWM_GRP_CNT_PERIOD_BUFF(base, grp, cntNum) = CY_TCPWM_GRP_CNT_PERIOD_BUFF_DEFAULT;
165 TCPWM_GRP_CNT_TR_IN_SEL0(base, grp, cntNum) = CY_TCPWM_GRP_CNT_TR_IN_SEL0_DEFAULT;
166 TCPWM_GRP_CNT_TR_IN_SEL1(base, grp, cntNum) = CY_TCPWM_GRP_CNT_TR_IN_SEL1_DEFAULT;
167 TCPWM_GRP_CNT_TR_IN_EDGE_SEL(base, grp, cntNum) = CY_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_DEFAULT;
168 TCPWM_GRP_CNT_INTR_MASK(base, grp, cntNum) = CY_TCPWM_GRP_CNT_INTR_MASK_DEFAULT;
169
170 #else
171
172 /* Suppress a compiler warning about unused variables */
173 (void) base;
174 (void) cntNum;
175
176 #endif /* CY_IP_MXTCPWM_VERSION >= 2U */
177 }
178
179 #if defined(__cplusplus)
180 }
181 #endif
182
183 #endif /* CY_IP_MXTCPWM */
184
185 /* [] END OF FILE */
186
