1 /***************************************************************************//**
2 * \file cy_tcpwm_quaddec.c
3 * \version 1.70
4 *
5 * \brief
6 * The source file of the tcpwm driver.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2016-2021 Cypress Semiconductor Corporation
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_tcpwm_quaddec.h"
27
28 #ifdef CY_IP_MXTCPWM
29
30 #if defined(__cplusplus)
31 extern "C" {
32 #endif
33
34
35 /*******************************************************************************
36 * Function Name: Cy_TCPWM_QuadDec_Init
37 ****************************************************************************//**
38 *
39 * Initializes the counter in the TCPWM block for the QuadDec operation.
40 *
41 * \param base
42 * The pointer to a TCPWM instance.
43 *
44 * \param cntNum
45 * The Counter instance number in the selected TCPWM.
46 *
47 * \param config
48 * The pointer to a configuration structure. See \ref cy_stc_tcpwm_quaddec_config_t.
49 *
50 * \return error / status code. See \ref cy_en_tcpwm_status_t.
51 *
52 * \funcusage
53 * \snippet tcpwm/quaddec/snippet/main.c snippet_Cy_TCPWM_V1_QuadDec_Init
54 * \snippet tcpwm/quaddec/snippet/main.c snippet_Cy_TCPWM_V2_QuadDec_Init
55 *
56 *******************************************************************************/
Cy_TCPWM_QuadDec_Init(TCPWM_Type * base,uint32_t cntNum,cy_stc_tcpwm_quaddec_config_t const * config)57 cy_en_tcpwm_status_t Cy_TCPWM_QuadDec_Init(TCPWM_Type *base, uint32_t cntNum,
58 cy_stc_tcpwm_quaddec_config_t const *config)
59 {
60 cy_en_tcpwm_status_t status = CY_TCPWM_BAD_PARAM;
61
62 if ((NULL != base) && (NULL != config))
63 {
64 #if (CY_IP_MXTCPWM_VERSION == 1U)
65
66 if(config->resolution <= CY_TCPWM_QUADDEC_X4)
67 {
68 TCPWM_CNT_CTRL(base, cntNum) = ( _VAL2FLD(TCPWM_CNT_CTRL_QUADRATURE_MODE, config->resolution) |
69 _VAL2FLD(TCPWM_CNT_CTRL_MODE, CY_TCPWM_QUADDEC_CTRL_QUADDEC_MODE));
70
71 if (CY_TCPWM_INPUT_CREATOR != config->phiAInput)
72 {
73 TCPWM_CNT_TR_CTRL0(base, cntNum) = (_VAL2FLD(TCPWM_CNT_TR_CTRL0_COUNT_SEL, config->phiAInput) |
74 _VAL2FLD(TCPWM_CNT_TR_CTRL0_START_SEL, config->phiBInput) |
75 _VAL2FLD(TCPWM_CNT_TR_CTRL0_RELOAD_SEL, config->indexInput) |
76 _VAL2FLD(TCPWM_CNT_TR_CTRL0_STOP_SEL, config->stopInput));
77 }
78
79 TCPWM_CNT_TR_CTRL1(base, cntNum) = (_VAL2FLD(TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE, CY_TCPWM_INPUT_LEVEL) |
80 _VAL2FLD(TCPWM_CNT_TR_CTRL1_COUNT_EDGE, CY_TCPWM_INPUT_LEVEL) |
81 _VAL2FLD(TCPWM_CNT_TR_CTRL1_START_EDGE, CY_TCPWM_INPUT_LEVEL) |
82 _VAL2FLD(TCPWM_CNT_TR_CTRL1_RELOAD_EDGE, config->indexInputMode) |
83 _VAL2FLD(TCPWM_CNT_TR_CTRL1_STOP_EDGE, config->stopInputMode));
84
85 TCPWM_CNT_INTR_MASK(base, cntNum) = config->interruptSources;
86
87 status = CY_TCPWM_SUCCESS;
88 }
89 else
90 {
91 status = CY_TCPWM_UNSUPPORTED_FEATURE;
92 }
93 #else
94 uint32_t grp = TCPWM_GRP_CNT_GET_GRP(cntNum);
95 bool enabled_bit = _FLD2BOOL(TCPWM_GRP_CNT_V2_CTRL_ENABLED, TCPWM_GRP_CNT_CTRL(base, grp, cntNum));
96
97 TCPWM_GRP_CNT_CTRL(base, grp, cntNum) =
98 ( _VAL2FLD(TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE, config->resolution) |
99 _VAL2FLD(TCPWM_GRP_CNT_V2_CTRL_MODE, CY_TCPWM_QUADDEC_CTRL_QUADDEC_MODE) |
100 _VAL2FLD(TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE, config->quadMode) |
101 (config->enableCompare0Swap ? TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Msk : 0UL) |
102 _VAL2FLD(TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD, (config->captureOnIndex ? CY_TCPWM_QUADDEC_CAPTURE_ON_INDEX : CY_TCPWM_QUADDEC_CAPTURE_ON_WRAP_AROUND)) |
103 #if defined (CY_IP_MXS40TCPWM)
104 _VAL2FLD(TCPWM_GRP_CNT_V3_CTRL_SWAP_ENABLED, config->buffer_swap_enable) |
105 #endif
106 (enabled_bit ? TCPWM_GRP_CNT_V2_CTRL_ENABLED_Msk : 0UL));
107
108 TCPWM_GRP_CNT_TR_IN_SEL0(base, grp, cntNum) =
109 (_VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL, config->capture0OrIndex1Input) |
110 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL, config->phiAInput) |
111 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL, config->indexInput) |
112 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL, config->stopInput));
113
114 TCPWM_GRP_CNT_TR_IN_SEL1(base, grp, cntNum) =
115 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL, config->phiBInput);
116
117 TCPWM_GRP_CNT_CC0(base, grp, cntNum) = config->compare0;
118 TCPWM_GRP_CNT_CC0_BUFF(base, grp, cntNum) = config->compareBuf0;
119 TCPWM_GRP_CNT_PERIOD(base, grp, cntNum) = config->period0;
120
121 TCPWM_GRP_CNT_TR_IN_EDGE_SEL(base, grp, cntNum) =
122 (_VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE, config->capture0OrIndex1InputMode) |
123 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE, config->phiAInputMode) |
124 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE, config->phiBInputMode) |
125 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE, config->indexInputMode) |
126 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE, config->stopInputMode));
127
128 if(TCPWM_GRP_CC1(base, grp))
129 {
130 TCPWM_GRP_CNT_CC1(base, grp, cntNum) = config->compare1;
131 TCPWM_GRP_CNT_CC1_BUFF(base, grp, cntNum) = config->compareBuf1;
132
133 TCPWM_GRP_CNT_CTRL(base, grp, cntNum) |=
134 (config->enableCompare1Swap ? TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Msk : 0UL);
135
136 TCPWM_GRP_CNT_TR_IN_SEL1(base, grp, cntNum) |=
137 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL, config->capture1Input);
138
139 TCPWM_GRP_CNT_TR_IN_EDGE_SEL(base, grp, cntNum) |=
140 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE, config->capture1InputMode);
141 }
142
143 TCPWM_GRP_CNT_TR_OUT_SEL(base, grp, cntNum) =
144 (_VAL2FLD(TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0, config->trigger0Event) |
145 _VAL2FLD(TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1, config->trigger1Event));
146
147 TCPWM_GRP_CNT_INTR_MASK(base, grp, cntNum) = config->interruptSources;
148
149 status = CY_TCPWM_SUCCESS;
150 #endif
151 }
152
153 return(status);
154 }
155
156
157 /*******************************************************************************
158 * Function Name: Cy_TCPWM_QuadDec_DeInit
159 ****************************************************************************//**
160 *
161 * De-initializes the counter in the TCPWM block, returns register values to
162 * default.
163 *
164 * \param base
165 * The pointer to a TCPWM instance.
166 *
167 * \param cntNum
168 * The Counter instance number in the selected TCPWM.
169 *
170 * \param config
171 * The pointer to a configuration structure. See \ref cy_stc_tcpwm_quaddec_config_t.
172 *
173 * \funcusage
174 * \snippet tcpwm/quaddec/snippet/main.c snippet_Cy_TCPWM_QuadDec_DeInit
175 *
176 *******************************************************************************/
Cy_TCPWM_QuadDec_DeInit(TCPWM_Type * base,uint32_t cntNum,cy_stc_tcpwm_quaddec_config_t const * config)177 void Cy_TCPWM_QuadDec_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_quaddec_config_t const *config)
178 {
179 #if (CY_IP_MXTCPWM_VERSION == 1U)
180
181 TCPWM_CNT_CTRL(base, cntNum) = CY_TCPWM_CNT_CTRL_DEFAULT;
182 TCPWM_CNT_COUNTER(base, cntNum) = CY_TCPWM_CNT_COUNTER_DEFAULT;
183 TCPWM_CNT_CC(base, cntNum) = CY_TCPWM_CNT_CC_DEFAULT;
184 TCPWM_CNT_CC_BUFF(base, cntNum) = CY_TCPWM_CNT_CC_BUFF_DEFAULT;
185 TCPWM_CNT_PERIOD(base, cntNum) = CY_TCPWM_CNT_PERIOD_DEFAULT;
186 TCPWM_CNT_PERIOD_BUFF(base, cntNum) = CY_TCPWM_CNT_PERIOD_BUFF_DEFAULT;
187 TCPWM_CNT_TR_CTRL1(base, cntNum) = CY_TCPWM_CNT_TR_CTRL1_DEFAULT;
188 TCPWM_CNT_TR_CTRL2(base, cntNum) = CY_TCPWM_CNT_TR_CTRL2_DEFAULT;
189 TCPWM_CNT_INTR(base, cntNum) = CY_TCPWM_CNT_INTR_DEFAULT;
190 TCPWM_CNT_INTR_SET(base, cntNum) = CY_TCPWM_CNT_INTR_SET_DEFAULT;
191 TCPWM_CNT_INTR_MASK(base, cntNum) = CY_TCPWM_CNT_INTR_MASK_DEFAULT;
192
193 if (CY_TCPWM_INPUT_CREATOR != config->phiAInput)
194 {
195 TCPWM_CNT_TR_CTRL0(base, cntNum) = CY_TCPWM_CNT_TR_CTRL0_DEFAULT;
196 }
197 #else
198 (void)config;
199 uint32_t grp = TCPWM_GRP_CNT_GET_GRP(cntNum);
200 bool enabled_bit = _FLD2BOOL(TCPWM_GRP_CNT_V2_CTRL_ENABLED, TCPWM_GRP_CNT_CTRL(base, grp, cntNum));
201
202 TCPWM_GRP_CNT_CTRL(base, grp, cntNum) = (CY_TCPWM_GRP_CNT_CTRL_DEFAULT | (enabled_bit ? TCPWM_GRP_CNT_V2_CTRL_ENABLED_Msk : 0UL));
203 TCPWM_GRP_CNT_DT(base, grp, cntNum) = CY_TCPWM_GRP_CNT_DT_DEFAULT;
204 TCPWM_GRP_CNT_COUNTER(base, grp, cntNum) = CY_TCPWM_GRP_CNT_COUNTER_DEFAULT;
205 TCPWM_GRP_CNT_TR_PWM_CTRL(base, grp, cntNum) = CY_TCPWM_GRP_CNT_TR_PWM_CTRL_DEFAULT;
206 TCPWM_GRP_CNT_CC0(base, grp, cntNum) = CY_TCPWM_GRP_CNT_CC0_DEFAULT;
207 TCPWM_GRP_CNT_CC0_BUFF(base, grp, cntNum) = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT;
208 TCPWM_GRP_CNT_PERIOD(base, grp, cntNum) = CY_TCPWM_GRP_CNT_PERIOD_DEFAULT;
209 TCPWM_GRP_CNT_PERIOD_BUFF(base, grp, cntNum) = CY_TCPWM_GRP_CNT_PERIOD_BUFF_DEFAULT;
210 TCPWM_GRP_CNT_TR_IN_SEL0(base, grp, cntNum) = CY_TCPWM_GRP_CNT_TR_IN_SEL0_DEFAULT;
211 TCPWM_GRP_CNT_TR_IN_SEL1(base, grp, cntNum) = CY_TCPWM_GRP_CNT_TR_IN_SEL1_DEFAULT;
212 TCPWM_GRP_CNT_TR_IN_EDGE_SEL(base, grp, cntNum) = CY_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_DEFAULT;
213 TCPWM_GRP_CNT_INTR_MASK(base, grp, cntNum) = CY_TCPWM_GRP_CNT_INTR_MASK_DEFAULT;
214 #endif
215 }
216
217 #if defined(__cplusplus)
218 }
219 #endif
220
221 #endif /* CY_IP_MXTCPWM */
222
223 /* [] END OF FILE */
224
