1 /***************************************************************************//**
2 * \file system_psoc6_cm0plus.c
3 * \version 2.90.1
4 *
5 * The device system-source file.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2016-2020 Cypress Semiconductor Corporation
10 * Copyright (c) 2024, Arm Limited. All rights reserved.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include <stdbool.h>
27 #include "system_psoc6.h"
28 #include "cy_device.h"
29 #include "cy_device_headers.h"
30 #include "cy_syslib.h"
31 #include "cy_sysclk.h"
32 #include "cy_wdt.h"
33
34 #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
35 #include "cy_ipc_sema.h"
36 #include "cy_ipc_pipe.h"
37 #include "cy_ipc_drv.h"
38
39 #if defined(CY_DEVICE_PSOC6ABLE2)
40 #include "cy_flash.h"
41 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
42 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
43
44 #if defined(CY_DEVICE_SECURE)
45 #include "cy_pra.h"
46 #endif /* defined(CY_DEVICE_SECURE) */
47
48
49 /*******************************************************************************
50 * SystemCoreClockUpdate()
51 *******************************************************************************/
52
53 /** Default HFClk frequency in Hz */
54 #define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
55
56 /** Default PeriClk frequency in Hz */
57 #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
58
59 /** Default SlowClk system core frequency in Hz */
60 #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
61
62
63 /**
64 * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
65 * which is the system clock frequency supplied to the SysTick timer and the
66 * processor core clock.
67 * This variable implements CMSIS Core global variable.
68 * Refer to the [CMSIS documentation]
69 * (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
70 * for more details.
71 * This variable can be used by debuggers to query the frequency
72 * of the debug timer or to configure the trace clock speed.
73 *
74 * \attention Compilers must be configured to avoid removing this variable in case
75 * the application program is not using it. Debugging systems require the variable
76 * to be physically present in memory so that it can be examined to configure the debugger. */
77 uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
78
79 /** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
80 uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
81
82 /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
83 uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
84
85 /** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
86 uint32_t cy_BleEcoClockFreqHz = 0UL;
87
88
89 /*******************************************************************************
90 * SystemInit()
91 *******************************************************************************/
92
93 /* CLK_FLL_CONFIG default values */
94 #define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
95 #define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
96 #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
97 #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
98
99
100 /*******************************************************************************
101 * SystemCoreClockUpdate (void)
102 *******************************************************************************/
103
104 /* Do not use these definitions directly in your application */
105 #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
106 #define CY_DELAY_1K_THRESHOLD (1000u)
107 #define CY_DELAY_1M_THRESHOLD (1000000u)
108
109 uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
110
111 uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
112
113 uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
114 CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
115
116
117 /*******************************************************************************
118 * Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4()
119 *******************************************************************************/
120 #define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL)
121 #define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
122 #define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL)
123
124
125 /*******************************************************************************
126 * Function Name: SystemInit
127 ****************************************************************************//**
128 *
129 * Initializes the system:
130 * - Restores FLL registers to the default state.
131 * - Unlocks and disables WDT.
132 * - Calls Cy_PDL_Init() function to define the driver library.
133 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
134 * - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
135 * - Calls \ref SystemCoreClockUpdate().
136 *
137 *******************************************************************************/
SystemInit(void)138 void SystemInit(void)
139 {
140 Cy_PDL_Init(CY_DEVICE_CFG);
141
142 /* Restore FLL registers to the default state as they are not restored by the ROM code */
143 uint32_t copy = SRSS->CLK_FLL_CONFIG;
144 copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
145 SRSS->CLK_FLL_CONFIG = copy;
146
147 copy = SRSS->CLK_ROOT_SELECT[0u];
148 copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
149 SRSS->CLK_ROOT_SELECT[0u] = copy;
150
151 SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
152 SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
153 SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
154 SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
155
156 /* Unlock and disable WDT */
157 Cy_WDT_Unlock();
158 Cy_WDT_Disable();
159
160 Cy_SystemInit();
161 SystemCoreClockUpdate();
162
163 /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
164 REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
165
166 /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
167 REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
168
169 #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
170 /* Allocate and initialize semaphores for the system operations. */
171 CY_SECTION_SHAREDMEM
172 static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
173
174 (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
175
176
177 /********************************************************************************
178 *
179 * Initializes the system pipes. The system pipes are used by BLE and Flash.
180 *
181 * If the default startup file is not used, or SystemInit() is not called in your
182 * project, call the following three functions prior to executing any flash or
183 * EmEEPROM write or erase operation:
184 * -# Cy_IPC_Sema_Init()
185 * -# Cy_IPC_Pipe_Config()
186 * -# Cy_IPC_Pipe_Init()
187 * -# Cy_Flash_Init()
188 *
189 *******************************************************************************/
190
191 /* Create an array of endpoint structures */
192 static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
193
194 Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
195
196 static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
197
198 static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 =
199 {
200 /* .ep0ConfigData */
201 {
202 /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
203 /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
204 /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
205 /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
206 /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
207 },
208 /* .ep1ConfigData */
209 {
210 /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
211 /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
212 /* .ipcNotifierMuxNumber */ 0u,
213 /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
214 /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
215 },
216 /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
217 /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
218 /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
219 };
220
221 Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
222
223 #if defined(CY_DEVICE_PSOC6ABLE2)
224 Cy_Flash_Init();
225 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
226
227 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
228
229 #if defined(CY_DEVICE_SECURE)
230 /* Initialize Protected Regsiter Access driver. */
231 Cy_PRA_Init();
232 #endif /* defined(CY_DEVICE_SECURE) */
233 }
234
235
236 /*******************************************************************************
237 * Function Name: Cy_SystemInit
238 ****************************************************************************//**
239 *
240 * The function is called during device startup. Once project compiled as part of
241 * the PSoC Creator project, the Cy_SystemInit() function is generated by the
242 * PSoC Creator.
243 *
244 * The function generated by PSoC Creator performs all of the necessary device
245 * configuration based on the design settings. This includes settings from the
246 * Design Wide Resources (DWR) such as Clocks and Pins as well as any component
247 * configuration that is necessary.
248 *
249 *******************************************************************************/
Cy_SystemInit(void)250 __WEAK void Cy_SystemInit(void)
251 {
252 /* Empty weak function. The actual implementation to be in the PSoC Creator
253 * generated strong function.
254 */
255 }
256
257
258 /*******************************************************************************
259 * Function Name: SystemCoreClockUpdate
260 ****************************************************************************//**
261 *
262 * Gets core clock frequency and updates \ref SystemCoreClock.
263 *
264 * Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
265 * Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
266 *
267 *******************************************************************************/
SystemCoreClockUpdate(void)268 void SystemCoreClockUpdate (void)
269 {
270 uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
271
272 if (0UL != locHf0Clock)
273 {
274 cy_Hfclk0FreqHz = locHf0Clock;
275 cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
276 SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider());
277
278 /* Sets clock frequency for Delay API */
279 cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
280 cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
281 cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
282 }
283 }
284
285
286 #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
287 /*******************************************************************************
288 * Function Name: Cy_SysGetCM4Status
289 ****************************************************************************//**
290 *
291 * Returns the Cortex-M4 core power mode.
292 *
293 * \return \ref group_system_config_cm4_status_macro
294 *
295 *******************************************************************************/
Cy_SysGetCM4Status(void)296 uint32_t Cy_SysGetCM4Status(void)
297 {
298 uint32_t regValue;
299
300 /* Get current power mode */
301 regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk;
302
303 return (regValue);
304 }
305
306
307 /*******************************************************************************
308 * Function Name: Cy_SysEnableCM4
309 ****************************************************************************//**
310 *
311 * Sets vector table base address and enables the Cortex-M4 core.
312 *
313 * \note If the CPU is already enabled, it is reset and then enabled.
314 *
315 * \param vectorTableOffset The offset of the vector table base address from
316 * memory address 0x00000000. The offset should be multiple to 1024 bytes.
317 *
318 *******************************************************************************/
Cy_SysEnableCM4(uint32_t vectorTableOffset)319 void Cy_SysEnableCM4(uint32_t vectorTableOffset)
320 {
321 uint32_t regValue;
322 uint32_t interruptState;
323 uint32_t cpuState;
324
325 CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL);
326
327 interruptState = Cy_SysLib_EnterCriticalSection();
328
329 cpuState = Cy_SysGetCM4Status();
330 if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
331 {
332 Cy_SysResetCM4();
333 }
334
335 CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
336
337 regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
338 regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
339 regValue |= CY_SYS_CM4_STATUS_ENABLED;
340 CPUSS->CM4_PWR_CTL = regValue;
341
342 while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
343 {
344 /* Wait for the power mode to take effect */
345 }
346
347 Cy_SysLib_ExitCriticalSection(interruptState);
348 }
349
350
351 /*******************************************************************************
352 * Function Name: Cy_SysDisableCM4
353 ****************************************************************************//**
354 *
355 * Disables the Cortex-M4 core and waits for the mode to take the effect.
356 *
357 * \warning Do not call the function while the Cortex-M4 is executing because
358 * such a call may corrupt/abort a pending bus-transaction by the CPU and cause
359 * unexpected behavior in the system including a deadlock. Call the function
360 * while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
361 * the \ref group_syspm Power Management (syspm) API to put the CPU into the
362 * low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the
363 * CPU.
364 *
365 *******************************************************************************/
Cy_SysDisableCM4(void)366 void Cy_SysDisableCM4(void)
367 {
368 uint32_t interruptState;
369 uint32_t regValue;
370
371 interruptState = Cy_SysLib_EnterCriticalSection();
372
373 regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
374 regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
375 regValue |= CY_SYS_CM4_STATUS_DISABLED;
376 CPUSS->CM4_PWR_CTL = regValue;
377
378 while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
379 {
380 /* Wait for the power mode to take effect */
381 }
382
383 Cy_SysLib_ExitCriticalSection(interruptState);
384 }
385
386
387 /*******************************************************************************
388 * Function Name: Cy_SysRetainCM4
389 ****************************************************************************//**
390 *
391 * Retains the Cortex-M4 core and exists without waiting for the mode to take
392 * effect.
393 *
394 * \note The retained mode can be entered only from the enabled mode.
395 *
396 * \warning Do not call the function while the Cortex-M4 is executing because
397 * such a call may corrupt/abort a pending bus-transaction by the CPU and cause
398 * unexpected behavior in the system including a deadlock. Call the function
399 * while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
400 * the \ref group_syspm Power Management (syspm) API to put the CPU into the
401 * low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
402 *
403 *******************************************************************************/
Cy_SysRetainCM4(void)404 void Cy_SysRetainCM4(void)
405 {
406 uint32_t interruptState;
407 uint32_t regValue;
408
409 interruptState = Cy_SysLib_EnterCriticalSection();
410
411 regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
412 regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
413 regValue |= CY_SYS_CM4_STATUS_RETAINED;
414 CPUSS->CM4_PWR_CTL = regValue;
415
416 Cy_SysLib_ExitCriticalSection(interruptState);
417 }
418
419
420 /*******************************************************************************
421 * Function Name: Cy_SysResetCM4
422 ****************************************************************************//**
423 *
424 * Resets the Cortex-M4 core and waits for the mode to take the effect.
425 *
426 * \note The reset mode can not be entered from the retained mode.
427 *
428 * \warning Do not call the function while the Cortex-M4 is executing because
429 * such a call may corrupt/abort a pending bus-transaction by the CPU and cause
430 * unexpected behavior in the system including a deadlock. Call the function
431 * while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
432 * the \ref group_syspm Power Management (syspm) API to put the CPU into the
433 * low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
434 *
435 *******************************************************************************/
Cy_SysResetCM4(void)436 void Cy_SysResetCM4(void)
437 {
438 uint32_t interruptState;
439 uint32_t regValue;
440
441 interruptState = Cy_SysLib_EnterCriticalSection();
442
443 regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
444 regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
445 regValue |= CY_SYS_CM4_STATUS_RESET;
446 CPUSS->CM4_PWR_CTL = regValue;
447
448 while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
449 {
450 /* Wait for the power mode to take effect */
451 }
452
453 Cy_SysLib_ExitCriticalSection(interruptState);
454 }
455 #endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */
456
457 #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
458 /*******************************************************************************
459 * Function Name: Cy_SysIpcPipeIsrCm0
460 ****************************************************************************//**
461 *
462 * This is the interrupt service routine for the system pipe.
463 *
464 *******************************************************************************/
Cy_SysIpcPipeIsrCm0(void)465 void Cy_SysIpcPipeIsrCm0(void)
466 {
467 Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR);
468 }
469 #endif
470
471
472 /*******************************************************************************
473 * Function Name: Cy_MemorySymbols
474 ****************************************************************************//**
475 *
476 * The intention of the function is to declare boundaries of the memories for the
477 * MDK compilers. For the rest of the supported compilers, this is done using
478 * linker configuration files. The following symbols used by the cymcuelftool.
479 *
480 *******************************************************************************/
481 #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
Cy_MemorySymbols(void)482 __asm void Cy_MemorySymbols(void)
483 {
484 /* Flash */
485 EXPORT __cy_memory_0_start
486 EXPORT __cy_memory_0_length
487 EXPORT __cy_memory_0_row_size
488
489 /* Working Flash */
490 EXPORT __cy_memory_1_start
491 EXPORT __cy_memory_1_length
492 EXPORT __cy_memory_1_row_size
493
494 /* Supervisory Flash */
495 EXPORT __cy_memory_2_start
496 EXPORT __cy_memory_2_length
497 EXPORT __cy_memory_2_row_size
498
499 /* XIP */
500 EXPORT __cy_memory_3_start
501 EXPORT __cy_memory_3_length
502 EXPORT __cy_memory_3_row_size
503
504 /* eFuse */
505 EXPORT __cy_memory_4_start
506 EXPORT __cy_memory_4_length
507 EXPORT __cy_memory_4_row_size
508
509 /* Flash */
510 __cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
511 __cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
512 __cy_memory_0_row_size EQU 0x200
513
514 /* Flash region for EEPROM emulation */
515 __cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
516 __cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
517 __cy_memory_1_row_size EQU 0x200
518
519 /* Supervisory Flash */
520 __cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
521 __cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
522 __cy_memory_2_row_size EQU 0x200
523
524 /* XIP */
525 __cy_memory_3_start EQU __cpp(CY_XIP_BASE)
526 __cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
527 __cy_memory_3_row_size EQU 0x200
528
529 /* eFuse */
530 __cy_memory_4_start EQU __cpp(0x90700000)
531 __cy_memory_4_length EQU __cpp(0x100000)
532 __cy_memory_4_row_size EQU __cpp(1)
533 }
534 #endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
535
536 __NO_RETURN void __WEAK PendSV_Handler(void);
PendSV_Handler(void)537 void PendSV_Handler(void) {
538 while(1);
539 }
540
541 /* [] END OF FILE */
542
