1 /***************************************************************************//**
2 * \file system_psoc6_cm0plus.c
3 * \version 2.90.1
4 *
5 * The device system-source file.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2016-2020 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24
25 #include <stdbool.h>
26 #include "system_psoc6.h"
27 #include "cy_device.h"
28 #include "cy_device_headers.h"
29 #include "cy_syslib.h"
30 #include "cy_sysclk.h"
31 #include "cy_wdt.h"
32
33 #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
34 #include "cy_ipc_sema.h"
35 #include "cy_ipc_pipe.h"
36 #include "cy_ipc_drv.h"
37
38 #if defined(CY_DEVICE_PSOC6ABLE2)
39 #include "cy_flash.h"
40 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
41 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
42
43 #if defined(CY_DEVICE_SECURE)
44 #include "cy_pra.h"
45 #endif /* defined(CY_DEVICE_SECURE) */
46
47
48 /*******************************************************************************
49 * SystemCoreClockUpdate()
50 *******************************************************************************/
51
52 /** Default HFClk frequency in Hz */
53 #define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
54
55 /** Default PeriClk frequency in Hz */
56 #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
57
58 /** Default SlowClk system core frequency in Hz */
59 #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
60
61
62 /**
63 * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
64 * which is the system clock frequency supplied to the SysTick timer and the
65 * processor core clock.
66 * This variable implements CMSIS Core global variable.
67 * Refer to the [CMSIS documentation]
68 * (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
69 * for more details.
70 * This variable can be used by debuggers to query the frequency
71 * of the debug timer or to configure the trace clock speed.
72 *
73 * \attention Compilers must be configured to avoid removing this variable in case
74 * the application program is not using it. Debugging systems require the variable
75 * to be physically present in memory so that it can be examined to configure the debugger. */
76 uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
77
78 /** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
79 uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
80
81 /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
82 uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
83
84 /** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
85 uint32_t cy_BleEcoClockFreqHz = 0UL;
86
87
88 /*******************************************************************************
89 * SystemInit()
90 *******************************************************************************/
91
92 /* CLK_FLL_CONFIG default values */
93 #define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
94 #define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
95 #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
96 #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
97
98
99 /*******************************************************************************
100 * SystemCoreClockUpdate (void)
101 *******************************************************************************/
102
103 /* Do not use these definitions directly in your application */
104 #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
105 #define CY_DELAY_1K_THRESHOLD (1000u)
106 #define CY_DELAY_1M_THRESHOLD (1000000u)
107
108 uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
109
110 uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
111
112 uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
113 CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
114
115
116 /*******************************************************************************
117 * Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4()
118 *******************************************************************************/
119 #define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL)
120 #define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
121 #define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL)
122
123
124 /*******************************************************************************
125 * Function Name: SystemInit
126 ****************************************************************************//**
127 *
128 * Initializes the system:
129 * - Restores FLL registers to the default state.
130 * - Unlocks and disables WDT.
131 * - Calls Cy_PDL_Init() function to define the driver library.
132 * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
133 * - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
134 * - Calls \ref SystemCoreClockUpdate().
135 *
136 *******************************************************************************/
SystemInit(void)137 void SystemInit(void)
138 {
139 Cy_PDL_Init(CY_DEVICE_CFG);
140
141 /* Restore FLL registers to the default state as they are not restored by the ROM code */
142 uint32_t copy = SRSS->CLK_FLL_CONFIG;
143 copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
144 SRSS->CLK_FLL_CONFIG = copy;
145
146 copy = SRSS->CLK_ROOT_SELECT[0u];
147 copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
148 SRSS->CLK_ROOT_SELECT[0u] = copy;
149
150 SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
151 SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
152 SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
153 SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
154
155 /* Unlock and disable WDT */
156 Cy_WDT_Unlock();
157 Cy_WDT_Disable();
158
159 Cy_SystemInit();
160 SystemCoreClockUpdate();
161
162 /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
163 REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
164
165 /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
166 REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
167
168 #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
169 /* Allocate and initialize semaphores for the system operations. */
170 CY_SECTION_SHAREDMEM
171 static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
172
173 (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
174
175
176 /********************************************************************************
177 *
178 * Initializes the system pipes. The system pipes are used by BLE and Flash.
179 *
180 * If the default startup file is not used, or SystemInit() is not called in your
181 * project, call the following three functions prior to executing any flash or
182 * EmEEPROM write or erase operation:
183 * -# Cy_IPC_Sema_Init()
184 * -# Cy_IPC_Pipe_Config()
185 * -# Cy_IPC_Pipe_Init()
186 * -# Cy_Flash_Init()
187 *
188 *******************************************************************************/
189
190 /* Create an array of endpoint structures */
191 static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
192
193 Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
194
195 static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
196
197 static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 =
198 {
199 /* .ep0ConfigData */
200 {
201 /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
202 /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
203 /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
204 /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
205 /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
206 },
207 /* .ep1ConfigData */
208 {
209 /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
210 /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
211 /* .ipcNotifierMuxNumber */ 0u,
212 /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
213 /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
214 },
215 /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
216 /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
217 /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
218 };
219
220 Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
221
222 #if defined(CY_DEVICE_PSOC6ABLE2)
223 Cy_Flash_Init();
224 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
225
226 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
227
228 #if defined(CY_DEVICE_SECURE)
229 /* Initialize Protected Regsiter Access driver. */
230 Cy_PRA_Init();
231 #endif /* defined(CY_DEVICE_SECURE) */
232 }
233
234
235 /*******************************************************************************
236 * Function Name: Cy_SystemInit
237 ****************************************************************************//**
238 *
239 * The function is called during device startup. Once project compiled as part of
240 * the PSoC Creator project, the Cy_SystemInit() function is generated by the
241 * PSoC Creator.
242 *
243 * The function generated by PSoC Creator performs all of the necessary device
244 * configuration based on the design settings. This includes settings from the
245 * Design Wide Resources (DWR) such as Clocks and Pins as well as any component
246 * configuration that is necessary.
247 *
248 *******************************************************************************/
Cy_SystemInit(void)249 __WEAK void Cy_SystemInit(void)
250 {
251 /* Empty weak function. The actual implementation to be in the PSoC Creator
252 * generated strong function.
253 */
254 }
255
256
257 /*******************************************************************************
258 * Function Name: SystemCoreClockUpdate
259 ****************************************************************************//**
260 *
261 * Gets core clock frequency and updates \ref SystemCoreClock.
262 *
263 * Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
264 * Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
265 *
266 *******************************************************************************/
SystemCoreClockUpdate(void)267 void SystemCoreClockUpdate (void)
268 {
269 uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
270
271 if (0UL != locHf0Clock)
272 {
273 cy_Hfclk0FreqHz = locHf0Clock;
274 cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
275 SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider());
276
277 /* Sets clock frequency for Delay API */
278 cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
279 cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
280 cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
281 }
282 }
283
284
285 #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
286 /*******************************************************************************
287 * Function Name: Cy_SysGetCM4Status
288 ****************************************************************************//**
289 *
290 * Returns the Cortex-M4 core power mode.
291 *
292 * \return \ref group_system_config_cm4_status_macro
293 *
294 *******************************************************************************/
Cy_SysGetCM4Status(void)295 uint32_t Cy_SysGetCM4Status(void)
296 {
297 uint32_t regValue;
298
299 /* Get current power mode */
300 regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk;
301
302 return (regValue);
303 }
304
305
306 /*******************************************************************************
307 * Function Name: Cy_SysEnableCM4
308 ****************************************************************************//**
309 *
310 * Sets vector table base address and enables the Cortex-M4 core.
311 *
312 * \note If the CPU is already enabled, it is reset and then enabled.
313 *
314 * \param vectorTableOffset The offset of the vector table base address from
315 * memory address 0x00000000. The offset should be multiple to 1024 bytes.
316 *
317 *******************************************************************************/
Cy_SysEnableCM4(uint32_t vectorTableOffset)318 void Cy_SysEnableCM4(uint32_t vectorTableOffset)
319 {
320 uint32_t regValue;
321 uint32_t interruptState;
322 uint32_t cpuState;
323
324 CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL);
325
326 interruptState = Cy_SysLib_EnterCriticalSection();
327
328 cpuState = Cy_SysGetCM4Status();
329 if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
330 {
331 Cy_SysResetCM4();
332 }
333
334 CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
335
336 regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
337 regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
338 regValue |= CY_SYS_CM4_STATUS_ENABLED;
339 CPUSS->CM4_PWR_CTL = regValue;
340
341 while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
342 {
343 /* Wait for the power mode to take effect */
344 }
345
346 Cy_SysLib_ExitCriticalSection(interruptState);
347 }
348
349
350 /*******************************************************************************
351 * Function Name: Cy_SysDisableCM4
352 ****************************************************************************//**
353 *
354 * Disables the Cortex-M4 core and waits for the mode to take the effect.
355 *
356 * \warning Do not call the function while the Cortex-M4 is executing because
357 * such a call may corrupt/abort a pending bus-transaction by the CPU and cause
358 * unexpected behavior in the system including a deadlock. Call the function
359 * while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
360 * the \ref group_syspm Power Management (syspm) API to put the CPU into the
361 * low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the
362 * CPU.
363 *
364 *******************************************************************************/
Cy_SysDisableCM4(void)365 void Cy_SysDisableCM4(void)
366 {
367 uint32_t interruptState;
368 uint32_t regValue;
369
370 interruptState = Cy_SysLib_EnterCriticalSection();
371
372 regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
373 regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
374 regValue |= CY_SYS_CM4_STATUS_DISABLED;
375 CPUSS->CM4_PWR_CTL = regValue;
376
377 while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
378 {
379 /* Wait for the power mode to take effect */
380 }
381
382 Cy_SysLib_ExitCriticalSection(interruptState);
383 }
384
385
386 /*******************************************************************************
387 * Function Name: Cy_SysRetainCM4
388 ****************************************************************************//**
389 *
390 * Retains the Cortex-M4 core and exists without waiting for the mode to take
391 * effect.
392 *
393 * \note The retained mode can be entered only from the enabled mode.
394 *
395 * \warning Do not call the function while the Cortex-M4 is executing because
396 * such a call may corrupt/abort a pending bus-transaction by the CPU and cause
397 * unexpected behavior in the system including a deadlock. Call the function
398 * while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
399 * the \ref group_syspm Power Management (syspm) API to put the CPU into the
400 * low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
401 *
402 *******************************************************************************/
Cy_SysRetainCM4(void)403 void Cy_SysRetainCM4(void)
404 {
405 uint32_t interruptState;
406 uint32_t regValue;
407
408 interruptState = Cy_SysLib_EnterCriticalSection();
409
410 regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
411 regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
412 regValue |= CY_SYS_CM4_STATUS_RETAINED;
413 CPUSS->CM4_PWR_CTL = regValue;
414
415 Cy_SysLib_ExitCriticalSection(interruptState);
416 }
417
418
419 /*******************************************************************************
420 * Function Name: Cy_SysResetCM4
421 ****************************************************************************//**
422 *
423 * Resets the Cortex-M4 core and waits for the mode to take the effect.
424 *
425 * \note The reset mode can not be entered from the retained mode.
426 *
427 * \warning Do not call the function while the Cortex-M4 is executing because
428 * such a call may corrupt/abort a pending bus-transaction by the CPU and cause
429 * unexpected behavior in the system including a deadlock. Call the function
430 * while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
431 * the \ref group_syspm Power Management (syspm) API to put the CPU into the
432 * low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
433 *
434 *******************************************************************************/
Cy_SysResetCM4(void)435 void Cy_SysResetCM4(void)
436 {
437 uint32_t interruptState;
438 uint32_t regValue;
439
440 interruptState = Cy_SysLib_EnterCriticalSection();
441
442 regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
443 regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
444 regValue |= CY_SYS_CM4_STATUS_RESET;
445 CPUSS->CM4_PWR_CTL = regValue;
446
447 while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
448 {
449 /* Wait for the power mode to take effect */
450 }
451
452 Cy_SysLib_ExitCriticalSection(interruptState);
453 }
454 #endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */
455
456 #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
457 /*******************************************************************************
458 * Function Name: Cy_SysIpcPipeIsrCm0
459 ****************************************************************************//**
460 *
461 * This is the interrupt service routine for the system pipe.
462 *
463 *******************************************************************************/
Cy_SysIpcPipeIsrCm0(void)464 void Cy_SysIpcPipeIsrCm0(void)
465 {
466 Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR);
467 }
468 #endif
469
470
471 /*******************************************************************************
472 * Function Name: Cy_MemorySymbols
473 ****************************************************************************//**
474 *
475 * The intention of the function is to declare boundaries of the memories for the
476 * MDK compilers. For the rest of the supported compilers, this is done using
477 * linker configuration files. The following symbols used by the cymcuelftool.
478 *
479 *******************************************************************************/
480 #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
Cy_MemorySymbols(void)481 __asm void Cy_MemorySymbols(void)
482 {
483 /* Flash */
484 EXPORT __cy_memory_0_start
485 EXPORT __cy_memory_0_length
486 EXPORT __cy_memory_0_row_size
487
488 /* Working Flash */
489 EXPORT __cy_memory_1_start
490 EXPORT __cy_memory_1_length
491 EXPORT __cy_memory_1_row_size
492
493 /* Supervisory Flash */
494 EXPORT __cy_memory_2_start
495 EXPORT __cy_memory_2_length
496 EXPORT __cy_memory_2_row_size
497
498 /* XIP */
499 EXPORT __cy_memory_3_start
500 EXPORT __cy_memory_3_length
501 EXPORT __cy_memory_3_row_size
502
503 /* eFuse */
504 EXPORT __cy_memory_4_start
505 EXPORT __cy_memory_4_length
506 EXPORT __cy_memory_4_row_size
507
508 /* Flash */
509 __cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
510 __cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
511 __cy_memory_0_row_size EQU 0x200
512
513 /* Flash region for EEPROM emulation */
514 __cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
515 __cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
516 __cy_memory_1_row_size EQU 0x200
517
518 /* Supervisory Flash */
519 __cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
520 __cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
521 __cy_memory_2_row_size EQU 0x200
522
523 /* XIP */
524 __cy_memory_3_start EQU __cpp(CY_XIP_BASE)
525 __cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
526 __cy_memory_3_row_size EQU 0x200
527
528 /* eFuse */
529 __cy_memory_4_start EQU __cpp(0x90700000)
530 __cy_memory_4_length EQU __cpp(0x100000)
531 __cy_memory_4_row_size EQU __cpp(1)
532 }
533 #endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
534
535
536 /* [] END OF FILE */
537
