1 /***************************************************************************//**
2 * \file cy_syspm_v4.c
3 * \version 5.94
4 *
5 * This driver provides the source code for API power management.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_device.h"
27 #include "cy_sysclk.h"
28
29 #if defined (CY_IP_MXS22SRSS)
30
31 #include "cy_syspm.h"
32
33 #include "cy_syspm_ppu.h"
34
35 #include "cy_rram.h"
36
37
38
39 /*******************************************************************************
40 * Internal Functions
41 *******************************************************************************/
42
43
44 /*******************************************************************************
45 * Internal Defines
46 *******************************************************************************/
47
48 /* The define for number of callback roots */
49 #define CALLBACK_ROOT_NR (8U)
50
51 /* The mask to unlock the Hibernate power mode */
52 #define HIBERNATE_UNLOCK_VAL ((uint32_t) 0x3Au << SRSS_PWR_HIBERNATE_UNLOCK_Pos)
53
54 /* The mask to set the Hibernate power mode */
55 #define SET_HIBERNATE_MODE ((HIBERNATE_UNLOCK_VAL |\
56 SRSS_PWR_HIBERNATE_FREEZE_Msk |\
57 SRSS_PWR_HIBERNATE_HIBERNATE_Msk))
58
59 /* The mask to retain the Hibernate power mode status */
60 #define HIBERNATE_RETAIN_STATUS_MASK ((SRSS_PWR_HIBERNATE_TOKEN_Msk |\
61 SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\
62 SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\
63 SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\
64 SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk))
65
66 /** The mask for the Hibernate wakeup sources */
67 #define HIBERNATE_WAKEUP_MASK ((SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_SRC_Msk |\
68 SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_CSV_BAK_Msk |\
69 SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_RTC_Msk |\
70 SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_WDT_Msk))
71
72 /** The define to update the token to indicate the transition into Hibernate */
73 #define HIBERNATE_TOKEN ((uint32_t) 0x1BU << SRSS_PWR_HIBERNATE_TOKEN_Pos)
74
75 /* The wait time for transition into the minimum regulator current mode
76 */
77 #define SET_MIN_CURRENT_MODE_DELAY_US (1U)
78
79 /* The wait delay time that occurs before the active reference is settled.
80 * Intermediate delay is used in transition into the normal regulator current
81 * mode, it should be two IHO cycles, which is (2 x 1/50000000)
82 * = 1 micro second(Approximated)
83 */
84 #define ACT_REF_SETTLE_DELAY_US (1U)
85
86 /* The wait delay time that occurs after the active reference is settled.
87 * Final delay is used in transition into the normal regulator current mode
88 */
89 #define SET_NORMAL_CURRENT_MODE_DELAY_US (1U)
90
91 /* The internal define of the tries number in the
92 * Cy_SysPm_SystemSetMinRegulatorCurrent() function
93 */
94 #define WAIT_DELAY_TRIES (100U)
95
96 /* The internal define of the tries number in the
97 * Cy_SysPm_SystemSetMinRegulatorCurrent() function
98 */
99 #define CY_SYSPM_CBUCK_BUSY_RETRY_COUNT (100U)
100 #define CY_SYSPM_CBUCK_BUSY_RETRY_DELAY_MS (1U)
101
102 /* SRAM TRIM Values
103 */
104 #define RAM_TRIM_VAL_A 0x0000000AU
105 #define RAM_TRIM_VAL_B 0x0000000BU
106 #define RAM_TRIM_VAL_C 0x0000000CU
107 #define RAM_TRIM_VAL_F 0x0000000FU
108 #define RAM_TRIM_VAL_1B 0x0000001BU
109 #define RAM_TRIM_VAL_2D 0x0000002DU
110 #define RAM_TRIM_VAL_3F 0x0000003FU
111 #define RAM_TRIM_VAL_202 0x00000202U
112 #define RAM_TRIM_VAL_203 0x00000203U
113 #define RAM_TRIM_VAL_204 0x00000204U
114 #define RAM_TRIM_VAL_206 0x00000206U
115 #define RAM_TRIM_VAL_207 0x00000207U
116 #define RAM_TRIM_VAL_20A 0x0000020AU
117 #define RAM_TRIM_VAL_20B 0x0000020BU
118 #define RAM_TRIM_VAL_20C 0x0000020CU
119 #define RAM_TRIM_VAL_20F 0x0000020FU
120 #define RAM_TRIM_VAL_21A 0x0000021AU
121 #define RAM_TRIM_VAL_21B 0x0000021BU
122 #define RAM_TRIM_VAL_21F 0x0000021FU
123 #define RAM_TRIM_VAL_22D 0x0000022DU
124 #define RAM_TRIM_VAL_23D 0x0000023DU
125 #define RAM_TRIM_VAL_23F 0x0000023FU
126 #define RAM_TRIM_VAL_342 0x00000342U
127 #define RAM_TRIM_VAL_343 0x00000343U
128 #define RAM_TRIM_VAL_603 0x00000603U
129 #define RAM_TRIM_VAL_604 0x00000604U
130 #define RAM_TRIM_VAL_605 0x00000605U
131 #define RAM_TRIM_VAL_606 0x00000606U
132 #define RAM_TRIM_VAL_607 0x00000607U
133 #define RAM_TRIM_VAL_60B 0x0000060BU
134 #define RAM_TRIM_VAL_60C 0x0000060CU
135 #define RAM_TRIM_VAL_60F 0x0000060FU
136 #define RAM_TRIM_VAL_61B 0x0000061BU
137 #define RAM_TRIM_VAL_61C 0x0000061CU
138 #define RAM_TRIM_VAL_61D 0x0000061DU
139 #define RAM_TRIM_VAL_61F 0x0000061FU
140 #define RAM_TRIM_VAL_62D 0x0000062DU
141 #define RAM_TRIM_VAL_63D 0x0000063DU
142 #define RAM_TRIM_VAL_63F 0x0000063FU
143 #define RAM_TRIM_VAL_743 0x00000743U
144 #define RAM_TRIM_VAL_E3F 0x00000E3FU
145 #define RAM_TRIM_VAL_1E3F 0x00001E3FU
146
147
148 /*******************************************************************************
149 * Internal Variables
150 *******************************************************************************/
151
152 /* Array of the callback roots */
153 static cy_stc_syspm_callback_t* pmCallbackRoot[CALLBACK_ROOT_NR] = {(void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U};
154
155 /* The array of the pointers to failed callback */
156 static cy_stc_syspm_callback_t* failedCallback[CALLBACK_ROOT_NR] = {(void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U, (void *)0U};
157
158
Cy_SysPm_Init(void)159 void Cy_SysPm_Init(void)
160 {
161 if(CY_SYSPM_WARM_BOOT_MODE != Cy_SysPm_GetBootMode())
162 {
163 /* Set Default mode to DEEPSLEEP */
164 (void)Cy_SysPm_SetDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP);
165 }
166 else
167 {
168 /* Call the registered callback functions with the CY_SYSPM_AFTER_TRANSITION
169 * parameter
170 */
171 if (pmCallbackRoot[CY_SYSPM_DEEPSLEEP_RAM] != NULL)
172 {
173 (void)Cy_SysPm_ExecuteCallback(((cy_en_syspm_callback_type_t)CY_SYSPM_DEEPSLEEP_RAM), CY_SYSPM_AFTER_TRANSITION); /* Suppress a compiler warning about unused return value */
174 }
175 }
176 }
177
Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor)178 cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor)
179 {
180 uint32_t interruptState;
181 uint32_t cbSleepRootIdx = (uint32_t) CY_SYSPM_SLEEP;
182 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
183
184 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor));
185
186 /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */
187 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
188 {
189 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_READY);
190 }
191
192 /* The CPU can switch into the Sleep power mode only when
193 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
194 * parameter return CY_SYSPM_SUCCESS.
195 */
196 if(retVal == CY_SYSPM_SUCCESS)
197 {
198 /* Call the registered callback functions with
199 * CY_SYSPM_BEFORE_TRANSITION parameter
200 */
201 interruptState = Cy_SysLib_EnterCriticalSection();
202 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
203 {
204 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_BEFORE_TRANSITION);
205 }
206
207 /* The CPU enters the Sleep power mode upon execution of WFI/WFE */
208 SCB_SCR &= (uint32_t) ~SCB_SCR_SLEEPDEEP_Msk;
209
210 if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
211 {
212 __WFI();
213 }
214 else
215 {
216 __WFE();
217 }
218 Cy_SysLib_ExitCriticalSection(interruptState);
219
220 /* Call the registered callback functions with the
221 * CY_SYSPM_AFTER_TRANSITION parameter
222 */
223 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
224 {
225 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_AFTER_TRANSITION);
226 }
227 }
228 else
229 {
230 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
231 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
232 * parameter
233 */
234 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_FAIL);
235 retVal = CY_SYSPM_FAIL;
236 }
237 return retVal;
238 }
239
240
Cy_SysPm_SetSysDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)241 cy_en_syspm_status_t Cy_SysPm_SetSysDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)
242 {
243 cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
244
245 switch(deepSleepMode)
246 {
247 case CY_SYSPM_MODE_DEEPSLEEP:
248 {
249 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_MAIN_BASE, (uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
250 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SRAM0_BASE, (uint32_t)CY_SYSTEM_SRAM0_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
251 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SRAM1_BASE, (uint32_t)CY_SYSTEM_SRAM1_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
252 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SYSCPU_BASE, (uint32_t)CY_SYSTEM_SYSCPU_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
253
254 #if (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)
255 SCS_CPPWR &= ~(SCS_CPPWR_SU10_Msk);
256 #endif
257
258 retVal = CY_SYSPM_SUCCESS;
259 }
260 break;
261
262 case CY_SYSPM_MODE_DEEPSLEEP_RAM:
263 {
264 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_MAIN_BASE, (uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
265 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SRAM0_BASE, (uint32_t)CY_SYSTEM_SRAM0_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
266 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SRAM1_BASE, (uint32_t)CY_SYSTEM_SRAM1_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
267 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SYSCPU_BASE, (uint32_t)CY_SYSTEM_SYSCPU_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
268
269 #if (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)
270 SCS_CPPWR |= SCS_CPPWR_SU10_Msk;
271 #endif
272
273 retVal = CY_SYSPM_SUCCESS;
274 }
275 break;
276
277 case CY_SYSPM_MODE_DEEPSLEEP_OFF:
278 {
279 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_MAIN_BASE, (uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
280 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SRAM0_BASE, (uint32_t)CY_SYSTEM_SRAM0_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
281 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SRAM1_BASE, (uint32_t)CY_SYSTEM_SRAM1_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
282 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SYSCPU_BASE, (uint32_t)CY_SYSTEM_SYSCPU_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
283
284 #if (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)
285 SCS_CPPWR |= SCS_CPPWR_SU10_Msk;
286 #endif
287
288 retVal = CY_SYSPM_SUCCESS;
289 }
290 break;
291
292 default:
293 retVal = CY_SYSPM_BAD_PARAM;
294 break;
295 }
296 return retVal;
297 }
298
299
Cy_SysPm_SetAppDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)300 cy_en_syspm_status_t Cy_SysPm_SetAppDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)
301 {
302 cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
303
304 switch(deepSleepMode)
305 {
306 case CY_SYSPM_MODE_DEEPSLEEP:
307 {
308 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_PD1_BASE, (uint32_t)CY_SYSTEM_PD1_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
309 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_APPCPU_BASE, (uint32_t)CY_SYSTEM_APPCPU_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
310 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_APPSS_BASE, (uint32_t)CY_SYSTEM_APPSS_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
311 retVal = CY_SYSPM_SUCCESS;
312 }
313 break;
314
315 case CY_SYSPM_MODE_DEEPSLEEP_RAM:
316 {
317 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_PD1_BASE, (uint32_t)CY_SYSTEM_PD1_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
318 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_APPCPU_BASE, (uint32_t)CY_SYSTEM_APPCPU_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
319 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_APPSS_BASE, (uint32_t)CY_SYSTEM_APPSS_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
320 retVal = CY_SYSPM_SUCCESS;
321 }
322 break;
323
324 case CY_SYSPM_MODE_DEEPSLEEP_OFF:
325 {
326 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_PD1_BASE, (uint32_t)CY_SYSTEM_PD1_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
327 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_APPCPU_BASE, (uint32_t)CY_SYSTEM_APPCPU_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
328 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_APPSS_BASE, (uint32_t)CY_SYSTEM_APPSS_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
329 retVal = CY_SYSPM_SUCCESS;
330 }
331 break;
332
333 default:
334 retVal = CY_SYSPM_BAD_PARAM;
335 break;
336 }
337 return retVal;
338 }
339
Cy_SysPm_SetDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)340 cy_en_syspm_status_t Cy_SysPm_SetDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)
341 {
342 return Cy_SysPm_SetSysDeepSleepMode(deepSleepMode);
343 }
344
Cy_SysPm_SetSOCMEMDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)345 cy_en_syspm_status_t Cy_SysPm_SetSOCMEMDeepSleepMode(cy_en_syspm_deep_sleep_mode_t deepSleepMode)
346 {
347 cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
348
349 switch(deepSleepMode)
350 {
351 case CY_SYSPM_MODE_DEEPSLEEP:
352 {
353 if(cy_pd_ppu_get_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE) == PPU_V1_MODE_ON)
354 {
355 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE, (uint32_t)CY_SYSTEM_SOCMEM_PPU_DEEPSLEEP_MODE); /* Suppress a compiler warning about unused return value */
356 }
357 retVal = CY_SYSPM_SUCCESS;
358 }
359 break;
360
361 case CY_SYSPM_MODE_DEEPSLEEP_RAM:
362 {
363 if(cy_pd_ppu_get_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE) == PPU_V1_MODE_ON)
364 {
365 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE, (uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_RAM_MODE); /* Suppress a compiler warning about unused return value */
366 }
367 retVal = CY_SYSPM_SUCCESS;
368 }
369 break;
370
371 case CY_SYSPM_MODE_DEEPSLEEP_OFF:
372 {
373 if(cy_pd_ppu_get_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE) == PPU_V1_MODE_ON)
374 {
375 (void)cy_pd_ppu_set_power_mode((struct ppu_v1_reg *)CY_PPU_SOCMEM_BASE, (uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_OFF_MODE); /* Suppress a compiler warning about unused return value */
376 }
377 retVal = CY_SYSPM_SUCCESS;
378 }
379 break;
380
381 default:
382 retVal = CY_SYSPM_BAD_PARAM;
383 break;
384 }
385 return retVal;
386 }
387
388
Cy_SysPm_GetDeepSleepMode(void)389 cy_en_syspm_deep_sleep_mode_t Cy_SysPm_GetDeepSleepMode(void)
390 {
391 uint32_t mode;
392 cy_en_syspm_deep_sleep_mode_t deepSleepMode;
393
394 mode = (uint32_t)cy_pd_ppu_get_programmed_power_mode((struct ppu_v1_reg *)CY_PPU_MAIN_BASE);
395
396 switch(mode)
397 {
398 case CY_SYSTEM_DEEPSLEEP_PPU_MODES:
399 {
400 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP;
401 }
402 break;
403
404 case CY_SYSTEM_DEEPSLEEP_RAM_PPU_MODES:
405 {
406 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP_RAM;
407 }
408 break;
409
410 case CY_SYSTEM_DEEPSLEEP_OFF_PPU_MODES:
411 {
412 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP_OFF;
413 }
414 break;
415
416 default:
417 {
418 deepSleepMode = CY_SYSPM_MODE_DEEPSLEEP_NONE;
419 }
420 break;
421 }
422
423 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_deep_sleep_mode_t enum.');
424 return ((cy_en_syspm_deep_sleep_mode_t)deepSleepMode);
425 }
426
Cy_SysPm_GetBootMode(void)427 cy_en_syspm_boot_mode_t Cy_SysPm_GetBootMode(void)
428 {
429 uint32_t resCause, resCause2;
430 cy_en_syspm_boot_mode_t deepSleepWakeMode = CY_SYSPM_POR_BOOT_MODE;
431
432 resCause = SRSS_RES_CAUSE;
433 resCause2 = SRSS_RES_CAUSE2;
434
435 if((resCause == 0UL) || (resCause2 == 0UL))
436 {
437 switch(Cy_SysPm_GetDeepSleepMode())
438 {
439 case CY_SYSPM_MODE_DEEPSLEEP_RAM:
440 {
441 deepSleepWakeMode = CY_SYSPM_WARM_BOOT_MODE;
442 }
443 break;
444
445 case CY_SYSPM_MODE_DEEPSLEEP_OFF:
446 {
447 deepSleepWakeMode = CY_SYSPM_COLD_BOOT_MODE;
448 }
449 break;
450
451 default:
452 {
453 deepSleepWakeMode = CY_SYSPM_POR_BOOT_MODE;
454 }
455 break;
456 }
457
458 }
459
460 return ((cy_en_syspm_boot_mode_t)deepSleepWakeMode);
461 }
462
Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor)463 cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor)
464 {
465 uint32_t interruptState;
466 uint32_t cbDeepSleepRootIdx = (uint32_t) Cy_SysPm_GetDeepSleepMode();
467 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
468
469 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor));
470 CY_ASSERT_L3(CY_SYSPM_IS_DEEPSLEEP_MODE_VALID(cbDeepSleepRootIdx));
471
472 //Check if LPM is ready
473 if(!Cy_SysPm_IsLpmReady())
474 {
475 retVal = CY_SYSPM_FAIL;
476 }
477 else
478 {
479 /* Call the registered callback functions with the CY_SYSPM_CHECK_READY
480 * parameter
481 */
482 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
483 {
484 retVal = Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_CHECK_READY);
485 }
486
487 /* The CPU can switch into the Deep Sleep power mode only when
488 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
489 * parameter return CY_SYSPM_SUCCESS
490 */
491 if (retVal == CY_SYSPM_SUCCESS)
492 {
493 /* Call the registered callback functions with the
494 * CY_SYSPM_BEFORE_TRANSITION parameter
495 */
496 interruptState = Cy_SysLib_EnterCriticalSection();
497 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
498 {
499 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_BEFORE_TRANSITION);
500 }
501
502 Cy_Syspm_SetRAMTrimsPreDS();
503
504 /* The CPU enters Deep Sleep mode upon execution of WFI/WFE
505 * use Cy_SysPm_SetDeepSleepMode to set various deepsleep modes */
506 SCB_SCR |= SCB_SCR_SLEEPDEEP_Msk;
507
508 if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
509 {
510 __WFI();
511 }
512 else
513 {
514 __WFE();
515 }
516
517 Cy_Syspm_SetRAMTrimsPostDS();
518
519 Cy_SysLib_ExitCriticalSection(interruptState);
520 }
521 if (retVal == CY_SYSPM_SUCCESS)
522 {
523 /* Call the registered callback functions with the CY_SYSPM_AFTER_TRANSITION
524 * parameter
525 */
526 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
527 {
528 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_AFTER_TRANSITION);
529 }
530 }
531 else
532 {
533 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
534 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
535 * parameter
536 */
537 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
538 {
539 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_CHECK_FAIL);
540 }
541 }
542 }
543 return retVal;
544 }
545
Cy_SysPm_SystemEnterHibernate(void)546 cy_en_syspm_status_t Cy_SysPm_SystemEnterHibernate(void)
547 {
548 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
549 uint32_t cbHibernateRootIdx = (uint32_t) CY_SYSPM_HIBERNATE;
550 /* Call the registered callback functions with the
551 * CY_SYSPM_CHECK_READY parameter
552 */
553 if (pmCallbackRoot[cbHibernateRootIdx] != NULL)
554 {
555 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_READY);
556 }
557
558 /* The system can switch into Hibernate power mode only when
559 * all executed registered callback functions with CY_SYSPM_CHECK_READY
560 * parameter return CY_SYSPM_SUCCESS.
561 */
562 if(retVal == CY_SYSPM_SUCCESS)
563 {
564 /* Call registered callback functions with CY_SYSPM_BEFORE_TRANSITION
565 * parameter
566 */
567 (void) Cy_SysLib_EnterCriticalSection();
568 if (pmCallbackRoot[cbHibernateRootIdx] != NULL)
569 {
570 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_BEFORE_TRANSITION);
571 }
572
573 /* Preserve the token that will be retained through a wakeup sequence.
574 * This could be used by Cy_SysLib_GetResetReason() to differentiate
575 * Wakeup from a general reset event.
576 * Preserve the wakeup source(s) configuration.
577 */
578 SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE | HIBERNATE_TOKEN);
579
580 /* Clear Previous Wakeup Reasons */
581 Cy_SysPm_ClearHibernateWakeupCause();
582
583 /* Disable overriding by the peripherals the next pin-freeze command */
584 SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
585
586 /* The second write causes freezing of I/O cells to save the I/O-cell state */
587 SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
588
589 /* Third write cause system to enter Hibernate */
590 SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
591
592 /* Read register to make sure it is settled */
593 (void) SRSS_PWR_HIBERNATE;
594
595 /* Wait for transition */
596 __WFI();
597
598 /* The callback function calls with the CY_SYSPM_AFTER_TRANSITION
599 * parameter in the Hibernate power mode are not applicable as system
600 * wake-up was made on system reboot.
601 */
602
603 /* A wakeup from Hibernate is performed by toggling of the wakeup
604 * pins, or WDT matches, or Backup domain alarm expires. This depends on
605 * what item is configured in the Hibernate register. After a wakeup
606 * event, a normal Boot procedure occurs.
607 * There is no need to exit from the critical section.
608 */
609 }
610 else
611 {
612 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
613 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
614 * parameter. The return value should be CY_SYSPM_SUCCESS.
615 */
616 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_FAIL);
617 retVal = CY_SYSPM_FAIL;
618 }
619 return retVal;
620 }
621
Cy_SysPm_SystemSetMinRegulatorCurrent(void)622 cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void)
623 {
624 cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED;
625
626 /* Check if the power circuits are ready to enter into regulator minimum
627 * current mode
628 */
629 if (Cy_SysPm_IsLpmReady())
630 {
631 SRSS_PWR_CTL2 |= (SRSS_PWR_CTL2_BGREF_LPMODE_Msk |
632 SRSS_PWR_CTL2_PORBOD_LPMODE_Msk);
633
634 /* This wait time allows the circuits to remove their dependence on
635 * the Active mode circuits, such as active Reference
636 */
637 Cy_SysLib_DelayUs(SET_MIN_CURRENT_MODE_DELAY_US);
638
639 /* Disable active reference */
640 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_REFSYS_VBUF_DIS_Msk;
641
642 retVal = CY_SYSPM_SUCCESS;
643 }
644
645 return retVal;
646
647
648 }
649
Cy_SysPm_SystemSetNormalRegulatorCurrent(void)650 cy_en_syspm_status_t Cy_SysPm_SystemSetNormalRegulatorCurrent(void)
651 {
652 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
653
654 uint32_t timeOut = WAIT_DELAY_TRIES;
655
656 /* Configure the regulator normal current mode for the POR/BOD circuits
657 * and for the Voltage References
658 */
659
660 /* Bring Regulators Power Circuit out of LPMODE */
661 SRSS_PWR_CTL2 &= (uint32_t)~(SRSS_PWR_CTL2_REFSYS_VBUF_DIS_Msk |
662 SRSS_PWR_CTL2_PORBOD_LPMODE_Msk);
663
664 /* This wait time allows setting active Reference */
665 Cy_SysLib_DelayUs(ACT_REF_SETTLE_DELAY_US);
666
667 while ((0U == _FLD2VAL(SRSS_PWR_CTL2_REFSYS_VREF_OK, SRSS_PWR_CTL2)) && (0U != timeOut))
668 {
669 timeOut--;
670 }
671
672 if (0U != timeOut)
673 {
674 /* Disable the low-power for Bandgap reference circuit */
675 SRSS_PWR_CTL2 &= (uint32_t) ~SRSS_PWR_CTL2_BGREF_LPMODE_Msk;
676
677 /* Delay to finally set the normal current mode */
678 Cy_SysLib_DelayUs(SET_NORMAL_CURRENT_MODE_DELAY_US);
679
680 retVal= CY_SYSPM_SUCCESS;
681 }
682
683 return retVal;
684
685 }
686
687
Cy_SysPm_SystemIsMinRegulatorCurrentSet(void)688 bool Cy_SysPm_SystemIsMinRegulatorCurrentSet(void)
689 {
690 return ((0U != _FLD2VAL(SRSS_PWR_CTL2_REFSYS_VBUF_DIS, SRSS_PWR_CTL2)) ? false : true);
691 }
692
693
Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode)694 cy_en_syspm_status_t Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode)
695 {
696 CY_ASSERT_L3(CY_SYSPM_IS_LDO_MODE_VALID(mode));
697
698 cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED;
699
700 switch (mode)
701 {
702 case CY_SYSPM_LDO_MODE_NORMAL:
703 {
704 retVal = Cy_SysPm_SystemSetNormalRegulatorCurrent();
705 }
706 break;
707
708 case CY_SYSPM_LDO_MODE_MIN:
709 {
710 retVal = Cy_SysPm_SystemSetMinRegulatorCurrent();
711 }
712 break;
713
714 default:
715 retVal = CY_SYSPM_FAIL;
716 break;
717 }
718
719 return retVal;
720 }
721
Cy_SysPm_LdoGetMode(void)722 cy_en_syspm_ldo_mode_t Cy_SysPm_LdoGetMode(void)
723 {
724 cy_en_syspm_ldo_mode_t retVal;
725
726 if (Cy_SysPm_SystemIsMinRegulatorCurrentSet())
727 {
728 retVal = CY_SYSPM_LDO_MODE_MIN;
729 }
730 else
731 {
732 retVal = CY_SYSPM_LDO_MODE_NORMAL;
733 }
734
735 return retVal;
736 }
737
Cy_SysPm_CpuSleepOnExit(bool enable)738 void Cy_SysPm_CpuSleepOnExit(bool enable)
739 {
740 if(enable)
741 {
742 /* Enable sleep-on-exit feature */
743 SCB_SCR |= SCB_SCR_SLEEPONEXIT_Msk;
744 }
745 else
746 {
747 /* Disable sleep-on-exit feature */
748 SCB_SCR &= (uint32_t) ~(SCB_SCR_SLEEPONEXIT_Msk);
749 }
750 }
751
Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource)752 void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource)
753 {
754 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource));
755
756 uint32_t polarityMask = 0U;
757 uint32_t wakeSrcMask = 0U;
758
759 /* LPCOMP0 & LPCOMP1 */
760 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_HIGH)))
761 {
762 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK;
763 }
764
765 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_HIGH)))
766 {
767 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK;
768 }
769
770 /* PIN0 & PIN1 */
771 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_HIGH)))
772 {
773 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_PIN0_MASK;
774 }
775
776 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_HIGH)))
777 {
778 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_PIN1_MASK;
779 }
780
781 /* RTC */
782 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_RTC_ALARM))
783 {
784 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_RTC_MASK;
785 }
786
787 /* WDT */
788 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_WDT))
789 {
790 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_WDT_MASK;
791 }
792
793 /* Polarity Mask */
794 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_HIGH))
795 {
796 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK;
797 }
798
799 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_HIGH))
800 {
801 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK;
802 }
803
804 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_HIGH))
805 {
806 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK;
807 }
808
809 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_HIGH))
810 {
811 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK;
812 }
813
814 SRSS_PWR_HIB_WAKE_CTL = (SRSS_PWR_HIB_WAKE_CTL | wakeSrcMask);
815 SRSS_PWR_HIB_WAKE_CTL2 = (SRSS_PWR_HIB_WAKE_CTL2 | polarityMask);
816
817 /* Read registers to make sure it is settled */
818 (void) SRSS_PWR_HIB_WAKE_CTL;
819 (void) SRSS_PWR_HIB_WAKE_CTL2;
820
821 }
822
Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource)823 void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource)
824 {
825 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource));
826
827 uint32_t polarityMask = 0U;
828 uint32_t wakeSrcMask = 0U;
829
830 /* LPCOMP0 & LPCOMP1 */
831 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_HIGH)))
832 {
833 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK;
834 }
835
836 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_HIGH)))
837 {
838 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK;
839 }
840
841 /* PIN0 & PIN1 */
842 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_HIGH)))
843 {
844 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_PIN0_MASK;
845 }
846
847 if ((0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW)) || (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_HIGH)))
848 {
849 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_PIN1_MASK;
850 }
851
852 /* RTC */
853 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_RTC_ALARM))
854 {
855 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_RTC_MASK;
856 }
857
858 /* WDT */
859 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_WDT))
860 {
861 wakeSrcMask |= CY_SYSPM_HIB_WAKEUP_WDT_MASK;
862 }
863
864 /* Polarity Mask */
865 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_HIGH))
866 {
867 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK;
868 }
869
870 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_HIGH))
871 {
872 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK;
873 }
874
875 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN0_HIGH))
876 {
877 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK;
878 }
879
880 if (0U != (wakeupSource & (uint32_t)CY_SYSPM_HIBERNATE_PIN1_HIGH))
881 {
882 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK;
883 }
884
885 SRSS_PWR_HIB_WAKE_CTL = (SRSS_PWR_HIB_WAKE_CTL & (~wakeSrcMask));
886 SRSS_PWR_HIB_WAKE_CTL2 = (SRSS_PWR_HIB_WAKE_CTL2 & (~polarityMask));
887
888 /* Read registers to make sure it is settled */
889 (void) SRSS_PWR_HIB_WAKE_CTL;
890 (void) SRSS_PWR_HIB_WAKE_CTL2;
891 }
892
Cy_SysPm_GetHibernateWakeupCause(void)893 cy_en_syspm_hibernate_wakeup_source_t Cy_SysPm_GetHibernateWakeupCause(void)
894 {
895 uint32_t wakeupCause;
896 uint32_t wakeupCausePolarity;
897
898 wakeupCause = SRSS_PWR_HIB_WAKE_CAUSE;
899
900 wakeupCausePolarity = (wakeupCause & (uint32_t)(CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK |
901 CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK |
902 CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK |
903 CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK ));
904
905 switch(wakeupCause)
906 {
907 case CY_SYSPM_HIB_WAKEUP_PIN0_POS:
908 {
909 if (0U != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK))
910 {
911 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_PIN0_HIGH);
912 }
913 else
914 {
915 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_PIN0_LOW);
916 }
917 }
918 break;
919
920 case CY_SYSPM_HIB_WAKEUP_PIN1_POS:
921 {
922 if (0U != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK))
923 {
924 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_PIN1_HIGH);
925 }
926 else
927 {
928 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_PIN1_LOW);
929 }
930 }
931 break;
932
933 case CY_SYSPM_HIB_WAKEUP_LPCOMP0_POS:
934 {
935 if (0U != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK))
936 {
937 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_HIGH);
938 }
939 else
940 {
941 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_LPCOMP0_LOW);
942 }
943 }
944 break;
945
946 case CY_SYSPM_HIB_WAKEUP_LPCOMP1_POS:
947 {
948 if (0U != (wakeupCausePolarity & (uint32_t)CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK))
949 {
950 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_HIGH);
951 }
952 else
953 {
954 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_LPCOMP1_LOW);
955 }
956 }
957 break;
958
959 case CY_SYSPM_HIB_WAKEUP_RTC_MASK:
960 {
961 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_RTC_ALARM);
962 }
963 break;
964
965 case CY_SYSPM_HIB_WAKEUP_WDT_MASK:
966 {
967 wakeupCause = ((uint32_t)CY_SYSPM_HIBERNATE_WDT);
968 }
969 break;
970
971 default:
972 CY_ASSERT_L2(false);
973 break;
974 }
975
976 return (cy_en_syspm_hibernate_wakeup_source_t)wakeupCause;
977 }
978
Cy_SysPm_ClearHibernateWakeupCause(void)979 void Cy_SysPm_ClearHibernateWakeupCause(void)
980 {
981 uint32_t temp = SRSS_PWR_HIB_WAKE_CAUSE;
982 SRSS_PWR_HIB_WAKE_CAUSE = temp;
983 }
984
Cy_SysPm_CoreBuckSetVoltage(cy_en_syspm_core_buck_voltage_t voltage)985 cy_en_syspm_status_t Cy_SysPm_CoreBuckSetVoltage(cy_en_syspm_core_buck_voltage_t voltage)
986 {
987 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(voltage));
988
989 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL, SRSS_PWR_CBUCK_CTL_CBUCK_VSEL, voltage);
990
991 return Cy_SysPm_CoreBuckStatus();
992 }
993
Cy_SysPm_CoreBuckGetVoltage(void)994 cy_en_syspm_core_buck_voltage_t Cy_SysPm_CoreBuckGetVoltage(void)
995 {
996 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_core_buck_voltage_t enum.');
997 return (cy_en_syspm_core_buck_voltage_t)(_FLD2VAL(SRSS_PWR_CBUCK_CTL_CBUCK_VSEL, SRSS_PWR_CBUCK_CTL));
998 }
999
Cy_SysPm_CoreBuckSetMode(cy_en_syspm_core_buck_mode_t mode)1000 void Cy_SysPm_CoreBuckSetMode(cy_en_syspm_core_buck_mode_t mode)
1001 {
1002 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_MODE_VALID(mode));
1003
1004 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL, SRSS_PWR_CBUCK_CTL_CBUCK_MODE, mode);
1005 }
1006
Cy_SysPm_CoreBuckGetMode(void)1007 cy_en_syspm_core_buck_mode_t Cy_SysPm_CoreBuckGetMode(void)
1008 {
1009 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_core_buck_mode_t enum.');
1010 return (cy_en_syspm_core_buck_mode_t)(_FLD2VAL(SRSS_PWR_CBUCK_CTL_CBUCK_MODE, SRSS_PWR_CBUCK_CTL));
1011 }
1012
Cy_SysPm_CoreBuckDpslpSetVoltage(cy_en_syspm_core_buck_voltage_t voltage)1013 cy_en_syspm_status_t Cy_SysPm_CoreBuckDpslpSetVoltage(cy_en_syspm_core_buck_voltage_t voltage)
1014 {
1015 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(voltage));
1016
1017 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_DPSLP_CTL, SRSS_PWR_CBUCK_DPSLP_CTL_CBUCK_DPSLP_VSEL, voltage);
1018
1019 return Cy_SysPm_CoreBuckStatus();
1020 }
1021
Cy_SysPm_CoreBuckDpslpGetVoltage(void)1022 cy_en_syspm_core_buck_voltage_t Cy_SysPm_CoreBuckDpslpGetVoltage(void)
1023 {
1024 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_core_buck_voltage_t enum.');
1025 return (cy_en_syspm_core_buck_voltage_t)(_FLD2VAL(SRSS_PWR_CBUCK_DPSLP_CTL_CBUCK_DPSLP_VSEL, SRSS_PWR_CBUCK_DPSLP_CTL));
1026 }
1027
Cy_SysPm_CoreBuckDpslpSetMode(cy_en_syspm_core_buck_mode_t mode)1028 void Cy_SysPm_CoreBuckDpslpSetMode(cy_en_syspm_core_buck_mode_t mode)
1029 {
1030 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_MODE_VALID(mode));
1031
1032 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_DPSLP_CTL, SRSS_PWR_CBUCK_DPSLP_CTL_CBUCK_DPSLP_MODE, mode);
1033 }
1034
Cy_SysPm_CoreBuckDpslpGetMode(void)1035 cy_en_syspm_core_buck_mode_t Cy_SysPm_CoreBuckDpslpGetMode(void)
1036 {
1037 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_core_buck_mode_t enum.');
1038 return (cy_en_syspm_core_buck_mode_t)(_FLD2VAL(SRSS_PWR_CBUCK_DPSLP_CTL_CBUCK_DPSLP_MODE, SRSS_PWR_CBUCK_DPSLP_CTL));
1039 }
1040
Cy_SysPm_CoreBuckDpslpEnableOverride(bool enable)1041 void Cy_SysPm_CoreBuckDpslpEnableOverride(bool enable)
1042 {
1043 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_DPSLP_CTL, SRSS_PWR_CBUCK_DPSLP_CTL_CBUCK_DPSLP_OVERRIDE, ((enable) ? 1UL : 0UL));
1044 }
1045
Cy_SysPm_CoreBuckDpslpIsOverrideEnabled(void)1046 bool Cy_SysPm_CoreBuckDpslpIsOverrideEnabled(void)
1047 {
1048 return (_FLD2BOOL(SRSS_PWR_CBUCK_DPSLP_CTL_CBUCK_DPSLP_OVERRIDE, SRSS_PWR_CBUCK_DPSLP_CTL)? true : false);
1049 }
1050
1051
Cy_SysPm_CoreBuckSetProfile(cy_en_syspm_core_buck_profile_t profile)1052 void Cy_SysPm_CoreBuckSetProfile(cy_en_syspm_core_buck_profile_t profile)
1053 {
1054 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_PROFILE_VALID(profile));
1055
1056 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL2, SRSS_PWR_CBUCK_CTL2_CBUCK_PROFILE, profile);
1057 }
1058
Cy_SysPm_CoreBuckGetProfile(void)1059 cy_en_syspm_core_buck_profile_t Cy_SysPm_CoreBuckGetProfile(void)
1060 {
1061 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_core_buck_profile_t enum.');
1062 return (cy_en_syspm_core_buck_profile_t)(_FLD2VAL(SRSS_PWR_CBUCK_CTL2_CBUCK_PROFILE, SRSS_PWR_CBUCK_CTL2));
1063 }
1064
Cy_SysPm_CoreBuckStatus(void)1065 cy_en_syspm_status_t Cy_SysPm_CoreBuckStatus(void)
1066 {
1067 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
1068 uint32_t syspmCbuckRetry = CY_SYSPM_CBUCK_BUSY_RETRY_COUNT;
1069
1070 while((_FLD2VAL(SRSS_PWR_CBUCK_STATUS_PMU_DONE, SRSS_PWR_CBUCK_STATUS) == 0U) && (syspmCbuckRetry != 0U))
1071 {
1072 syspmCbuckRetry--;
1073 Cy_SysLib_Delay(CY_SYSPM_CBUCK_BUSY_RETRY_DELAY_MS);
1074 }
1075
1076 if(syspmCbuckRetry != 0UL)
1077 {
1078 retVal = CY_SYSPM_SUCCESS;
1079 }
1080
1081 return retVal;
1082 }
1083
Cy_SysPm_RetLdoStatus(void)1084 cy_en_syspm_status_t Cy_SysPm_RetLdoStatus(void)
1085 {
1086 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
1087 uint32_t syspmCbuckRetry = CY_SYSPM_CBUCK_BUSY_RETRY_COUNT;
1088
1089 while((_FLD2VAL(SRSS_PWR_CBUCK_STATUS_RETLDO_DONE, SRSS_PWR_CBUCK_STATUS) == 0U) && (syspmCbuckRetry != 0U))
1090 {
1091 syspmCbuckRetry--;
1092 Cy_SysLib_Delay(CY_SYSPM_CBUCK_BUSY_RETRY_DELAY_MS);
1093 }
1094
1095 if(syspmCbuckRetry != 0UL)
1096 {
1097 retVal = CY_SYSPM_SUCCESS;
1098 }
1099
1100 return retVal;
1101 }
1102
Cy_SysPm_RetLdoConfigure(cy_stc_syspm_retldo_params_t * retLdoParam)1103 cy_en_syspm_status_t Cy_SysPm_RetLdoConfigure(cy_stc_syspm_retldo_params_t *retLdoParam)
1104 {
1105 CY_ASSERT_L2(CY_SYSPM_IS_RETLDO_VOLTAGE_VALID(retLdoParam->activeVoltSel));
1106 CY_ASSERT_L2(CY_SYSPM_IS_RETLDO_VOLTAGE_VALID(retLdoParam->deepsleepVoltSel));
1107 CY_ASSERT_L2(CY_SYSPM_IS_RETLDO_GAIN_VALID(retLdoParam->activeGain));
1108 CY_ASSERT_L2(CY_SYSPM_IS_RETLDO_GAIN_VALID(retLdoParam->deepsleepGain));
1109
1110 CY_REG32_CLR_SET(SRSS_PWR_RETLDO_CTL, SRSS_PWR_RETLDO_CTL_RETLDO_LVL, retLdoParam->activeVoltSel);
1111 CY_REG32_CLR_SET(SRSS_PWR_RETLDO_CTL, SRSS_PWR_RETLDO_CTL_RETLDO_GAIN, retLdoParam->activeGain);
1112
1113 CY_REG32_CLR_SET(SRSS_PWR_RETLDO_CTL, SRSS_PWR_RETLDO_CTL_RETLDO_LVL_DPSLP, retLdoParam->deepsleepVoltSel);
1114 CY_REG32_CLR_SET(SRSS_PWR_RETLDO_CTL, SRSS_PWR_RETLDO_CTL_RETLDO_GAIN_DPSLP, retLdoParam->deepsleepGain);
1115
1116 return Cy_SysPm_RetLdoStatus();
1117 }
1118
Cy_SysPm_SramLdoStatus(void)1119 cy_en_syspm_status_t Cy_SysPm_SramLdoStatus(void)
1120 {
1121 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
1122 uint32_t syspmCbuckRetry = CY_SYSPM_CBUCK_BUSY_RETRY_COUNT;
1123
1124 while((_FLD2VAL(SRSS_PWR_CBUCK_STATUS_SRAMLDO_DONE, SRSS_PWR_CBUCK_STATUS) == 0U) && (syspmCbuckRetry != 0U))
1125 {
1126 syspmCbuckRetry--;
1127 Cy_SysLib_Delay(CY_SYSPM_CBUCK_BUSY_RETRY_DELAY_MS);
1128 }
1129
1130 if(syspmCbuckRetry != 0UL)
1131 {
1132 retVal = CY_SYSPM_SUCCESS;
1133 }
1134
1135 return retVal;
1136 }
1137
Cy_SysPm_SramLdoEnable(bool enable)1138 void Cy_SysPm_SramLdoEnable(bool enable)
1139 {
1140 CY_REG32_CLR_SET(SRSS_PWR_SRAMLDO_CTL, SRSS_PWR_SRAMLDO_CTL_SRAMLDO_EN, (enable ? 1U : 0U));
1141 }
1142
Cy_SysPm_SramLdoSetVoltage(cy_en_syspm_sramldo_voltage_t voltage)1143 cy_en_syspm_status_t Cy_SysPm_SramLdoSetVoltage(cy_en_syspm_sramldo_voltage_t voltage)
1144 {
1145 CY_ASSERT_L2(CY_SYSPM_IS_SRAMLDO_VOLTAGE_VALID(voltage));
1146
1147 CY_REG32_CLR_SET(SRSS_PWR_SRAMLDO_CTL, SRSS_PWR_SRAMLDO_CTL_SRAMLDO_VOUT, voltage);
1148
1149 return Cy_SysPm_SramLdoStatus();
1150 }
1151
Cy_SysPm_SramLdoGetVoltage(void)1152 cy_en_syspm_sramldo_voltage_t Cy_SysPm_SramLdoGetVoltage(void)
1153 {
1154 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_sramldo_voltage_t enum.');
1155 return (cy_en_syspm_sramldo_voltage_t)(_FLD2VAL(SRSS_PWR_SRAMLDO_CTL_SRAMLDO_VOUT, SRSS_PWR_SRAMLDO_CTL));
1156 }
1157
Cy_SysPm_SramLdoConfigure(cy_stc_syspm_sramldo_params_t * sramLdoParam)1158 cy_en_syspm_status_t Cy_SysPm_SramLdoConfigure(cy_stc_syspm_sramldo_params_t *sramLdoParam)
1159 {
1160 CY_ASSERT_L2(CY_SYSPM_IS_SRAMLDO_VOLTAGE_VALID(sramLdoParam->sramLdoVoltSel));
1161
1162 CY_REG32_CLR_SET(SRSS_PWR_SRAMLDO_CTL, SRSS_PWR_SRAMLDO_CTL_SRAMLDO_EN, (sramLdoParam->sramLdoEnable ? 1U : 0U));
1163
1164 CY_REG32_CLR_SET(SRSS_PWR_SRAMLDO_CTL, SRSS_PWR_SRAMLDO_CTL_SRAMLDO_DPSLP_EN, (sramLdoParam->deepsleepSramLdoEnable ? 1U : 0U));
1165
1166 CY_REG32_CLR_SET(SRSS_PWR_SRAMLDO_CTL, SRSS_PWR_SRAMLDO_CTL_SRAMLDO_VOUT, sramLdoParam->sramLdoVoltSel);
1167
1168 return Cy_SysPm_SramLdoStatus();
1169 }
1170
Cy_SysPm_MiscLdoStatus(void)1171 cy_en_syspm_status_t Cy_SysPm_MiscLdoStatus(void)
1172 {
1173 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
1174 uint32_t syspmCbuckRetry = CY_SYSPM_CBUCK_BUSY_RETRY_COUNT;
1175
1176 while((_FLD2VAL(SRSS_PWR_CBUCK_STATUS_MISCLDO_DONE, SRSS_PWR_CBUCK_STATUS) == 0U) && (syspmCbuckRetry != 0U))
1177 {
1178 syspmCbuckRetry--;
1179 Cy_SysLib_Delay(CY_SYSPM_CBUCK_BUSY_RETRY_DELAY_MS);
1180 }
1181
1182 if(syspmCbuckRetry != 0UL)
1183 {
1184 retVal = CY_SYSPM_SUCCESS;
1185 }
1186
1187 return retVal;
1188 }
1189
Cy_SysPm_MiscLdoConfigure(cy_stc_syspm_miscldo_params_t * miscLdoParam)1190 cy_en_syspm_status_t Cy_SysPm_MiscLdoConfigure(cy_stc_syspm_miscldo_params_t *miscLdoParam)
1191 {
1192 CY_ASSERT_L2(CY_SYSPM_IS_MISCLDO_VOLTAGE_VALID(miscLdoParam->miscLdoVoltSel));
1193 CY_ASSERT_L2(CY_SYSPM_IS_MISCLDO_VCCACT_TRIM_VALID(miscLdoParam->miscLdoVaccActTrimSel));
1194 CY_ASSERT_L2(CY_SYSPM_IS_MISCLDO_MODE_VALID(miscLdoParam->miscLdoMode));
1195
1196 CY_REG32_CLR_SET(SRSS_PWR_MISCLDO_CTL, SRSS_PWR_MISCLDO_CTL_MISCLDO_EN, (miscLdoParam->miscLdoEnable ? 1U : 0U));
1197
1198 CY_REG32_CLR_SET(SRSS_PWR_MISCLDO_CTL, SRSS_PWR_MISCLDO_CTL_MISCLDO_MODE, miscLdoParam->miscLdoMode);
1199
1200 CY_REG32_CLR_SET(SRSS_PWR_MISCLDO_CTL, SRSS_PWR_MISCLDO_CTL_MISCLDO_VOUT, miscLdoParam->miscLdoVoltSel);
1201
1202 CY_REG32_CLR_SET(SRSS_PWR_MISCLDO_CTL, SRSS_PWR_MISCLDO_CTL_MISCLDO_VCCACT_TRIM, miscLdoParam->miscLdoVaccActTrimSel);
1203
1204 return Cy_SysPm_MiscLdoStatus();
1205 }
1206
Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t * handler)1207 bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t* handler)
1208 {
1209 bool retVal = false;
1210
1211 /* Verify the input parameters. */
1212 if ((handler != NULL) && (handler->callbackParams != NULL) && (handler->callback != NULL))
1213 {
1214 uint32_t callbackRootIdx = (uint32_t) handler->type;
1215
1216 /* If the callback list is not empty. */
1217 if (pmCallbackRoot[callbackRootIdx] != NULL)
1218 {
1219 cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx];
1220 cy_stc_syspm_callback_t* insertPos = curCallback;
1221
1222 /* Find the callback after which the new callback is to be
1223 * inserted. Ensure the given callback has not been registered.
1224 */
1225 while ((NULL != curCallback->nextItm) && (curCallback != handler))
1226 {
1227 curCallback = curCallback->nextItm;
1228 /* Callbacks with the same order value are stored in the order
1229 * they are registered.
1230 */
1231 if (curCallback->order <= handler->order)
1232 {
1233 insertPos = curCallback;
1234 }
1235 }
1236 /* If the callback has not been registered. */
1237 if (curCallback != handler)
1238 {
1239 /* If the callback is to be inserted at the beginning of the list. */
1240 if ((insertPos->prevItm == NULL) && (handler->order < insertPos->order))
1241 {
1242 handler->nextItm = insertPos;
1243 handler->prevItm = NULL;
1244 handler->nextItm->prevItm = handler;
1245 pmCallbackRoot[callbackRootIdx] = handler;
1246 }
1247 else
1248 {
1249 handler->nextItm = insertPos->nextItm;
1250 handler->prevItm = insertPos;
1251
1252 /* If the callback is not inserted at the end of the list. */
1253 if (handler->nextItm != NULL)
1254 {
1255 handler->nextItm->prevItm = handler;
1256 }
1257 insertPos->nextItm = handler;
1258 }
1259 retVal = true;
1260 }
1261 }
1262 else
1263 {
1264 /* The callback list is empty. */
1265 pmCallbackRoot[callbackRootIdx] = handler;
1266 handler->nextItm = NULL;
1267 handler->prevItm = NULL;
1268 retVal = true;
1269 }
1270 }
1271 return retVal;
1272 }
1273
Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const * handler)1274 bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler)
1275 {
1276 bool retVal = false;
1277
1278 if (handler != NULL)
1279 {
1280 uint32_t callbackRootIdx = (uint32_t) handler->type;
1281 cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx];
1282
1283 /* Search requested callback item in the linked list */
1284 while (curCallback != NULL)
1285 {
1286 /* Requested callback is found */
1287 if (curCallback == handler)
1288 {
1289 retVal = true;
1290 break;
1291 }
1292
1293 /* Go to next callback item in the linked list */
1294 curCallback = curCallback->nextItm;
1295 }
1296
1297 if (retVal)
1298 {
1299 /* Requested callback is first in the list */
1300 if (pmCallbackRoot[callbackRootIdx] == handler)
1301 {
1302 /* Check whether this the only callback registered */
1303 if (pmCallbackRoot[callbackRootIdx]->nextItm != NULL)
1304 {
1305 pmCallbackRoot[callbackRootIdx] = pmCallbackRoot[callbackRootIdx]->nextItm;
1306 pmCallbackRoot[callbackRootIdx]->prevItm = NULL;
1307 }
1308 else
1309 {
1310 /* We had only one callback */
1311 pmCallbackRoot[callbackRootIdx] = NULL;
1312 }
1313 }
1314 else
1315 {
1316 /* Update links of related to unregistered callback items */
1317 curCallback->prevItm->nextItm = curCallback->nextItm;
1318
1319 if (curCallback->nextItm != NULL)
1320 {
1321 curCallback->nextItm->prevItm = curCallback->prevItm;
1322 }
1323 }
1324 }
1325 }
1326
1327 return retVal;
1328 }
1329
Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type,cy_en_syspm_callback_mode_t mode)1330 cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, cy_en_syspm_callback_mode_t mode)
1331 {
1332 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_TYPE_VALID(type));
1333 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_MODE_VALID(mode));
1334
1335 static cy_stc_syspm_callback_t* lastExecutedCallback = NULL;
1336 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
1337 cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[(uint32_t) type];
1338 cy_stc_syspm_callback_params_t curParams;
1339
1340 if ((mode == CY_SYSPM_BEFORE_TRANSITION) || (mode == CY_SYSPM_CHECK_READY))
1341 {
1342 /* Execute registered callbacks with order from first registered to the
1343 * last registered. Stop executing if CY_SYSPM_FAIL was returned in
1344 * CY_SYSPM_CHECK_READY mode
1345 */
1346 while ((curCallback != NULL) && ((retVal != CY_SYSPM_FAIL) || (mode != CY_SYSPM_CHECK_READY)))
1347 {
1348 /* The modes defined in the .skipMode element are not executed */
1349 if (0UL == ((uint32_t) mode & curCallback->skipMode))
1350 {
1351 /* Update elements for local callback parameter values */
1352 curParams.base = curCallback->callbackParams->base;
1353 curParams.context = curCallback->callbackParams->context;
1354
1355 retVal = curCallback->callback(&curParams, mode);
1356
1357 /* Update callback pointer with value of executed callback.
1358 * Such update is required to execute further callbacks in
1359 * backward order after exit from LP mode or to undo
1360 * configuration after callback returned fail: from last called
1361 * to first registered.
1362 */
1363 lastExecutedCallback = curCallback;
1364 }
1365 curCallback = curCallback->nextItm;
1366 }
1367
1368 if (mode == CY_SYSPM_CHECK_READY)
1369 {
1370 /* Update the pointer to the failed callback with the result of the callback execution.
1371 * If the callback fails, the value of the pointer will be updated
1372 * with the address of the callback which returned CY_SYSPM_FAIL, else,
1373 * it will be updated with NULL.
1374 */
1375 if(retVal == CY_SYSPM_FAIL)
1376 {
1377 failedCallback[(uint32_t) type] = lastExecutedCallback;
1378 }
1379 else
1380 {
1381 failedCallback[(uint32_t) type] = NULL;
1382 }
1383 }
1384 }
1385 else
1386 {
1387 /* Execute registered callbacks with order from lastCallback or last
1388 * executed to the first registered callback. Such a flow is required if
1389 * a previous callback function returned CY_SYSPM_FAIL or a previous
1390 * callback mode was CY_SYSPM_BEFORE_TRANSITION. Such an order is
1391 * required to undo configurations in correct backward order.
1392 */
1393 if (mode != CY_SYSPM_CHECK_FAIL)
1394 {
1395 while (curCallback->nextItm != NULL)
1396 {
1397 curCallback = curCallback->nextItm;
1398 }
1399 }
1400 else
1401 {
1402 /* Skip last executed callback that returns CY_SYSPM_FAIL, as this
1403 * callback already knows that it failed.
1404 */
1405 curCallback = lastExecutedCallback;
1406
1407 if (curCallback != NULL)
1408 {
1409 curCallback = curCallback->prevItm;
1410 }
1411 }
1412
1413 /* Execute callback functions with required type and mode */
1414 while (curCallback != NULL)
1415 {
1416 /* The modes defined in the .skipMode element are not executed */
1417 if (0UL == ((uint32_t) mode & curCallback->skipMode))
1418 {
1419 /* Update elements for local callback parameter values */
1420 curParams.base = curCallback->callbackParams->base;
1421 curParams.context = curCallback->callbackParams->context;
1422
1423 retVal = curCallback->callback(&curParams, mode);
1424 }
1425 curCallback = curCallback->prevItm;
1426 }
1427 }
1428
1429 return retVal;
1430 }
1431
Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t type)1432 cy_stc_syspm_callback_t* Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t type)
1433 {
1434 return failedCallback[(uint32_t) type];
1435 }
1436
Cy_SysPm_IoUnfreeze(void)1437 void Cy_SysPm_IoUnfreeze(void)
1438 {
1439 uint32_t interruptState;
1440 interruptState = Cy_SysLib_EnterCriticalSection();
1441
1442 /* Preserve the last reset reason and wakeup polarity. Then, unfreeze I/O:
1443 * write PWR_HIBERNATE.FREEZE=0, .UNLOCK=0x3A, .HIBERANTE=0
1444 */
1445 SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & HIBERNATE_RETAIN_STATUS_MASK) | HIBERNATE_UNLOCK_VAL;
1446
1447 /* Lock the Hibernate mode:
1448 * write PWR_HIBERNATE.HIBERNATE=0, UNLOCK=0x00, HIBERANTE=0
1449 */
1450 SRSS_PWR_HIBERNATE &= HIBERNATE_RETAIN_STATUS_MASK;
1451
1452 /* Read register to make sure it is settled */
1453 (void) SRSS_PWR_HIBERNATE;
1454
1455 Cy_SysLib_ExitCriticalSection(interruptState);
1456 }
1457
Cy_SysPm_IoIsFrozen(void)1458 bool Cy_SysPm_IoIsFrozen(void)
1459 {
1460 return (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_FREEZE, SRSS_PWR_HIBERNATE));
1461 }
1462
Cy_SysPm_DeepSleepIoUnfreeze(void)1463 void Cy_SysPm_DeepSleepIoUnfreeze(void)
1464 {
1465 uint32_t interruptState;
1466 interruptState = Cy_SysLib_EnterCriticalSection();
1467
1468 /* Unfreeze IO's which are frozen during DEEPSLEEP-RAM/OFF
1469 * Entry
1470 */
1471 /* For PD0 */
1472 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_FREEZE_DPSLP_Msk;
1473
1474 /* For PD1 */
1475 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_FREEZE_DPSLP_PD1_Msk;
1476
1477 Cy_SysLib_ExitCriticalSection(interruptState);
1478 }
1479
Cy_SysPm_DeepSleepIoIsFrozen(void)1480 bool Cy_SysPm_DeepSleepIoIsFrozen(void)
1481 {
1482 return ((0U != _FLD2VAL(SRSS_PWR_CTL2_FREEZE_DPSLP, SRSS_PWR_CTL2)) || (0U != _FLD2VAL(SRSS_PWR_CTL2_FREEZE_DPSLP_PD1, SRSS_PWR_CTL2)));
1483 }
1484
Cy_SysPm_CpuSendWakeupEvent(void)1485 void Cy_SysPm_CpuSendWakeupEvent(void)
1486 {
1487 __SEV();
1488 }
1489
Cy_SysPm_IsLpmReady(void)1490 bool Cy_SysPm_IsLpmReady(void)
1491 {
1492 return (_FLD2BOOL(SRSS_PWR_CTL_LPM_READY, SRSS_PWR_CTL)? true : false);
1493 }
1494
Cy_SysPm_SetSOCMemPartActivePwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum,cy_en_syspm_socmem_sram_pwr_mode_t socmemSramPwrMode)1495 cy_en_syspm_status_t Cy_SysPm_SetSOCMemPartActivePwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum, cy_en_syspm_socmem_sram_pwr_mode_t socmemSramPwrMode)
1496 {
1497 CY_ASSERT_L3((socmemSramPwrMode == CY_SYSPM_SOCMEM_SRAM_ACTIVE_MODE_ON) || (socmemSramPwrMode == CY_SYSPM_SOCMEM_SRAM_ACTIVE_MODE_OFF));
1498 CY_ASSERT_L3(socmemSramPartNum < CY_SOCMEM_PARTITION_NR);
1499
1500 /* Unlock PWR Partition Control */
1501 /* Clear bit 0(CLR0)*/
1502 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR0;
1503 /* Clear bit 1(CLR1)*/
1504 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR1;
1505
1506 switch(socmemSramPwrMode)
1507 {
1508 case CY_SYSPM_SOCMEM_SRAM_ACTIVE_MODE_ON:
1509 {
1510 CY_REG32_CLR_SET(SOCMEM_PWR_PARTITION_CTL(socmemSramPartNum), SOCMEM_PWR_PARTITION_CTL_ACT_OFF, 0UL);
1511 }
1512 break;
1513
1514 case CY_SYSPM_SOCMEM_SRAM_ACTIVE_MODE_OFF:
1515 {
1516 CY_REG32_CLR_SET(SOCMEM_PWR_PARTITION_CTL(socmemSramPartNum), SOCMEM_PWR_PARTITION_CTL_ACT_OFF, 1UL);
1517 }
1518 break;
1519
1520 default:
1521 {
1522 CY_ASSERT_L3(false);
1523 }
1524 break;
1525 }
1526
1527 /* Wait for the PWR_DONE status */
1528 while(!_FLD2BOOL(SOCMEM_PWR_STATUS_PWR_DONE, SOCMEM_PWR_STATUS)){}
1529
1530 /* Lock PWR Partition Control(Set SET01) */
1531 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_SET01;
1532
1533 return CY_SYSPM_SUCCESS;
1534 }
1535
Cy_SysPm_SetSOCMemPartDsPwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum,cy_en_syspm_socmem_sram_pwr_mode_t socmemSramPwrMode)1536 cy_en_syspm_status_t Cy_SysPm_SetSOCMemPartDsPwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum, cy_en_syspm_socmem_sram_pwr_mode_t socmemSramPwrMode)
1537 {
1538 CY_ASSERT_L3((socmemSramPwrMode == CY_SYSPM_SOCMEM_SRAM_DS_MODE_RET_ON) || (socmemSramPwrMode == CY_SYSPM_SOCMEM_SRAM_DS_MODE_RET_OFF));
1539 CY_ASSERT_L3(socmemSramPartNum < CY_SOCMEM_PARTITION_NR);
1540
1541 /* Unlock PWR Partition Control */
1542 /* Clear bit 0(CLR0)*/
1543 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR0;
1544 /* Clear bit 1(CLR1)*/
1545 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR1;
1546
1547 switch(socmemSramPwrMode)
1548 {
1549 case CY_SYSPM_SOCMEM_SRAM_DS_MODE_RET_ON:
1550 {
1551 CY_REG32_CLR_SET(SOCMEM_PWR_PARTITION_CTL(socmemSramPartNum), SOCMEM_PWR_PARTITION_CTL_RET_OFF, 0UL);
1552 }
1553 break;
1554
1555 case CY_SYSPM_SOCMEM_SRAM_DS_MODE_RET_OFF:
1556 {
1557 CY_REG32_CLR_SET(SOCMEM_PWR_PARTITION_CTL(socmemSramPartNum), SOCMEM_PWR_PARTITION_CTL_RET_OFF, 1UL);
1558 }
1559 break;
1560
1561 default:
1562 {
1563 CY_ASSERT_L3(false);
1564 }
1565 break;
1566 }
1567
1568 /* Lock PWR Partition Control(Set SET01) */
1569 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_SET01;
1570
1571 return CY_SYSPM_SUCCESS;
1572 }
1573
1574
Cy_SysPm_GetSOCMemSramPartActivePwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum)1575 cy_en_syspm_socmem_sram_pwr_mode_t Cy_SysPm_GetSOCMemSramPartActivePwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum)
1576 {
1577 cy_en_syspm_socmem_sram_pwr_mode_t value;
1578
1579 CY_ASSERT_L3(socmemSramPartNum < CY_SOCMEM_PARTITION_NR);
1580
1581 /* Unlock PWR Partition Control */
1582 /* Clear bit 0(CLR0)*/
1583 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR0;
1584 /* Clear bit 1(CLR1)*/
1585 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR1;
1586
1587
1588 value = (((SOCMEM_PWR_PARTITION_CTL(socmemSramPartNum) & (SOCMEM_PWR_PARTITION_CTL_ACT_OFF_Msk)) != 0UL) ? CY_SYSPM_SOCMEM_SRAM_ACTIVE_MODE_OFF:CY_SYSPM_SOCMEM_SRAM_ACTIVE_MODE_ON);
1589
1590 /* Lock PWR Partition Control(Set SET01) */
1591 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_SET01;
1592
1593 return value;
1594 }
1595
Cy_SysPm_GetSOCMemSramPartDsPwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum)1596 cy_en_syspm_socmem_sram_pwr_mode_t Cy_SysPm_GetSOCMemSramPartDsPwrMode(cy_en_syspm_socmem_sram_partition_index_t socmemSramPartNum)
1597 {
1598 cy_en_syspm_socmem_sram_pwr_mode_t value;
1599
1600 CY_ASSERT_L3(socmemSramPartNum < CY_SOCMEM_PARTITION_NR);
1601
1602 /* Unlock PWR Partition Control */
1603 /* Clear bit 0(CLR0)*/
1604 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR0;
1605 /* Clear bit 1(CLR1)*/
1606 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_CLR1;
1607
1608
1609 value = (((SOCMEM_PWR_PARTITION_CTL(socmemSramPartNum) & (SOCMEM_PWR_PARTITION_CTL_RET_OFF_Msk)) != 0UL) ? CY_SYSPM_SOCMEM_SRAM_DS_MODE_RET_OFF:CY_SYSPM_SOCMEM_SRAM_DS_MODE_RET_ON);
1610
1611 /* Lock PWR Partition Control(Set SET01) */
1612 SOCMEM_PWR_PARTITION_CTL_LOCK = SOCMEM_PWR_PARTITION_CTL_LOCK_SET01;
1613
1614 return value;
1615 }
1616
1617
1618 /* This API is an inline version of Cy_SysPm_SetSRAMMacroPwrMode */
Cy_SysPm_SetSRAMMacroPwrModeInline(cy_en_syspm_sram_index_t sramNum,uint32_t sramMacroNum,cy_en_syspm_sram_pwr_mode_t sramPwrMode)1619 __STATIC_FORCEINLINE cy_en_syspm_status_t Cy_SysPm_SetSRAMMacroPwrModeInline(cy_en_syspm_sram_index_t sramNum, uint32_t sramMacroNum, cy_en_syspm_sram_pwr_mode_t sramPwrMode)
1620 {
1621 CY_ASSERT_L3((sramNum == CY_SYSPM_SRAM0_MEMORY) || (sramNum == CY_SYSPM_SRAM1_MEMORY));
1622 CY_ASSERT_L3((sramPwrMode == CY_SYSPM_SRAM_PWR_MODE_ON) || (sramPwrMode == CY_SYSPM_SRAM_PWR_MODE_OFF));
1623 CY_ASSERT_L3(sramMacroNum < CY_CPUSS_RAMC_MACRO_NR(sramNum));
1624
1625 /* Unlock PWR MACRO Control */
1626 /* Clear bit 0(CLR0)*/
1627 MXSRAMC_PWR_MACRO_CTL_LOCK(sramNum) = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR0;
1628 /* Clear bit 1(CLR1)*/
1629 MXSRAMC_PWR_MACRO_CTL_LOCK(sramNum) = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR1;
1630
1631 if(sramPwrMode == CY_SYSPM_SRAM_PWR_MODE_ON)
1632 {
1633 /* Enable the Macro Number */
1634 MXSRAMC_PWR_MACRO_CTL(sramNum) &= ~(0x1UL << (uint32_t)sramMacroNum);
1635 }
1636 else
1637 {
1638 /* Disable the Macro Number */
1639 MXSRAMC_PWR_MACRO_CTL(sramNum) |= (0x1UL << (uint32_t)sramMacroNum);
1640 }
1641 /* Wait for the PWR_DONE status */
1642 while(!_FLD2BOOL(RAMC_STATUS_PWR_DONE, MXSRAMC_STATUS(sramNum))){}
1643
1644 /* Lock PWR MACRO Control(Set SET01) */
1645 MXSRAMC_PWR_MACRO_CTL_LOCK(sramNum) = MXSRAMC_PWR_MACRO_CTL_LOCK_SET01;
1646
1647 return CY_SYSPM_SUCCESS;
1648 }
1649
Cy_SysPm_SetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum,uint32_t sramMacroNum,cy_en_syspm_sram_pwr_mode_t sramPwrMode)1650 cy_en_syspm_status_t Cy_SysPm_SetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum, uint32_t sramMacroNum, cy_en_syspm_sram_pwr_mode_t sramPwrMode)
1651 {
1652 return Cy_SysPm_SetSRAMMacroPwrModeInline(sramNum, sramMacroNum, sramPwrMode);
1653 }
1654
Cy_SysPm_GetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum,uint32_t sramMacroNum)1655 cy_en_syspm_sram_pwr_mode_t Cy_SysPm_GetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum, uint32_t sramMacroNum)
1656 {
1657 cy_en_syspm_sram_pwr_mode_t value;
1658
1659 CY_ASSERT_L3((sramNum == CY_SYSPM_SRAM0_MEMORY) || (sramNum == CY_SYSPM_SRAM1_MEMORY));
1660 CY_ASSERT_L3(sramMacroNum < CY_CPUSS_RAMC_MACRO_NR(sramNum));
1661
1662 /* Unlock PWR MACRO Control */
1663 /* Clear bit 0(CLR0)*/
1664 MXSRAMC_PWR_MACRO_CTL_LOCK(sramNum) = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR0;
1665 /* Clear bit 1(CLR1)*/
1666 MXSRAMC_PWR_MACRO_CTL_LOCK(sramNum) = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR1;
1667
1668 value = (((MXSRAMC_PWR_MACRO_CTL(sramNum) & (0x1UL << (uint32_t)sramMacroNum)) != 0UL) ? CY_SYSPM_SRAM_PWR_MODE_OFF:CY_SYSPM_SRAM_PWR_MODE_ON);
1669
1670 /* Lock PWR MACRO Control(Set SET01) */
1671 MXSRAMC_PWR_MACRO_CTL_LOCK(sramNum) = MXSRAMC_PWR_MACRO_CTL_LOCK_SET01;
1672
1673 return value;
1674
1675 }
1676
1677
Cy_SysPm_SetSRAMPwrMode(cy_en_syspm_sram_index_t sramNum,cy_en_syspm_sram_pwr_mode_t sramPwrMode)1678 cy_en_syspm_status_t Cy_SysPm_SetSRAMPwrMode(cy_en_syspm_sram_index_t sramNum, cy_en_syspm_sram_pwr_mode_t sramPwrMode)
1679 {
1680 uint8_t macroNum;
1681 CY_ASSERT_L3((sramNum == CY_SYSPM_SRAM0_MEMORY) || (sramNum == CY_SYSPM_SRAM1_MEMORY));
1682 CY_ASSERT_L3((sramPwrMode == CY_SYSPM_SRAM_PWR_MODE_ON) || (sramPwrMode == CY_SYSPM_SRAM_PWR_MODE_OFF));
1683
1684 for(macroNum = 0; (macroNum < CY_CPUSS_RAMC_MACRO_NR(sramNum));macroNum++)
1685 {
1686 (void)Cy_SysPm_SetSRAMMacroPwrMode(sramNum, (uint32_t)macroNum, sramPwrMode);
1687 }
1688
1689 return CY_SYSPM_SUCCESS;
1690 }
1691
Cy_SysPm_TriggerSoftReset(void)1692 void Cy_SysPm_TriggerSoftReset(void)
1693 {
1694 SRSS_RES_SOFT_CTL = SRSS_RES_SOFT_CTL_TRIGGER_SOFT_Msk;
1695 }
1696
Cy_SysPm_IsSystemLp(void)1697 bool Cy_SysPm_IsSystemLp(void)
1698 {
1699 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_LP) != 0U);
1700 }
1701
Cy_SysPm_IsSystemUlp(void)1702 bool Cy_SysPm_IsSystemUlp(void)
1703 {
1704 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_ULP) != 0U);
1705 }
1706
Cy_SysPm_IsSystemMf(void)1707 bool Cy_SysPm_IsSystemMf(void)
1708 {
1709 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_MF) != 0U);
1710 }
1711
Cy_Syspm_SetTRIMRAMCtl(uint8_t index,uint32_t trimValue)1712 static void Cy_Syspm_SetTRIMRAMCtl(uint8_t index, uint32_t trimValue)
1713 {
1714 SRSS_TRIM_RAM_CTL(index) = trimValue;
1715 }
1716
Cy_SysPm_SystemEnterLpToDs(void)1717 static void Cy_SysPm_SystemEnterLpToDs(void)
1718 {
1719 /* LP to DS Sequence */
1720
1721 /* LP->DS(1) */
1722 /* Change frequency to 4MHz */
1723 /* TBD */
1724
1725 /* LP->DS(2) */
1726 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_203);
1727 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_203);
1728
1729 /* LP->DS(3) */
1730 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_207);
1731 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_207);
1732
1733 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_20F);
1734 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_20F);
1735
1736 /* LP->DS(4) */
1737 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_20F);
1738 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_20F);
1739
1740 /* LP->DS(5) */
1741 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_21F);
1742 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_21F);
1743
1744 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_21F);
1745 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_21F);
1746
1747 /* LP->DS(6) */
1748 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_23F);
1749 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_23F);
1750
1751 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_23F);
1752 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_23F);
1753
1754 /* LP->DS(7) */
1755 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_63F);
1756 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_63F);
1757
1758 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_63F);
1759 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_63F);
1760
1761 /* LP->DS(8) */
1762 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_E3F);
1763 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_E3F);
1764
1765 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_E3F);
1766 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_E3F);
1767
1768 /* LP->DS(9) */
1769 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_1E3F);
1770 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_1E3F);
1771 }
1772
Cy_SysPm_SystemEnterDsToLp(void)1773 static void Cy_SysPm_SystemEnterDsToLp(void)
1774 {
1775 /* DS to LP Sequence */
1776
1777 /* DS->LP(2) */
1778 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_E3F);
1779 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_E3F);
1780
1781 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_63F);
1782 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_63F);
1783
1784 /* DS->LP(3) */
1785 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_63F);
1786 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_63F);
1787
1788 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_23F);
1789 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_23F);
1790
1791 /* DS->LP(4) */
1792 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_23F);
1793 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_23F);
1794
1795 /* DS->LP(5) */
1796 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_21F);
1797 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_21F);
1798
1799 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_21F);
1800 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_21F);
1801
1802 /* DS->LP(6) */
1803 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_21B);
1804 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_21B);
1805
1806 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_21B);
1807 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_21B);
1808
1809 /* DS->LP(7) */
1810 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_21A);
1811 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_21A);
1812
1813 /* DS->LP(8) */
1814 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_20A);
1815 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_20A);
1816
1817 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_20B);
1818 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_20B);
1819
1820 /* DS->LP(9) */
1821 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_202);
1822 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_202);
1823
1824 /* DS->LP(10) */
1825 /* Change frequency to 400MHz */
1826 /* TBD */
1827 }
1828
Cy_SysPm_SystemEnterMfToDs(void)1829 static void Cy_SysPm_SystemEnterMfToDs(void)
1830 {
1831 /* MF to DS Sequence */
1832
1833 /* MF->DS(1) */
1834 /* Change frequency to 4MHz */
1835 /* TBD */
1836
1837 /* MF->DS(2) */
1838 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_605);
1839 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_605);
1840
1841 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_605);
1842 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_605);
1843
1844 /* MF->DS(3) */
1845 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_607);
1846 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_607);
1847
1848 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_607);
1849 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_607);
1850
1851 /* MF->DS(4) */
1852 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_60F);
1853 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_60F);
1854
1855 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_60F);
1856 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_60F);
1857
1858 /* MF->DS(5) */
1859 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_61F);
1860 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_61F);
1861
1862 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_61F);
1863 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_61F);
1864
1865 /* MF->DS(6) */
1866 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_63F);
1867 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_63F);
1868
1869 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_63F);
1870 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_63F);
1871
1872 /* MF->DS(7) */
1873 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_E3F);
1874 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_E3F);
1875
1876 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_E3F);
1877 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_E3F);
1878
1879 /* MF->DS(8) */
1880 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_1E3F);
1881 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_1E3F);
1882
1883 }
1884
Cy_SysPm_SystemEnterDsToMf(void)1885 static void Cy_SysPm_SystemEnterDsToMf(void)
1886 {
1887 /* DS to MF Sequence */
1888
1889 /* DS->MF(2) */
1890 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_E3F);
1891 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_E3F);
1892
1893 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_63F);
1894 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_63F);
1895
1896 /* DS->MF(3) */
1897 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_63F);
1898 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_63F);
1899
1900 /* DS->MF(4) */
1901 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_61F);
1902 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_61F);
1903
1904 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_61F);
1905 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_61F);
1906
1907 /* DS->MF(5) */
1908 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_61D);
1909 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_61D);
1910
1911 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_61D);
1912 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_61D);
1913
1914 /* DS->MF(6) */
1915 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_61C);
1916 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_61C);
1917
1918 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_61C);
1919 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_61C);
1920
1921 /* DS->MF(7) */
1922 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_60C);
1923 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_60C);
1924
1925 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_60C);
1926 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_60C);
1927
1928 /* DS->MF(8) */
1929 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_604);
1930 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_604);
1931
1932 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_604);
1933 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_604);
1934
1935 /* DS->MF(9) */
1936 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_202);
1937 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_202);
1938
1939 /* DS->MF(10) */
1940 /* Change frequency to 120MHz */
1941 /* TBD */
1942 }
1943
1944
Cy_SysPm_SystemEnterUlpToDs(void)1945 static void Cy_SysPm_SystemEnterUlpToDs(void)
1946 {
1947 /* ULP to DS Sequence */
1948
1949 /* ULP->DS(1) */
1950 /* Change frequency to 4MHz */
1951 /* TBD */
1952
1953 /* ULP->DS(2) */
1954 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_607);
1955 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_607);
1956
1957 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_607);
1958 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_607);
1959
1960 /* ULP->DS(3) */
1961 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_60F);
1962 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_60F);
1963
1964 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_60F);
1965 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_60F);
1966
1967 /* ULP->DS(4) */
1968 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_61F);
1969 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_61F);
1970
1971 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_61F);
1972 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_61F);
1973
1974 /* ULP->DS(5) */
1975 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_63F);
1976 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_63F);
1977
1978 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_63F);
1979 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_63F);
1980
1981 /* ULP->DS(6) */
1982 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_E3F);
1983 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_E3F);
1984
1985 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_E3F);
1986 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_E3F);
1987
1988 /* ULP->DS(7) */
1989 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_1E3F);
1990 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_1E3F);
1991
1992 }
1993
Cy_SysPm_SystemEnterDsToUlp(void)1994 static void Cy_SysPm_SystemEnterDsToUlp(void)
1995 {
1996 /* DS to ULP Sequence */
1997
1998 /* DS->ULP(2) */
1999 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_E3F);
2000 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_E3F);
2001
2002 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_63F);
2003 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_63F);
2004
2005 /* DS->ULP(3) */
2006 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_63F);
2007 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_63F);
2008
2009 /* DS->ULP(4) */
2010 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_61F);
2011 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_61F);
2012
2013 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_61F);
2014 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_61F);
2015
2016 /* DS->ULP(5) */
2017 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_61B);
2018 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_61B);
2019
2020 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_61B);
2021 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_61B);
2022
2023 /* DS->ULP(6) */
2024 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_60B);
2025 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_60B);
2026
2027 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_60B);
2028 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_60B);
2029
2030 /* DS->ULP(7) */
2031 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_603);
2032 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_603);
2033
2034 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_603);
2035 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_603);
2036
2037 /* DS->ULP(8) */
2038 /* Change frequency to 50MHz */
2039 /* TBD */
2040 }
2041
Cy_Syspm_SetRAMTrimsPreDS(void)2042 void Cy_Syspm_SetRAMTrimsPreDS(void)
2043 {
2044 if(Cy_SysPm_IsSystemLp())
2045 {
2046 Cy_SysPm_SystemEnterLpToDs();
2047 }
2048 else if(Cy_SysPm_IsSystemMf())
2049 {
2050 Cy_SysPm_SystemEnterMfToDs();
2051 }
2052 else if(Cy_SysPm_IsSystemUlp())
2053 {
2054 Cy_SysPm_SystemEnterUlpToDs();
2055 }
2056 else
2057 {
2058 /* Do Nothing */
2059 }
2060 }
2061
Cy_Syspm_SetRAMTrimsPostDS(void)2062 void Cy_Syspm_SetRAMTrimsPostDS(void)
2063 {
2064 if(Cy_SysPm_IsSystemLp())
2065 {
2066 Cy_SysPm_SystemEnterDsToLp();
2067 }
2068 else if(Cy_SysPm_IsSystemMf())
2069 {
2070 Cy_SysPm_SystemEnterDsToMf();
2071 }
2072 else if(Cy_SysPm_IsSystemUlp())
2073 {
2074 Cy_SysPm_SystemEnterDsToUlp();
2075 }
2076 else
2077 {
2078 /* Do Nothing */
2079 }
2080 }
2081
Cy_SysPm_SystemEnterLpToMf(void)2082 static cy_en_syspm_status_t Cy_SysPm_SystemEnterLpToMf(void)
2083 {
2084 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2085
2086 /* LP to MF Sequence */
2087
2088 /* 1) M33 send IPC to m0seccpuss - Operating mode change target */
2089 //TBD
2090
2091 /* 2) Retention Level change */
2092 //TBD
2093
2094 /* 3) Reduce the frequency so it is at least ??% (400MHz to <=75MHz) below the static timing closure limits at the new voltage setting for SRAM timing margin */
2095 (void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_DIVIDE_BY_6);//i.e. 66.66MHz, Assuming 400MHz as source clock to HF0.
2096
2097 /* 4) SRAM trim updates - LP->MF(2) through LP->MF(5) */
2098 /* LP->MF(2) */
2099 Cy_Syspm_SetTRIMRAMCtl(0U, RAM_TRIM_VAL_343);
2100 Cy_Syspm_SetTRIMRAMCtl(1U, RAM_TRIM_VAL_343);
2101
2102 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_206);
2103 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_206);
2104
2105 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_20F);
2106 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_20F);
2107
2108 Cy_Syspm_SetTRIMRAMCtl(6U, RAM_TRIM_VAL_3F);
2109 Cy_Syspm_SetTRIMRAMCtl(7U, RAM_TRIM_VAL_3F);
2110
2111 Cy_Syspm_SetTRIMRAMCtl(8U, RAM_TRIM_VAL_B);
2112
2113 /* LP->MF(3) */
2114 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_204);
2115 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_204);
2116
2117 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_20C);
2118 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_20C);
2119
2120 Cy_Syspm_SetTRIMRAMCtl(6U, RAM_TRIM_VAL_2D);
2121 Cy_Syspm_SetTRIMRAMCtl(7U, RAM_TRIM_VAL_2D);
2122
2123 /* LP->MF(4) */
2124 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_204);
2125 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_204);
2126
2127 /* LP->MF(5) */
2128 Cy_Syspm_SetTRIMRAMCtl(0U, RAM_TRIM_VAL_743);
2129 Cy_Syspm_SetTRIMRAMCtl(1U, RAM_TRIM_VAL_743);
2130
2131 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_604);
2132 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_604);
2133
2134 Cy_Syspm_SetTRIMRAMCtl(6U, RAM_TRIM_VAL_22D);
2135 Cy_Syspm_SetTRIMRAMCtl(7U, RAM_TRIM_VAL_22D);
2136
2137 /* 5) Change the voltage */
2138 Cy_SysPm_CoreBuckSetProfile(CY_SYSPM_CORE_BUCK_PROFILE_MF);
2139
2140 if(CY_SYSPM_SUCCESS != Cy_SysPm_CoreBuckStatus())
2141 {
2142 retVal = CY_SYSPM_FAIL;
2143 }
2144 else
2145 {
2146 retVal = Cy_SysPm_SramLdoSetVoltage(CY_SYSPM_SRAMLDO_VOLTAGE_0_80V);
2147
2148 if((CY_SYSPM_SUCCESS != retVal) || (CY_SYSPM_SUCCESS != Cy_SysPm_SramLdoStatus()))
2149 {
2150 retVal = CY_SYSPM_FAIL;
2151 }
2152 else
2153 {
2154 /* 6) SRAM trim updates - LP->MF(7) */
2155 /* LP->MF(7) */
2156 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_604);
2157 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_604);
2158
2159 /* 7) M33 send IPC to m0seccpuss - Voltage at target level */
2160 //TBD
2161
2162 /* 8) Change RRAM to MF mode */
2163 Cy_RRAM_SetVoltageMode(RRAMC0, CY_RRAM_VMODE_MF);
2164
2165 /* 9) Change Frequency */
2166 (void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_DIVIDE_BY_3);//Set to 133.33MHz
2167
2168 /* 10) M33 sends IPC to m0seccpuss - Frequency at target level */
2169 //TBD
2170 }
2171 }
2172
2173
2174 return retVal;
2175 }
2176
Cy_SysPm_SystemEnterMfToLp(void)2177 static cy_en_syspm_status_t Cy_SysPm_SystemEnterMfToLp(void)
2178 {
2179 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2180
2181 /* MF to LP Sequence */
2182
2183 /* 1) M33 send IPC to m0seccpuss - Operating mode change target */
2184 //TBD
2185
2186 /* 2) Retention Level change */
2187 //TBD
2188
2189 /* 3) Reduce frequency by at least 38% (120MHz to <=75MHz) for SRAM timing margin */
2190 (void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_DIVIDE_BY_6);//i.e. 66.66MHz, Assuming 400MHz as source clock to HF0.
2191
2192 /* 4) SRAM trim updates - MF->LP(2) through MF->LP(5) */
2193 /* MF->LP(2) */
2194 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_606);
2195 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_606);
2196
2197 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_606);
2198 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_606);
2199
2200 Cy_Syspm_SetTRIMRAMCtl(6U, RAM_TRIM_VAL_23F);
2201 Cy_Syspm_SetTRIMRAMCtl(7U, RAM_TRIM_VAL_23F);
2202
2203 /* MF->LP(3) */
2204 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_607);
2205 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_607);
2206
2207 /* MF->LP(4) */
2208 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_60F);
2209 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_60F);
2210
2211 /* MF->LP(5) */
2212 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_20F);
2213 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_20F);
2214
2215 /* 5) Change the voltage */
2216 Cy_SysPm_CoreBuckSetProfile(CY_SYSPM_CORE_BUCK_PROFILE_LP);
2217
2218 if(CY_SYSPM_SUCCESS != Cy_SysPm_CoreBuckStatus())
2219 {
2220 retVal = CY_SYSPM_FAIL;
2221 }
2222 else
2223 {
2224 retVal = Cy_SysPm_SramLdoSetVoltage(CY_SYSPM_SRAMLDO_VOLTAGE_0_90V);
2225
2226 if((CY_SYSPM_SUCCESS != retVal) || (CY_SYSPM_SUCCESS != Cy_SysPm_SramLdoStatus()))
2227 {
2228 retVal = CY_SYSPM_FAIL;
2229 }
2230 else
2231 {
2232 /* 6) SRAM trim updates - MF->LP(7) & MF->LP(8) */
2233 /* MF->LP(7) */
2234 Cy_Syspm_SetTRIMRAMCtl(0U, RAM_TRIM_VAL_343);
2235 Cy_Syspm_SetTRIMRAMCtl(1U, RAM_TRIM_VAL_343);
2236
2237 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_206);
2238 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_206);
2239
2240 Cy_Syspm_SetTRIMRAMCtl(6U, RAM_TRIM_VAL_3F);
2241 Cy_Syspm_SetTRIMRAMCtl(7U, RAM_TRIM_VAL_3F);
2242
2243 Cy_Syspm_SetTRIMRAMCtl(8U, RAM_TRIM_VAL_A);
2244
2245 /* MF->LP(8) */
2246 Cy_Syspm_SetTRIMRAMCtl(0U, RAM_TRIM_VAL_342);
2247 Cy_Syspm_SetTRIMRAMCtl(1U, RAM_TRIM_VAL_342);
2248
2249 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_202);
2250 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_202);
2251
2252 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_20B);
2253 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_20B);
2254
2255 Cy_Syspm_SetTRIMRAMCtl(6U, RAM_TRIM_VAL_1B);
2256 Cy_Syspm_SetTRIMRAMCtl(7U, RAM_TRIM_VAL_1B);
2257
2258 /* 7) M33 send IPC to m0seccpuss - Voltage at target level */
2259 //TBD
2260
2261 /* 8) Change RRAM to LP mode */
2262 Cy_RRAM_SetVoltageMode(RRAMC0, CY_RRAM_VMODE_LP);
2263
2264 /* 9) Change Frequency */
2265 (void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);//Set to 400MHz
2266
2267 /* 10) M33 sends IPC to m0seccpuss - Frequency at target level */
2268 //TBD
2269 }
2270 }
2271
2272
2273 return retVal;
2274 }
2275
Cy_SysPm_SystemEnterUlpToMf(void)2276 static cy_en_syspm_status_t Cy_SysPm_SystemEnterUlpToMf(void)
2277 {
2278 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2279
2280 /* ULP to MF Sequence */
2281
2282 /* 1) M33 send IPC to m0seccpuss - Operating mode change target */
2283 //TBD
2284
2285 /* 2) Retention Level change */
2286 //TBD
2287
2288 /* 3) ULP->MF(1), Reduce frequency by at least 18% (50MHz to <= 41MHz) for SRAM timing margin */
2289 (void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_DIVIDE_BY_10); //i.e. 40MHz, Assuming 400MHz as source clock to HF0.
2290
2291 /* 4) SRAM trim updates - ULP->MF(3) through ULP->MF(5) */
2292 /* ULP->MF(3) */
2293 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_607);
2294 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_607);
2295
2296 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_607);
2297 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_607);
2298
2299 Cy_Syspm_SetTRIMRAMCtl(6U, RAM_TRIM_VAL_63D);
2300 Cy_Syspm_SetTRIMRAMCtl(7U, RAM_TRIM_VAL_63D);
2301
2302 Cy_Syspm_SetTRIMRAMCtl(8U, RAM_TRIM_VAL_F);
2303
2304 /* ULP->MF(4) */
2305 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_606);
2306 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_606);
2307
2308 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_606);
2309 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_606);
2310
2311 Cy_Syspm_SetTRIMRAMCtl(6U, RAM_TRIM_VAL_62D);
2312 Cy_Syspm_SetTRIMRAMCtl(7U, RAM_TRIM_VAL_62D);
2313
2314 Cy_Syspm_SetTRIMRAMCtl(8U, RAM_TRIM_VAL_B);
2315
2316 /* ULP->MF(5) */
2317 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_604);
2318 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_604);
2319
2320 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_604);
2321 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_604);
2322
2323 /* 5) Change the voltage */
2324 Cy_SysPm_CoreBuckSetProfile(CY_SYSPM_CORE_BUCK_PROFILE_MF);
2325
2326 if(CY_SYSPM_SUCCESS != Cy_SysPm_CoreBuckStatus())
2327 {
2328 retVal = CY_SYSPM_FAIL;
2329 }
2330 else
2331 {
2332 /* 5.1 Disable the SRAMLDO allowing CBUCK to supply SRAM Core */
2333 Cy_SysPm_SramLdoEnable(false);
2334
2335 /* 6) SRAM trim updates - ULP->MF(7) */
2336 Cy_Syspm_SetTRIMRAMCtl(6U, RAM_TRIM_VAL_22D);
2337 Cy_Syspm_SetTRIMRAMCtl(7U, RAM_TRIM_VAL_22D);
2338
2339
2340 /* 7) M33 send IPC to m0seccpuss - Voltage at target level */
2341 //TBD
2342
2343 /* 8) Change RRAM to MF mode */
2344 Cy_RRAM_SetVoltageMode(RRAMC0, CY_RRAM_VMODE_MF);
2345
2346 /* 9) Change Frequency */
2347 (void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_DIVIDE_BY_3);//TBD-Set to 120MHz
2348
2349 /* 10) M33 sends IPC to m0seccpuss - Frequency at target level */
2350 //TBD
2351 }
2352 return retVal;
2353 }
2354
Cy_SysPm_SystemEnterMfToUlp(void)2355 static cy_en_syspm_status_t Cy_SysPm_SystemEnterMfToUlp(void)
2356 {
2357 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2358
2359 /* MF to ULP Sequence */
2360
2361 /* 1) M33 send IPC to m0seccpuss - Operating mode change target */
2362 //TBD
2363
2364 /* 2) Retention Level change */
2365 //TBD
2366
2367 /* 3) Reduce the operating frequency so it is at least 66% (120MHz to 41MHz) */
2368 (void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_DIVIDE_BY_10); //i.e. 40MHz, Assuming 400MHz as source clock to HF0.
2369
2370 /* MF->ULP(2) */
2371 Cy_Syspm_SetTRIMRAMCtl(6U, RAM_TRIM_VAL_23D);
2372 Cy_Syspm_SetTRIMRAMCtl(7U, RAM_TRIM_VAL_23D);
2373
2374 Cy_Syspm_SetTRIMRAMCtl(8U, RAM_TRIM_VAL_F);
2375
2376 /* MF->ULP(3) */
2377 Cy_Syspm_SetTRIMRAMCtl(6U, RAM_TRIM_VAL_63D);
2378 Cy_Syspm_SetTRIMRAMCtl(7U, RAM_TRIM_VAL_63D);
2379
2380 /* 5) Change the voltage */
2381 /* 5.1 Enable the SRAMLDO to supply SRAM Core */
2382 Cy_SysPm_SramLdoEnable(true);
2383
2384 if(CY_SYSPM_SUCCESS != Cy_SysPm_SramLdoStatus())
2385 {
2386 retVal = CY_SYSPM_FAIL;
2387 }
2388 else
2389 {
2390 /* 5.2 Select the ULP voltage profile */
2391 Cy_SysPm_CoreBuckSetProfile(CY_SYSPM_CORE_BUCK_PROFILE_ULP);
2392
2393 if(CY_SYSPM_SUCCESS != Cy_SysPm_CoreBuckStatus())
2394 {
2395 retVal = CY_SYSPM_FAIL;
2396 }
2397 else
2398 {
2399 /* 6) SRAM trim updates - MF->ULP(5) & MF->ULP(7) */
2400 /* MF->ULP(5) */
2401 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_606);
2402 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_606);
2403
2404 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_606);
2405 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_606);
2406
2407 Cy_Syspm_SetTRIMRAMCtl(6U, RAM_TRIM_VAL_61D);
2408 Cy_Syspm_SetTRIMRAMCtl(7U, RAM_TRIM_VAL_61D);
2409
2410 Cy_Syspm_SetTRIMRAMCtl(8U, RAM_TRIM_VAL_C);
2411
2412 /* MF->ULP(6) */
2413 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_607);
2414 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_607);
2415
2416 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_607);
2417 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_607);
2418
2419 /* MF->ULP(7) */
2420 Cy_Syspm_SetTRIMRAMCtl(2U, RAM_TRIM_VAL_603);
2421 Cy_Syspm_SetTRIMRAMCtl(3U, RAM_TRIM_VAL_603);
2422
2423 Cy_Syspm_SetTRIMRAMCtl(4U, RAM_TRIM_VAL_603);
2424 Cy_Syspm_SetTRIMRAMCtl(5U, RAM_TRIM_VAL_603);
2425
2426 /* 7) M33 send IPC to m0seccpuss - Voltage at target level */
2427 //TBD
2428
2429 /* 8) Change RRAM to ULP mode */
2430 Cy_RRAM_SetVoltageMode(RRAMC0, CY_RRAM_VMODE_ULP);
2431
2432 /* 9) Change Frequency */
2433 (void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_DIVIDE_BY_8);//Set to 50MHz
2434
2435 /* 10) M33 sends IPC to m0seccpuss - Frequency at target level */
2436 //TBD
2437 }
2438 }
2439
2440 return retVal;
2441 }
2442
Cy_SysPm_SystemEnterLp(void)2443 cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void)
2444 {
2445 uint32_t interruptState;
2446 uint32_t cbLpRootIdx = (uint32_t) CY_SYSPM_LP;
2447 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2448
2449 /* Call the registered callback functions with the
2450 * CY_SYSPM_CHECK_READY parameter
2451 */
2452 if (pmCallbackRoot[cbLpRootIdx] != NULL)
2453 {
2454 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_CHECK_READY);
2455 }
2456
2457 /* The system can switch into LP only when
2458 * all executed registered callback functions with the
2459 * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS
2460 */
2461 if (retVal == CY_SYSPM_SUCCESS)
2462 {
2463
2464 /* Call the registered callback functions with the
2465 * CY_SYSPM_BEFORE_TRANSITION parameter
2466 */
2467 interruptState = Cy_SysLib_EnterCriticalSection();
2468 if (pmCallbackRoot[cbLpRootIdx] != NULL)
2469 {
2470 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_BEFORE_TRANSITION);
2471 }
2472
2473 if(Cy_SysPm_IsSystemMf())
2474 {
2475 (void) Cy_SysPm_SystemEnterMfToLp();
2476 }
2477 else if(Cy_SysPm_IsSystemUlp())
2478 {
2479 (void) Cy_SysPm_SystemEnterUlpToMf();
2480 (void) Cy_SysPm_SystemEnterMfToLp();
2481 }
2482 else
2483 {
2484 /*Block added to avoid MISRA errors */
2485 }
2486
2487 Cy_SysLib_ExitCriticalSection(interruptState);
2488
2489 /* Call the registered callback functions with the
2490 * CY_SYSPM_AFTER_TRANSITION parameter
2491 */
2492 if (pmCallbackRoot[cbLpRootIdx] != NULL)
2493 {
2494 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_AFTER_TRANSITION);
2495 }
2496 }
2497 else
2498 {
2499 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
2500 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
2501 * parameter
2502 */
2503 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_CHECK_FAIL);
2504 retVal = CY_SYSPM_FAIL;
2505 }
2506
2507 return retVal;
2508 }
2509
2510
Cy_SysPm_SystemEnterUlp(void)2511 cy_en_syspm_status_t Cy_SysPm_SystemEnterUlp(void)
2512 {
2513 uint32_t interruptState;
2514 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2515 uint32_t cbUlpRootIdx = (uint32_t) CY_SYSPM_ULP;
2516
2517 /* Call the registered callback functions with the
2518 * CY_SYSPM_CHECK_READY parameter
2519 */
2520 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2521 {
2522 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_CHECK_READY);
2523 }
2524
2525 /* The system can switch into the ULP only when
2526 * all executed registered callback functions with the
2527 * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS
2528 */
2529 if (retVal == CY_SYSPM_SUCCESS)
2530 {
2531 /* Call the registered callback functions with the
2532 * CY_SYSPM_BEFORE_TRANSITION parameter
2533 */
2534 interruptState = Cy_SysLib_EnterCriticalSection();
2535 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2536 {
2537 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_BEFORE_TRANSITION);
2538 }
2539
2540 if(Cy_SysPm_IsSystemMf())
2541 {
2542 (void) Cy_SysPm_SystemEnterMfToUlp();
2543 }
2544 else if(Cy_SysPm_IsSystemLp())
2545 {
2546 (void) Cy_SysPm_SystemEnterLpToMf();
2547 (void) Cy_SysPm_SystemEnterMfToUlp();
2548 }
2549 else
2550 {
2551 /*Block added to avoid MISRA errors */
2552 }
2553
2554 Cy_SysLib_ExitCriticalSection(interruptState);
2555
2556 /* Call the registered callback functions with the
2557 * CY_SYSPM_AFTER_TRANSITION parameter
2558 */
2559 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2560 {
2561 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_AFTER_TRANSITION);
2562 }
2563 }
2564 else
2565 {
2566 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
2567 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
2568 * parameter
2569 */
2570 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_CHECK_FAIL);
2571 retVal = CY_SYSPM_FAIL;
2572 }
2573
2574 return retVal;
2575 }
2576
2577
Cy_SysPm_SystemEnterMf(void)2578 cy_en_syspm_status_t Cy_SysPm_SystemEnterMf(void)
2579 {
2580 uint32_t interruptState;
2581 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
2582 uint32_t cbUlpRootIdx = (uint32_t) CY_SYSPM_MF;
2583
2584 /* Call the registered callback functions with the
2585 * CY_SYSPM_CHECK_READY parameter
2586 */
2587 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2588 {
2589 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_MF, CY_SYSPM_CHECK_READY);
2590 }
2591
2592 /* The system can switch into the ULP only when
2593 * all executed registered callback functions with the
2594 * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS
2595 */
2596 if (retVal == CY_SYSPM_SUCCESS)
2597 {
2598 /* Call the registered callback functions with the
2599 * CY_SYSPM_BEFORE_TRANSITION parameter
2600 */
2601 interruptState = Cy_SysLib_EnterCriticalSection();
2602 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2603 {
2604 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_MF, CY_SYSPM_BEFORE_TRANSITION);
2605 }
2606
2607 if(Cy_SysPm_IsSystemLp())
2608 {
2609 (void) Cy_SysPm_SystemEnterLpToMf();
2610 }
2611 else if(Cy_SysPm_IsSystemUlp())
2612 {
2613 (void) Cy_SysPm_SystemEnterUlpToMf();
2614 }
2615 else
2616 {
2617 /*Block added to avoid MISRA errors */
2618 }
2619
2620 Cy_SysLib_ExitCriticalSection(interruptState);
2621
2622 /* Call the registered callback functions with the
2623 * CY_SYSPM_AFTER_TRANSITION parameter
2624 */
2625 if (pmCallbackRoot[cbUlpRootIdx] != NULL)
2626 {
2627 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_MF, CY_SYSPM_AFTER_TRANSITION);
2628 }
2629 }
2630 else
2631 {
2632 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
2633 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
2634 * parameter
2635 */
2636 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_MF, CY_SYSPM_CHECK_FAIL);
2637 retVal = CY_SYSPM_FAIL;
2638 }
2639
2640 return retVal;
2641 }
2642
2643
Cy_SysPm_ReadStatus(void)2644 uint32_t Cy_SysPm_ReadStatus(void)
2645 {
2646 uint32_t pmStatus = 0UL;
2647
2648 /* Check whether the device is in ULP/MFLP mode by reading
2649 * the core buck profile:
2650 * - 0.7V (nominal) - System ULP mode
2651 * - 0.8V (nominal) - System MF mode
2652 * - 0.9V (nominal) - System LP mode
2653 */
2654
2655 /* Read current active regulator */
2656 /* Current active regulator is LDO */
2657 if (Cy_SysPm_CoreBuckGetProfile() == CY_SYSPM_CORE_BUCK_PROFILE_LP)
2658 {
2659 pmStatus |= CY_SYSPM_STATUS_SYSTEM_LP;
2660 }
2661 else if (Cy_SysPm_CoreBuckGetProfile() == CY_SYSPM_CORE_BUCK_PROFILE_ULP)
2662 {
2663 pmStatus |= CY_SYSPM_STATUS_SYSTEM_ULP;
2664 }
2665 else
2666 {
2667 pmStatus |= CY_SYSPM_STATUS_SYSTEM_MF;
2668 }
2669
2670 /* Check whether CM33 is in the deep sleep mode*/
2671 if((0u != _FLD2VAL(MXCM33_CM33_STATUS_SLEEPING, MXCM33_CM33_STATUS)) &&
2672 (0u != _FLD2VAL(MXCM33_CM33_STATUS_SLEEPDEEP, MXCM33_CM33_STATUS)))
2673 {
2674 pmStatus |= (uint32_t) CY_SYSPM_STATUS_CM33_DEEPSLEEP;
2675 }
2676 /* Check whether CM33 is in the sleep mode*/
2677 else if (0u != _FLD2VAL(MXCM33_CM33_STATUS_SLEEPING, MXCM33_CM33_STATUS))
2678 {
2679 pmStatus |= CY_SYSPM_STATUS_CM33_SLEEP;
2680 }
2681 else
2682 {
2683 pmStatus |= CY_SYSPM_STATUS_CM33_ACTIVE;
2684 }
2685
2686 /* Check whether CM55 is in the deep sleep mode*/
2687 if((0u != _FLD2VAL(MXCM55_CM55_STATUS_SLEEPING, MXCM55_CM55_STATUS)) &&
2688 (0u != _FLD2VAL(MXCM55_CM55_STATUS_SLEEPDEEP, MXCM55_CM55_STATUS)))
2689 {
2690 pmStatus |= (uint32_t) CY_SYSPM_STATUS_CM55_DEEPSLEEP;
2691 }
2692 /* Check whether CM33 is in the sleep mode*/
2693 else if (0u != _FLD2VAL(MXCM55_CM55_STATUS_SLEEPING, MXCM55_CM55_STATUS))
2694 {
2695 pmStatus |= CY_SYSPM_STATUS_CM55_SLEEP;
2696 }
2697 else
2698 {
2699 pmStatus |= CY_SYSPM_STATUS_CM55_ACTIVE;
2700 }
2701
2702 return pmStatus;
2703 }
2704
Cy_SysPm_Cm33IsActive(void)2705 bool Cy_SysPm_Cm33IsActive(void)
2706 {
2707 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM33_ACTIVE) != 0u);
2708 }
2709
Cy_SysPm_Cm33IsSleep(void)2710 bool Cy_SysPm_Cm33IsSleep(void)
2711 {
2712 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM33_SLEEP) != 0u);
2713 }
2714
Cy_SysPm_Cm33IsDeepSleep(void)2715 bool Cy_SysPm_Cm33IsDeepSleep(void)
2716 {
2717 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM33_DEEPSLEEP) != 0u);
2718 }
2719
Cy_SysPm_Cm55IsActive(void)2720 bool Cy_SysPm_Cm55IsActive(void)
2721 {
2722 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM55_ACTIVE) != 0u);
2723 }
2724
Cy_SysPm_Cm55IsSleep(void)2725 bool Cy_SysPm_Cm55IsSleep(void)
2726 {
2727 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM55_SLEEP) != 0u);
2728 }
2729
Cy_SysPm_Cm55IsDeepSleep(void)2730 bool Cy_SysPm_Cm55IsDeepSleep(void)
2731 {
2732 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM55_DEEPSLEEP) != 0u);
2733 }
2734
2735
2736 #endif /* CY_IP_MXS22SRSS */
2737 /* [] END OF FILE */
2738
