1 /***************************************************************************//**
2 * \file cy_syspm_v3.c
3 * \version 5.94
4 *
5 * This driver provides the source code for API power management.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_device.h"
27 #include "cy_sysclk.h"
28
29 #if defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)
30
31 #include "cy_syspm.h"
32
33 /*******************************************************************************
34 * Internal Functions
35 *******************************************************************************/
36
37 /*******************************************************************************
38 * Internal Defines
39 *******************************************************************************/
40
41 /* The define for number of callback roots */
42 #define CALLBACK_ROOT_NR (5U)
43
44 /* The mask to unlock the Hibernate power mode */
45 #define HIBERNATE_UNLOCK_VAL ((uint32_t) 0x3Au << SRSS_PWR_HIBERNATE_UNLOCK_Pos)
46
47 /* The mask to set the Hibernate power mode */
48 #define SET_HIBERNATE_MODE ((HIBERNATE_UNLOCK_VAL |\
49 SRSS_PWR_HIBERNATE_FREEZE_Msk |\
50 SRSS_PWR_HIBERNATE_HIBERNATE_Msk))
51
52 /* The mask to retain the Hibernate power mode status */
53 #define HIBERNATE_RETAIN_STATUS_MASK ((SRSS_PWR_HIBERNATE_TOKEN_Msk |\
54 SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\
55 SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\
56 SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\
57 SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk))
58
59 /** The mask for the Hibernate wakeup sources */
60 #define HIBERNATE_WAKEUP_MASK ((SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\
61 SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\
62 SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\
63 SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk))
64
65 /** The define to update the token to indicate the transition into Hibernate */
66 #define HIBERNATE_TOKEN ((uint32_t) 0x1BU << SRSS_PWR_HIBERNATE_TOKEN_Pos)
67
68 /* The wait time for transition into the minimum regulator current mode
69 */
70 #define SET_MIN_CURRENT_MODE_DELAY_US (1U)
71
72 /* The wait delay time that occurs before the active reference is settled.
73 * Intermediate delay is used in transition into the normal regulator current
74 * mode
75 */
76 #define ACT_REF_SETTLE_DELAY_US (6U)
77
78 /* The wait delay time that occurs after the active reference is settled.
79 * Final delay is used in transition into the normal regulator current mode
80 */
81 #define SET_NORMAL_CURRENT_MODE_DELAY_US (1U)
82
83 /* The internal define of the tries number in the
84 * Cy_SysPm_SystemSetMinRegulatorCurrent() function
85 */
86 #define WAIT_DELAY_TRIES (100U)
87
88 /* The internal define of the tries number in the
89 * Cy_Syspm_ReghcConfigure(), Cy_Syspm_ReghcDeConfigure() functions
90 */
91 #define REGHC_WAIT_DELAY_TRIES_US (20U)
92
93
94 /* The internal define of the tries number in the
95 * Cy_SysPm_SystemSetMinRegulatorCurrent() function
96 */
97 #define CY_SYSPM_CBUCK_BUSY_RETRY_COUNT (100U)
98 #define CY_SYSPM_CBUCK_BUSY_RETRY_DELAY_MS (1U)
99
100
101
102 /*******************************************************************************
103 * Internal Variables
104 *******************************************************************************/
105
106 /* Array of the callback roots */
107 static cy_stc_syspm_callback_t* pmCallbackRoot[CALLBACK_ROOT_NR] = {(void *)0, (void *)0, (void *)0, (void *)0, (void *)0};
108
109 /* The array of the pointers to failed callback */
110 static cy_stc_syspm_callback_t* failedCallback[CALLBACK_ROOT_NR] = {(void *)0, (void *)0, (void *)0, (void *)0, (void *)0};
111
Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor)112 cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor)
113 {
114 uint32_t interruptState;
115 uint32_t cbSleepRootIdx = (uint32_t) CY_SYSPM_SLEEP;
116 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
117
118 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor));
119
120 /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */
121 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
122 {
123 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_READY);
124 }
125
126 /* The CPU can switch into the Sleep power mode only when
127 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
128 * parameter return CY_SYSPM_SUCCESS.
129 */
130 if(retVal == CY_SYSPM_SUCCESS)
131 {
132 /* Call the registered callback functions with
133 * CY_SYSPM_BEFORE_TRANSITION parameter
134 */
135 interruptState = Cy_SysLib_EnterCriticalSection();
136 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
137 {
138 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_BEFORE_TRANSITION);
139 }
140
141 /* The CPU enters the Sleep power mode upon execution of WFI/WFE */
142 SCB_SCR &= (uint32_t) ~SCB_SCR_SLEEPDEEP_Msk;
143
144 if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
145 {
146 __WFI();
147 }
148 else
149 {
150 __WFE();
151 }
152 Cy_SysLib_ExitCriticalSection(interruptState);
153
154 /* Call the registered callback functions with the
155 * CY_SYSPM_AFTER_TRANSITION parameter
156 */
157 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
158 {
159 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_AFTER_TRANSITION);
160 }
161 }
162 else
163 {
164 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
165 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
166 * parameter
167 */
168 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_FAIL);
169 retVal = CY_SYSPM_FAIL;
170 }
171 return retVal;
172 }
173
Cy_SysPm_SystemLpActiveEnter(void)174 cy_en_syspm_status_t Cy_SysPm_SystemLpActiveEnter(void)
175 {
176 uint32_t interruptState;
177 uint32_t cbSleepRootIdx = (uint32_t)CY_SYSPM_LPACTIVE_ENTER;
178 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
179
180 /* Step-1: Wait until PWR_CTL.LPM_READY==1 to indicate low power circuits are ready. */
181 if(!Cy_SysPm_IsLpmReady())
182 {
183 retVal = CY_SYSPM_FAIL;
184 }
185 else
186 {
187 /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */
188 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
189 {
190 retVal = Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_CHECK_READY);
191 }
192
193 if (retVal == CY_SYSPM_SUCCESS)
194 {
195 /* The CPU can switch into the LPACTIVE power mode only when
196 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
197 * parameter return CY_SYSPM_SUCCESS.
198 */
199 /* Call the registered callback functions with
200 * CY_SYSPM_BEFORE_TRANSITION parameter
201 */
202 interruptState = Cy_SysLib_EnterCriticalSection();
203 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
204 {
205 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_BEFORE_TRANSITION); /* Suppress a compiler warning about unused return value */
206 }
207
208 /* Configure the low-power operating mode for Linear Core regulator */
209 if(Cy_SysPm_LdoIsEnabled())
210 {
211 SRSS_PWR_CTL2 |= _VAL2FLD(SRSS_PWR_CTL2_BGREF_LPMODE, 1u);
212 }
213
214 /* This wait time allows the circuits to remove their dependence on
215 * the Active mode circuits, such as Active Reference
216 */
217 Cy_SysLib_DelayUs(CY_SYSPM_ACTIVE_TO_LP_WAIT_US);
218
219 Cy_SysLib_ExitCriticalSection(interruptState);
220
221 /* Call the registered callback functions with the
222 * CY_SYSPM_AFTER_TRANSITION parameter
223 */
224 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
225 {
226 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_AFTER_TRANSITION); /* Suppress a compiler warning about unused return value */
227 }
228 }
229 else
230 {
231 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
232 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
233 * parameter
234 */
235 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_CHECK_FAIL); /* Suppress a compiler warning about unused return value */
236 retVal = CY_SYSPM_FAIL;
237 }
238 }
239 return retVal;
240 }
241
Cy_SysPm_SystemLpActiveExit(void)242 cy_en_syspm_status_t Cy_SysPm_SystemLpActiveExit(void)
243 {
244 uint32_t interruptState;
245 uint32_t cbSleepRootIdx = (uint32_t)CY_SYSPM_LPACTIVE_EXIT;
246 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
247
248 /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */
249 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
250 {
251 retVal = Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_CHECK_READY);
252 }
253
254 if (retVal == CY_SYSPM_SUCCESS)
255 {
256 /* The CPU can switch into the LPACTIVE power mode only when
257 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
258 * parameter return CY_SYSPM_SUCCESS.
259 */
260 /* Call the registered callback functions with
261 * CY_SYSPM_BEFORE_TRANSITION parameter
262 */
263 interruptState = Cy_SysLib_EnterCriticalSection();
264 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
265 {
266 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_BEFORE_TRANSITION); /* Suppress a compiler warning about unused return value */
267 }
268
269 /* This wait time allows setting Active Reference */
270 Cy_SysLib_DelayUs(CY_SYSPM_LP_TO_ACTIVE_WAIT_BEFORE_US);
271
272 /* Configure the normal operation mode */
273 SRSS_PWR_CTL2 &= ((uint32_t) (~SRSS_PWR_CTL2_BGREF_LPMODE_Msk));
274
275 /* This wait time allows setting Active Reference */
276 Cy_SysLib_DelayUs(CY_SYSPM_LP_TO_ACTIVE_WAIT_AFTER_US);
277
278 Cy_SysLib_ExitCriticalSection(interruptState);
279
280 /* Call the registered callback functions with the
281 * CY_SYSPM_AFTER_TRANSITION parameter
282 */
283 if (pmCallbackRoot[cbSleepRootIdx] != NULL)
284 {
285 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_AFTER_TRANSITION); /* Suppress a compiler warning about unused return value */
286 }
287 }
288 else
289 {
290 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
291 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
292 * parameter
293 */
294 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbSleepRootIdx, CY_SYSPM_CHECK_FAIL); /* Suppress a compiler warning about unused return value */
295 retVal = CY_SYSPM_FAIL;
296 }
297 return retVal;
298 }
299
Cy_SysPm_IsSystemLpActiveEnabled(void)300 bool Cy_SysPm_IsSystemLpActiveEnabled(void)
301 {
302 return (_FLD2BOOL(SRSS_PWR_CTL2_BGREF_LPMODE, SRSS_PWR_CTL2)? true : false);
303 }
304
Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor)305 cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor)
306 {
307 uint32_t interruptState;
308 uint32_t cbDeepSleepRootIdx = (uint32_t) CY_SYSPM_DEEPSLEEP;
309 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
310
311 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor));
312
313 //Check if LPM is ready
314 if(!Cy_SysPm_IsLpmReady())
315 {
316 retVal = CY_SYSPM_FAIL;
317 }
318 else
319 {
320 /* Call the registered callback functions with the CY_SYSPM_CHECK_READY
321 * parameter
322 */
323 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
324 {
325 retVal = Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_CHECK_READY);
326 }
327
328 /* The CPU can switch into the Deep Sleep power mode only when
329 * all executed registered callback functions with the CY_SYSPM_CHECK_READY
330 * parameter return CY_SYSPM_SUCCESS
331 */
332 if (retVal == CY_SYSPM_SUCCESS)
333 {
334 /* Call the registered callback functions with the
335 * CY_SYSPM_BEFORE_TRANSITION parameter
336 */
337 interruptState = Cy_SysLib_EnterCriticalSection();
338 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
339 {
340 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_BEFORE_TRANSITION);
341 }
342 /* The CPU enters Deep Sleep mode upon execution of WFI/WFE
343 * use Cy_SysPm_SetDeepSleepMode to set various deepsleep modes TBD*/
344 SCB_SCR |= SCB_SCR_SLEEPDEEP_Msk;
345
346 if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
347 {
348 __WFI();
349 }
350 else
351 {
352 __WFE();
353 }
354
355 Cy_SysLib_ExitCriticalSection(interruptState);
356 }
357 if (retVal == CY_SYSPM_SUCCESS)
358 {
359 /* Call the registered callback functions with the CY_SYSPM_AFTER_TRANSITION
360 * parameter
361 */
362 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
363 {
364 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_AFTER_TRANSITION);
365 }
366 }
367 else
368 {
369 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
370 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
371 * parameter
372 */
373 if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL)
374 {
375 (void) Cy_SysPm_ExecuteCallback((cy_en_syspm_callback_type_t)cbDeepSleepRootIdx, CY_SYSPM_CHECK_FAIL);
376 }
377 }
378 }
379 return retVal;
380 }
381
Cy_SysPm_SystemEnterHibernate(void)382 cy_en_syspm_status_t Cy_SysPm_SystemEnterHibernate(void)
383 {
384 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
385 uint32_t cbHibernateRootIdx = (uint32_t) CY_SYSPM_HIBERNATE;
386 /* Call the registered callback functions with the
387 * CY_SYSPM_CHECK_READY parameter
388 */
389 if (pmCallbackRoot[cbHibernateRootIdx] != NULL)
390 {
391 retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_READY);
392 }
393
394 /* The system can switch into Hibernate power mode only when
395 * all executed registered callback functions with CY_SYSPM_CHECK_READY
396 * parameter return CY_SYSPM_SUCCESS.
397 */
398 if(retVal == CY_SYSPM_SUCCESS)
399 {
400 /* Call registered callback functions with CY_SYSPM_BEFORE_TRANSITION
401 * parameter
402 */
403 (void) Cy_SysLib_EnterCriticalSection();
404 if (pmCallbackRoot[cbHibernateRootIdx] != NULL)
405 {
406 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_BEFORE_TRANSITION);
407 }
408
409 /* Preserve the token that will be retained through a wakeup sequence.
410 * This could be used by Cy_SysLib_GetResetReason() to differentiate
411 * Wakeup from a general reset event.
412 * Preserve the wakeup source(s) configuration.
413 */
414 SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & HIBERNATE_WAKEUP_MASK) | HIBERNATE_TOKEN;
415
416 /* Disable overriding by the peripherals the next pin-freeze command */
417 SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
418
419 /* The second write causes freezing of I/O cells to save the I/O-cell state */
420 SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
421
422 /* Third write cause system to enter Hibernate */
423 SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE;
424
425 /* Read register to make sure it is settled */
426 (void) SRSS_PWR_HIBERNATE;
427
428 /* Wait for transition */
429 __WFI();
430
431 /* The callback function calls with the CY_SYSPM_AFTER_TRANSITION
432 * parameter in the Hibernate power mode are not applicable as system
433 * wake-up was made on system reboot.
434 */
435
436 /* A wakeup from Hibernate is performed by toggling of the wakeup
437 * pins, or WDT matches, or Backup domain alarm expires. This depends on
438 * what item is configured in the Hibernate register. After a wakeup
439 * event, a normal Boot procedure occurs.
440 * There is no need to exit from the critical section.
441 */
442 }
443 else
444 {
445 /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
446 * undo everything done in the callback with the CY_SYSPM_CHECK_READY
447 * parameter. The return value should be CY_SYSPM_SUCCESS.
448 */
449 (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_FAIL);
450 retVal = CY_SYSPM_FAIL;
451 }
452 return retVal;
453 }
454
Cy_SysPm_SystemSetMinRegulatorCurrent(void)455 cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void)
456 {
457 cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED;
458
459 /* Check if the power circuits are ready to enter into regulator minimum
460 * current mode
461 */
462 if (Cy_SysPm_IsLpmReady())
463 {
464 SRSS_PWR_CTL2 |= (SRSS_PWR_CTL2_BGREF_LPMODE_Msk);
465
466 /* This wait time allows the circuits to remove their dependence on
467 * the Active mode circuits, such as active Reference
468 */
469 Cy_SysLib_DelayUs(SET_MIN_CURRENT_MODE_DELAY_US);
470
471 retVal = CY_SYSPM_SUCCESS;
472 }
473
474 return retVal;
475 }
476
Cy_SysPm_SystemSetNormalRegulatorCurrent(void)477 cy_en_syspm_status_t Cy_SysPm_SystemSetNormalRegulatorCurrent(void)
478 {
479 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
480
481 /* Disable the low-power for Bandgap reference circuit */
482 SRSS_PWR_CTL2 &= (uint32_t) ~SRSS_PWR_CTL2_BGREF_LPMODE_Msk;
483
484 /* This wait time allows setting active Reference */
485 Cy_SysLib_DelayUs(ACT_REF_SETTLE_DELAY_US);
486
487 retVal= CY_SYSPM_SUCCESS;
488
489 return retVal;
490 }
491
Cy_SysPm_IsBgRefCtrl(void)492 bool Cy_SysPm_IsBgRefCtrl(void)
493 {
494 return (0U != _FLD2VAL(SRSS_PWR_CTL2_BGREF_LPMODE, SRSS_PWR_CTL2));
495 }
496
Cy_SysPm_BgRefCtrl(bool enable)497 void Cy_SysPm_BgRefCtrl(bool enable)
498 {
499 if(enable)
500 {
501 SRSS_PWR_CTL2 |= (uint32_t) SRSS_PWR_CTL2_BGREF_LPMODE_Msk;
502 }
503 else
504 {
505 SRSS_PWR_CTL2 &= (uint32_t) ~SRSS_PWR_CTL2_BGREF_LPMODE_Msk;
506 }
507 }
508
Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode)509 cy_en_syspm_status_t Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode)
510 {
511 CY_ASSERT_L3(CY_SYSPM_IS_LDO_MODE_VALID(mode));
512
513 cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED;
514
515 switch (mode)
516 {
517 case CY_SYSPM_LDO_MODE_NORMAL:
518 {
519 retVal = Cy_SysPm_SystemSetNormalRegulatorCurrent();
520 }
521 break;
522
523 case CY_SYSPM_LDO_MODE_MIN:
524 {
525 retVal = Cy_SysPm_SystemSetMinRegulatorCurrent();
526 }
527 break;
528
529 case CY_SYSPM_LDO_MODE_DISABLED:
530 {
531 /* Disable the LDO, Deep Sleep, nWell, and Retention regulators */
532 SRSS_PWR_CTL2 |= (_VAL2FLD(SRSS_PWR_CTL2_DPSLP_REG_DIS, 1U) |
533 _VAL2FLD(SRSS_PWR_CTL2_LINREG_DIS, 1U));
534
535 retVal = CY_SYSPM_SUCCESS;
536 }
537 break;
538
539 default:
540 retVal = CY_SYSPM_FAIL;
541 break;
542 }
543
544 return retVal;
545 }
546
Cy_SysPm_LdoGetMode(void)547 cy_en_syspm_ldo_mode_t Cy_SysPm_LdoGetMode(void)
548 {
549 cy_en_syspm_ldo_mode_t retVal;
550
551 if (!Cy_SysPm_LdoIsEnabled())
552 {
553 retVal = CY_SYSPM_LDO_MODE_DISABLED;
554 }
555 else if (Cy_SysPm_SystemIsMinRegulatorCurrentSet())
556 {
557 retVal = CY_SYSPM_LDO_MODE_MIN;
558 }
559 else
560 {
561 retVal = CY_SYSPM_LDO_MODE_NORMAL;
562 }
563
564 return retVal;
565 }
566
Cy_SysPm_LdoIsEnabled(void)567 bool Cy_SysPm_LdoIsEnabled(void)
568 {
569 return ((0U != _FLD2VAL(SRSS_PWR_CTL2_LINREG_DIS, SRSS_PWR_CTL2)) ? false : true);
570 }
571
572
Cy_SysPm_CpuSleepOnExit(bool enable)573 void Cy_SysPm_CpuSleepOnExit(bool enable)
574 {
575 if(enable)
576 {
577 /* Enable sleep-on-exit feature */
578 SCB_SCR |= SCB_SCR_SLEEPONEXIT_Msk;
579 }
580 else
581 {
582 /* Disable sleep-on-exit feature */
583 SCB_SCR &= (uint32_t) ~(SCB_SCR_SLEEPONEXIT_Msk);
584 }
585 }
586
Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource)587 void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource)
588 {
589 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource));
590
591 uint32_t polarityMask = 0U;
592
593 if (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, wakeupSource))
594 {
595 /* Reconfigure the wakeup pins and LPComp polarity based on the input */
596 if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK))
597 {
598 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK;
599 }
600
601 if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK))
602 {
603 polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK;
604 }
605
606 if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_PIN0_MASK))
607 {
608 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK;
609 }
610
611 if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_PIN1_MASK))
612 {
613 polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK;
614 }
615 }
616
617 SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & (uint32_t) ~polarityMask) | wakeupSource;
618
619 /* Read register to make sure it is settled */
620 (void) SRSS_PWR_HIBERNATE;
621 }
622
Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource)623 void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource)
624 {
625 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource));
626
627 uint32_t clearWakeupSourceMask = wakeupSource & (uint32_t) ~SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk;
628
629 if (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, wakeupSource))
630 {
631 /* Clear the high active level of the requested sources */
632 if ((uint32_t) CY_SYSPM_HIBERNATE_LPCOMP0_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_LPCOMP0_HIGH))
633 {
634 clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK;
635 }
636
637 if ((uint32_t) CY_SYSPM_HIBERNATE_LPCOMP1_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_LPCOMP1_HIGH))
638 {
639 clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK;
640 }
641
642 if ((uint32_t) CY_SYSPM_HIBERNATE_PIN0_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_PIN0_HIGH))
643 {
644 clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK;
645 }
646
647 if ((uint32_t) CY_SYSPM_HIBERNATE_PIN1_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_PIN1_HIGH))
648 {
649 clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK;
650 }
651 }
652
653 SRSS_PWR_HIBERNATE &= (uint32_t) ~clearWakeupSourceMask;
654
655 /* Read register to make sure it is settled */
656 (void) SRSS_PWR_HIBERNATE;
657 }
658
Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t * handler)659 bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t* handler)
660 {
661 bool retVal = false;
662
663 /* Verify the input parameters. */
664 if ((handler != NULL) && (handler->callbackParams != NULL) && (handler->callback != NULL))
665 {
666 uint32_t callbackRootIdx = (uint32_t) handler->type;
667
668 /* If the callback list is not empty. */
669 if (pmCallbackRoot[callbackRootIdx] != NULL)
670 {
671 cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx];
672 cy_stc_syspm_callback_t* insertPos = curCallback;
673
674 /* Find the callback after which the new callback is to be
675 * inserted. Ensure the given callback has not been registered.
676 */
677 while ((NULL != curCallback->nextItm) && (curCallback != handler))
678 {
679 curCallback = curCallback->nextItm;
680 /* Callbacks with the same order value are stored in the order
681 * they are registered.
682 */
683 if (curCallback->order <= handler->order)
684 {
685 insertPos = curCallback;
686 }
687 }
688 /* If the callback has not been registered. */
689 if (curCallback != handler)
690 {
691 /* If the callback is to be inserted at the beginning of the list. */
692 if ((insertPos->prevItm == NULL) && (handler->order < insertPos->order))
693 {
694 handler->nextItm = insertPos;
695 handler->prevItm = NULL;
696 handler->nextItm->prevItm = handler;
697 pmCallbackRoot[callbackRootIdx] = handler;
698 }
699 else
700 {
701 handler->nextItm = insertPos->nextItm;
702 handler->prevItm = insertPos;
703
704 /* If the callback is not inserted at the end of the list. */
705 if (handler->nextItm != NULL)
706 {
707 handler->nextItm->prevItm = handler;
708 }
709 insertPos->nextItm = handler;
710 }
711 retVal = true;
712 }
713 }
714 else
715 {
716 /* The callback list is empty. */
717 pmCallbackRoot[callbackRootIdx] = handler;
718 handler->nextItm = NULL;
719 handler->prevItm = NULL;
720 retVal = true;
721 }
722 }
723 return retVal;
724 }
725
Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const * handler)726 bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler)
727 {
728 bool retVal = false;
729
730 if (handler != NULL)
731 {
732 uint32_t callbackRootIdx = (uint32_t) handler->type;
733 cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx];
734
735 /* Search requested callback item in the linked list */
736 while (curCallback != NULL)
737 {
738 /* Requested callback is found */
739 if (curCallback == handler)
740 {
741 retVal = true;
742 break;
743 }
744
745 /* Go to next callback item in the linked list */
746 curCallback = curCallback->nextItm;
747 }
748
749 if (retVal)
750 {
751 /* Requested callback is first in the list */
752 if (pmCallbackRoot[callbackRootIdx] == handler)
753 {
754 /* Check whether this the only callback registered */
755 if (pmCallbackRoot[callbackRootIdx]->nextItm != NULL)
756 {
757 pmCallbackRoot[callbackRootIdx] = pmCallbackRoot[callbackRootIdx]->nextItm;
758 pmCallbackRoot[callbackRootIdx]->prevItm = NULL;
759 }
760 else
761 {
762 /* We had only one callback */
763 pmCallbackRoot[callbackRootIdx] = NULL;
764 }
765 }
766 else
767 {
768 /* Update links of related to unregistered callback items */
769 curCallback->prevItm->nextItm = curCallback->nextItm;
770
771 if (curCallback->nextItm != NULL)
772 {
773 curCallback->nextItm->prevItm = curCallback->prevItm;
774 }
775 }
776 }
777 }
778
779 return retVal;
780 }
781
Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type,cy_en_syspm_callback_mode_t mode)782 cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, cy_en_syspm_callback_mode_t mode)
783 {
784 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_TYPE_VALID(type));
785 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_MODE_VALID(mode));
786
787 static cy_stc_syspm_callback_t* lastExecutedCallback = NULL;
788 cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
789 cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[(uint32_t) type];
790 cy_stc_syspm_callback_params_t curParams;
791
792 if ((mode == CY_SYSPM_BEFORE_TRANSITION) || (mode == CY_SYSPM_CHECK_READY))
793 {
794 /* Execute registered callbacks with order from first registered to the
795 * last registered. Stop executing if CY_SYSPM_FAIL was returned in
796 * CY_SYSPM_CHECK_READY mode
797 */
798 while ((curCallback != NULL) && ((retVal != CY_SYSPM_FAIL) || (mode != CY_SYSPM_CHECK_READY)))
799 {
800 /* The modes defined in the .skipMode element are not executed */
801 if (0UL == ((uint32_t) mode & curCallback->skipMode))
802 {
803 /* Update elements for local callback parameter values */
804 curParams.base = curCallback->callbackParams->base;
805 curParams.context = curCallback->callbackParams->context;
806
807 retVal = curCallback->callback(&curParams, mode);
808
809 /* Update callback pointer with value of executed callback.
810 * Such update is required to execute further callbacks in
811 * backward order after exit from LP mode or to undo
812 * configuration after callback returned fail: from last called
813 * to first registered.
814 */
815 lastExecutedCallback = curCallback;
816 }
817 curCallback = curCallback->nextItm;
818 }
819
820 if (mode == CY_SYSPM_CHECK_READY)
821 {
822 /* Update the pointer to the failed callback with the result of the callback execution.
823 * If the callback fails, the value of the pointer will be updated
824 * with the address of the callback which returned CY_SYSPM_FAIL, else,
825 * it will be updated with NULL.
826 */
827 if(retVal == CY_SYSPM_FAIL)
828 {
829 failedCallback[(uint32_t) type] = lastExecutedCallback;
830 }
831 else
832 {
833 failedCallback[(uint32_t) type] = NULL;
834 }
835 }
836 }
837 else
838 {
839 /* Execute registered callbacks with order from lastCallback or last
840 * executed to the first registered callback. Such a flow is required if
841 * a previous callback function returned CY_SYSPM_FAIL or a previous
842 * callback mode was CY_SYSPM_BEFORE_TRANSITION. Such an order is
843 * required to undo configurations in correct backward order.
844 */
845 if (mode != CY_SYSPM_CHECK_FAIL)
846 {
847 while (curCallback->nextItm != NULL)
848 {
849 curCallback = curCallback->nextItm;
850 }
851 }
852 else
853 {
854 /* Skip last executed callback that returns CY_SYSPM_FAIL, as this
855 * callback already knows that it failed.
856 */
857 curCallback = lastExecutedCallback;
858
859 if (curCallback != NULL)
860 {
861 curCallback = curCallback->prevItm;
862 }
863 }
864
865 /* Execute callback functions with required type and mode */
866 while (curCallback != NULL)
867 {
868 /* The modes defined in the .skipMode element are not executed */
869 if (0UL == ((uint32_t) mode & curCallback->skipMode))
870 {
871 /* Update elements for local callback parameter values */
872 curParams.base = curCallback->callbackParams->base;
873 curParams.context = curCallback->callbackParams->context;
874
875 retVal = curCallback->callback(&curParams, mode);
876 }
877 curCallback = curCallback->prevItm;
878 }
879 }
880
881 return retVal;
882 }
883
Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t type)884 cy_stc_syspm_callback_t* Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t type)
885 {
886 return failedCallback[(uint32_t) type];
887 }
888
889 /*******************************************************************************
890 * Function Name: Cy_SysPm_IoFreeze
891 ****************************************************************************//**
892 *
893 * Freezes IOs.
894 *
895 * Freezes the IO cells directly to save the IO-cell state on a wakeup from the
896 * Hibernate. Do not call this function before entering the
897 * Hibernate mode, because Cy_SysPm_Hibernate() function freezes the IO cells.
898 *
899 ******************************************************************************/
Cy_SysPm_IoFreeze(void)900 void Cy_SysPm_IoFreeze(void)
901 {
902 uint32_t interruptState;
903 uint32_t regValue;
904
905 interruptState = Cy_SysLib_EnterCriticalSection();
906
907 /* Check the FREEZE state to avoid a recurrent IO-cells freeze attempt,
908 * because the second call to this function will cause an accidental switch
909 * to the hibernate mode (the system will enter the hibernate mode immediately
910 * after writing to the hibernate bit because both UNLOCK and FREEZE were set
911 * correctly in the previous call to this function).
912 */
913 if(!Cy_SysPm_IoIsFrozen())
914 {
915 /* Clear the unlock field for correct freeze of the IO cells */
916 SRSS_PWR_HIBERNATE = _CLR_SET_FLD32U((SRSS_PWR_HIBERNATE), SRSS_PWR_HIBERNATE_UNLOCK, 0u);
917
918 /* Disable overriding by the peripherals the next pin-freeze command */
919 SRSS_PWR_HIBERNATE |= CY_SYSPM_PWR_HIBERNATE_UNLOCK |
920 _VAL2FLD(SRSS_PWR_HIBERNATE_FREEZE, 1u) |
921 _VAL2FLD(SRSS_PWR_HIBERNATE_HIBERNATE, 1u);
922
923 /* If Read is after Write, read this register two times to delay
924 * enough time for internal settling.
925 */
926 (void) SRSS_PWR_HIBERNATE;
927 (void) SRSS_PWR_HIBERNATE;
928
929 /* The second Write causes freeze of IO cells to save the IO-cell state */
930 regValue = SRSS_PWR_HIBERNATE;
931 SRSS_PWR_HIBERNATE = regValue;
932 }
933 Cy_SysLib_ExitCriticalSection(interruptState);
934 }
935
Cy_SysPm_IoUnfreeze(void)936 void Cy_SysPm_IoUnfreeze(void)
937 {
938 uint32_t interruptState;
939 interruptState = Cy_SysLib_EnterCriticalSection();
940
941 /* Preserve the last reset reason and wakeup polarity. Then, unfreeze I/O:
942 * write PWR_HIBERNATE.FREEZE=0, .UNLOCK=0x3A, .HIBERANTE=0
943 */
944 SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & HIBERNATE_RETAIN_STATUS_MASK) | HIBERNATE_UNLOCK_VAL;
945
946 /* Lock the Hibernate mode:
947 * write PWR_HIBERNATE.HIBERNATE=0, UNLOCK=0x00, HIBERANTE=0
948 */
949 SRSS_PWR_HIBERNATE &= HIBERNATE_RETAIN_STATUS_MASK;
950
951 /* Read register to make sure it is settled */
952 (void) SRSS_PWR_HIBERNATE;
953
954 Cy_SysLib_ExitCriticalSection(interruptState);
955 }
956
Cy_SysPm_IoIsFrozen(void)957 bool Cy_SysPm_IoIsFrozen(void)
958 {
959 return (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_FREEZE, SRSS_PWR_HIBERNATE));
960 }
961
Cy_SysPm_CpuSendWakeupEvent(void)962 void Cy_SysPm_CpuSendWakeupEvent(void)
963 {
964 __SEV();
965 }
966
Cy_SysPm_IsLpmReady(void)967 bool Cy_SysPm_IsLpmReady(void)
968 {
969 return (_FLD2BOOL(SRSS_PWR_CTL_LPM_READY, SRSS_PWR_CTL)? true : false);
970 }
971
Cy_SysPm_BackupSetSupply(cy_en_syspm_vddbackup_control_t vddBackControl)972 void Cy_SysPm_BackupSetSupply(cy_en_syspm_vddbackup_control_t vddBackControl)
973 {
974 CY_UNUSED_PARAMETER(vddBackControl);
975
976 #if (SRSS_BACKUP_VBCK_PRESENT)
977 CY_ASSERT_L3(CY_SYSPM_IS_VDDBACKUP_VALID(vddBackControl));
978
979 BACKUP_CTL = _CLR_SET_FLD32U((BACKUP_CTL), BACKUP_CTL_VDDBAK_CTL, (uint32_t) vddBackControl);
980 #endif
981 }
982
983
Cy_SysPm_BackupGetSupply(void)984 cy_en_syspm_vddbackup_control_t Cy_SysPm_BackupGetSupply(void)
985 {
986 #if (SRSS_BACKUP_VBCK_PRESENT)
987 uint32_t retVal;
988 retVal = _FLD2VAL(BACKUP_CTL_VDDBAK_CTL, BACKUP_CTL);
989
990 return ((cy_en_syspm_vddbackup_control_t) retVal);
991 #else
992 return (CY_SYSPM_VDDBACKUP_DEFAULT);
993 #endif
994 }
995
996
Cy_SysPm_BackupEnableVoltageMeasurement(void)997 void Cy_SysPm_BackupEnableVoltageMeasurement(void)
998 {
999 #if (SRSS_BACKUP_VBCK_PRESENT)
1000 BACKUP_CTL |= BACKUP_CTL_VBACKUP_MEAS_Msk;
1001 #endif
1002 }
1003
1004
Cy_SysPm_BackupDisableVoltageMeasurement(void)1005 void Cy_SysPm_BackupDisableVoltageMeasurement(void)
1006 {
1007 #if (SRSS_BACKUP_VBCK_PRESENT)
1008 BACKUP_CTL &= ((uint32_t) ~BACKUP_CTL_VBACKUP_MEAS_Msk);
1009 #endif
1010 }
1011
1012
Cy_SysPm_BackupSuperCapCharge(cy_en_syspm_sc_charge_key_t key)1013 void Cy_SysPm_BackupSuperCapCharge(cy_en_syspm_sc_charge_key_t key)
1014 {
1015 CY_UNUSED_PARAMETER(key);
1016
1017 #if (SRSS_BACKUP_VBCK_PRESENT)
1018 CY_ASSERT_L3(CY_SYSPM_IS_SC_CHARGE_KEY_VALID(key));
1019
1020 if(key == CY_SYSPM_SC_CHARGE_ENABLE)
1021 {
1022 BACKUP_CTL = _CLR_SET_FLD32U((BACKUP_CTL), BACKUP_CTL_EN_CHARGE_KEY, (uint32_t) CY_SYSPM_SC_CHARGE_ENABLE);
1023 }
1024 else
1025 {
1026 BACKUP_CTL &= ((uint32_t) ~BACKUP_CTL_EN_CHARGE_KEY_Msk);
1027 }
1028 #endif
1029 }
1030
Cy_SysPm_BackupWordStore(uint32_t wordIndex,uint32_t * wordSrcPointer,uint32_t wordSize)1031 void Cy_SysPm_BackupWordStore(uint32_t wordIndex, uint32_t *wordSrcPointer, uint32_t wordSize)
1032 {
1033 CY_ASSERT_L3(CY_SYSPM_IS_WORD_INDEX_VALID(wordIndex));
1034 CY_ASSERT_L3(CY_SYSPM_IS_WORD_SIZE_VALID(wordSize + wordIndex));
1035
1036 while(wordSize != 0UL)
1037 {
1038 BACKUP_BREG[wordIndex] = *wordSrcPointer;
1039
1040 wordIndex++;
1041 wordSrcPointer++;
1042 wordSize--;
1043 }
1044 }
1045
Cy_SysPm_BackupWordReStore(uint32_t wordIndex,uint32_t * wordDstPointer,uint32_t wordSize)1046 void Cy_SysPm_BackupWordReStore(uint32_t wordIndex, uint32_t *wordDstPointer, uint32_t wordSize)
1047 {
1048 CY_ASSERT_L3(CY_SYSPM_IS_WORD_INDEX_VALID(wordIndex));
1049 CY_ASSERT_L3(CY_SYSPM_IS_WORD_SIZE_VALID(wordSize + wordIndex));
1050
1051 while(wordSize != 0UL)
1052 {
1053 *wordDstPointer = BACKUP_BREG[wordIndex];
1054
1055 wordIndex++;
1056 wordDstPointer++;
1057 wordSize--;
1058 }
1059 }
1060
Cy_SysPm_SetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum,uint32_t sramMacroNum,cy_en_syspm_sram_pwr_mode_t sramPwrMode)1061 cy_en_syspm_status_t Cy_SysPm_SetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum, uint32_t sramMacroNum, cy_en_syspm_sram_pwr_mode_t sramPwrMode)
1062 {
1063 cy_en_syspm_status_t status = CY_SYSPM_BAD_PARAM;
1064
1065 CY_ASSERT_L1( sramNum < CPUSS_SRAM_COUNT );
1066
1067 if(sramNum == CY_SYSPM_SRAM0_MEMORY)
1068 {
1069 CY_ASSERT_L1( sramMacroNum < CPUSS_RAMC0_MACRO_NR );
1070 if (sramMacroNum < CPUSS_RAMC0_MACRO_NR)
1071 {
1072 CPUSS_RAM0_PWR_MACRO_CTL(sramMacroNum) = _VAL2FLD(CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY) |
1073 _VAL2FLD(CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE, sramPwrMode);
1074 status = CY_SYSPM_SUCCESS;
1075 }
1076 }
1077 else if(sramNum == CY_SYSPM_SRAM1_MEMORY)
1078 {
1079 CY_ASSERT_L1( CPUSS_RAMC1_PRESENT );
1080 CY_ASSERT_L1( sramMacroNum == 0UL );
1081
1082 CPUSS_RAM1_PWR_CTL = _VAL2FLD(CPUSS_RAM1_PWR_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY) |
1083 _VAL2FLD(CPUSS_RAM1_PWR_CTL_PWR_MODE, sramPwrMode);
1084 status = CY_SYSPM_SUCCESS;
1085 }
1086 else if(sramNum == CY_SYSPM_SRAM2_MEMORY)
1087 {
1088 CY_ASSERT_L1( CPUSS_RAMC2_PRESENT );
1089 CY_ASSERT_L1( sramMacroNum == 0UL );
1090
1091 CPUSS_RAM2_PWR_CTL = _VAL2FLD(CPUSS_RAM2_PWR_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY) |
1092 _VAL2FLD(CPUSS_RAM2_PWR_CTL_PWR_MODE, sramPwrMode);
1093 status = CY_SYSPM_SUCCESS;
1094 }
1095 else
1096 {
1097 /* Invalid SRAM Number */
1098 }
1099
1100 return status;
1101 }
1102
1103
Cy_SysPm_GetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum,uint32_t sramMacroNum)1104 cy_en_syspm_sram_pwr_mode_t Cy_SysPm_GetSRAMMacroPwrMode(cy_en_syspm_sram_index_t sramNum, uint32_t sramMacroNum)
1105 {
1106 uint32_t retVal = (uint32_t)CY_SYSPM_SRAM_PWR_MODE_INVALID;
1107
1108 CY_ASSERT_L1( sramNum < CPUSS_SRAM_COUNT );
1109
1110 if(sramNum == CY_SYSPM_SRAM0_MEMORY)
1111 {
1112 CY_ASSERT_L1( sramMacroNum < CPUSS_RAMC0_MACRO_NR );
1113 if (sramMacroNum < CPUSS_RAMC0_MACRO_NR)
1114 {
1115 retVal = _FLD2VAL(CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE, CPUSS_RAM0_PWR_MACRO_CTL(sramMacroNum));
1116 }
1117 }
1118 else if(sramNum == CY_SYSPM_SRAM1_MEMORY)
1119 {
1120 CY_ASSERT_L1( sramMacroNum == 0UL );
1121 retVal = _FLD2VAL(CPUSS_RAM1_PWR_CTL_PWR_MODE, CPUSS_RAM1_PWR_CTL);
1122 }
1123 else if(sramNum == CY_SYSPM_SRAM2_MEMORY)
1124 {
1125 CY_ASSERT_L1( sramMacroNum == 0UL );
1126 retVal = _FLD2VAL(CPUSS_RAM2_PWR_CTL_PWR_MODE, CPUSS_RAM2_PWR_CTL);
1127 }
1128 else
1129 {
1130 /* Invalid SRAM Number */
1131 }
1132 return (cy_en_syspm_sram_pwr_mode_t)retVal;
1133 }
1134
1135
Cy_SysPm_SetSRAMPwrMode(cy_en_syspm_sram_index_t sramNum,cy_en_syspm_sram_pwr_mode_t sramPwrMode)1136 cy_en_syspm_status_t Cy_SysPm_SetSRAMPwrMode(cy_en_syspm_sram_index_t sramNum, cy_en_syspm_sram_pwr_mode_t sramPwrMode)
1137 {
1138 uint32 idx;
1139
1140 cy_en_syspm_status_t status = CY_SYSPM_BAD_PARAM;
1141 CY_ASSERT_L1( sramNum < CPUSS_SRAM_COUNT );
1142
1143 if(sramNum == CY_SYSPM_SRAM0_MEMORY)
1144 {
1145 for(idx = 0UL; idx < CPUSS_RAMC0_MACRO_NR; idx++)
1146 {
1147 CPUSS_RAM0_PWR_MACRO_CTL(idx) = _VAL2FLD(CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY) |
1148 _VAL2FLD(CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE, sramPwrMode);
1149 }
1150 status = CY_SYSPM_SUCCESS;
1151 }
1152 else if(sramNum == CY_SYSPM_SRAM1_MEMORY)
1153 {
1154 CY_ASSERT_L1( CPUSS_RAMC1_PRESENT );
1155 CPUSS_RAM1_PWR_CTL = _VAL2FLD(CPUSS_RAM1_PWR_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY) |
1156 _VAL2FLD(CPUSS_RAM1_PWR_CTL_PWR_MODE, sramPwrMode);
1157 status = CY_SYSPM_SUCCESS;
1158
1159 }
1160 else if(sramNum == CY_SYSPM_SRAM2_MEMORY)
1161 {
1162 CY_ASSERT_L1( CPUSS_RAMC2_PRESENT );
1163 CPUSS_RAM2_PWR_CTL = _VAL2FLD(CPUSS_RAM2_PWR_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY) |
1164 _VAL2FLD(CPUSS_RAM2_PWR_CTL_PWR_MODE, sramPwrMode);
1165 status = CY_SYSPM_SUCCESS;
1166
1167 }
1168 else
1169 {
1170 /* Invalid SRAM Number */
1171 }
1172
1173 return status;
1174 }
1175
1176
1177 /*******************************************************************************
1178 * Function Name: Cy_SysPm_ReadStatus
1179 ****************************************************************************//**
1180 *
1181 * Reads the status of the core(s).
1182 *
1183 * \return The current power mode. See \ref group_syspm_return_status.
1184 *
1185 *******************************************************************************/
Cy_SysPm_ReadStatus(void)1186 uint32_t Cy_SysPm_ReadStatus(void)
1187 {
1188 uint32_t interruptState;
1189 uint32_t pmStatus = 0u;
1190 interruptState = Cy_SysLib_EnterCriticalSection();
1191
1192 /* Check whether CM7_0 is in the deep sleep mode*/
1193 if((0u != _FLD2VAL(CPUSS_CM7_0_STATUS_SLEEPING, CPUSS_CM7_0_STATUS)) &&
1194 (0u != _FLD2VAL(CPUSS_CM7_0_STATUS_SLEEPDEEP, CPUSS_CM7_0_STATUS)))
1195 {
1196 pmStatus |= CY_SYSPM_STATUS_CM7_0_DEEPSLEEP;
1197 }
1198 /* Check whether CM7_0 is in the sleep mode*/
1199 else if(0u != _FLD2VAL(CPUSS_CM7_0_STATUS_SLEEPING, CPUSS_CM7_0_STATUS))
1200 {
1201 pmStatus |= CY_SYSPM_STATUS_CM7_0_SLEEP;
1202 }
1203 else
1204 {
1205 pmStatus |= CY_SYSPM_STATUS_CM7_0_ACTIVE;
1206 }
1207
1208 /* Check whether CM7_1 is in the deep sleep mode*/
1209 if((0u != _FLD2VAL(CPUSS_CM7_1_STATUS_SLEEPING, CPUSS_CM7_1_STATUS)) &&
1210 (0u != _FLD2VAL(CPUSS_CM7_1_STATUS_SLEEPDEEP, CPUSS_CM7_1_STATUS)))
1211 {
1212 pmStatus |= CY_SYSPM_STATUS_CM7_1_DEEPSLEEP;
1213 }
1214 /* Check whether CM7_1 is in the sleep mode*/
1215 else if(0u != _FLD2VAL(CPUSS_CM7_1_STATUS_SLEEPING, CPUSS_CM7_1_STATUS))
1216 {
1217 pmStatus |= CY_SYSPM_STATUS_CM7_1_SLEEP;
1218 }
1219 else
1220 {
1221 pmStatus |= CY_SYSPM_STATUS_CM7_1_ACTIVE;
1222 }
1223
1224
1225 /* Check whether CM0p is in the deep sleep mode*/
1226 if((0u != _FLD2VAL(CPUSS_CM0_STATUS_SLEEPING, CPUSS_CM0_STATUS)) &&
1227 (0u != _FLD2VAL(CPUSS_CM0_STATUS_SLEEPDEEP, CPUSS_CM0_STATUS)))
1228 {
1229 pmStatus |= (uint32_t) CY_SYSPM_STATUS_CM0_DEEPSLEEP;
1230 }
1231 /* Check whether CM0p is in the sleep mode*/
1232 else if (0u != _FLD2VAL(CPUSS_CM0_STATUS_SLEEPING, CPUSS_CM0_STATUS))
1233 {
1234 pmStatus |= CY_SYSPM_STATUS_CM0_SLEEP;
1235 }
1236 else
1237 {
1238 pmStatus |= CY_SYSPM_STATUS_CM0_ACTIVE;
1239 }
1240
1241 /* Check whether the device is in LPACTIVE mode or not */
1242 if(Cy_SysPm_IsSystemLpActiveEnabled())
1243 {
1244 pmStatus |= CY_SYSPM_STATUS_SYSTEM_LOWPOWER;
1245 }
1246
1247 Cy_SysLib_ExitCriticalSection(interruptState);
1248
1249 return(pmStatus);
1250 }
1251
Cy_SysPm_Cm7IsActive(uint8_t core)1252 bool Cy_SysPm_Cm7IsActive(uint8_t core)
1253 {
1254 bool status = false;
1255
1256 if(core == CORE_CM7_0)
1257 {
1258 status = ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM7_0_ACTIVE) != 0u);
1259 }
1260 else if(core == CORE_CM7_1)
1261 {
1262 status = ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM7_1_ACTIVE) != 0u);
1263 }
1264 else
1265 {
1266 /* CM7 Not active */
1267 }
1268
1269 return status;
1270 }
1271
Cy_SysPm_Cm7IsSleep(uint8_t core)1272 bool Cy_SysPm_Cm7IsSleep(uint8_t core)
1273 {
1274 bool status = false;
1275
1276 if(core == CORE_CM7_0)
1277 {
1278 status = ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM7_0_SLEEP) != 0u);
1279 }
1280 else if(core == CORE_CM7_1)
1281 {
1282 status = ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM7_1_SLEEP) != 0u);
1283 }
1284 else
1285 {
1286 /* CM7 Not active */
1287 }
1288
1289 return status;
1290 }
1291
Cy_SysPm_Cm7IsDeepSleep(uint8_t core)1292 bool Cy_SysPm_Cm7IsDeepSleep(uint8_t core)
1293 {
1294 bool status = false;
1295
1296 if(core == CORE_CM7_0)
1297 {
1298 status = ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM7_0_DEEPSLEEP) != 0u);
1299 }
1300 else if(core == CORE_CM7_1)
1301 {
1302 status = ((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM7_1_DEEPSLEEP) != 0u);
1303 }
1304 else
1305 {
1306 /* CM7 Not active */
1307 }
1308
1309 return status;
1310 }
1311
1312
Cy_SysPm_Cm7IsLowPower(uint8_t core)1313 bool Cy_SysPm_Cm7IsLowPower(uint8_t core)
1314 {
1315 bool status = false;
1316
1317 if(core == CORE_CM7_0)
1318 {
1319 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM7_0_LOWPOWER) != 0u);
1320 }
1321 else if(core == CORE_CM7_1)
1322 {
1323 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM7_1_LOWPOWER) != 0u);
1324 }
1325 else
1326 {
1327 /* CM7 Not active */
1328 }
1329
1330 return status;
1331 }
1332
Cy_SysPm_Cm0IsActive(void)1333 bool Cy_SysPm_Cm0IsActive(void)
1334 {
1335 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_ACTIVE) != 0u);
1336 }
1337
1338
Cy_SysPm_Cm0IsLowPower(void)1339 bool Cy_SysPm_Cm0IsLowPower(void)
1340 {
1341 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_LOWPOWER) != 0u);
1342 }
1343
Cy_SysPm_Cm0IsSleep(void)1344 bool Cy_SysPm_Cm0IsSleep(void)
1345 {
1346 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_SLEEP) != 0u);
1347 }
1348
Cy_SysPm_Cm0IsDeepSleep(void)1349 bool Cy_SysPm_Cm0IsDeepSleep(void)
1350 {
1351 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_DEEPSLEEP) != 0u);
1352 }
1353
Cy_SysPm_IsSystemLp(void)1354 bool Cy_SysPm_IsSystemLp(void)
1355 {
1356 return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_LOWPOWER) != 0u);
1357 }
1358
1359
Cy_SysPm_PmicEnable(void)1360 void Cy_SysPm_PmicEnable(void)
1361 {
1362 if(CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
1363 {
1364 BACKUP_PMIC_CTL =
1365 _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) |
1366 _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1u) |
1367 _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN, 1u);
1368 }
1369 }
1370
1371
Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t polarity)1372 void Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t polarity)
1373 {
1374 if(CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
1375 {
1376 BACKUP_PMIC_CTL =
1377 (_VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) |
1378 _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_POLARITY, polarity)) &
1379 ((uint32_t) ~ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN, 1u));
1380 }
1381 }
1382
1383
Cy_SysPm_PmicAlwaysEnable(void)1384 void Cy_SysPm_PmicAlwaysEnable(void)
1385 {
1386 BACKUP_PMIC_CTL |= _VAL2FLD(BACKUP_PMIC_CTL_PMIC_ALWAYSEN, 1u);
1387 }
1388
1389
Cy_SysPm_PmicEnableOutput(void)1390 void Cy_SysPm_PmicEnableOutput(void)
1391 {
1392 if(CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
1393 {
1394 BACKUP_PMIC_CTL |=
1395 _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) | _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1u);
1396 }
1397 }
1398
1399
Cy_SysPm_PmicDisableOutput(void)1400 void Cy_SysPm_PmicDisableOutput(void)
1401 {
1402 if(CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL))
1403 {
1404 BACKUP_PMIC_CTL =
1405 (BACKUP_PMIC_CTL | _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY)) &
1406 ((uint32_t) ~ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1u));
1407 }
1408 }
1409
1410
Cy_SysPm_PmicLock(void)1411 void Cy_SysPm_PmicLock(void)
1412 {
1413 BACKUP_PMIC_CTL = _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_UNLOCK, 0u);
1414 }
1415
1416
Cy_SysPm_PmicUnlock(void)1417 void Cy_SysPm_PmicUnlock(void)
1418 {
1419 BACKUP_PMIC_CTL = _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY);
1420 }
1421
1422
Cy_SysPm_PmicIsEnabled(void)1423 bool Cy_SysPm_PmicIsEnabled(void)
1424 {
1425 return(0u != _FLD2VAL(BACKUP_PMIC_CTL_PMIC_EN, BACKUP_PMIC_CTL));
1426 }
1427
1428
Cy_SysPm_PmicIsOutputEnabled(void)1429 bool Cy_SysPm_PmicIsOutputEnabled(void)
1430 {
1431 return (0U != _FLD2VAL(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, BACKUP_PMIC_CTL));
1432 }
1433
1434
Cy_SysPm_PmicIsLocked(void)1435 bool Cy_SysPm_PmicIsLocked(void)
1436 {
1437 return((_FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL) == CY_SYSPM_PMIC_UNLOCK_KEY) ? false : true);
1438 }
1439
Cy_SysPm_OvdEnable(cy_en_syspm_ovd_sel_t ovdSel)1440 void Cy_SysPm_OvdEnable(cy_en_syspm_ovd_sel_t ovdSel)
1441 {
1442 switch(ovdSel)
1443 {
1444 case CY_SYSPM_OVD_ON_VDDD:
1445 SRSS_PWR_SSV_CTL |= SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk;
1446 break;
1447
1448 case CY_SYSPM_OVD_ON_VDDA:
1449 SRSS_PWR_SSV_CTL |= SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk;
1450 break;
1451
1452 case CY_SYSPM_OVD_ON_VCCD:
1453 SRSS_PWR_SSV_CTL |= SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk;
1454 break;
1455
1456 default:
1457 (void)SRSS_PWR_SSV_STATUS; /* To Fix Coverity */
1458 break;
1459 }
1460 }
1461
1462
Cy_SysPm_OvdDisable(cy_en_syspm_ovd_sel_t ovdSel)1463 void Cy_SysPm_OvdDisable(cy_en_syspm_ovd_sel_t ovdSel)
1464 {
1465 switch(ovdSel)
1466 {
1467 case CY_SYSPM_OVD_ON_VDDD:
1468 SRSS_PWR_SSV_CTL &= (uint32_t) ~SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk;
1469 break;
1470
1471 case CY_SYSPM_OVD_ON_VDDA:
1472 SRSS_PWR_SSV_CTL &= (uint32_t) ~SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk;
1473 break;
1474
1475 case CY_SYSPM_OVD_ON_VCCD:
1476 SRSS_PWR_SSV_CTL &= (uint32_t) ~SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk;
1477 break;
1478
1479 default:
1480 (void)SRSS_PWR_SSV_STATUS; /* To Fix Coverity */
1481 break;
1482 }
1483 }
1484
1485
Cy_SysPm_OvdVdddSelect(cy_en_syspm_ovd_vddd_sel_t ovdVdddSel)1486 void Cy_SysPm_OvdVdddSelect(cy_en_syspm_ovd_vddd_sel_t ovdVdddSel)
1487 {
1488 SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_OVDVDDD_VSEL, ovdVdddSel);
1489 }
1490
1491
Cy_SysPm_OvdVddaSelect(cy_en_syspm_ovd_vdda_sel_t ovdVddaSel)1492 void Cy_SysPm_OvdVddaSelect(cy_en_syspm_ovd_vdda_sel_t ovdVddaSel)
1493 {
1494 SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_OVDVDDA_VSEL, ovdVddaSel);
1495 }
1496
1497
Cy_SysPm_OvdActionSelect(cy_en_syspm_ovd_action_select_t ovdActionSelect)1498 void Cy_SysPm_OvdActionSelect(cy_en_syspm_ovd_action_select_t ovdActionSelect)
1499 {
1500 CY_ASSERT(CY_OVD_CHECK_ACTION_CFG(ovdActionSelect));
1501
1502 SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_OVDVDDA_ACTION, ovdActionSelect);
1503 }
1504
1505
Cy_SysPm_BodEnable(cy_en_syspm_bod_sel_t bodSel)1506 void Cy_SysPm_BodEnable(cy_en_syspm_bod_sel_t bodSel)
1507 {
1508 switch(bodSel)
1509 {
1510 case CY_SYSPM_BOD_ON_VDDD:
1511 SRSS_PWR_SSV_CTL |= SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Msk;
1512 break;
1513
1514 case CY_SYSPM_BOD_ON_VDDA:
1515 SRSS_PWR_SSV_CTL |= SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Msk;
1516 break;
1517
1518 case CY_SYSPM_BOD_ON_VCCD:
1519 SRSS_PWR_SSV_CTL |= SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Msk;
1520 break;
1521
1522 default:
1523 (void)SRSS_PWR_SSV_STATUS; /* To Fix Coverity */
1524 break;
1525 }
1526 }
1527
1528
Cy_SysPm_BodDisable(cy_en_syspm_bod_sel_t bodSel)1529 void Cy_SysPm_BodDisable(cy_en_syspm_bod_sel_t bodSel)
1530 {
1531 switch(bodSel)
1532 {
1533 case CY_SYSPM_BOD_ON_VDDD:
1534 SRSS_PWR_SSV_CTL &= (uint32_t) ~SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Msk;
1535 break;
1536
1537 case CY_SYSPM_BOD_ON_VDDA:
1538 SRSS_PWR_SSV_CTL &= (uint32_t) ~SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Msk;
1539 break;
1540
1541 case CY_SYSPM_BOD_ON_VCCD:
1542 SRSS_PWR_SSV_CTL &= (uint32_t) ~SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Msk;
1543 break;
1544
1545 default:
1546 (void)SRSS_PWR_SSV_STATUS; /* To Fix Coverity */
1547 break;
1548 }
1549 }
1550
1551
Cy_SysPm_BodVdddSelect(cy_en_syspm_bod_vddd_sel_t bodVdddSel)1552 void Cy_SysPm_BodVdddSelect(cy_en_syspm_bod_vddd_sel_t bodVdddSel)
1553 {
1554 SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_BODVDDD_VSEL, bodVdddSel);
1555 }
1556
1557
Cy_SysPm_BodVddaSelect(cy_en_syspm_bod_vdda_sel_t bodVddaSel)1558 void Cy_SysPm_BodVddaSelect(cy_en_syspm_bod_vdda_sel_t bodVddaSel)
1559 {
1560 SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_BODVDDA_VSEL, bodVddaSel);
1561 }
1562
1563
Cy_SysPm_BodActionSelect(cy_en_syspm_bod_action_select_t bodActionSelect)1564 void Cy_SysPm_BodActionSelect(cy_en_syspm_bod_action_select_t bodActionSelect)
1565 {
1566 CY_ASSERT(CY_BOD_CHECK_ACTION_CFG(bodActionSelect));
1567
1568 SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_BODVDDA_ACTION, bodActionSelect);
1569 }
1570
1571
Cy_SysPm_SupplySupervisionStatus(cy_en_syspm_supply_entity_select_t supplyEntitySelect)1572 bool Cy_SysPm_SupplySupervisionStatus(cy_en_syspm_supply_entity_select_t supplyEntitySelect)
1573 {
1574 bool returnStatus = false;
1575
1576 CY_ASSERT_L3(CY_OVD_CHECK_SUPPLY_ENTITY(supplyEntitySelect));
1577
1578 switch(supplyEntitySelect)
1579 {
1580 case CY_SYSPM_ENTITY_BOD_VDDD:
1581 returnStatus = (0u != _FLD2VAL(SRSS_PWR_SSV_STATUS_BODVDDD_OK, SRSS_PWR_SSV_STATUS));
1582 break;
1583
1584 case CY_SYSPM_ENTITY_BOD_VDDA:
1585 returnStatus = (0u != _FLD2VAL(SRSS_PWR_SSV_STATUS_BODVDDA_OK, SRSS_PWR_SSV_STATUS));
1586 break;
1587
1588 case CY_SYSPM_ENTITY_BOD_VCCD:
1589 returnStatus = (0u != _FLD2VAL(SRSS_PWR_SSV_STATUS_BODVCCD_OK, SRSS_PWR_SSV_STATUS));
1590 break;
1591
1592 case CY_SYSPM_ENTITY_OVD_VDDD:
1593 returnStatus = (0u != _FLD2VAL(SRSS_PWR_SSV_STATUS_OVDVDDD_OK, SRSS_PWR_SSV_STATUS));
1594 break;
1595
1596 case CY_SYSPM_ENTITY_OVD_VDDA:
1597 returnStatus = (0u != _FLD2VAL(SRSS_PWR_SSV_STATUS_OVDVDDA_OK, SRSS_PWR_SSV_STATUS));
1598 break;
1599
1600 case CY_SYSPM_ENTITY_OVD_VCCD:
1601 returnStatus = (0u != _FLD2VAL(SRSS_PWR_SSV_STATUS_OVDVCCD_OK, SRSS_PWR_SSV_STATUS));
1602 break;
1603
1604 default:
1605 (void)SRSS_PWR_SSV_STATUS; /* To Fix Coverity */
1606 break;
1607 }
1608
1609 return (returnStatus);
1610 }
1611
Cy_SysPm_SystemIsMinRegulatorCurrentSet(void)1612 bool Cy_SysPm_SystemIsMinRegulatorCurrentSet(void)
1613 {
1614 uint32_t regMask = Cy_SysPm_LdoIsEnabled() ? CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_LDO_MASK : CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_BUCK_MASK;
1615
1616 return ((SRSS_PWR_CTL & regMask) == regMask);
1617 }
1618
Cy_SysPm_LinearRegDisable(void)1619 void Cy_SysPm_LinearRegDisable(void)
1620 {
1621 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_LINREG_DIS_Msk;
1622 }
1623
Cy_SysPm_LinearRegEnable(void)1624 void Cy_SysPm_LinearRegEnable(void)
1625 {
1626 SRSS_PWR_CTL2 &= (uint32_t) ~SRSS_PWR_CTL2_LINREG_DIS_Msk;
1627 }
1628
Cy_SysPm_LinearRegGetStatus(void)1629 bool Cy_SysPm_LinearRegGetStatus(void)
1630 {
1631 return (_FLD2BOOL(SRSS_PWR_CTL2_LINREG_OK, SRSS_PWR_CTL2));
1632 }
1633
Cy_SysPm_DeepSleepRegDisable(void)1634 void Cy_SysPm_DeepSleepRegDisable(void)
1635 {
1636 SRSS_PWR_CTL2 |= SRSS_PWR_CTL2_DPSLP_REG_DIS_Msk;
1637 }
1638
Cy_SysPm_DeepSleepRegEnable(void)1639 void Cy_SysPm_DeepSleepRegEnable(void)
1640 {
1641 SRSS_PWR_CTL2 &= (uint32_t) ~SRSS_PWR_CTL2_DPSLP_REG_DIS_Msk;
1642 }
1643
Cy_SySPm_IsDeepSleepRegEnabled(void)1644 bool Cy_SySPm_IsDeepSleepRegEnabled(void)
1645 {
1646 return(0u == _FLD2VAL(SRSS_PWR_CTL2_DPSLP_REG_DIS, SRSS_PWR_CTL2));
1647 }
1648
Cy_SysPm_ReghcSelectMode(cy_en_syspm_reghc_mode_t mode)1649 void Cy_SysPm_ReghcSelectMode(cy_en_syspm_reghc_mode_t mode)
1650 {
1651 CY_REG32_CLR_SET(SRSS_PWR_REGHC_CTL, SRSS_PWR_REGHC_CTL_REGHC_MODE, mode);
1652 }
1653
Cy_SysPm_ReghcGetMode(void)1654 cy_en_syspm_reghc_mode_t Cy_SysPm_ReghcGetMode(void)
1655 {
1656 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_reghc_mode_t enum.');
1657 return (cy_en_syspm_reghc_mode_t)(_FLD2VAL(SRSS_PWR_REGHC_CTL_REGHC_MODE, SRSS_PWR_REGHC_CTL));
1658 }
1659
Cy_SysPm_ReghcSelectDriveOut(cy_en_syspm_reghc_drive_out_t drvOut)1660 void Cy_SysPm_ReghcSelectDriveOut(cy_en_syspm_reghc_drive_out_t drvOut)
1661 {
1662 CY_REG32_CLR_SET(SRSS_PWR_REGHC_CTL, SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT, drvOut);
1663 }
1664
Cy_SysPm_ReghcGetDriveOut(void)1665 cy_en_syspm_reghc_drive_out_t Cy_SysPm_ReghcGetDriveOut(void)
1666 {
1667 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_syspm_reghc_drive_out_t enum.');
1668 return (cy_en_syspm_reghc_drive_out_t)(_FLD2VAL(SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT, SRSS_PWR_REGHC_CTL));
1669 }
1670
Cy_SysPm_ReghcAdjustOutputVoltage(cy_en_syspm_reghc_vadj_t trim)1671 void Cy_SysPm_ReghcAdjustOutputVoltage(cy_en_syspm_reghc_vadj_t trim)
1672 {
1673 CY_REG32_CLR_SET(SRSS_PWR_REGHC_CTL, SRSS_PWR_REGHC_CTL_REGHC_VADJ, trim);
1674 }
1675
Cy_SysPm_ReghcDisableIntSupplyWhileExtActive(void)1676 void Cy_SysPm_ReghcDisableIntSupplyWhileExtActive(void)
1677 {
1678 SRSS_PWR_REGHC_CTL &= (uint32_t) ~SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Msk;
1679 }
1680
Cy_SysPm_ReghcEnableIntSupplyWhileExtActive(void)1681 void Cy_SysPm_ReghcEnableIntSupplyWhileExtActive(void)
1682 {
1683 SRSS_PWR_REGHC_CTL |= SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Msk;
1684 }
1685
1686
Cy_SysPm_ReghcDisablePmicEnableOutput(void)1687 void Cy_SysPm_ReghcDisablePmicEnableOutput(void)
1688 {
1689 SRSS_PWR_REGHC_CTL &= (uint32_t) ~SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Msk;
1690 SRSS_PWR_REGHC_CTL &= (uint32_t) ~SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Msk;
1691 }
1692
Cy_SysPm_ReghcEnablePmicEnableOutput(bool polarity)1693 void Cy_SysPm_ReghcEnablePmicEnableOutput(bool polarity)
1694 {
1695 SRSS_PWR_REGHC_CTL |= SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Msk;
1696
1697 if(polarity)
1698 {
1699 SRSS_PWR_REGHC_CTL |= SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Msk;
1700 }
1701 else
1702 {
1703 SRSS_PWR_REGHC_CTL &= (uint32_t) ~SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Msk;
1704 }
1705 }
1706
Cy_SysPm_ReghcEnablePmicStatusInput(bool polarity)1707 void Cy_SysPm_ReghcEnablePmicStatusInput(bool polarity)
1708 {
1709 SRSS_PWR_REGHC_CTL |= SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Msk;
1710
1711 if(polarity)
1712 {
1713 SRSS_PWR_REGHC_CTL |= SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Msk;
1714 }
1715 else
1716 {
1717 SRSS_PWR_REGHC_CTL &= (uint32_t) ~SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Msk;
1718 }
1719
1720 }
1721
Cy_SysPm_ReghcDisablePmicStatusInput(void)1722 void Cy_SysPm_ReghcDisablePmicStatusInput(void)
1723 {
1724 SRSS_PWR_REGHC_CTL &= (uint32_t) ~SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Msk;
1725 }
1726
Cy_SysPm_ReghcSetPmicStatusWaitTime(uint16_t waitTime)1727 void Cy_SysPm_ReghcSetPmicStatusWaitTime(uint16_t waitTime)
1728 {
1729 CY_REG32_CLR_SET(SRSS_PWR_REGHC_CTL, SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT, waitTime);
1730 }
1731
Cy_SysPm_ReghcIsConfigured(void)1732 bool Cy_SysPm_ReghcIsConfigured(void)
1733 {
1734 return (_FLD2BOOL(SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED, SRSS_PWR_REGHC_CTL));
1735 }
1736
Cy_SysPm_ReghcSetConfigured(void)1737 void Cy_SysPm_ReghcSetConfigured(void)
1738 {
1739 SRSS_PWR_REGHC_CTL |= SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED_Msk;
1740 }
1741
Cy_SysPm_ReghcDisable(void)1742 void Cy_SysPm_ReghcDisable(void)
1743 {
1744 SRSS_PWR_REGHC_CTL2 &= (uint32_t) ~SRSS_PWR_REGHC_CTL2_REGHC_EN_Msk;
1745 }
1746
Cy_SysPm_ReghcEnable(void)1747 void Cy_SysPm_ReghcEnable(void)
1748 {
1749 SRSS_PWR_REGHC_CTL2 |= SRSS_PWR_REGHC_CTL2_REGHC_EN_Msk;
1750 }
1751
Cy_SysPm_ReghcDisablePmicStatusTimeout(void)1752 void Cy_SysPm_ReghcDisablePmicStatusTimeout(void)
1753 {
1754 SRSS_PWR_REGHC_CTL2 &= (uint32_t) ~SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Msk;
1755 }
1756
Cy_SysPm_ReghcEnablePmicStatusTimeout(uint8_t timeout)1757 void Cy_SysPm_ReghcEnablePmicStatusTimeout(uint8_t timeout)
1758 {
1759 CY_REG32_CLR_SET(SRSS_PWR_REGHC_CTL2, SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT, timeout);
1760 }
1761
Cy_SysPm_ReghcIsEnabled(void)1762 bool Cy_SysPm_ReghcIsEnabled(void)
1763 {
1764 return (_FLD2BOOL(SRSS_PWR_REGHC_STATUS_REGHC_ENABLED, SRSS_PWR_REGHC_STATUS));
1765 }
1766
Cy_SysPm_ReghcIsStatusOk(void)1767 bool Cy_SysPm_ReghcIsStatusOk(void)
1768 {
1769 return (_FLD2BOOL(SRSS_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK, SRSS_PWR_REGHC_STATUS));
1770 }
1771
Cy_SysPm_ReghcIsSequencerBusy(void)1772 bool Cy_SysPm_ReghcIsSequencerBusy(void)
1773 {
1774 return (_FLD2BOOL(SRSS_PWR_REGHC_STATUS_REGHC_SEQ_BUSY, SRSS_PWR_REGHC_STATUS));
1775 }
1776
Cy_SysPm_ReghcDisableVAdj(void)1777 void Cy_SysPm_ReghcDisableVAdj(void)
1778 {
1779 SRSS_PWR_REGHC_CTL4 |= SRSS_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Msk;
1780 }
1781
Cy_SysPm_ReghcEnableVAdj(void)1782 void Cy_SysPm_ReghcEnableVAdj(void)
1783 {
1784 SRSS_PWR_REGHC_CTL4 &= (uint32_t) ~SRSS_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Msk;
1785 }
1786
Cy_SysPm_ReghcDisablePmicInDeepSleep(void)1787 void Cy_SysPm_ReghcDisablePmicInDeepSleep(void)
1788 {
1789 SRSS_PWR_REGHC_CTL4 &= (uint32_t) ~SRSS_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Msk;
1790 }
1791
Cy_SysPm_ReghcEnablePmicInDeepSleep(void)1792 void Cy_SysPm_ReghcEnablePmicInDeepSleep(void)
1793 {
1794 SRSS_PWR_REGHC_CTL4 |= SRSS_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Msk;
1795 }
1796
Cy_SysPm_ReghcIsOcdWithinLimits(void)1797 bool Cy_SysPm_ReghcIsOcdWithinLimits(void)
1798 {
1799 return (_FLD2BOOL(SRSS_PWR_REGHC_STATUS_REGHC_OCD_OK, SRSS_PWR_REGHC_STATUS));
1800 }
1801
Cy_SysPm_ReghcIsCircuitEnabledAndOperating(void)1802 bool Cy_SysPm_ReghcIsCircuitEnabledAndOperating(void)
1803 {
1804 return (_FLD2BOOL(SRSS_PWR_REGHC_STATUS_REGHC_CKT_OK, SRSS_PWR_REGHC_STATUS));
1805 }
1806
Cy_SysPm_ReghcConfigure(cy_en_syspm_reghc_mode_t mode,cy_en_syspm_reghc_vadj_t vadj)1807 cy_en_syspm_status_t Cy_SysPm_ReghcConfigure(cy_en_syspm_reghc_mode_t mode, cy_en_syspm_reghc_vadj_t vadj)
1808 {
1809 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
1810 uint32_t timeOut = REGHC_WAIT_DELAY_TRIES_US;
1811
1812 /* Current support is for External Transistor mode only */
1813 CY_ASSERT_L3(mode == CY_SYSPM_REGHC_MODE_TRANSISTOR);
1814
1815 /* a. Write PWR_REGHC_CTL.REGHC_MODE = 0 to configure the external transistor mode. */
1816 Cy_SysPm_ReghcSelectMode(mode);
1817
1818 /* b. Write PWR_REGHC_CTL.REGHC_TRANS_USE_OCD = 1 */
1819 //HW default is "1"
1820
1821 /* c. Write PWR_REGHC_CTL.REGHC_VADJ to the required feedback setting.*/
1822 Cy_SysPm_ReghcAdjustOutputVoltage(vadj);
1823
1824 /* d. Write PWR_REGHC_CTL.REGHC_CONFIGURED = 1. */
1825 Cy_SysPm_ReghcSetConfigured();
1826
1827 /* e. Execute the system call (LoadRegulatorTrims) to change internal regulator trims. */
1828 //HW takes care
1829
1830 /* f. Write PWR_REGHC_CTL2.REGHC_EN = 1. */
1831 Cy_SysPm_ReghcEnable();
1832
1833 /* g. Wait until PWR_REGHC_STATUS.REGHC_SEQ_BUSY = 0 and PWR_REGHC_STATUS.REGHC_ENABLED = 1.
1834 * This should occur within 15us.
1835 */
1836 while (((true == Cy_SysPm_ReghcIsSequencerBusy()) || (false == Cy_SysPm_ReghcIsEnabled())) && (0U != timeOut))
1837 {
1838 Cy_SysLib_DelayUs(1U);
1839 timeOut--;
1840 }
1841
1842 if (0U != timeOut)
1843 {
1844 retVal= CY_SYSPM_SUCCESS;
1845 }
1846
1847 return retVal;
1848 }
1849
Cy_SysPm_ReghcDeConfigure(void)1850 cy_en_syspm_status_t Cy_SysPm_ReghcDeConfigure(void)
1851 {
1852 cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT;
1853 uint32_t timeOut = REGHC_WAIT_DELAY_TRIES_US;
1854
1855 /* a. Write PWR_REGHC_CTL2.REGHC_EN = 0. */
1856 Cy_SysPm_ReghcDisable();
1857
1858 /* b. Wait until PWR_REGHC_STATUS.REGHC_SEQ_BUSY = 0 and PWR_REGHC_STATUS.REGHC_ENABLED = 0.
1859 * This should occur within 10 us.
1860 */
1861 while (((true == Cy_SysPm_ReghcIsSequencerBusy()) || (true == Cy_SysPm_ReghcIsEnabled())) && (0U != timeOut))
1862 {
1863 Cy_SysLib_DelayUs(1U);
1864 timeOut--;
1865 }
1866
1867 if (0U != timeOut)
1868 {
1869 retVal= CY_SYSPM_SUCCESS;
1870 }
1871
1872 return retVal;
1873 }
1874
1875 #endif /* (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3) */
1876
1877 /* [] END OF FILE */
1878
