1 /***************************************************************************//**
2 * \file cy_syslib.c
3 * \version 3.60
4 *
5 * Description:
6 * Provides system API implementation for the SysLib driver.
7 *
8 ********************************************************************************
9 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_device.h"
27
28 #if defined (CY_IP_M33SYSCPUSS) || defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS) || defined(CY_IP_M55APPCPUSS)
29
30 #include "cy_syslib.h"
31
32 #if defined (CY_IP_M33SYSCPUSS)
33 #include "cy_efuse.h"
34 #endif
35
36 #ifdef CY_IP_M4CPUSS
37 #include "cy_ipc_drv.h"
38 #endif
39 #if !defined(NDEBUG)
40 #include <string.h>
41 #endif /* NDEBUG */
42
43 #if defined (CY_DEVICE_SECURE)
44 #include "cy_pra.h"
45 #endif /* defined (CY_DEVICE_SECURE) */
46
47 #ifdef CY_IP_M4CPUSS
48 /* Flash wait states (ULP mode at 0.9v) */
49 #define CY_SYSLIB_FLASH_ULP_WS_0_FREQ_MAX ( 16UL)
50 #define CY_SYSLIB_FLASH_ULP_WS_1_FREQ_MAX ( 33UL)
51 #define CY_SYSLIB_FLASH_ULP_WS_2_FREQ_MAX ( 50UL)
52
53 /* ROM and SRAM wait states for the slow clock domain (LP mode at 1.1v) */
54 #define CY_SYSLIB_LP_SLOW_WS_0_FREQ_MAX (100UL)
55 #define CY_SYSLIB_LP_SLOW_WS_1_FREQ_MAX (120UL)
56
57 /* ROM and SRAM wait states for the slow clock domain (ULP mode at 0.9v) */
58 #define CY_SYSLIB_ULP_SLOW_WS_0_FREQ_MAX ( 25UL)
59 #define CY_SYSLIB_ULP_SLOW_WS_1_FREQ_MAX ( 50UL)
60 #elif (defined(CY_IP_M33SYSCPUSS) && (CY_IP_M33SYSCPUSS))
61 /* These definitions can be removed once SystemCorClockUpdate() function is implemented */
62 #define CY_SYSCLK_IMO_FREQ (8000000UL) /* Hz */
63 #define CY_DELAY_1K_THRESHOLD (1000u)
64 #define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
65 #define CY_DELAY_1M_THRESHOLD (1000000u)
66 #define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
67
68 #elif defined(CY_IP_M7CPUSS)
69 #define CY_SYSLIB_LP_SLOW_WS_0_FREQ_MAX (100UL)
70
71 #endif
72
73 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2))
74 /* RESET_CAUSE2 macro for SRSSv1 devices (nominally CAT1A devices except TVIIBE) */
75 #define CY_SRSS_RES_CAUSE2_CSV_LOSS_Msk (SRSS_RES_CAUSE2_RESET_CSV_HF_LOSS_Msk)
76 #define CY_SRSS_RES_CAUSE2_CSV_LOSS_Pos (SRSS_RES_CAUSE2_RESET_CSV_HF_LOSS_Pos)
77 #define CY_SRSS_RES_CAUSE2_CSV_ERROR_Msk (SRSS_RES_CAUSE2_RESET_CSV_HF_FREQ_Msk)
78 #define CY_SRSS_RES_CAUSE2_CSV_ERROR_Pos (SRSS_RES_CAUSE2_RESET_CSV_HF_FREQ_Pos)
79 #endif
80
81 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
82 /* RESET_CAUSE2 macro for SRSSv2 and v3 (nominally CAT1C and TVIIBE CAT1A devices) */
83 #define CY_SRSS_RES_CAUSE2_CSV_LOSS_Msk (SRSS_RES_CAUSE2_RESET_CSV_HF_Msk)
84 #define CY_SRSS_RES_CAUSE2_CSV_LOSS_Pos (SRSS_RES_CAUSE2_RESET_CSV_HF_Pos)
85 #define CY_SRSS_RES_CAUSE2_CSV_ERROR_Msk (SRSS_RES_CAUSE2_RESET_CSV_REF_Msk)
86 #define CY_SRSS_RES_CAUSE2_CSV_ERROR_Pos (SRSS_RES_CAUSE2_RESET_CSV_REF_Pos)
87 #endif
88
89 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || defined(CY_IP_MXS22SRSS)
90 /* RESET_CAUSE2 macro for CAT1B, CAT1D devices */
91 #define CY_SRSS_RES_CAUSE2_CSV_LOSS_Msk (SRSS_RES_CAUSE2_RESET_CSV_HF_Msk)
92 #define CY_SRSS_RES_CAUSE2_CSV_LOSS_Pos (SRSS_RES_CAUSE2_RESET_CSV_HF_Pos)
93 #define CY_SRSS_RES_CAUSE2_CSV_ERROR_Msk (SRSS_RES_CAUSE2_RESET_CSV_REF_Msk)
94 #define CY_SRSS_RES_CAUSE2_CSV_ERROR_Pos (SRSS_RES_CAUSE2_RESET_CSV_REF_Pos)
95 #endif
96
97 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
98 /** Holds the flag to indicate if the System woke up from Warm Boot or not */
99 bool cy_WakeupFromWarmBootStatus = false;
100 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) */
101
102 #if !defined(NDEBUG)
103 CY_NOINIT char_t cy_assertFileName[CY_MAX_FILE_NAME_SIZE + 1];
104 CY_NOINIT uint32_t cy_assertLine;
105 #endif /* NDEBUG */
106
107 #if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED)
108 CY_NOINIT cy_stc_fault_frame_t cy_faultFrame;
109 #endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
110
111 #if defined(__ARMCC_VERSION)
112 #if (__ARMCC_VERSION >= 6010050)
Cy_SysLib_AsmInfiniteLoop(void)113 static void Cy_SysLib_AsmInfiniteLoop(void) { __ASM (" b . "); };
114 #else
Cy_SysLib_AsmInfiniteLoop(void)115 static __ASM void Cy_SysLib_AsmInfiniteLoop(void) { b . };
116 #endif /* (__ARMCC_VERSION >= 6010050) */
117 #endif /* (__ARMCC_VERSION) */
118
119 #if defined(CY_INIT_CODECOPY_ENABLE)
120 CY_SECTION_INIT_CODECOPY_BEGIN
121 #endif
Cy_SysLib_Delay(uint32_t milliseconds)122 void Cy_SysLib_Delay(uint32_t milliseconds)
123 {
124 uint32_t max_delay_ms = 0xFFFFFFFFU / (cy_delayFreqKhz * CY_SYSLIB_DELAY_CALIBRATION_FACTOR);
125
126 while(milliseconds > max_delay_ms)
127 {
128 /* This loop prevents an overflow in value passed to Cy_SysLib_DelayCycles() API. */
129 Cy_SysLib_DelayCycles(max_delay_ms * cy_delayFreqKhz * CY_SYSLIB_DELAY_CALIBRATION_FACTOR);
130 milliseconds -= max_delay_ms;
131 }
132
133 Cy_SysLib_DelayCycles(milliseconds * cy_delayFreqKhz * CY_SYSLIB_DELAY_CALIBRATION_FACTOR);
134 }
135
136
Cy_SysLib_DelayUs(uint16_t microseconds)137 void Cy_SysLib_DelayUs(uint16_t microseconds)
138 {
139 Cy_SysLib_DelayCycles((uint32_t) microseconds * cy_delayFreqMhz * CY_SYSLIB_DELAY_CALIBRATION_FACTOR);
140 }
141
Cy_SysLib_Rtos_Delay(uint32_t milliseconds)142 __WEAK void Cy_SysLib_Rtos_Delay(uint32_t milliseconds)
143 {
144 Cy_SysLib_Delay(milliseconds);
145 }
146
Cy_SysLib_Rtos_DelayUs(uint16_t microseconds)147 __WEAK void Cy_SysLib_Rtos_DelayUs(uint16_t microseconds)
148 {
149 Cy_SysLib_DelayUs(microseconds);
150 }
151
Cy_SysLib_Halt(uint32_t reason)152 __NO_RETURN void Cy_SysLib_Halt(uint32_t reason)
153 {
154 if(0U != reason)
155 {
156 /* To remove an unreferenced local variable warning */
157 }
158
159 #if defined (__ARMCC_VERSION)
160 __BKPT(0x0);
161 #elif defined(__GNUC__)
162 CY_HALT();
163 #elif defined (__ICCARM__)
164 CY_HALT();
165 #else
166 #error "An unsupported toolchain"
167 #endif /* (__ARMCC_VERSION) */
168
169 while(true) {}
170 }
171
172
Cy_SysLib_AssertFailed(const char_t * file,uint32_t line)173 __WEAK void Cy_SysLib_AssertFailed(const char_t * file, uint32_t line)
174 {
175 #if !defined(NDEBUG) || defined(CY_DOXYGEN)
176 (void) strncpy(cy_assertFileName, file, CY_MAX_FILE_NAME_SIZE);
177 cy_assertLine = line;
178 Cy_SysLib_Halt(0UL);
179 #else
180 (void) file;
181 (void) line;
182 #endif /* !defined(NDEBUG) || defined(CY_DOXYGEN) */
183 }
184
185 #ifdef CY_IP_M4CPUSS
186
187
Cy_SysLib_ClearFlashCacheAndBuffer(void)188 void Cy_SysLib_ClearFlashCacheAndBuffer(void)
189 {
190 #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE)
191 CY_PRA_REG32_SET(CY_PRA_INDX_FLASHC_FLASH_CMD, FLASHC_FLASH_CMD_INV_Msk);
192 #else
193 FLASHC_FLASH_CMD = FLASHC_FLASH_CMD_INV_Msk;
194 #endif /* CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) */
195 }
196 #endif
197
198
Cy_SysLib_ResetBackupDomain(void)199 cy_en_syslib_status_t Cy_SysLib_ResetBackupDomain(void)
200 {
201 BACKUP_RESET = BACKUP_RESET_RESET_Msk;
202 return (Cy_SysLib_GetResetStatus());
203 }
204
Cy_SysLib_GetResetReason(void)205 uint32_t Cy_SysLib_GetResetReason(void)
206 {
207 uint32_t retVal = SRSS_RES_CAUSE;
208
209 if(0U != _FLD2VAL(SRSS_PWR_HIBERNATE_TOKEN, SRSS_PWR_HIBERNATE))
210 {
211 retVal |= CY_SYSLIB_RESET_HIB_WAKEUP;
212 }
213
214 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS40SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2)) || defined(CY_IP_MXS22SRSS)
215 if(0U != _FLD2VAL(CY_SRSS_RES_CAUSE2_CSV_LOSS, SRSS_RES_CAUSE2))
216 {
217 retVal |= CY_SYSLIB_RESET_CSV_LOSS_WAKEUP;
218 }
219
220 if(0U != _FLD2VAL(CY_SRSS_RES_CAUSE2_CSV_ERROR, SRSS_RES_CAUSE2))
221 {
222 retVal |= CY_SYSLIB_RESET_CSV_ERROR_WAKEUP;
223 }
224 #endif
225 return (retVal);
226 }
227
228
Cy_SysLib_ClearResetReason(void)229 void Cy_SysLib_ClearResetReason(void)
230 {
231 /* RES_CAUSE and RES_CAUSE2 register's bits are RW1C (every bit is cleared upon writing 1),
232 * so write all ones to clear all the reset reasons.
233 */
234 SRSS_RES_CAUSE = 0xFFFFFFFFU;
235 SRSS_RES_CAUSE2 = 0xFFFFFFFFU;
236
237 if(0U != _FLD2VAL(SRSS_PWR_HIBERNATE_TOKEN, SRSS_PWR_HIBERNATE))
238 {
239 /* Clears PWR_HIBERNATE token */
240 #if CY_CPU_CORTEX_M4 && defined (CY_DEVICE_SECURE)
241 CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_PWR_HIBERNATE, SRSS_PWR_HIBERNATE_TOKEN, 0UL);
242 #else
243 SRSS_PWR_HIBERNATE &= ~SRSS_PWR_HIBERNATE_TOKEN_Msk;
244 #endif /* CY_CPU_CORTEX_M4 && defined (CY_DEVICE_SECURE) */
245 }
246 }
247
248 #ifdef CY_IP_M4CPUSS
249 #if (CY_CPU_CORTEX_M0P)
250
251
Cy_SysLib_SoftResetCM4(void)252 void Cy_SysLib_SoftResetCM4(void)
253 {
254 static uint32_t msg;
255
256 msg = CY_IPC_DATA_FOR_CM4_SOFT_RESET;
257
258 /* Tries to acquire the IPC structure and pass the arguments to SROM API.
259 * SROM API parameters:
260 * ipcPtr: IPC Structure 0 reserved for M0+ Secure Access.
261 * notifyEvent_Intr: 1U - IPC Interrupt Structure 1 is used for Releasing IPC 0 (M0+ NMI Handler).
262 * msgPtr: &msg - The address of SRAM with the API's parameters.
263 */
264 if(CY_IPC_DRV_SUCCESS != Cy_IPC_Drv_SendMsgPtr(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL_CM0), 1U, (void *) &msg))
265 {
266 CY_ASSERT(0U != 0U);
267 }
268
269 while(Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL_CM0)))
270 {
271 /* Waits until SROM API runs the command (sent over the IPC channel) and releases the IPC0 structure. */
272 }
273 }
274 #endif /* CY_CPU_CORTEX_M0P || defined (CY_DOXYGEN) */
275
276
277 #if defined (CY_IP_M4CPUSS) && (!(defined (SRSS_HT_VARIANT) && (SRSS_HT_VARIANT == 1u)))
278
Cy_SysLib_GetUniqueId(void)279 uint64_t Cy_SysLib_GetUniqueId(void)
280 {
281 uint32_t uniqueIdHi;
282 uint32_t uniqueIdLo;
283
284 uniqueIdHi = ((uint32_t) SFLASH_DIE_YEAR << (CY_UNIQUE_ID_DIE_YEAR_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
285 (((uint32_t)SFLASH_DIE_MINOR & 1U) << (CY_UNIQUE_ID_DIE_MINOR_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
286 ((uint32_t) SFLASH_DIE_SORT << (CY_UNIQUE_ID_DIE_SORT_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
287 ((uint32_t) SFLASH_DIE_Y << (CY_UNIQUE_ID_DIE_Y_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
288 ((uint32_t) SFLASH_DIE_X);
289
290 uniqueIdLo = ((uint32_t) SFLASH_DIE_WAFER << CY_UNIQUE_ID_DIE_WAFER_Pos) |
291 ((uint32_t) SFLASH_DIE_LOT(2U) << CY_UNIQUE_ID_DIE_LOT_2_Pos) |
292 ((uint32_t) SFLASH_DIE_LOT(1U) << CY_UNIQUE_ID_DIE_LOT_1_Pos) |
293 ((uint32_t) SFLASH_DIE_LOT(0U));
294
295 return (((uint64_t) uniqueIdHi << CY_UNIQUE_ID_DIE_X_Pos) | uniqueIdLo);
296 }
297 #endif /* defined (CY_IP_M4CPUSS) && (!(defined (SRSS_HT_VARIANT) && (SRSS_HT_VARIANT == 1u))) */
298 #endif
299
300
301 #if ((defined (CY_IP_M33SYSCPUSS) && defined(CY_IP_MXEFUSE)) && defined (CY_UNIQE_DEVICE_ID_PRESENT_SFLASH))
302 #define CY_DIE_REG_EFUSE_OFFSET 0x74
303 #define CY_DIE_REG_COUNT 3U
304
Cy_SysLib_GetUniqueId(void)305 uint64_t Cy_SysLib_GetUniqueId(void)
306 {
307 #if (!CY_UNIQE_DEVICE_ID_PRESENT_SFLASH)
308 uint32_t uniqueIdHi;
309 uint32_t uniqueIdLo;
310 uint32_t dieRead[3];
311 cy_en_efuse_status_t status = CY_EFUSE_ERR_UNC;
312
313 if(Cy_EFUSE_IsEnabled(EFUSE))
314 {
315
316 status = Cy_EFUSE_ReadWordArray(EFUSE, dieRead, CY_DIE_REG_EFUSE_OFFSET, CY_DIE_REG_COUNT);
317
318 if(status == CY_EFUSE_SUCCESS)
319 {
320 uniqueIdHi = ((uint32_t) _FLD2VAL(EFUSE_DATA_DIE_2_YEAR, dieRead[2]) << (CY_UNIQUE_ID_DIE_YEAR_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
321 (((uint32_t)_FLD2VAL(EFUSE_DATA_DIE_2_REVISION_ID, dieRead[2]) & 1U) << (CY_UNIQUE_ID_DIE_MINOR_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
322 ((uint32_t) _FLD2VAL(EFUSE_DATA_DIE_1_SORT, dieRead[1]) << (CY_UNIQUE_ID_DIE_SORT_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
323 ((uint32_t) _FLD2VAL(EFUSE_DATA_DIE_1_Y, dieRead[1]) << (CY_UNIQUE_ID_DIE_Y_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
324 ((uint32_t) _FLD2VAL(EFUSE_DATA_DIE_1_X, dieRead[1]));
325
326 uniqueIdLo = (((uint32_t) _FLD2VAL(EFUSE_DATA_DIE_0_WAFER, dieRead[0]) << CY_UNIQUE_ID_DIE_WAFER_Pos) |
327 ((uint32_t) _FLD2VAL(EFUSE_DATA_DIE_0_LOT, dieRead[0])));
328
329 return (((uint64_t) uniqueIdHi << CY_UNIQUE_ID_DIE_X_Pos) | uniqueIdLo);
330 }
331 else
332 {
333 return 0UL;
334 }
335 }
336 else
337 {
338 return 0UL;
339 }
340 #else
341 uint32_t uniqueIdHi;
342 uint32_t uniqueIdLo;
343
344 uniqueIdHi = ((uint32_t) SFLASH_DIE_YEAR << (CY_UNIQUE_ID_DIE_YEAR_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
345 (((uint32_t)SFLASH_DIE_MINOR & 1U) << (CY_UNIQUE_ID_DIE_MINOR_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
346 ((uint32_t) SFLASH_DIE_SORT << (CY_UNIQUE_ID_DIE_SORT_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
347 ((uint32_t) SFLASH_DIE_Y << (CY_UNIQUE_ID_DIE_Y_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
348 ((uint32_t) SFLASH_DIE_X);
349
350 uniqueIdLo = ((uint32_t) SFLASH_DIE_WAFER << CY_UNIQUE_ID_DIE_WAFER_Pos) |
351 ((uint32_t) SFLASH_DIE_LOT(2U) << CY_UNIQUE_ID_DIE_LOT_2_Pos) |
352 ((uint32_t) SFLASH_DIE_LOT(1U) << CY_UNIQUE_ID_DIE_LOT_1_Pos) |
353 ((uint32_t) SFLASH_DIE_LOT(0U));
354
355 return (((uint64_t) uniqueIdHi << CY_UNIQUE_ID_DIE_X_Pos) | uniqueIdLo);
356 #endif
357 }
358 #endif
359
360
361 #if defined(CY_INIT_CODECOPY_ENABLE)
362 CY_SECTION_INIT_CODECOPY_END
363 #endif
364
365 #if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED)
366
367
Cy_SysLib_FaultHandler(uint32_t const * faultStackAddr)368 void Cy_SysLib_FaultHandler(uint32_t const *faultStackAddr)
369 {
370 /* Stores general registers */
371 cy_faultFrame.r0 = faultStackAddr[CY_R0_Pos];
372 cy_faultFrame.r1 = faultStackAddr[CY_R1_Pos];
373 cy_faultFrame.r2 = faultStackAddr[CY_R2_Pos];
374 cy_faultFrame.r3 = faultStackAddr[CY_R3_Pos];
375 cy_faultFrame.r12 = faultStackAddr[CY_R12_Pos];
376 cy_faultFrame.lr = faultStackAddr[CY_LR_Pos];
377 cy_faultFrame.pc = faultStackAddr[CY_PC_Pos];
378 cy_faultFrame.psr = faultStackAddr[CY_PSR_Pos];
379
380 #if (defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS) || CY_IP_M33SYSCPUSS || CY_IP_M55APPCPUSS)
381 #if (CY_CPU_CORTEX_M4 || (defined (CY_CPU_CORTEX_M7) && CY_CPU_CORTEX_M7) || \
382 (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55))
383 /* Stores the Configurable Fault Status Register state with the fault cause */
384 cy_faultFrame.cfsr.cfsrReg = SCB->CFSR;
385 /* Stores the Hard Fault Status Register */
386 cy_faultFrame.hfsr.hfsrReg = SCB->HFSR;
387 /* Stores the System Handler Control and State Register */
388 cy_faultFrame.shcsr.shcsrReg = SCB->SHCSR;
389 /* Store MemMange fault address */
390 cy_faultFrame.mmfar = SCB->MMFAR;
391 /* Store Bus fault address */
392 cy_faultFrame.bfar = SCB->BFAR;
393
394 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
395 (defined (__FPU_USED ) && (__FPU_USED == 1U)))
396 /* Checks cumulative exception bits for floating-point exceptions */
397 if(0U != (__get_FPSCR() & (CY_FPSCR_IXC_Msk | CY_FPSCR_IDC_Msk)))
398 {
399 cy_faultFrame.s0 = faultStackAddr[CY_S0_Pos];
400 cy_faultFrame.s1 = faultStackAddr[CY_S1_Pos];
401 cy_faultFrame.s2 = faultStackAddr[CY_S2_Pos];
402 cy_faultFrame.s3 = faultStackAddr[CY_S3_Pos];
403 cy_faultFrame.s4 = faultStackAddr[CY_S4_Pos];
404 cy_faultFrame.s5 = faultStackAddr[CY_S5_Pos];
405 cy_faultFrame.s6 = faultStackAddr[CY_S6_Pos];
406 cy_faultFrame.s7 = faultStackAddr[CY_S7_Pos];
407 cy_faultFrame.s8 = faultStackAddr[CY_S8_Pos];
408 cy_faultFrame.s9 = faultStackAddr[CY_S9_Pos];
409 cy_faultFrame.s10 = faultStackAddr[CY_S10_Pos];
410 cy_faultFrame.s11 = faultStackAddr[CY_S11_Pos];
411 cy_faultFrame.s12 = faultStackAddr[CY_S12_Pos];
412 cy_faultFrame.s13 = faultStackAddr[CY_S13_Pos];
413 cy_faultFrame.s14 = faultStackAddr[CY_S14_Pos];
414 cy_faultFrame.s15 = faultStackAddr[CY_S15_Pos];
415 cy_faultFrame.fpscr = faultStackAddr[CY_FPSCR_Pos];
416 }
417 #endif /* __FPU_PRESENT */
418 #endif /* CY_CPU_CORTEX_M4, CY_CPU_CORTEX_M7, CY_CPU_CORTEX_M33, CY_CPU_CORTEX_M55 */
419 #endif
420 Cy_SysLib_ProcessingFault();
421 }
422
423
Cy_SysLib_ProcessingFault(void)424 __WEAK void Cy_SysLib_ProcessingFault(void)
425 {
426 #if defined(__ARMCC_VERSION)
427 /* Assembly implementation of an infinite loop
428 * is used for the armcc compiler to preserve the call stack.
429 * Otherwise, the compiler destroys the call stack,
430 * because treats this API as a no return function.
431 */
432 Cy_SysLib_AsmInfiniteLoop();
433 #else
434 while(true) {}
435 #endif /* (__ARMCC_VERSION) */
436 }
437 #endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) || defined(CY_DOXYGEN) */
438
439 #if defined(CY_INIT_CODECOPY_ENABLE)
440 CY_SECTION_INIT_CODECOPY_BEGIN
441 #endif
442
Cy_SysLib_SetWaitStates(bool ulpMode,uint32_t clkHfMHz)443 void Cy_SysLib_SetWaitStates(bool ulpMode, uint32_t clkHfMHz)
444 {
445 #if defined(CY_IP_M4CPUSS) || defined(CY_IP_M7CPUSS)
446 #if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) || defined(CY_IP_M7CPUSS)
447 uint32_t waitStates;
448 uint32_t freqMax;
449
450 #if defined(CY_IP_M7CPUSS)
451 CY_ASSERT_L1(ulpMode == false);
452 #endif
453
454 #if defined(CY_IP_M7CPUSS)
455 freqMax = CY_SYSLIB_LP_SLOW_WS_0_FREQ_MAX;
456 #else
457 freqMax = ulpMode ? CY_SYSLIB_ULP_SLOW_WS_0_FREQ_MAX : CY_SYSLIB_LP_SLOW_WS_0_FREQ_MAX;
458 #endif
459 waitStates = (clkHfMHz <= freqMax) ? 0UL : 1UL;
460
461 /* ROM */
462 CPUSS_ROM_CTL = _CLR_SET_FLD32U(CPUSS_ROM_CTL, CPUSS_ROM_CTL_SLOW_WS, waitStates);
463 CPUSS_ROM_CTL = _CLR_SET_FLD32U(CPUSS_ROM_CTL, CPUSS_ROM_CTL_FAST_WS, 0UL);
464
465 /* SRAM */
466 CPUSS_RAM0_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM0_CTL0, CPUSS_RAM0_CTL0_SLOW_WS, waitStates);
467 CPUSS_RAM0_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM0_CTL0, CPUSS_RAM0_CTL0_FAST_WS, 0UL);
468 #if defined (RAMC1_PRESENT) && (RAMC1_PRESENT == 1UL)
469 CPUSS_RAM1_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM1_CTL0, CPUSS_RAM1_CTL0_SLOW_WS, waitStates);
470 CPUSS_RAM1_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM1_CTL0, CPUSS_RAM1_CTL0_FAST_WS, 0UL);
471 #endif /* defined (RAMC1_PRESENT) && (RAMC1_PRESENT == 1UL) */
472 #if defined (RAMC2_PRESENT) && (RAMC2_PRESENT == 1UL)
473 CPUSS_RAM2_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM2_CTL0, CPUSS_RAM2_CTL0_SLOW_WS, waitStates);
474 CPUSS_RAM2_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM2_CTL0, CPUSS_RAM2_CTL0_FAST_WS, 0UL);
475 #endif /* defined (RAMC2_PRESENT) && (RAMC2_PRESENT == 1UL) */
476
477 /* Flash */
478 #if defined(CY_IP_M7CPUSS)
479 if (clkHfMHz <= CY_SYSLIB_LP_SLOW_WS_0_FREQ_MAX)
480 {
481 waitStates = 0UL;
482 }
483 else
484 {
485 waitStates = 1UL;
486 }
487
488 FLASHC_FLASH_CTL = _CLR_SET_FLD32U(FLASHC_FLASH_CTL, FLASHC_FLASH_CTL_WS, waitStates);
489
490 #else
491 if (ulpMode)
492 {
493 waitStates = (clkHfMHz <= CY_SYSLIB_FLASH_ULP_WS_0_FREQ_MAX) ? 0UL :
494 ((clkHfMHz <= CY_SYSLIB_FLASH_ULP_WS_1_FREQ_MAX) ? 1UL : 2UL);
495 }
496 else
497 {
498 waitStates = (clkHfMHz <= cy_device->flashCtlMainWs0Freq) ? 0UL :
499 ((clkHfMHz <= cy_device->flashCtlMainWs1Freq) ? 1UL :
500 ((clkHfMHz <= cy_device->flashCtlMainWs2Freq) ? 2UL :
501 ((clkHfMHz <= cy_device->flashCtlMainWs3Freq) ? 3UL :
502 ((clkHfMHz <= cy_device->flashCtlMainWs4Freq) ? 4UL : 5UL))));
503 }
504
505 FLASHC_FLASH_CTL = _CLR_SET_FLD32U(FLASHC_FLASH_CTL, FLASHC_FLASH_CTL_MAIN_WS, waitStates);
506 #endif
507
508 #else
509 (void) ulpMode;
510 (void) clkHfMHz;
511 #endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) || defined(CY_IP_M7CPUSS) */
512 #endif /* defined(CY_IP_M4CPUSS) || defined(CY_IP_M7CPUSS) */
513
514 (void) ulpMode;
515 (void) clkHfMHz;
516 }
517
518
Cy_SysLib_GetDeviceRevision(void)519 uint8_t Cy_SysLib_GetDeviceRevision(void)
520 {
521 #if defined (CY_IP_M4CPUSS) && !(defined (SRSS_HT_VARIANT) && (SRSS_HT_VARIANT == 1u))
522 return ((SFLASH_SI_REVISION_ID == 0UL) ? CY_SYSLIB_DEVICE_REV_0A : SFLASH_SI_REVISION_ID);
523 #elif defined(CY_IP_M33SYSCPUSS) || defined(CY_IP_M7CPUSS) || (defined (SRSS_HT_VARIANT) && (SRSS_HT_VARIANT == 1u))
524 return ((uint8_t)((_FLD2VAL(CPUSS_PRODUCT_ID_MINOR_REV, CPUSS_PRODUCT_ID) << 4U) | _FLD2VAL(CPUSS_PRODUCT_ID_MAJOR_REV, CPUSS_PRODUCT_ID)));
525 #else
526 return 0;
527 #endif
528 }
529
Cy_SysLib_GetDevice(void)530 uint16_t Cy_SysLib_GetDevice(void)
531 {
532 #if defined (CY_IP_M4CPUSS) && !(defined (SRSS_HT_VARIANT) && (SRSS_HT_VARIANT == 1u))
533 return ((SFLASH_FAMILY_ID == 0UL) ? CY_SYSLIB_DEVICE_PSOC6ABLE2 : SFLASH_FAMILY_ID);
534 #elif defined(CY_IP_M33SYSCPUSS)
535 return CPUSS_FAMILYID;
536 #else
537 return 0;
538 #endif
539 }
540
541 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
Cy_Syslib_SetWarmBootEntryPoint(uint32_t * entryPoint,bool enable)542 void Cy_Syslib_SetWarmBootEntryPoint(uint32_t *entryPoint, bool enable)
543 {
544 *(uint32_t *)CY_SYSPM_BOOTROM_ENTRYPOINT_ADDR = (uint32_t)entryPoint | (enable ? CY_SYSPM_BOOTROM_DSRAM_DBG_ENABLE_MASK : 0UL) ;
545 }
546
Cy_SysLib_IsDSRAMWarmBootEntry(void)547 bool Cy_SysLib_IsDSRAMWarmBootEntry(void)
548 {
549 return cy_WakeupFromWarmBootStatus;
550 }
551
Cy_SysLib_ClearDSRAMWarmBootEntryStatus(void)552 void Cy_SysLib_ClearDSRAMWarmBootEntryStatus(void)
553 {
554 cy_WakeupFromWarmBootStatus = false;
555 }
556 #endif
557
558
559 #if defined(CY_IP_MXS22SRSS)
Cy_SysLib_GetDeviceLCS(void)560 cy_en_syslib_lcs_mode_t Cy_SysLib_GetDeviceLCS(void)
561 {
562 cy_en_syslib_lcs_mode_t lcsMode;
563
564 lcsMode = (cy_en_syslib_lcs_mode_t)CY_GET_REG32(SRSS_DECODED_LCS_DATA);
565
566 switch (lcsMode)
567 {
568 case CY_SYSLIB_LCS_VIRGIN:
569 case CY_SYSLIB_LCS_SORT:
570 case CY_SYSLIB_LCS_PROVISIONED:
571 case CY_SYSLIB_LCS_NORMAL_PROVISIONED:
572 case CY_SYSLIB_LCS_NORMAL:
573 case CY_SYSLIB_LCS_SECURE:
574 case CY_SYSLIB_LCS_NORMAL_NO_SECURE:
575 case CY_SYSLIB_LCS_RMA:
576 break;
577 default:
578 lcsMode = CY_SYSLIB_LCS_CORRUPTED;
579 break;
580 }
581
582 return lcsMode;
583 }
584 #endif
585
586 #if defined(CY_INIT_CODECOPY_ENABLE)
587 CY_SECTION_INIT_CODECOPY_END
588 #endif
589
590 #endif /* CY_IP_M33SYSCPUSS, CY_IP_M4CPUSS */
591
592 /* [] END OF FILE */
593
