1 /***************************************************************************//**
2 * \file cy_sysint.c
3 * \version 1.120
4 *
5 * \brief
6 * Provides an API implementation of the SysInt driver.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
11 * an affiliate of Cypress Semiconductor Corporation.
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *******************************************************************************/
26
27 #include "cy_device.h"
28
29 #if defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS)
30
31 #include "cy_sysint.h"
32
33 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 8.4', 1, 'Intentionally, the prototype and definition are in the same place.')
34 #if defined (CY_IP_M7CPUSS) || (defined (CY_IP_M4CPUSS) && (CY_IP_M4CPUSS_VERSION == 2u) && (CPUSS_SYSTEM_IRQ_PRESENT)) || defined (CY_DOXYGEN)
35 __WEAK cy_israddress * Cy_SysInt_SystemIrqUserTableRamPointer = NULL;
36 #endif /* defined (CY_IP_M7CPUSS) || (defined (CY_IP_M4CPUSS) && (CY_IP_M4CPUSS_VERSION == 2u) && (CPUSS_SYSTEM_IRQ_PRESENT)) || defined (CY_DOXYGEN) */
37 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.4')
38
39 CY_MISRA_FP_BLOCK_START('MISRA C-2012 Rule 8.3', 1, 'Only one prototype will be picked for compilation')
40 #if (((CY_CPU_CORTEX_M0P) || defined (CY_IP_M7CPUSS) || defined (CY_DOXYGEN)) && !defined(CY_IP_M0SECCPUSS))
Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum,cy_en_intr_t intrSrc)41 void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, cy_en_intr_t intrSrc)
42 #else
43 void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, IRQn_Type intrSrc)
44 #endif
45 {
46 CY_ASSERT_L3(CY_SYSINT_IS_NMI_NUM_VALID(nmiNum));
47
48 #if (defined(CY_IP_M4CPUSS) && (CY_CPU_CORTEX_M0P))
49 CY_ASSERT_L1(CY_SYSINT_IS_PC_0);
50 #endif
51
52 #if defined (CY_IP_M4CPUSS)
53 if (CY_CPUSS_V1)
54 {
55 nmiNum = CY_SYSINT_NMI1; /* For CPUSS_ver1 the NMI number is 1 */
56 }
57 #endif
58
59 #if (CY_CPU_CORTEX_M0P)
60 CPUSS_CM0_NMI_CTL((uint32_t)nmiNum - 1UL) = (uint32_t)intrSrc;
61 #elif (CY_CPU_CORTEX_M4)
62 CPUSS_CM4_NMI_CTL((uint32_t)nmiNum - 1UL) = (uint32_t)intrSrc;
63 #else
64 if(0UL != CY_IS_CM7_CORE_0)
65 {
66 CPUSS_CM7_0_NMI_CTL((uint32_t)nmiNum - 1UL) = (uint32_t)intrSrc;
67 }
68 else
69 {
70 CPUSS_CM7_1_NMI_CTL((uint32_t)nmiNum - 1UL) = (uint32_t)intrSrc;
71 }
72 #endif
73 }
74
75 #if (((CY_CPU_CORTEX_M0P) || defined(CY_IP_M7CPUSS) || defined (CY_DOXYGEN)) && !defined(CY_IP_M0SECCPUSS))
Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum)76 cy_en_intr_t Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum)
77 #else
78 IRQn_Type Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum)
79 #endif
80 {
81 CY_ASSERT_L3(CY_SYSINT_IS_NMI_NUM_VALID(nmiNum));
82
83 #if (defined(CY_IP_M4CPUSS) && (CY_CPU_CORTEX_M0P))
84 if (CY_CPUSS_V1)
85 {
86 nmiNum = CY_SYSINT_NMI1; /* For CPUSS_ver1 the NMI number is 1 */
87 }
88 #endif
89
90 #if (CY_CPU_CORTEX_M0P)
91 return ((cy_en_intr_t)(CPUSS_CM0_NMI_CTL((uint32_t)nmiNum - 1UL)));
92 #elif (CY_CPU_CORTEX_M4)
93 return ((IRQn_Type)(CPUSS_CM4_NMI_CTL((uint32_t)nmiNum - 1UL)));
94 #else
95 if(0UL != CY_IS_CM7_CORE_0)
96 {
97 return ((cy_en_intr_t)(CPUSS_CM7_0_NMI_CTL((uint32_t)nmiNum - 1UL)));
98 }
99 else
100 {
101 return ((cy_en_intr_t)(CPUSS_CM7_1_NMI_CTL((uint32_t)nmiNum - 1UL)));
102 }
103 #endif
104 }
105 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.3')
106
Cy_SysInt_Init(const cy_stc_sysint_t * config,cy_israddress userIsr)107 cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddress userIsr)
108 {
109 cy_en_sysint_status_t status = CY_SYSINT_SUCCESS;
110
111 if(NULL != config)
112 {
113 CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority));
114
115 #if defined (CY_IP_M4CPUSS)
116 #if (CY_CPU_CORTEX_M0P)
117 (void)userIsr; /* Suppress a compiler warning about unused variables */
118 if (config->intrSrc > SysTick_IRQn)
119 {
120 Cy_SysInt_SetInterruptSource(config->intrSrc, config->cm0pSrc);
121 NVIC_SetPriority((IRQn_Type)(config->intrSrc), config->intrPriority);
122
123 #if (defined (CPUSS_SYSTEM_IRQ_PRESENT) && (CPUSS_SYSTEM_IRQ_PRESENT == 1u))
124 (void)Cy_SysInt_SetSystemIrqVector(((cy_en_intr_t)config->cm0pSrc), userIsr);
125 #else
126 /* Set the new vector only if it was moved to __ramVectors */
127 if (SCB->VTOR == (uint32_t)&__ramVectors)
128 {
129 (void)Cy_SysInt_SetVector(config->intrSrc, userIsr);
130 }
131 #endif
132 }
133 else
134 {
135 status = CY_SYSINT_BAD_PARAM;
136
137 NVIC_SetPriority((IRQn_Type)(config->cm0pSrc), config->intrPriority);
138 /* Set the new vector only if it was moved to __ramVectors */
139 if (SCB->VTOR == (uint32_t)&__ramVectors)
140 {
141 (void)Cy_SysInt_SetVector(config->intrSrc, userIsr);
142 }
143 }
144 #elif (defined (CY_IP_M4CPUSS) && (CY_IP_M4CPUSS_VERSION == 2) && (CPUSS_SYSTEM_IRQ_PRESENT))
145 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to IRQn_Type enum.');
146 IRQn_Type IRQn = (IRQn_Type)((uint32_t)config->intrSrc >> CY_SYSINT_INTRSRC_MUXIRQ_SHIFT) ; /* Fetch bit 12-15 to get CPU IRQ value */
147 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_intr_t enum.');
148 cy_en_intr_t devIntrSrc = (cy_en_intr_t)((uint32_t)config->intrSrc & CY_SYSINT_INTRSRC_MASK); /* Fetch bit 0-11 to get system interrupt value */
149 CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority));
150 if (IRQn > SysTick_IRQn && IRQn < Internal0_IRQn)
151 {
152 Cy_SysInt_SetInterruptSource(IRQn, devIntrSrc);
153
154 NVIC_SetPriority(IRQn, config->intrPriority);
155
156 (void)Cy_SysInt_SetSystemIrqVector(devIntrSrc, userIsr);
157 }
158 else
159 {
160 status = CY_SYSINT_BAD_PARAM;
161
162 /* Set the new vector only if it was moved to __ramVectors */
163 if (SCB->VTOR == (uint32_t)&__ramVectors)
164 {
165 (void)Cy_SysInt_SetVector(config->intrSrc, userIsr);
166 }
167 }
168 #else
169 {
170
171 NVIC_SetPriority(config->intrSrc, config->intrPriority);
172
173 /* Set the new vector only if it was moved to __ramVectors */
174 if (SCB->VTOR == (uint32_t)&__ramVectors)
175 {
176 (void)Cy_SysInt_SetVector(config->intrSrc, userIsr);
177 }
178 }
179 #endif /* (CY_CPU_CORTEX_M0P) */
180 #endif /* defined (CY_IP_M4CPUSS) */
181
182 #if defined (CY_IP_M7CPUSS)
183 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to IRQn_Type enum.');
184 IRQn_Type IRQn = (IRQn_Type)((uint32_t)config->intrSrc >> CY_SYSINT_INTRSRC_MUXIRQ_SHIFT) ; /* Fetch bit 16-31 to get CPU IRQ value */
185 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_intr_t enum.');
186 cy_en_intr_t devIntrSrc = (cy_en_intr_t)((uint32_t)config->intrSrc & CY_SYSINT_INTRSRC_MASK); /* Fetch bit 0-15 to get system interrupt value */
187 CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority));
188 #if (CY_CPU_CORTEX_M0P)
189 if (IRQn > NvicMux1_IRQn && IRQn < Internal0_IRQn) /* CPU IRQ0 and IRQ1 for CM0+ are used by ROM and not meant for user. */
190 #else
191 if (IRQn > SysTick_IRQn && IRQn < Internal0_IRQn)
192 #endif
193 {
194 Cy_SysInt_SetInterruptSource(IRQn, devIntrSrc);
195 }
196 else
197 {
198 status = CY_SYSINT_BAD_PARAM;
199 }
200
201 NVIC_SetPriority(IRQn, config->intrPriority);
202
203 #if (defined (CPUSS_SYSTEM_IRQ_PRESENT) && (CPUSS_SYSTEM_IRQ_PRESENT == 1u))
204 (void)Cy_SysInt_SetSystemIrqVector(devIntrSrc, userIsr);
205 #endif /* (defined (CPUSS_SYSTEM_IRQ_PRESENT) && (CPUSS_SYSTEM_IRQ_PRESENT == 1u)) */
206 #endif
207 }
208 else
209 {
210 status = CY_SYSINT_BAD_PARAM;
211 }
212
213 return(status);
214 }
215
216 #if (((CY_CPU_CORTEX_M0P) || defined (CY_IP_M7CPUSS) || (defined (CY_IP_M4CPUSS) && (CY_IP_M4CPUSS_VERSION == 2) && (CPUSS_SYSTEM_IRQ_PRESENT)) || defined (CY_DOXYGEN)) && !defined(CY_IP_M0SECCPUSS))
Cy_SysInt_SetInterruptSource(IRQn_Type IRQn,cy_en_intr_t devIntrSrc)217 void Cy_SysInt_SetInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc)
218 {
219 #if defined (CY_IP_M4CPUSS)
220 if (CY_CPUSS_V1)
221 {
222 uint32_t regPos = ((uint32_t)IRQn >> CY_SYSINT_CM0P_MUX_SHIFT);
223 if(0UL == (regPos & (uint32_t)~CY_SYSINT_MUX_REG_MSK))
224 {
225 uint32_t bitfield_Pos = (uint32_t)((uint32_t)IRQn - (uint32_t)(regPos << CY_SYSINT_CM0P_MUX_SHIFT)) << CY_SYSINT_CM0P_MUX_SCALE;
226 uint32_t bitfield_Msk = (uint32_t)(CY_SYSINT_CM0P_MUX_MASK << bitfield_Pos);
227
228 CY_REG32_CLR_SET(CPUSS_CM0_INT_CTL[regPos], bitfield, devIntrSrc);
229 }
230 }
231 else /* CPUSS_V2 */
232 {
233 CY_ASSERT_L1(CY_CPUSS_DISCONNECTED_IRQN != devIntrSrc); /* Disconnection feature doesn't work for CPUSS_V2 */
234 #if (CY_CPU_CORTEX_M0P)
235 CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc] = _VAL2FLD(CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX, IRQn)
236 | CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
237 #else
238 CPUSS_CM4_SYSTEM_INT_CTL[devIntrSrc] = _VAL2FLD(CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_IDX, IRQn)
239 | CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
240 #endif
241 }
242 #endif
243
244 #if defined (CY_IP_M7CPUSS)
245 CY_ASSERT_L1(CY_CPUSS_DISCONNECTED_IRQN != devIntrSrc);
246 #if (CY_CPU_CORTEX_M0P)
247 CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc] = _VAL2FLD(CPUSS_CM0_SYSTEM_INT_CTL_CM0_CPU_INT_IDX, IRQn)
248 | CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
249 #else
250 if (0UL != CY_IS_CM7_CORE_0)
251 {
252 CPUSS_CM7_0_SYSTEM_INT_CTL[devIntrSrc] = _VAL2FLD(CPUSS_CM7_0_SYSTEM_INT_CTL_CPU_INT_IDX, IRQn)
253 | CPUSS_CM7_0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
254 }
255 else
256 {
257 CPUSS_CM7_1_SYSTEM_INT_CTL[devIntrSrc] = _VAL2FLD(CPUSS_CM7_1_SYSTEM_INT_CTL_CPU_INT_IDX, IRQn)
258 | CPUSS_CM7_1_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
259 }
260 #endif
261 #endif
262 }
263
264 #if (defined(CY_IP_M4CPUSS) && (CY_CPU_CORTEX_M0P)) || defined (CY_DOXYGEN)
Cy_SysInt_DisconnectInterruptSource(IRQn_Type IRQn,cy_en_intr_t devIntrSrc)265 void Cy_SysInt_DisconnectInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc)
266 {
267 if (CY_CPUSS_V1)
268 {
269 Cy_SysInt_SetInterruptSource(IRQn, CY_CPUSS_DISCONNECTED_IRQN);
270 }
271 else /* CPUSS_V2 */
272 {
273 CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc] &= (uint32_t)~ CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
274 }
275 }
276
277
Cy_SysInt_GetInterruptSource(IRQn_Type IRQn)278 cy_en_intr_t Cy_SysInt_GetInterruptSource(IRQn_Type IRQn)
279 {
280 uint32_t tempReg = CY_CPUSS_NOT_CONNECTED_IRQN;
281
282 if (CY_CPUSS_V1)
283 {
284 uint32_t regPos = ((uint32_t)IRQn >> CY_SYSINT_CM0P_MUX_SHIFT);
285 if(0UL == (regPos & (uint32_t)~CY_SYSINT_MUX_REG_MSK))
286 {
287 uint32_t bitfield_Pos = ((uint32_t)IRQn - (regPos << CY_SYSINT_CM0P_MUX_SHIFT)) << CY_SYSINT_CM0P_MUX_SCALE;
288 uint32_t bitfield_Msk = (uint32_t)(CY_SYSINT_CM0P_MUX_MASK << bitfield_Pos);
289
290 tempReg = _FLD2VAL(bitfield, CPUSS_CM0_INT_CTL[regPos]);
291 }
292 }
293
294 return ((cy_en_intr_t)tempReg);
295 }
296 #endif
297
Cy_SysInt_GetNvicConnection(cy_en_intr_t devIntrSrc)298 IRQn_Type Cy_SysInt_GetNvicConnection(cy_en_intr_t devIntrSrc)
299 {
300 uint32_t tempReg = CY_CPUSS_NOT_CONNECTED_IRQN;
301
302 #if defined (CY_IP_M4CPUSS)
303 #if (CY_CPU_CORTEX_M0P)
304 if (CY_SYSINT_ENABLE == _FLD2VAL(CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID, CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc]))
305 {
306 tempReg = _FLD2VAL(CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX, CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc]);
307 }
308 #else
309 if ((!CY_CPUSS_V1) && (CY_SYSINT_ENABLE == _FLD2VAL(CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_VALID, CPUSS_CM4_SYSTEM_INT_CTL[devIntrSrc])))
310 {
311 tempReg = _FLD2VAL(CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_IDX, CPUSS_CM4_SYSTEM_INT_CTL[devIntrSrc]);
312 }
313 #endif /* (CY_CPU_CORTEX_M0P) */
314 #endif
315
316 #if defined (CY_IP_M7CPUSS)
317 #if (CY_CPU_CORTEX_M0P)
318 if ((CY_SYSINT_ENABLE == _FLD2VAL(CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_VALID, CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc])))
319 {
320 tempReg = _FLD2VAL(CPUSS_CM0_SYSTEM_INT_CTL_CM0_CPU_INT_IDX, CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc]);
321 }
322 #else
323 if (CY_IS_CM7_CORE_0 && (CY_SYSINT_ENABLE == _FLD2VAL(CPUSS_CM7_0_SYSTEM_INT_CTL_CPU_INT_VALID, CPUSS_CM7_0_SYSTEM_INT_CTL[devIntrSrc])))
324 {
325 tempReg = _FLD2VAL(CPUSS_CM7_0_SYSTEM_INT_CTL_CPU_INT_IDX, CPUSS_CM7_0_SYSTEM_INT_CTL[devIntrSrc]);
326 }
327 else if ((CY_SYSINT_ENABLE == _FLD2VAL(CPUSS_CM7_1_SYSTEM_INT_CTL_CPU_INT_VALID, CPUSS_CM7_1_SYSTEM_INT_CTL[devIntrSrc])))
328 {
329 tempReg = _FLD2VAL(CPUSS_CM7_1_SYSTEM_INT_CTL_CPU_INT_IDX, CPUSS_CM7_1_SYSTEM_INT_CTL[devIntrSrc]);
330 }
331 else
332 {
333 /* No active core */
334 }
335 #endif
336 #endif
337 return ((IRQn_Type)tempReg);
338 }
339
340
Cy_SysInt_GetInterruptActive(IRQn_Type IRQn)341 cy_en_intr_t Cy_SysInt_GetInterruptActive(IRQn_Type IRQn)
342 {
343 uint32_t tempReg = CY_CPUSS_NOT_CONNECTED_IRQN;
344 uint32_t locIdx = (uint32_t)IRQn & CY_SYSINT_INT_STATUS_MSK;
345
346 #if defined (CY_IP_M4CPUSS)
347 #if (CY_CPU_CORTEX_M0P)
348 if(CY_SYSINT_ENABLE == _FLD2VAL(CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_VALID, CPUSS_CM0_INT_STATUS[locIdx]))
349 {
350 tempReg = _FLD2VAL(CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_IDX, CPUSS_CM0_INT_STATUS[locIdx]);
351 }
352 #else
353 if (!CY_CPUSS_V1)
354 {
355 if(CY_SYSINT_ENABLE == _FLD2VAL(CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_VALID, CPUSS_CM4_INT_STATUS[locIdx]))
356 {
357 tempReg = _FLD2VAL(CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_IDX, CPUSS_CM4_INT_STATUS[locIdx]);
358 }
359 }
360 #endif /* (CY_CPU_CORTEX_M0P) */
361 #endif
362
363 #if defined (CY_IP_M7CPUSS)
364 #if (CY_CPU_CORTEX_M0P)
365 if(CY_SYSINT_ENABLE == _FLD2VAL(CPUSS_CM0_INT0_STATUS_SYSTEM_INT_VALID, CPUSS_CM0_INT_STATUS_BASE[locIdx]))
366 {
367 tempReg = _FLD2VAL(CPUSS_CM0_INT0_STATUS_SYSTEM_INT_IDX, CPUSS_CM0_INT_STATUS_BASE[locIdx]);
368 }
369 #else
370 if((CY_IS_CM7_CORE_0) && (CY_SYSINT_ENABLE == _FLD2VAL(CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_0_INT_STATUS[locIdx])))
371 {
372 tempReg = _FLD2VAL(CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_IDX, CPUSS_CM7_0_INT_STATUS[locIdx]);
373 }
374 else if(CY_SYSINT_ENABLE == _FLD2VAL(CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_1_INT_STATUS[locIdx]))
375 {
376 tempReg = _FLD2VAL(CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_IDX, CPUSS_CM7_1_INT_STATUS[locIdx]);
377 }
378 else
379 {
380 /* No active core */
381 }
382 #endif
383 #endif
384 return ((cy_en_intr_t)tempReg);
385 }
386
387 #endif
388
389
Cy_SysInt_SetVector(IRQn_Type IRQn,cy_israddress userIsr)390 cy_israddress Cy_SysInt_SetVector(IRQn_Type IRQn, cy_israddress userIsr)
391 {
392 cy_israddress prevIsr;
393
394 /* Set the new vector only if it was moved to __ramVectors */
395 if (SCB->VTOR == (uint32_t)&__ramVectors)
396 {
397 CY_ASSERT_L1(CY_SYSINT_IS_VECTOR_VALID(userIsr));
398
399 prevIsr = __ramVectors[CY_INT_IRQ_BASE + (uint32_t)IRQn];
400 __ramVectors[CY_INT_IRQ_BASE + (uint32_t)IRQn] = userIsr;
401
402 #if defined (CY_IP_M7CPUSS)
403 #if (CY_CPU_CORTEX_M7)
404 // Ensure that above change in the vector table is cleaned from Data Cache,
405 // and Instruction Cache is invalidated, so that CPU fetches the correct address
406 SCB_CleanDCache_by_Addr((uint32_t*)&__ramVectors[CY_INT_IRQ_BASE + (uint32_t)IRQn], 4);
407 SCB_InvalidateICache();
408 #endif
409 #endif
410 }
411 else
412 {
413 prevIsr = __Vectors[CY_INT_IRQ_BASE + (uint32_t)IRQn];
414 }
415
416 return (prevIsr);
417 }
418
419
Cy_SysInt_GetVector(IRQn_Type IRQn)420 cy_israddress Cy_SysInt_GetVector(IRQn_Type IRQn)
421 {
422 cy_israddress currIsr;
423
424 /* Return the SRAM ISR address only if it was moved to __ramVectors */
425 if (SCB->VTOR == (uint32_t)&__ramVectors)
426 {
427 currIsr = __ramVectors[CY_INT_IRQ_BASE + (uint32_t)IRQn];
428 }
429 else
430 {
431 currIsr = __Vectors[CY_INT_IRQ_BASE + (uint32_t)IRQn];
432 }
433
434 return (currIsr);
435 }
436
437 #if (defined(CY_IP_M4CPUSS) && (!CY_CPU_CORTEX_M0P))
Cy_SysInt_SoftwareTrig(IRQn_Type IRQn)438 void Cy_SysInt_SoftwareTrig(IRQn_Type IRQn)
439 {
440 NVIC->STIR = (uint32_t)IRQn & CY_SYSINT_STIR_MASK;
441 }
442 #endif
443
444
445 /* These functions are compatible with M7 and M4 CPUSSv2 that also have the CPUSS_SYSTEM_IRQ_PRESENT. */
446 #if defined (CY_IP_M7CPUSS) || (defined (CY_IP_M4CPUSS) && (CY_IP_M4CPUSS_VERSION == 2u) && (CPUSS_SYSTEM_IRQ_PRESENT)) || defined (CY_DOXYGEN)
Cy_SysInt_InitExtIRQ(const cy_stc_sysint_t * config,cy_israddress userIsr)447 cy_en_sysint_status_t Cy_SysInt_InitExtIRQ(const cy_stc_sysint_t* config, cy_israddress userIsr)
448 {
449 cy_en_sysint_status_t status = CY_SYSINT_SUCCESS;
450
451 if(NULL != config)
452 {
453 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to IRQn_Type enum.');
454 IRQn_Type IRQn = (IRQn_Type)((uint32_t) config->intrSrc >> CY_SYSINT_INTRSRC_MUXIRQ_SHIFT);
455 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_intr_t enum.');
456 cy_en_intr_t devIntrSrc = (cy_en_intr_t)((uint32_t) config->intrSrc & CY_SYSINT_INTRSRC_MASK);
457 CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority));
458
459 #if (CY_CPU_CORTEX_M0P)
460 if (IRQn > NvicMux1_IRQn && IRQn < Internal0_IRQn)
461 #else
462 if (IRQn > SysTick_IRQn && IRQn < Internal0_IRQn)
463 #endif
464 {
465 Cy_SysInt_SetInterruptSource(IRQn, devIntrSrc);
466 }
467 else
468 {
469 status = CY_SYSINT_BAD_PARAM;
470 }
471 NVIC_SetPriority(IRQn, config->intrPriority);
472
473 /* Set the new vector only if it was moved to __ramVectors */
474 if (SCB->VTOR == (uint32_t)&__ramVectors)
475 {
476 (void)Cy_SysInt_SetVector(IRQn, userIsr);
477 }
478
479 }
480 else
481 {
482 status = CY_SYSINT_BAD_PARAM;
483 }
484
485 return(status);
486 }
487
488
Cy_SysInt_InitIntIRQ(const cy_stc_sysint_t * config,cy_israddress userIsr)489 cy_en_sysint_status_t Cy_SysInt_InitIntIRQ(const cy_stc_sysint_t* config, cy_israddress userIsr)
490 {
491 cy_en_sysint_status_t status = CY_SYSINT_SUCCESS;
492
493 if(NULL != config)
494 {
495 CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority));
496
497 if (((uint32_t)config->intrSrc >= (uint32_t)Internal0_IRQn) && ((uint32_t)config->intrSrc <= (uint32_t)Internal7_IRQn))
498 {
499
500 NVIC_SetPriority((IRQn_Type)config->intrSrc, config->intrPriority);
501
502 /* Set the new vector only if it was moved to __ramVectors */
503 if (SCB->VTOR == (uint32_t)&__ramVectors)
504 {
505 (void)Cy_SysInt_SetVector((IRQn_Type)config->intrSrc, userIsr);
506 }
507 }
508 else
509 {
510 status = CY_SYSINT_BAD_PARAM;
511 }
512
513 }
514 else
515 {
516 status = CY_SYSINT_BAD_PARAM;
517 }
518
519 return(status);
520 }
521
Cy_SysInt_SetSystemIrqVector(cy_en_intr_t sysIntSrc,cy_israddress userIsr)522 void Cy_SysInt_SetSystemIrqVector(cy_en_intr_t sysIntSrc, cy_israddress userIsr)
523 {
524 if (Cy_SysInt_SystemIrqUserTableRamPointer != NULL)
525 {
526 Cy_SysInt_SystemIrqUserTableRamPointer[sysIntSrc] = userIsr;
527 }
528 }
529
530
Cy_SysInt_GetSystemIrqVector(cy_en_intr_t sysIntSrc)531 cy_israddress Cy_SysInt_GetSystemIrqVector(cy_en_intr_t sysIntSrc)
532 {
533 cy_israddress userIsr = NULL;
534 if (Cy_SysInt_SystemIrqUserTableRamPointer != NULL)
535 {
536 userIsr = Cy_SysInt_SystemIrqUserTableRamPointer[sysIntSrc];
537 }
538
539 return userIsr;
540 }
541
542 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 14.3', 4, 'Valid Control expression conditions.')
Cy_SysInt_EnableSystemInt(cy_en_intr_t sysIntSrc)543 void Cy_SysInt_EnableSystemInt(cy_en_intr_t sysIntSrc)
544 {
545 if (CY_CPU_CORTEX_M0P)
546 {
547 CPUSS_CM0_SYSTEM_INT_CTL[sysIntSrc] |= CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
548 }
549 #if defined (CY_IP_M7CPUSS)
550 else if (CY_IS_CM7_CORE_0)
551 {
552 CPUSS_CM7_0_SYSTEM_INT_CTL[sysIntSrc] |= CPUSS_CM7_0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
553 }
554 else
555 {
556 CPUSS_CM7_1_SYSTEM_INT_CTL[sysIntSrc] |= CPUSS_CM7_1_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
557 }
558 #elif (CY_IP_M4CPUSS)
559 else
560 {
561 CPUSS_CM4_SYSTEM_INT_CTL[sysIntSrc] |= CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
562 }
563 #else
564 #error This version of the sysint driver only supports CM4 and CM7 devices.
565 #endif
566 }
567
568
Cy_SysInt_DisableSystemInt(cy_en_intr_t sysIntSrc)569 void Cy_SysInt_DisableSystemInt(cy_en_intr_t sysIntSrc)
570 {
571 if (CY_CPU_CORTEX_M0P)
572 {
573 CPUSS->CM0_SYSTEM_INT_CTL[sysIntSrc] &= (uint32_t) ~CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
574 }
575 #if defined (CY_IP_M7CPUSS)
576 else if (CY_IS_CM7_CORE_0)
577 {
578 CPUSS->CM7_0_SYSTEM_INT_CTL[sysIntSrc] &= (uint32_t) ~CPUSS_CM7_0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
579 }
580 else
581 {
582 CPUSS->CM7_1_SYSTEM_INT_CTL[sysIntSrc] &= (uint32_t) ~CPUSS_CM7_1_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
583 }
584 #elif (CY_IP_M4CPUSS)
585 else
586 {
587 CPUSS->CM4_SYSTEM_INT_CTL[sysIntSrc] &= (uint32_t) ~CPUSS_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Msk;
588 }
589 #else
590 #error This version of the sysint driver only supports CM4 and CM7 devices.
591 #endif
592 }
593 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 14.3')
594
595 #endif /* defined (CY_IP_M7CPUSS) || (defined (CY_IP_M4CPUSS) && (CY_IP_M4CPUSS_VERSION == 2u) && (CPUSS_SYSTEM_IRQ_PRESENT)) || defined (CY_DOXYGEN) */
596
597 #endif /* defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS) */
598
599 /* [] END OF FILE */
600
