1 /***************************************************************************//**
2 * \file cy_sd_host.h
3 * \version 2.20
4 *
5 * This file provides constants and parameter values for
6 * the SD Host Controller driver.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2018-2021 Cypress Semiconductor Corporation
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 /**
27 * \addtogroup group_sd_host
28 * \{
29 * This driver provides the user an easy method for accessing standard
30 * Host Controller Interface (HCI) registers and provides some simple
31 * functionality on top of the HCI for reading and writing data to
32 * an SD card, eMMc card or a SDIO device.
33 *
34 * The functions and other declarations used in this driver are in cy_sd_host.h.
35 * You can include cy_pdl.h to get access to all functions
36 * and declarations in the PDL.
37 *
38 * Features:
39 * * Supports data transfer using CPU, SDMA, ADMA2 and ADMA3 modes
40 * * Supports a configurable block size (1 to 65,535 Bytes)
41 * * Supports interrupt enabling and masking
42 * * Supports SD-HCI Host version 4 mode or less
43 * * Compliant with the SD 6.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
44 * * SD interface features:
45 * * - Supports the 4-bit interface
46 * * - Supports Ultra High Speed (UHS-I) mode
47 * * - Supports Default Speed (DS), High Speed (HS), SDR12, SDR25, SDR50, and DDR50 speed modes
48 * * - Supports SDIO card interrupts in both 1-bit and 4-bit modes
49 * * - Supports Standard capacity (SDSC), High capacity (SDHC)
50 * and Extended capacity (SDXC) memory
51 * * - Supports CRC and check for command and data packets
52 * * - Supports packet timeouts
53 * * - Handles the SDIO card interrupt
54 * * eMMC interface features:
55 * * - Supports 1-bit/4-bit/8-bit interfaces
56 * * - Supports legacy and High Speed SDR speed modes
57 * * - Supports CRC and check for command and data packets
58 * * - Supports packet timeouts
59 *
60 * Unsupported Features:
61 * * Wrap address transfers
62 * * eMMC boot operation
63 * * Suspend/Resume operation in an SDIO card
64 * * Operation in SDR104, UHS-II mode, HS200, and HS400
65 * * Serial Peripheral Interface (SPI) protocol mode
66 * * Interrupt input pins for the embedded SD system
67 * * Auto-tuning
68 * * Command queuing
69 *
70 * The SD, eMMC, and SDIO cards have the similar physical interface:
71 * clock, command line, and data lines.
72 * The SD card is removable and requires the SD card connector to connect
73 * to the PSoC device. This connector also has the card_mech_write_prot switch
74 * for mechanical write protection and the card_detect_n switch for card detection.
75 * The eMMC card also has DAT4-DAT7 pins for 8-bit mode and the EMMC_RESET pin.
76 * \image html sd_card_connector.png
77 * The driver has a low-level and high-level APIs.
78 * The low-level functions provide an easy method to read and write registers.
79 * Also, these functions allow valid interaction with an SD Card, eMMC card,
80 * and SDIO card.
81 * The high-level functions provide an easy mechanism to enumerate a device,
82 * read, write, and erase data. They are RTOS-friendly.
83 * When starting a command, these functions do not wait until the command completes.
84 * The interrupt and flags are used to check when the transfer completes.
85 * This allows to put RTOS delays in the user code.
86 *
87 * \section group_sd_host_section_Configuration_Considerations Configuration Considerations
88 * The SD Host driver configuration can be divided to a number of sequential
89 * steps listed below:
90 * * \ref group_sd_host_enable
91 * * \ref group_sd_host_pins
92 * * \ref group_sd_host_clock
93 * * \ref group_sd_host_intr
94 * * \ref group_sd_host_config
95 * * \ref group_sd_host_card_init
96 *
97 * \note
98 * The SD Host driver is built on top of the SDHC hardware block. The SDHC1 instance is
99 * used as an example for all code snippets. Modify the code to match your
100 * design.
101 *
102 * \subsection group_sd_host_enable Enable SD Host
103 * Enable the SDHC block calling \ref Cy_SD_Host_Enable.
104 *
105 * \subsection group_sd_host_pins Assign and Configure Pins
106 * Only dedicated SD Host pins can be used for SD Host operation. The HSIOM
107 * register must be configured to connect the block to the pins. Also, the SD Host
108 * pins must be configured in Strong Drive, Input buffer on:
109 *
110 * \snippet sd_host/snippet/main.c SD_HOST_CFG_PINS
111 *
112 * \subsection group_sd_host_clock Assign Clock Source
113 * The SD Host is sourced from the CLK_HF clock. The clock must be set to 100 MHz:
114 *
115 * \snippet sd_host/snippet/main.c SD_HOST_CFG_ASSIGN_CLOCK
116 *
117 * \subsection group_sd_host_intr Configure Interrupt (Optional)
118 * The user can set up the interrupt for SD Host operation.
119 * The user is responsible for writing its own Interrupt handler.
120 * The Interrupt must be called in the interrupt handler for the selected SDHC
121 * instance. Also this interrupt must be enabled in the NVIC otherwise
122 * it will not work.
123 * It is the user's responsibility to clear the normal and error interrupt statuses.
124 * The interrupt statuses can be read using \ref Cy_SD_Host_GetNormalInterruptStatus
125 * and \ref Cy_SD_Host_GetErrorInterruptStatus.
126 * To clear the interrupt statuses, use \ref Cy_SD_Host_ClearNormalInterruptStatus
127 * and \ref Cy_SD_Host_ClearErrorInterruptStatus.
128 *
129 * \snippet sd_host/snippet/main.c SD_HOST_INTR_A
130 * \snippet sd_host/snippet/main.c SD_HOST_INTR_B
131 *
132 * \subsection group_sd_host_config Configure SD Host
133 * To set up the SD Host driver, provide the configuration parameters in the
134 * \ref cy_stc_sd_host_init_config_t structure. Set the emmc parameter to true for
135 * the eMMC-device, otherwise set it to false. Set dmaType if DMA mode
136 * is used for read/write operations. The other parameters are optional for
137 * operation. To initialize the driver, call the \ref Cy_SD_Host_Init
138 * function providing a pointer to the filled \ref cy_stc_sd_host_init_config_t
139 * structure and allocated \ref cy_stc_sd_host_context_t.
140 *
141 * \snippet sd_host/snippet/main.c SD_HOST_CONTEXT
142 * \snippet sd_host/snippet/main.c SD_HOST_CFG
143 *
144 * The SD, eMMC or SDIO card can be configured using the \ref Cy_SD_Host_InitCard
145 * function as a pointer to the filled \ref cy_stc_sd_host_sd_card_config_t
146 * structure and allocated \ref cy_stc_sd_host_context_t.
147 *
148 * \subsection group_sd_host_card_init Initialize the card
149 * Finally, enable the card operation calling
150 * \ref Cy_SD_Host_InitCard.
151 *
152 * \snippet sd_host/snippet/main.c SD_HOST_ENABLE_CARD_INIT
153 *
154 * \section group_sd_host_use_cases Common Use Cases
155 *
156 * \subsection group_sd_host_sd_card_mode SD card Operation
157 * The master API is divided into two categories:
158 * \ref group_sd_host_high_level_functions and
159 * \ref group_sd_host_low_level_functions. Therefore, there are two
160 * methods for initiating SD card transactions using either <b>Low-Level</b> or
161 * <b>High-Level</b> API.
162 *
163 * \subsubsection group_sd_host_master_hl Use High-Level Functions
164 * Call \ref Cy_SD_Host_Read or \ref Cy_SD_Host_Write to
165 * communicate with the SD memory device. These functions do not block
166 * in DMA mode and only start a transaction. After a transaction starts,
167 * the user should check the further data-transaction complete event.
168 * The example below shows sending and reading data in DMA mode.
169 *
170 * \snippet sd_host/snippet/main.c SD_HOST_WRITE_READ_ADMA2
171 *
172 * \subsubsection group_sd_host_master_ll Use Low-Level Functions
173 * Call \ref Cy_SD_Host_InitDataTransfer to initialize the SD block
174 * for a data transfer. It does not start a transfer. To start a transfer
175 * call \ref Cy_SD_Host_SendCommand after calling this function.
176 * If DMA is not used for Data transfer then the buffer needs to be filled
177 * with data first if this is a write.
178 * Wait the transfer complete event.
179 * ADMA3 mode requires calling \ref Cy_SD_Host_InitDataTransfer to
180 * initialize the DMA transaction. The ADMA3 mode example is shown below.
181 *
182 * \snippet sd_host/snippet/main.c SD_HOST_WRITE_READ_ADMA3
183 *
184 * \subsection group_sd_host_emmc_card_mode eMMC Card Operation
185 * eMMC cards use the same API for writing and reading data.
186 * Additionally, eMMC requires configuring GPIO pins for DAT signals
187 * in 8-bit mode and card_emmc_reset_n pin if needed.
188 * The emmc member of \ref cy_stc_sd_host_init_config_t structure must
189 * be set to "true".
190 *
191 * \subsection group_sd_host_sdio_combo_card_mode eMMC SDIO or Combo Card Operation
192 * \ref Cy_SD_Host_InitCard() initializes all types of cards and
193 * automatically detects the card type: SD, SDIO or Combo card.
194 * SDIO cards have their input-output (I/O) functions that can be
195 * controlled using the GPIO driver.
196 * Combo Cards can use both I/O and memory API.
197 *
198 * \section group_sd_host_lp Low Power Support
199 * The SD Host does not operate in Hibernate and Deep Sleep modes but it
200 * can automatically continue write/read operation after restoring from
201 * Deep Sleep mode. SD CLK must be disabled before going to Deep Sleep mode
202 * and can be enabled after wake up from Deep Sleep mode.
203 * To reduce the power consumption in Active mode, the user can stop
204 * the clock of the SD bus but the following interrupts can be allowed:
205 * Card Insert, Card Removal and SDIO Interrupt.
206 *
207 * \section group_sd_host_remove_insert SD Card Removal and Insertion
208 * SD card removal or insertion can be detected by calling
209 * \ref Cy_SD_Host_GetNormalInterruptStatus which returns
210 * the card removal or card insertion events
211 * (CY_SD_HOST_CARD_REMOVAL or CY_SD_HOST_CARD_INSERTION bits).
212 * These events should be reset using
213 * \ref Cy_SD_Host_ClearNormalInterruptStatus when they occur.
214 * When the card is removed, the SDHC block disables the CMD/DAT output.
215 * It is recommended to set DAT pins to
216 * the Digital High-Z (CY_GPIO_DM_HIGHZ) drive mode when
217 * card removal is detected. This can be doing using the GPIO driver.
218 * When the card is inserted, the SDHC block automatically disables
219 * the card power and clock. After card insertion,
220 * the user should set the DAT pins drive mode back to Strong Drive,
221 * Input buffer on (CY_GPIO_DM_STRONG), and then call \ref Cy_SD_Host_InitCard.
222 * \note If CARD_INTERRUPT is enabled and DAT pins are not set to
223 * Digital High-Z drive mode then the interrupt will continuously
224 * trigger because the DAT1 line is driven low upon card re-insertion.
225 * The user will have to detect the card removal in the ISR handler,
226 * apply the power to the card using \ref Cy_SD_Host_EnableCardVoltage,
227 * set to the DAT pins drive mode to the Digital High-Z (CY_GPIO_DM_HIGHZ)
228 * and clear CY_SD_HOST_CARD_INTERRUPT bit
229 * using \ref Cy_SD_Host_ClearNormalInterruptStatus.
230 *
231 * \section group_sd_host_low_voltage_signaling Low Voltage Signaling
232 * When lowVoltageSignaling is true, the SD Host driver sets UHS-I mode
233 * during the card initialization. The SD Host driver always starts talking
234 * to the card at 3.3V and then later switches to 1.8V. There is no internal
235 * regulator in the PSoC 6 to change SD signals from 3.3V to 1.8V.
236 * Thus, an external regulator is needed for the VDDIO of the PSoC device
237 * to provide the ability to go from 3.3V to 1.8V.
238 * The SD Host driver sets the io_volt_sel pin to high which is used to
239 * control the external regulator.
240 * \image html sd_host_low_voltage_signaling.png
241 *
242 * \section group_sd_host_more_information More Information
243 *
244 * Refer to the appropriate device technical reference manual (TRM) for
245 * a detailed description of the registers.
246 *
247 * \section group_sd_host_Changelog Changelog
248 * <table class="doxtable">
249 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
250 * <tr>
251 * <td> 2.20</td>
252 * <td>Updated API \ref Cy_SD_Host_InitDataTransfer to check for CMD/DATA line BUSY status.
253 * Updated API \ref Cy_SD_Host_DeepSleepCallback to support SW retention after deep sleep in CAT1C devices. </td>
254 * <td>Defect fixing.</td>
255 * </tr>
256 * <tr>
257 * <td> 2.10</td>
258 * <td>Updated the behaviour of \ref Cy_SD_Host_AbortTransfer function to check the R1B response. Minor documentation updates.</td>
259 * <td>Defect fixing. Documentation enhancement.</td>
260 * </tr>
261 * <tr>
262 * <td> 2.0</td>
263 * <td>Added support for DDR50 mode and modified Cy_SD_Host_InitCard() API
264 * to set highest possible bus speed mode. Minor documentation updates.</td>
265 * <td>New feature implementation and documentation enhancement.</td>
266 * </tr>
267 * <tr>
268 * <td> 1.90</td>
269 * <td>Fixed the Cy_SD_Host_SoftwareReset() function behaviour.
270 * Now it waits until corresponding reset bit gets cleared by SDHC IP block.</td>
271 * <td>Defect fixing.</td>
272 * </tr>
273 * <tr>
274 * <td> 1.80</td>
275 * <td>Added an internal function.</td>
276 * <td>Code efficiency enhancement.</td>
277 * </tr>
278 * <tr>
279 * <td>1.70</td>
280 * <td>Allow SDIO Card initialization through Cy_SD_Host_InitCard() API.
281 * Added new API Cy_SD_Host_GetBlockCount().
282 * </td>
283 * <td>Code enhancement, minor defect fixing.</td>
284 * </tr>
285 * <tr>
286 * <td>1.60</td>
287 * <td>Fixed/Documented MISRA 2012 violations.</td>
288 * <td>MISRA 2012 compliance.</td>
289 * </tr>
290 * <tr>
291 * <td>1.50.1</td>
292 * <td>Minor documentation updates.</td>
293 * <td>Documentation enhancement.</td>
294 * </tr>
295 * <tr>
296 * <td>1.50</td>
297 * <td>The default value of the SD-clock rump-up time during a wakeup
298 * from Deep Sleep is reduced to 1 us, for details,
299 * see \ref Cy_SD_Host_DeepSleepCallback description.</td>
300 * <td>Optimization for cases of specific wakeup timing requirements.</td>
301 * </tr>
302 * <tr>
303 * <td>1.40</td>
304 * <td>Added a possibility to
305 * customize the SD-clock rump-up time during a wakeup from Deep Sleep,
306 * for details, see \ref Cy_SD_Host_DeepSleepCallback description.</td>
307 * <td>Workaround for cases of specific wakeup timing requirements.</td>
308 * </tr>
309 * <tr>
310 * <td>1.30</td>
311 * <td>The internal function implementation is changed.</td>
312 * <td>Code efficiency enhancement, minor defect fixing.</td>
313 * </tr>
314 * <tr>
315 * <td rowspan="2"> 1.20</td>
316 * <td>Added the Cy_SD_Host_DeepSleepCallback() function.</td>
317 * <td>Driver maintenance.</td>
318 * </tr>
319 * <tr>
320 * <td>Fixed the Cy_SD_Host_GetCsd() function behaviour.
321 * Now the cy_stc_sd_host_context_t::maxSectorNum is being updated correctly</td>
322 * <td>Defect fixing.</td>
323 * </tr>
324 * <tr>
325 * <td> 1.10.1</td>
326 * <td>Documentation of the MISRA rule violation.</td>
327 * <td>MISRA compliance.</td>
328 * </tr>
329 * <tr>
330 * <td>1.10</td>
331 * <td>The PLL and CLK disable sequence in \ref Cy_SD_Host_DisableSdClk()
332 * is changed to disable CLK first.<br>
333 * The Low-Power Support section is updated with additional
334 * information about disabling CLK.<br>
335 * The context initialization in \ref Cy_SD_Host_Init() is corrected.<br>
336 * Updated the Write/Read sequence in \ref Cy_SD_Host_Read() and
337 * \ref Cy_SD_Host_Write()functions for non DMA mode.<br>
338 * </td>
339 * <td>Defect fixing.</td>
340 * </tr>
341 * <tr>
342 * <td>1.0</td>
343 * <td>The initial version.</td>
344 * <td></td>
345 * </tr>
346 * </table>
347 *
348 * \defgroup group_sd_host_macros Macros
349 * \{
350 * \defgroup group_sd_host_macros_general_purpose General Purpose Macros
351 * \defgroup group_sd_host_macros_card_states Card States
352 * \{
353 * The masks below can be used to check the CURRENT_STATE bitfield
354 * of the \ref Cy_SD_Host_GetCardStatus function return value.
355 * \}
356 * \defgroup group_sd_host_macros_card_status Card Status (CMD13) Bits
357 * \{
358 * The masks below can be used with the
359 * \ref Cy_SD_Host_GetCardStatus function.
360 * \}
361 * \defgroup group_sd_host_macros_scr SCR Register Masks
362 * \{
363 * The masks below can be used with the
364 * \ref Cy_SD_Host_GetScr function.
365 * \}
366 * \defgroup group_sd_host_macros_cid CID Register Masks
367 * \{
368 * The masks below can be used with the
369 * \ref Cy_SD_Host_GetCid function.
370 * \}
371 * \defgroup group_sd_host_macros_csd CSD Register Masks
372 * \{
373 * The masks below are for CSD Register Version 2.0 and can be
374 * used with the \ref Cy_SD_Host_GetCsd function.
375 * \}
376 * \defgroup group_sd_host_macros_events SD Host Events
377 * \{
378 * The constants below can be used with
379 * \ref Cy_SD_Host_GetNormalInterruptStatus,
380 * \ref Cy_SD_Host_ClearNormalInterruptStatus,
381 * \ref Cy_SD_Host_GetErrorInterruptStatus and
382 * \ref Cy_SD_Host_ClearErrorInterruptStatus functions.
383 * Each event is encoded in a separate bit, and therefore it is possible to
384 * notify about multiple events.
385 * \}
386 * \defgroup group_sd_host_macros_present_status SD Host Present Status
387 * \{
388 * The constants below can be used with the
389 * \ref Cy_SD_Host_GetPresentState function.
390 * Each status is encoded in a separate bit, and therefore it is possible to
391 * notify about multiple statuses.
392 * \}
393 * \}
394 * \defgroup group_sd_host_functions Functions
395 * \{
396 * \defgroup group_sd_host_high_level_functions High-Level
397 * \defgroup group_sd_host_low_level_functions Low-Level
398 * \defgroup group_sd_host_interrupt_functions Interrupt
399 * \}
400 * \defgroup group_sd_host_data_structures Data Structures
401 * \defgroup group_sd_host_enums Enumerated Types
402 */
403
404 #ifndef CY_SD_HOST_PDL_H
405 #define CY_SD_HOST_PDL_H
406
407 #include "cy_device.h"
408
409 #if defined (CY_IP_MXSDHC)
410
411 #include <stdbool.h>
412 #include <stddef.h>
413 #include "cy_syslib.h"
414 #include "cy_syspm.h"
415
416 #if defined (__CC_ARM)
417 #pragma anon_unions
418 #endif
419
420 /* C binding of definitions if building with C++ compiler */
421 #ifdef __cplusplus
422 extern "C"
423 {
424 #endif
425
426 /**
427 * \addtogroup group_sd_host_macros_general_purpose
428 * \{
429 */
430
431 /** Driver major version */
432 #define CY_SD_HOST_DRV_VERSION_MAJOR 2
433
434 /** Driver minor version */
435 #define CY_SD_HOST_DRV_VERSION_MINOR 20
436
437 /******************************************************************************
438 * API Constants
439 ******************************************************************************/
440
441 #define CY_SD_HOST_ID CY_PDL_DRV_ID(0x3AU) /**< SD_HOST PDL ID */
442
443 #define CY_SD_HOST_BLOCK_SIZE (512UL) /**< The SD memory card block size. */
444
445 #define CY_SD_HOST_SDSC_ADDR_SHIFT (9U) /**< This constant is used to get the
446 * address for the SDSC card using the
447 * shift operation instead of multiply to 512.
448 */
449
450 /* SD output clock. */
451 #define CY_SD_HOST_CLK_25M (25UL * 1000UL * 1000UL) /**< Clk = 25 MHz. */
452 #define CY_SD_HOST_CLK_50M (50UL * 1000UL * 1000UL) /**< Clk = 50 MHz. */
453 #define CY_SD_HOST_CLK_100M (100UL * 1000UL * 1000UL) /**< Clk = 100 MHz. */
454
455 #define CY_SD_HOST_CLK_RAMP_UP_TIME_MS (100UL) /**< The host power ramp up time. */
456
457 #ifndef CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP /* Define of the CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP
458 * suppresses CY_SD_HOST_CLK_RAMP_UP_TIME_MS_WAKEUP
459 */
460 #ifndef CY_SD_HOST_CLK_RAMP_UP_TIME_MS_WAKEUP /*
461 * This is legacy constant.
462 * It is left here just for backward compatibility.
463 * Do not use it in new designs.
464 */
465 #define CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP (1U) /**< The default host power ramp up time during wake up from deep sleep. */
466 #else
467 #define CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP (CY_SD_HOST_CLK_RAMP_UP_TIME_MS_WAKEUP * 1000U)
468 #endif /* !defined CY_SD_HOST_CLK_RAMP_UP_TIME_MS_WAKEUP */
469 #endif /* !defined CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP */
470
471 /* ADMA constants. */
472 #define CY_SD_HOST_ADMA_NOP (0x0UL) /**< Does not execute the current line and go to next line. */
473 #define CY_SD_HOST_ADMA_RSV (0x2UL) /**< Reserved. */
474 #define CY_SD_HOST_ADMA_TRAN (0x4UL) /**< Transfers data of one descriptor line. */
475 #define CY_SD_HOST_ADMA_LINK (0x6UL) /**< The link to another descriptor. */
476 #define CY_SD_HOST_ADMA3_CMD (0x1UL) /**< The Command descriptor. */
477 #define CY_SD_HOST_ADMA3_INTERGRATED (0x7UL) /**< The Integrated descriptor. */
478 #define CY_SD_HOST_ADMA2_DESCR_SIZE (0x2UL) /**< The ADMA2 descriptor size. */
479
480 /* ADMA descriptor table positions. */
481 #define CY_SD_HOST_ADMA_ATTR_VALID_POS (0U) /**< The ADMA Attr Valid position. */
482 #define CY_SD_HOST_ADMA_ATTR_END_POS (1U) /**< The ADMA Attr End position. */
483 #define CY_SD_HOST_ADMA_ATTR_INT_POS (2U) /**< The ADMA Attr Int position. */
484 #define CY_SD_HOST_ADMA_ACT_POS (3U) /**< The ADMA Act position. */
485 #define CY_SD_HOST_ADMA_RESERVED2_POS (6U) /**< The ADMA Reserved2 position. */
486 #define CY_SD_HOST_ADMA_LEN_POS (16U) /**< The ADMA Len position. */
487
488 /** \cond INTERNAL_MACROS */
489
490 #define CY_SD_HOST_EMMC_T_RSTW_US (1U)
491 #define CY_SD_HOST_EMMC_T_RSCA_US (200U)
492 #define CY_SD_HOST_INIT_CLK_FREQUENCY_KHZ (400U) /* The CLK frequency in kHz during card initialization. */
493 #define CY_SD_HOST_3_PERIODS_US (((1000U * 3U) / CY_SD_HOST_INIT_CLK_FREQUENCY_KHZ) + 1U)
494
495 /** \endcond */
496
497 /** \} group_sd_host_macros_general_purpose */
498
499 /**
500 * \addtogroup group_sd_host_macros_card_states
501 * \{
502 */
503
504 #define CY_SD_HOST_CARD_IDLE (0x0UL) /**< The card idle state. */
505 #define CY_SD_HOST_CARD_READY (0x1UL) /**< The card ready state. */
506 #define CY_SD_HOST_CARD_IDENT (0x2UL) /**< The card identification state. */
507 #define CY_SD_HOST_CARD_STBY (0x3UL) /**< The card stand-by state. */
508 #define CY_SD_HOST_CARD_TRAN (0x4UL) /**< The card transition state. */
509 #define CY_SD_HOST_CARD_DATA (0x5UL) /**< The card sending-data state. */
510 #define CY_SD_HOST_CARD_RCV (0x6UL) /**< The card receive-data state. */
511 #define CY_SD_HOST_CARD_PRG (0x7UL) /**< The card programming state. */
512 #define CY_SD_HOST_CARD_DIS (0x8UL) /**< The card disconnect state. */
513
514 /** \} group_sd_host_macros_card_states */
515
516 /**
517 * \addtogroup group_sd_host_macros_card_status
518 * \{
519 */
520
521 #define CY_SD_HOST_CMD13_OUT_OF_RANGE (31U) /**< The command's argument is out of range. */
522 #define CY_SD_HOST_CMD13_ADDRESS_ERROR (30U) /**< The address does not match the block length. */
523 #define CY_SD_HOST_CMD13_BLOCK_LEN_ERROR (29U) /**< The block length is not allowed for this card. */
524 #define CY_SD_HOST_CMD13_ERASE_SEQ_ERROR (28U) /**< An error in the sequence of erase commands occurred. */
525 #define CY_SD_HOST_CMD13_ERASE_PARAM (27U) /**< An invalid selection of write blocks for erase occurred. */
526 #define CY_SD_HOST_CMD13_WP_VIOLATION (26U) /**< The host attempts to write to a protected block
527 * or to the permanent write-protected card.
528 */
529 #define CY_SD_HOST_CMD13_CARD_IS_LOCKED (25U) /**< The card is locked by the host. */
530 #define CY_SD_HOST_CMD13_LOCK_ULOCK_FAILED (24U) /**< A sequence or password error occurred
531 * has been detected in the lock/unlock card command.
532 */
533 #define CY_SD_HOST_CMD13_COM_CRC_ERROR (23U) /**< The CRC of the previous command failed. */
534 #define CY_SD_HOST_CMD13_ILLEGAL_COMMAND (22U) /**< The command is not legal for the card state. */
535 #define CY_SD_HOST_CMD13_CARD_ECC_FAILED (21U) /**< The card internal ECC failed. */
536 #define CY_SD_HOST_CMD13_CC_ERROR (20U) /**< An internal card-controller error. */
537 #define CY_SD_HOST_CMD13_ERROR (19U) /**< A general or unknown error occurred. */
538 #define CY_SD_HOST_CMD13_CSD_OVERWRITE (16U) /**< Can be either one of the following
539 * errors:
540 * - The read only section of the CSD
541 * does not match the card content.
542 * - An attempt to reverse the copy (set
543 * as original) or permanent WP
544 * (unprotected) bits was made.
545 */
546 #define CY_SD_HOST_CMD13_WP_ERASE_SKIP (15U) /**< Set when only partial address space
547 * was erased due to existing write protected blocks
548 * or a temporary or permanent write protected
549 * card was erased.
550 */
551 #define CY_SD_HOST_CMD13_CARD_ECC_DISABLED (14U) /**< The command has been executed
552 * without using the internal ECC.
553 */
554 #define CY_SD_HOST_CMD13_CURRENT_STATE (9U) /**< The state of the card. */
555 #define CY_SD_HOST_CMD13_READY_FOR_DATA (8U) /**< The buffer is empty on the bus. */
556 #define CY_SD_HOST_CMD13_APP_CMD (5U) /**< The card will expect ACMD, or an
557 * indication that the command has
558 * been interpreted as ACMD.
559 */
560 #define CY_SD_HOST_CMD13_AKE_SEQ_ERROR (3U) /**< Error in the sequence of the
561 * authentication process.
562 */
563
564 #define CY_SD_HOST_CMD13_CURRENT_STATE_MSK (0x00001E00UL) /**< The current state mask of the card. */
565
566 /** \} group_sd_host_macros_card_status */
567
568 /**
569 * \addtogroup group_sd_host_macros_scr
570 * \{
571 */
572
573 #define CY_SD_HOST_SCR_SCR_STRUCTURE (0x000000F0UL) /**< Version number of the related SCR structure
574 * in the SD Memory Card Physical Layer Specification.
575 */
576
577 #define CY_SD_HOST_SCR_SD_SPEC (0x0000000FUL) /**< Describes the SD Memory Card Physical Layer
578 * Specification version supported by this card.
579 */
580
581 #define CY_SD_HOST_SCR_DATA_STAT_AFTER_ERASE (0x00008000UL) /**< Defines the data status after erase,
582 * whether it is '0' or '1' (the status is
583 * card vendor dependent).
584 */
585
586 #define CY_SD_HOST_SCR_SD_SECURITY (0x00007000UL) /**< Describes the security algorithm
587 * supported by the card.
588 */
589
590 #define CY_SD_HOST_SCR_SD_BUS_WIDTHS (0x00000F00UL) /**< Describes all the DAT bus widths that
591 * are supported by this card.
592 */
593
594 /** \} group_sd_host_macros_scr */
595
596 /**
597 * \addtogroup group_sd_host_macros_cid
598 * \{
599 */
600
601 #define CY_SD_HOST_SCR_CID_MDT (0x00000FFFUL) /**< The manufacturing date is composed of
602 * two hexadecimal digits (contained in cid[0]),
603 * one is 8 bits representing the year(y) and the
604 * other is 4 bits representing the month (m).
605 * The "m" field [11:8] is the month code. 1 = January.
606 * The "y" field [19:12] is the year code. 0 = 2000.
607 * As an example, the binary value of the Date field
608 * for production date "April 2018" will be:
609 * 00010010 0100.
610 */
611
612 #define CY_SD_HOST_SCR_CID_PSN_LSB (0xFFFF0000UL) /**< The mask for LSB part of the Serial Number
613 * (contained in cid[0]). The Serial Number is
614 * 32 bits of binary number.
615 */
616
617 #define CY_SD_HOST_SCR_CID_PSN_MSB (0x0000FFFFUL) /**< The mask for MSB part of the Serial Number
618 * (contained in cid[1]). The Serial Number is
619 * 32 bits of binary number.
620 */
621
622 #define CY_SD_HOST_SCR_CID_PRV (0x00FF0000UL) /**< The product revision is composed of two
623 * Binary Coded Decimal (BCD) digits (contained in cid[1]),
624 * four bits each, representing an "n.m" revision number.
625 * The "n" is the most significant nibble and "m" is the
626 * least significant nibble.
627 * As an example, the PRV binary value field for product
628 * revision "6.2" will be: 0110 0010b.
629 */
630
631 #define CY_SD_HOST_SCR_CID_PNM_LSB (0xFF000000UL) /**< The mask for LSB part (the first 8 bits) of the
632 * product name (contained in cid[1]). The product
633 * name is a string, 5-character ASCII string.
634 * As an example, the PNM hex value field for product name
635 * "EB1QT" will be: 0x4542315154.
636 */
637
638 #define CY_SD_HOST_SCR_CID_PNM_MSB (0xFFFFFFFFUL) /**< The mask for MSB part (the last 32 bits) of the
639 * product name (contained in cid[2]). The product
640 * name is a string, 5-character ASCII string.
641 * As an example, the PNM hex value field for product name
642 * "EB1QT" will be: 0x4542315154.
643 */
644
645 #define CY_SD_HOST_SCR_CID_OID (0x0000FFFFUL) /**< The mask for the OID (contained in cid[3]).
646 * The OID is a 2-character ASCII string that
647 * identifies the card OEM and/or the card contents
648 * (when used as a distribution media either on ROM or
649 * FLASH cards). The OID number is controlled, defined,
650 * and allocated to a SD Memory Card manufacturer by
651 * the SD-3C, LLC. This procedure is established to ensure
652 * uniqueness of the CID register.
653 * As an example, the OID hex value field for the card OEM
654 * "SM" will be: 0x534D.
655 */
656
657 #define CY_SD_HOST_SCR_CID_MID (0x00FF0000UL) /**< The mask for the MID (contained in cid[3]).
658 * MID is a 8-bit binary number that identifies the
659 * card manufacturer. The MID number is controlled,
660 * defined, and allocated to a SD Memory Card manufacturer
661 * by the SD-3C, LLC. This procedure is established to
662 * ensure uniqueness of the CID register.
663 */
664
665 /** \} group_sd_host_macros_cid */
666
667 /**
668 * \addtogroup group_sd_host_macros_csd
669 * \{
670 */
671
672 #define CY_SD_HOST_CSD_V2_CSD_STRUCTURE (0x0000FF00UL) /**< CSD structure (contained in csd[3]) */
673
674 #define CY_SD_HOST_CSD_V2_TAAC (0x0000FF00UL) /**< The data read access-time (contained in csd[3]).
675 * This field is fixed to 0Eh, which indicates 1 ms.
676 */
677
678 #define CY_SD_HOST_CSD_V2_NSAC (0x000000FFUL) /**< The data read access-time in CLK cycles (NSAC*100)
679 * (contained in csd[3]).
680 * This field is fixed to 00h. NSAC should not
681 * be used to calculate time-out values
682 * for CSD Version 2.0.
683 */
684
685 #define CY_SD_HOST_CSD_V2_TRAN_SPEED (0xFF000000UL) /**< The max. data transfer rate (contained in csd[2]).
686 * Equals to 0x32 (25 MHz) or 0x5A (50 MHz).
687 */
688
689 #define CY_SD_HOST_CSD_V2_CCC (0x00FFF000UL) /**< The card command classes (contained in csd[2]).
690 * The card command class register CCC defines which
691 * command classes are supported by this card.
692 * A value of 1 in a CCC bit means that the
693 * corresponding command class is supported.
694 */
695
696 #define CY_SD_HOST_CSD_V2_READ_BL_LEN (0x00000F00UL) /**< The max. read data block length (contained in csd[2]).
697 * This field is fixed to 9h, which
698 * indicates READ_BL_LEN=512 Byte.
699 */
700
701 #define CY_SD_HOST_CSD_V2_READ_BL_PARTIAL (0x00000080UL) /**< The partial blocks for read allowed (contained in csd[2]).
702 * This field is fixed to 0, which indicates
703 * partial block read is inhibited and only unit
704 * of block access is allowed.
705 */
706
707 #define CY_SD_HOST_CSD_V2_WRITE_BLK_MISALIGN (0x00000040UL) /**< The write block misalignment (contained in csd[2]).
708 * This field is fixed to 0, which indicates
709 * write access crossing physical block boundaries
710 * is always disabled in High Capacity SD Memory Card.
711 */
712
713 #define CY_SD_HOST_CSD_V2_READ_BLK_MISALIGN (0x00000020UL) /**< The read block misalignment (contained in csd[2]).
714 * This field is fixed to 0, which indicates
715 * read access crossing physical block boundaries
716 * is always disabled in High Capacity SD Memory Card.
717 */
718
719 #define CY_SD_HOST_CSD_V2_DSR_IMP (0x00000010UL) /**< The DSR implemented (contained in csd[2]).
720 * Defines if the configurable driver stage is
721 * integrated on the card.
722 */
723
724 #define CY_SD_HOST_CSD_V2_C_SIZE_MASK (0x3FFFFF00UL) /**< The device size (contained in csd[1]).
725 * This parameter is used to calculate the
726 * user data area capacity in the SD memory card
727 * (not include the protected area).
728 * The user data area capacity is calculated
729 * from C_SIZE as follows:
730 * memory capacity = (C_SIZE+1) * 512K byte.
731 */
732
733 #define CY_SD_HOST_CSD_V2_ERASE_BLK_EN (0x00000040UL) /**< The erase single block enable (contained in csd[1]).
734 * This field is fixed to 1, which means the
735 * host can erase one or multiple units of 512 bytes.
736 */
737
738 #define CY_SD_HOST_CSD_V2_SECTOR_SIZE_MSB (0x0000003FUL) /**< The MSB of erase sector size (6 MSB bits contained in csd[1]).
739 * SECTOR_SIZE is fixed to 7Fh, which indicates 64 KBytes.
740 * This value does not relate to erase operation.
741 * Version 2.00 cards indicates memory boundary by
742 * AU size and this field should not be used.
743 */
744
745 #define CY_SD_HOST_CSD_V2_SECTOR_SIZE_LSB (0x80000000UL) /**< The LSB of erase sector size
746 * (1 LSB bit of SECTOR_SIZE contained in csd[0]).
747 */
748
749 #define CY_SD_HOST_CSD_V2_WP_GRP_SIZE (0x7F000000UL) /**< The write protect group size (contained in csd[0]).
750 * This field is fixed to 00h. The High Capacity
751 * SD Memory Card does not support write protected groups.
752 */
753
754 #define CY_SD_HOST_CSD_V2_WP_GRP_ENABLE (0x00800000UL) /**< The write protect group enable (contained in csd[0]).
755 * This field is fixed to 0. The High Capacity SD Memory
756 * Card does not support write protected groups.
757 */
758
759 #define CY_SD_HOST_CSD_V2_R2W_FACTOR (0x001C0000UL) /**< The write speed factor (contained in csd[0]).
760 * This field is fixed to 2h, which indicates 4 multiples.
761 */
762
763 #define CY_SD_HOST_CSD_V2_WRITE_BL_LEN (0x0003C000UL) /**< The max. write data block length (contained in csd[0]).
764 * This field is fixed to 9h, which indicates
765 * WRITE_BL_LEN=512 Byte.
766 */
767
768 #define CY_SD_HOST_CSD_V2_WRITE_BL_PARTIAL (0x00002000UL) /**< The partial blocks for write allowed (contained in csd[0]).
769 * This field is fixed to 0, which indicates partial
770 * block read is inhibited and only unit of block
771 * access is allowed.
772 */
773
774 #define CY_SD_HOST_CSD_V2_FILE_FORMAT_GRP (0x00000080UL) /**< The File format group (contained in csd[0]).
775 * This field is set to 0. Host should not use this field.
776 */
777
778 #define CY_SD_HOST_CSD_V2_COPY (0x00000040UL) /**< The copy flag (OTP) (contained in csd[0]).
779 * Defines if the contents is original (=0) or
780 * has been copied (=1). The COPY bit for OTP and MTP
781 * devices, sold to end consumers, is set to 1,
782 * which identifies the card contents as a copy.
783 * The COPY bit is a one time programmable bit.
784 */
785
786 #define CY_SD_HOST_CSD_V2_PERM_WRITE_PROTECT (0x00000020UL) /**< The permanent write protection (contained in csd[0]).
787 * Permanently protects the entire card content
788 * against overwriting or erasing (all write and erase
789 * commands for this card are permanently disabled).
790 * The default value is 0, i.e. not permanently write
791 * protected.
792 */
793
794 #define CY_SD_HOST_CSD_V2_TMP_WRITE_PROTECT (0x00000010UL) /**< The temporary write protection (contained in csd[0]).
795 * Temporarily protects the entire card content
796 * from being overwritten or erased (all write
797 * and erase commands for this card are temporarily
798 * disabled). This bit can be set and reset.
799 * The default value is 0, i.e. not write protected.
800 */
801
802 #define CY_SD_HOST_CSD_V2_FILE_FORMAT (0x0000000CUL) /**< The File format (contained in csd[0]).
803 * This field is set to 0. Host should not use this field.
804 */
805
806
807 /** \} group_sd_host_macros_csd */
808
809 /**
810 * \addtogroup group_sd_host_macros_events
811 * \{
812 */
813
814 /**
815 * Command complete. In SD/eMMC mode, this event is set
816 * after detecting the end bit of a response except for Auto CMD12 and Auto CMD23.
817 * This event is not generated when the Response Interrupt is disabled.
818 */
819 #define CY_SD_HOST_CMD_COMPLETE (0x0001U)
820
821 /**
822 * Transfer complete. This event is set when a read/write
823 * transfer and a command with the Busy Status are completed.
824 */
825 #define CY_SD_HOST_XFER_COMPLETE (0x0002U)
826
827 /**
828 * Block gap. This event is set when both read/write
829 * transactions are stopped at the block gap due to a
830 * Stop-at-Block-Gap Request.
831 */
832 #define CY_SD_HOST_BGAP (0x0004U)
833
834 /**
835 * DMA Interrupt. This event is set if the Host Controller
836 * detects a SDMA Buffer Boundary during a transfer.
837 * For ADMA, the Host controller generates this
838 * interrupt by setting the Int field in the
839 * descriptor table.
840 * This interrupt is not generated after a Transfer
841 * Complete.
842 */
843 #define CY_SD_HOST_DMA_INTERRUPT (0x0008U)
844
845 /**
846 * The Buffer Write is ready. This event is set if
847 * the Buffer Write Enable changes from 0 to 1.
848 */
849 #define CY_SD_HOST_BUF_WR_READY (0x0010U)
850
851 /**
852 * The Buffer Read is ready. This event is set if
853 * the Buffer Read Enable changes from 0 to 1.
854 */
855 #define CY_SD_HOST_BUF_RD_READY (0x0020U)
856
857 /**
858 * Card insertion. This event is set if
859 * the Card Inserted in the Present State
860 * register changes from 0 to 1.
861 */
862 #define CY_SD_HOST_CARD_INSERTION (0x0040U)
863
864 /**
865 * Card removal. This event is set if
866 * the Card Inserted in the Present State
867 * register changes from 1 to 0.
868 */
869 #define CY_SD_HOST_CARD_REMOVAL (0x0080U)
870
871 /**
872 * The Card interrupt. This event reflects the
873 * synchronized value of DAT[1] Interrupt Input for SD Mode
874 */
875 #define CY_SD_HOST_CARD_INTERRUPT (0x0100U)
876
877 /**
878 * FX event.
879 * This status is set when R[14] of the response register is set to 1
880 * and Response Type R1/R5 is set to 0 in the Transfer Mode
881 * register. This interrupt is used with the response check function.
882 */
883 #define CY_SD_HOST_FX_EVENT (0x2000U)
884
885 /**
886 * Command Queuing event.
887 * This status is set if a Command Queuing/Crypto related event
888 * has occurred in eMMC/SD mode.
889 */
890 #define CY_SD_HOST_CQE_EVENT (0x4000U)
891
892 /**
893 * Error Interrupt.
894 * If any of the bits in the Error Interrupt Status
895 * register are set, then this bit is set.
896 */
897 #define CY_SD_HOST_ERR_INTERRUPT (0x8000U)
898
899 /**
900 * Command timeout error. In SD/eMMC Mode,
901 * this event is set only if no response is returned
902 * within 64 SD clock cycles from the end bit of the
903 * command. If the Host Controller detects a CMD line conflict,
904 * along with Command CRC Error bit, this event is set to 1,
905 * without waiting for 64 SD/eMMC card clock cycles.
906 */
907 #define CY_SD_HOST_CMD_TOUT_ERR (0x0001U)
908
909 /**
910 * Command CRC error. A Command CRC Error is generated
911 * in SD/eMMC mode when:
912 * 1. A response is returned and the Command Timeout
913 * Error is set to 0 (indicating no timeout),
914 * this bit is set to 1 when detecting a CRC error
915 * in the command response.
916 * 2. The Host Controller detects a CMD line conflict by
917 * monitoring the CMD line when a command is issued. If
918 * the Host Controller drives the CMD line to level 1, but
919 * detects level 0 on the CMD line at the next SD clock
920 * edge, then the Host Controller aborts the command (stop
921 * driving CMD line) and sets this bit to 1. The Command
922 * Timeout Error is also set to 1 to distinguish a CMD line
923 * conflict.
924 */
925 #define CY_SD_HOST_CMD_CRC_ERR (0x0002U)
926
927 /**
928 * Command End Bit error.
929 * This bit is set after detecting that the end bit of a command
930 * response is 0 in SD/eMMC mode.
931 */
932 #define CY_SD_HOST_CMD_END_BIT_ERR (0x0004U)
933
934 /**
935 * Command Index error.
936 * This bit is set if a Command Index error occurs in the
937 * command response in SD/eMMC mode.
938 */
939 #define CY_SD_HOST_CMD_IDX_ERR (0x0008U)
940
941 /**
942 * Data Timeout error.
943 * This bit is set in SD/eMMC mode when detecting one of the
944 * following timeout conditions:
945 * * Busy timeout for R1b, R5b type
946 * * Busy timeout after Write CRC status
947 * * Write CRC Status timeout
948 * * Read Data timeout.
949 */
950 #define CY_SD_HOST_DATA_TOUT_ERR (0x0010U)
951
952 /**
953 * Data CRC error.
954 * This error occurs in SD/eMMC mode after detecting a CRC
955 * error while transferring read data that uses the DAT line,
956 * after detecting the Write CRC status having a value other
957 * than 010 or when writing a CRC status timeout.
958 */
959 #define CY_SD_HOST_DATA_CRC_ERR (0x0020U)
960
961 /**
962 * Data End Bit error.
963 * This error occurs in SD/eMMC mode either when detecting 0
964 * at the end bit position of read data that uses the DAT line or
965 * at the end bit position of the CRC status.
966 */
967 #define CY_SD_HOST_DATA_END_BIT_ERR (0x0040U)
968
969 /**
970 * Current Limit error.
971 * The SD Host driver does not support this function,
972 * this bit is always set to 0.
973 */
974 #define CY_SD_HOST_CUR_LMT_ERR (0x0080U)
975
976 /**
977 * Auto CMD error.
978 * This error status is used by Auto CMD12 and Auto CMD23 in
979 * SD/eMMC mode. This bit is set after detecting that any of
980 * the bits D00 to D05 in the Auto CMD Error Status register has
981 * changed from 0 to 1. D07 is effective in case for Auto CMD12.
982 * The Auto CMD Error Status register is valid while this bit is set to
983 * 1 and may be cleared by clearing this bit.
984 */
985 #define CY_SD_HOST_AUTO_CMD_ERR (0x0100U)
986
987 /**
988 * ADMA error.
989 * This bit is set when the Host Controller detects an error during
990 * an ADMA-based data transfer. The possible reasons for an error:
991 * * An error response is received from the System bus;
992 * * ADMA3, ADMA2 Descriptors are invalid;
993 * * CQE Task or Transfer descriptors are invalid.
994 * When an error occurs, the state of the ADMA is saved in the
995 * ADMA Error Status register.
996 */
997 #define CY_SD_HOST_ADMA_ERR (0x0200U)
998
999 /**
1000 * Tuning error.
1001 * The SD Host driver does not support this function.
1002 */
1003 #define CY_SD_HOST_TUNING_ERR (0x0400U)
1004
1005 /**
1006 * Response error.
1007 * Host Controller Version 4.00 supports the response error check
1008 * function to avoid overhead of the response error check by Host
1009 * Driver during DMA execution. If the Response Error Check
1010 * Enable is set to 1 in the Transfer Mode register, the Host
1011 * Controller checks R1 or R5 response. If an error is detected
1012 * in a response, this bit is set to 1. This is applicable in
1013 * SD/eMMC mode.
1014 */
1015 #define CY_SD_HOST_RESP_ERR (0x0800U)
1016
1017 /**
1018 * Boot Acknowledgement error.
1019 * This bit is set when there is a timeout for boot
1020 * acknowledgement or after detecting the boot ACK status having
1021 * a value other than 010. This is applicable only when boot
1022 * acknowledgement is expected in eMMC mode.
1023 */
1024 #define CY_SD_HOST_BOOT_ACK_ERR (0x1000U)
1025
1026 /** \} group_sd_host_macros_events */
1027
1028 /**
1029 * \addtogroup group_sd_host_macros_present_status
1030 * \{
1031 */
1032
1033 /**
1034 * Command Inhibit (CMD).
1035 * This bit indicates the following:
1036 * - SD/eMMC mode: If this bit is set to 0, it indicates that the
1037 * CMD line is not in use and the Host controller can issue
1038 * an SD/eMMC command using the CMD line. This bit is
1039 * set when the command register is written. This bit is
1040 * cleared when the command response is received. This bit
1041 * is not cleared by the response of auto CMD12/23 but
1042 * cleared by the response of the Read/Write command.
1043 */
1044 #define CY_SD_HOST_CMD_INHIBIT (0x00000001UL)
1045
1046 /**
1047 * Command Inhibit (DAT).
1048 * This bit is applicable for SD/eMMC mode and is generated if
1049 * either the DAT line active or Read transfer active is set to 1. If
1050 * this bit is set to 0, it indicates that the Host Controller can
1051 * issue subsequent SD/eMMC commands.
1052 */
1053 #define CY_SD_HOST_CMD_CMD_INHIBIT_DAT (0x00000002UL)
1054
1055 /**
1056 * DAT Line Active (SD/eMMC Mode only).
1057 * This bit indicates whether one of the DAT lines on the
1058 * SD/eMMC bus is in use.
1059 * For Read transactions, this bit indicates whether a
1060 * read transfer is executing on the SD/eMMC bus.
1061 * For Write transactions, this bit indicates whether a
1062 * write transfer is executing on the SD/eMMC bus.
1063 * For a command with the Busy status, this status indicates whether the
1064 * command executing busy is executing on an SD or eMMC
1065 * bus.
1066 */
1067 #define CY_SD_HOST_DAT_LINE_ACTIVE (0x00000004UL)
1068
1069 /**
1070 * DAT[7:4] Line Signal Level.
1071 * These bits are used to check the DAT line level to recover from
1072 * errors and for debugging. These bits reflect the value of the
1073 * sd_dat_in (upper nibble) signal.
1074 */
1075 #define CY_SD_HOST_DAT_7_4 (0x000000F0UL)
1076
1077 /**
1078 * Write Transfer Active
1079 * This status indicates whether the Write transfer is active for
1080 * SD/eMMC mode.
1081 */
1082 #define CY_SD_HOST_WR_XFER_ACTIVE (0x00000100UL)
1083
1084 /**
1085 * Read Transfer Active.
1086 * This bit indicates whether the Read transfer is active for
1087 * SD/eMMC mode.
1088 */
1089 #define CY_SD_HOST_RD_XFER_ACTIVE (0x00000200UL)
1090
1091 /**
1092 * Buffer Write Enable.
1093 * This bit is used for non-DMA transfers. This bit is set if space
1094 * is available for writing data.
1095 */
1096 #define CY_SD_HOST_BUF_WR_ENABLE (0x00000400UL)
1097
1098 /**
1099 * Buffer Read Enable.
1100 * This bit is used for non-DMA transfers. This bit is set if valid
1101 * data exists in the Host buffer.
1102 */
1103 #define CY_SD_HOST_BUF_RD_ENABLE (0x00000800UL)
1104
1105 /**
1106 * Card Inserted.
1107 * This bit indicates whether a card has been inserted. The
1108 * Host Controller debounces this signal so that the Host Driver
1109 * does not need to wait for the signal to stabilize.
1110 */
1111 #define CY_SD_HOST_CARD_INSERTED (0x00010000UL)
1112
1113 /**
1114 * Card Stable.
1115 * This bit indicates the stability of the Card Detect Pin Level. A
1116 * card is not detected if this bit is set to 1 and the value of the
1117 * CARD_INSERTED bit is 0.
1118 */
1119 #define CY_SD_HOST_CARD_STABLE (0x00020000UL)
1120
1121 /**
1122 * Card Detect Pin Level.
1123 * This bit reflects the inverse synchronized value of the
1124 * card_detect_n signal.
1125 */
1126 #define CY_SD_HOST_CARD_DETECT_PIN_LEVEL (0x00040000UL)
1127
1128 /**
1129 * Write Protect Switch Pin Level.
1130 * This bit is supported only for memory and combo cards. This
1131 * bit reflects the synchronized value of the card_write_prot
1132 * signal.
1133 */
1134 #define CY_SD_HOST_WR_PROTECT_SW_LVL (0x00080000UL)
1135
1136 /**
1137 * DAT[3:0] Line Signal Level.
1138 * This bit is used to check the DAT line level to recover from
1139 * errors and for debugging. These bits reflect the value of the
1140 * sd_dat_in (lower nibble) signal.
1141 */
1142 #define CY_SD_HOST_DAT_3_0 (0x00F00000UL)
1143
1144 /**
1145 * DAT[0] Line Signal Level.
1146 * This bit is used to check the DAT0 line level to check R1b
1147 * response. This bit reflects the value of the sd_dat_in[0]
1148 * signal.
1149 */
1150 #define CY_SD_HOST_DAT_0_Msk (0x00100000UL)
1151
1152 /**
1153 * Command-Line Signal Level.
1154 * This bit is used to check the CMD line level to recover from
1155 * errors and for debugging. These bits reflect the value of the
1156 * sd_cmd_in signal.
1157 */
1158 #define CY_SD_HOST_CMD_LINE_LVL (0x01000000UL)
1159
1160 /**
1161 * Host Regulator Voltage Stable.
1162 * This bit is used to check whether the host regulator voltage is
1163 * stable for switching the voltage of UHS-I mode. This bit
1164 * reflects the synchronized value of the host_reg_vol_stable
1165 * signal.
1166 */
1167 #define CY_SD_HOST_HOST_REG_VOL (0x02000000UL)
1168
1169 /**
1170 * Command Not Issued by Error.
1171 * This bit is set if a command cannot be issued after setting
1172 * the command register due to an error except an Auto
1173 * CMD12 error.
1174 */
1175 #define CY_SD_HOST_CMD_ISSU_ERR (0x08000000UL)
1176
1177 /**
1178 * Sub Command Status.
1179 * This bit is used to distinguish between a main command and
1180 * a sub command status.
1181 */
1182 #define CY_SD_HOST_SUB_CMD_STAT (0x10000000UL)
1183
1184 /**
1185 * In Dormant Status.
1186 * This bit indicates whether UHS-II lanes enter the Dormant state
1187 * in the UHS-II mode. For SD/eMMC mode, this bit always
1188 * returns 0.
1189 */
1190 #define CY_SD_HOST_IN_DORMANT_ST (0x20000000UL)
1191
1192 /**
1193 * Lane Synchronization.
1194 * This bit indicates whether a lane is synchronized in UHSII
1195 * mode. For SD/eMMC mode, this bit always returns 0.
1196 */
1197 #define CY_SD_HOST_LANE_SYNC (0x40000000UL)
1198
1199 /**
1200 * UHS-II Interface Detection.
1201 * This bit indicates whether a card supports the UHS-II
1202 * interface. For SD/eMMC mode, this bit always returns 0.
1203 */
1204 #define CY_SD_HOST_UHS2_IF_DETECT (0x80000000UL)
1205
1206 /** \} group_sd_host_macros_present_status */
1207
1208
1209 /**
1210 * \addtogroup group_sd_host_enums
1211 * \{
1212 */
1213
1214 /******************************************************************************
1215 * Enumerations
1216 *****************************************************************************/
1217
1218 /** SD command types. */
1219 typedef enum
1220 {
1221 CY_SD_HOST_CMD_NORMAL = 0U, /**< Other commands */
1222 CY_SD_HOST_CMD_SUSPEND = 1U, /**< CMD52 for writing "Bus Suspend" in CCCR */
1223 CY_SD_HOST_CMD_RESUME = 2U, /**< CMD52 for writing "Function Select" in CCCR */
1224 CY_SD_HOST_CMD_ABORT = 3U /**< CMD12, CMD52 for writing "I/O Abort" in CCCR */
1225 }cy_en_sd_host_cmd_type_t;
1226
1227 /** SD Host auto command enable selection. */
1228 typedef enum
1229 {
1230 CY_SD_HOST_AUTO_CMD_NONE = 0U, /**< Auto command disable. */
1231 CY_SD_HOST_AUTO_CMD_12 = 1U, /**< Auto command 12 enable. */
1232 CY_SD_HOST_AUTO_CMD_23 = 2U, /**< Auto command 23 enable. */
1233 CY_SD_HOST_AUTO_CMD_AUTO = 3U /**< Auto command Auto enable. */
1234 }cy_en_sd_host_auto_cmd_t;
1235
1236 /** SD Host reset types. */
1237 typedef enum
1238 {
1239 CY_SD_HOST_RESET_DATALINE = 0U, /**< Reset the data circuit only. */
1240 CY_SD_HOST_RESET_CMD_LINE = 1U, /**< Reset the command circuit only. */
1241 CY_SD_HOST_RESET_ALL = 2U /**< Reset the whole SD Host controller. */
1242 }cy_en_sd_host_reset_t;
1243
1244 /** SD Host error interrupt types. */
1245 typedef enum
1246 {
1247 CY_SD_HOST_ADMA_ST_STOP = 0U, /**< Stop DMA - The SYS_ADR register points to
1248 * a location next to the error descriptor.
1249 */
1250 CY_SD_HOST_ADMA_ST_FDS = 1U, /**< Fetch Descriptor - The SYS_ADR register
1251 * points to the error descriptor.
1252 */
1253 CY_SD_HOST_ADMA_ST_TFR = 3U, /**< Transfer Data - SYS_ADR register points
1254 * to a location next to the error descriptor.
1255 */
1256 CY_SD_HOST_ADMA_LEN_ERR = 4U /**< The ADMA Length Mismatch error. */
1257 }cy_en_sd_host_adma_error_t;
1258
1259 /** Auto CMD Status error codes. */
1260 typedef enum
1261 {
1262 CY_SD_HOST_AUTO_CMD12_NOT_EXEC = 0U, /**< Auto CMD12 Not Executed. */
1263 CY_SD_HOST_AUTO_CMD_TOUT_ERR = 1U, /**< Auto CMD Timeout Error. */
1264 CY_SD_HOST_AUTO_CMD_CRC_ERR = 2U, /**< Auto CMD CRC Error. */
1265 CY_SD_HOST_AUTO_CMD_EBIT_ERR = 3U, /**< Auto CMD End Bit Error. */
1266 CY_SD_HOST_AUTO_CMD_IDX_ERR = 4U, /**< Auto CMD Index Error. */
1267 CY_SD_HOST_AUTO_CMD_RESP_ERR = 5U, /**< Auto CMD Response Error. */
1268 CY_SD_HOST_CMD_NOT_ISSUED_AUTO_CMD12 = 7U /**< Command Not Issued By Auto CMD12 Error. */
1269 } cy_en_sd_host_auto_cmd_status_t;
1270
1271 /** SD host error codes. */
1272 typedef enum
1273 {
1274 CY_SD_HOST_SUCCESS = 0U, /**< Successful. */
1275 CY_SD_HOST_ERROR = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 1U, /**< Non-specific error code. */
1276 CY_SD_HOST_ERROR_INVALID_PARAMETER = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 2U, /**< The provided parameter is not valid. */
1277 CY_SD_HOST_ERROR_OPERATION_IN_PROGRESS = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 3U, /**< A conflicting or requested operation is still in progress. */
1278 CY_SD_HOST_ERROR_UNINITIALIZED = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 4U, /**< The module (or part of it) was not initialized properly. */
1279 CY_SD_HOST_ERROR_TIMEOUT = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 5U, /**< A Time Out error occurred */
1280 CY_SD_HOST_OPERATION_INPROGRESS = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 6U, /**< The indicator for operation in progress. */
1281 CY_SD_HOST_ERROR_UNUSABLE_CARD = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 7U, /**< The card is unusable. */
1282 CY_SD_HOST_ERROR_DISCONNECTED = CY_SD_HOST_ID | CY_PDL_STATUS_ERROR | 8U /**< The card is disconnected. */
1283 } cy_en_sd_host_status_t;
1284
1285 /** The widths of the data bus. */
1286 typedef enum
1287 {
1288 CY_SD_HOST_BUS_WIDTH_1_BIT = 0U, /**< The 1-bit mode data transfer width. */
1289 CY_SD_HOST_BUS_WIDTH_4_BIT = 1U, /**< The 4-bit mode data transfer width. */
1290 CY_SD_HOST_BUS_WIDTH_8_BIT = 2U /**< The 8-bit mode data transfer width. */
1291 } cy_en_sd_host_bus_width_t;
1292
1293 /** The bus speed modes. */
1294 typedef enum
1295 {
1296 CY_SD_HOST_BUS_SPEED_DEFAULT = 0U, /**< Default Speed mode: 3.3V signaling at 25 MHz SDClk. */
1297 CY_SD_HOST_BUS_SPEED_HIGHSPEED = 1U, /**< High Speed mode: 3.3V signaling at 50 MHz SDClk. */
1298 CY_SD_HOST_BUS_SPEED_SDR12_5 = 2U, /**< SDR12: UHS-I (1.8V signaling) at 25 MHz SDClk (12.5 MB/sec). */
1299 CY_SD_HOST_BUS_SPEED_SDR25 = 3U, /**< SDR25: UHS-I (1.8V signaling) at 50 MHz SDClk (25 MB/sec). */
1300 CY_SD_HOST_BUS_SPEED_SDR50 = 4U, /**< SDR50: UHS-I (1.8V signaling) at 100 MHz SDClk (50 MB/sec). */
1301 CY_SD_HOST_BUS_SPEED_EMMC_LEGACY = 5U, /**< Backwards Compatibility with legacy MMC card (26MB/sec max). */
1302 CY_SD_HOST_BUS_SPEED_EMMC_HIGHSPEED_SDR = 6U, /**< eMMC High speed SDR (52MB/sec max) */
1303 CY_SD_HOST_BUS_SPEED_DDR50 = 7U /**< DDR50: UHS-I (1.8V signaling) at 50 MHz SDClk (50 MB/sec). */
1304 } cy_en_sd_host_bus_speed_mode_t;
1305
1306 /** The SD bus voltage select. */
1307 typedef enum
1308 {
1309 CY_SD_HOST_IO_VOLT_3_3V = 0U, /**< 3.3V.*/
1310 CY_SD_HOST_IO_VOLT_1_8V = 1U /**< 1.8V. */
1311 } cy_en_sd_host_io_voltage_t;
1312
1313 /** Erase type. */
1314 typedef enum
1315 {
1316 CY_SD_HOST_ERASE_ERASE = 0U, /**< The ERASE operation.*/
1317 CY_SD_HOST_ERASE_DISCARD = 1U, /**< The DISCARD operation. */
1318 CY_SD_HOST_ERASE_FULE = 2U, /**< The Full User Area Logical Erase (FULE) operation. */
1319 CY_SD_HOST_ERASE_SECURE = 3U, /**< The secure purge according to
1320 * Secure Removal Type in EXT_CSD
1321 * on the erase groups identified by the
1322 * startAddr&endAddr parameters and
1323 * any copies of those erase groups.
1324 */
1325 CY_SD_HOST_ERASE_SECURE_TRIM_STEP_2 = 4U, /**< The secure purge operation on
1326 * the write blocks according to
1327 * Secure Removal Type in EXT_CSD
1328 * and copies of those write blocks
1329 * that were previously identified
1330 * using \ref Cy_SD_Host_Erase with
1331 * CY_SD_HOST_ERASE_SECURE_TRIM_STEP_1
1332 */
1333 CY_SD_HOST_ERASE_SECURE_TRIM_STEP_1 = 5U, /**< Mark the write blocks, indicated
1334 * by the startAddr&endAddr parameters,
1335 * for secure erase.
1336 */
1337 CY_SD_HOST_ERASE_TRIM = 6U /**< Trim the write blocks identified by
1338 * the startAddr&endAddr parameters. The controller
1339 * can perform the actual erase at convenient time.
1340 */
1341 } cy_en_sd_host_erase_type_t;
1342
1343 /** Card type. */
1344 typedef enum
1345 {
1346 CY_SD_HOST_SD = 0U, /**< The Secure Digital card (SD). */
1347 CY_SD_HOST_SDIO = 1U, /**< The CD Input Output card (SDIO). */
1348 CY_SD_HOST_EMMC = 2U, /**< The Embedded Multimedia card (eMMC). */
1349 CY_SD_HOST_COMBO = 3U, /**< The Combo card (SD + SDIO). */
1350 CY_SD_HOST_UNUSABLE = 4U, /**< The unusable or not supported. */
1351 CY_SD_HOST_NOT_EMMC = 5U /**< The card is not eMMC. */
1352 } cy_en_sd_host_card_type_t;
1353
1354 /** The card capacity type. */
1355 typedef enum
1356 {
1357 CY_SD_HOST_SDSC = 0U, /**< SDSC - Secure Digital Standard Capacity (up to 2 GB). */
1358 CY_SD_HOST_SDHC = 1U, /**< SDHC - Secure Digital High Capacity (up to 32 GB). */
1359 CY_SD_HOST_EMMC_LESS_2G = 0U, /**< The eMMC block addressing for less than 2GB. */
1360 CY_SD_HOST_EMMC_GREATER_2G = 1U, /**< The eMMC block addressing for greater than 2GB. */
1361 CY_SD_HOST_SDXC = 2U, /**< SDXC - Secure Digital Extended Capacity (up to 2 TB). */
1362 CY_SD_HOST_UNSUPPORTED = 4U /**< Not supported. */
1363 }cy_en_sd_host_card_capacity_t;
1364
1365 /** SDHC response types. */
1366 typedef enum
1367 {
1368 CY_SD_HOST_RESPONSE_NONE = 0U, /**< No Response. */
1369 CY_SD_HOST_RESPONSE_LEN_136 = 1U, /**< Response Length 136. */
1370 CY_SD_HOST_RESPONSE_LEN_48 = 2U, /**< Response Length 48. */
1371 CY_SD_HOST_RESPONSE_LEN_48B = 3U /**< Response Length 48. Check Busy after response. */
1372 }cy_en_sd_host_response_type_t;
1373
1374 /** The DMA type enum. */
1375 typedef enum
1376 {
1377 CY_SD_HOST_DMA_SDMA = 0U, /**< SDMA mode. */
1378 CY_SD_HOST_DMA_ADMA2 = 2U, /**< ADMA2 mode. */
1379 CY_SD_HOST_DMA_ADMA2_ADMA3 = 3U /**< ADMA2-ADMA3 mode. */
1380 }cy_en_sd_host_dma_type_t;
1381
1382 /** Write Protect type enum. */
1383 typedef enum
1384 {
1385 CY_SD_HOST_PERMANENT = 0U, /**< The permanent write protect. */
1386 CY_SD_HOST_ENABLE_TEMPORARY = 1U, /**< The temporary write protect. */
1387 CY_SD_HOST_DISABLE_TEMPORARY = 2U /**< Clear the temporary write protect. */
1388 } cy_en_sd_host_write_protect_t;
1389
1390 /** Card status in R1 response type enum. */
1391 typedef enum
1392 {
1393 CY_SD_HOST_AKE_SEQ_ERROR_R1_RESP = 3U, /**< Error in the sequence of the authentication process. */
1394 CY_SD_HOST_APP_CMD_R1_RESP = 5U, /**< The card will expect ACMD, or an indication that the command has been interpreted as ACMD. */
1395 CY_SD_HOST_FX_EVENT_R1_RESP = 6U, /**< Extension Functions may set this bit to get host to deal with events. */
1396 CY_SD_HOST_READY_FOR_DATA_R1_RESP = 8U, /**< Corresponds to buffer empty signaling on the bus. */
1397 CY_SD_HOST_CURRENT_STATE_0_R1_RESP = 9U, /**< The state of the card when receiving the command. The four bits are interpreted as a binary coded number between 0 and 15. It is 0th bit. */
1398 CY_SD_HOST_CURRENT_STATE_1_R1_RESP = 10U, /**< The state of the card when receiving the command. The four bits are interpreted as a binary coded number between 0 and 15. It is 1st bit. */
1399 CY_SD_HOST_CURRENT_STATE_2_R1_RESP = 11U, /**< The state of the card when receiving the command. The four bits are interpreted as a binary coded number between 0 and 15. It is 2nd bit. */
1400 CY_SD_HOST_CURRENT_STATE_3_R1_RESP = 12U, /**< The state of the card when receiving the command. The four bits are interpreted as a binary coded number between 0 and 15. It is 3rd bit. */
1401 CY_SD_HOST_ERASE_RESET_R1_RESP = 13U, /**< It indicates if an erase sequence was cleared before executing because an out of erase sequence command was received. */
1402 CY_SD_HOST_CARD_ECC_DISABLED_R1_RESP = 14U, /**< It indicates if the command has been executed without using the internal ECC. */
1403 CY_SD_HOST_WP_ERASE_SKIP_R1_RESP = 15U, /**< It is set when only partial address space was erased due to existing write protected blocks or the temporary or permanent write protected card was erased. */
1404 CY_SD_HOST_CSD_OVERWRITE_R1_RESP = 16U, /**< It indicates read only section of the CSD does not match the card content or there was an attempt to reverse the copy or permanent WP bits was made. */
1405 CY_SD_HOST_ERROR_R1_RESP = 19U, /**< A general or an unknown error occurred during the operation. */
1406 CY_SD_HOST_CC_ERROR_R1_RESP = 20U, /**< Internal card controller error. */
1407 CY_SD_HOST_CARD_ECC_FAILED_R1_RESP = 21U, /**< Card internal ECC was applied but failed to correct the data. */
1408 CY_SD_HOST_ILLEGAL_COMMAND_R1_RESP = 22U, /**< Command not legal for the card. */
1409 CY_SD_HOST_COM_CRC_ERROR_R1_RESP = 23U, /**< The CRC check of the previous command failed. */
1410 CY_SD_HOST_LOCK_UNLOCK_FAILED_R1_RESP = 24U, /**< Set when a sequence or password error has been detected in lock/unlock card command. */
1411 CY_SD_HOST_CARD_IS_LOCKED_R1_RESP = 25U, /**< When set, signals that the card is locked by the host. */
1412 CY_SD_HOST_WP_VIOLATION_R1_RESP = 26U, /**< Set when the host attempts to write to a protected block or to the temporary or permanent write protected card. */
1413 CY_SD_HOST_ERASE_PARAM_R1_RESP = 27U, /**< An invalid selection of write-blocks for erase occurred. */
1414 CY_SD_HOST_ERASE_SEQ_ERROR_R1_RESP = 28U, /**< An error in the sequence of erase commands occurred. */
1415 CY_SD_HOST_BLOCK_LEN_ERROR_R1_RESP = 29U, /**< The transferred block length is not allowed for this card, or the number of transferred bytes does not match the block length. */
1416 CY_SD_HOST_ADDRESS_ERROR_R1_RESP = 30U, /**< A misaligned address which did not match the block length was used in the command. */
1417 CY_SD_HOST_OUT_OF_RANGE_R1_RESP = 31U, /**< The command's argument was out of the allowed range for this card. */
1418 } cy_en_sd_host_r1_response_t;
1419
1420 /** \} group_sd_host_enums */
1421
1422 /**
1423 * \addtogroup group_sd_host_data_structures
1424 * \{
1425 */
1426
1427 /******************************************************************************
1428 * Structures
1429 *****************************************************************************/
1430
1431 /** SD Host initialization configuration structure. */
1432 typedef struct
1433 {
1434 bool emmc; /**< Set to true of eMMC otherwise false. */
1435 cy_en_sd_host_dma_type_t dmaType; /**< Selects the DMA type to be used. */
1436 bool enableLedControl; /**< If true the SD clock controls one IO
1437 * used to indicate when the card
1438 * is being accessed.
1439 */
1440 } cy_stc_sd_host_init_config_t;
1441
1442 /** SD/eMMC card configuration structure. */
1443 typedef struct
1444 {
1445 bool lowVoltageSignaling; /**< If true, the host supports the 1.8V signaling. */
1446 cy_en_sd_host_bus_width_t busWidth; /**< The desired bus width. */
1447 cy_en_sd_host_card_type_t *cardType; /**< The card type. */
1448 uint32_t *rca; /**< The pointer to where to store the cards relative card address. */
1449 cy_en_sd_host_card_capacity_t *cardCapacity; /**< Stores the card capacity. */
1450 }cy_stc_sd_host_sd_card_config_t;
1451
1452 /** SD Host command configuration structure. */
1453 typedef struct
1454 {
1455 uint32_t commandIndex; /**< The index of the command. */
1456 uint32_t commandArgument; /**< The argument for the command. */
1457 bool enableCrcCheck; /**< Enables the CRC check on the response. */
1458 bool enableAutoResponseErrorCheck; /**< If true the hardware checks the response for errors. */
1459 cy_en_sd_host_response_type_t respType; /**< The response type. */
1460 bool enableIdxCheck; /**< Checks the index of the response. */
1461 bool dataPresent; /**< true: Data is present to
1462 * be transferred using the DAT line,
1463 * false: Commands use the CMD line only.
1464 */
1465 cy_en_sd_host_cmd_type_t cmdType; /**< The command type. */
1466 } cy_stc_sd_host_cmd_config_t;
1467
1468 /** The SD Host data transfer configuration structure. */
1469 typedef struct
1470 {
1471 uint32_t blockSize; /**< The size of the data block. */
1472 uint32_t numberOfBlock; /**< The number of blocks to send. */
1473 bool enableDma; /**< Enables DMA for the transaction. */
1474 cy_en_sd_host_auto_cmd_t autoCommand; /**< Selects which auto commands are used if any. */
1475 bool read; /**< true = Read from the card, false = Write to the card. */
1476 uint32_t* data; /**< The pointer to data to send/receive or
1477 * the pointer to the DMA descriptor.
1478 */
1479 uint32_t dataTimeout; /**< The timeout value for the transfer. */
1480 bool enableIntAtBlockGap; /**< Enables the interrupt generation at the block gap. */
1481 bool enReliableWrite; /**< For EMMC enables the reliable write. */
1482 }cy_stc_sd_host_data_config_t;
1483
1484 /** SD Host Write/Read structure. */
1485 typedef struct
1486 {
1487 uint32_t* data; /**< The pointer to data. */
1488 uint32_t address; /**< The address to Write/Read data on the card or eMMC. */
1489 uint32_t numberOfBlocks; /**< The number of blocks to Write/Read. */
1490 cy_en_sd_host_auto_cmd_t autoCommand; /**< Selects which auto commands are used if any. */
1491 uint32_t dataTimeout; /**< The timeout value for the transfer. */
1492 bool enReliableWrite; /**< For EMMC cards, enables the reliable write. */
1493 bool enableDma; /**< Enables DMA for the transaction. */
1494 } cy_stc_sd_host_write_read_config_t;
1495
1496 /** Context structure. */
1497 typedef struct
1498 {
1499 cy_en_sd_host_dma_type_t dmaType; /**< Defines the DMA type to be used. */
1500 cy_en_sd_host_card_capacity_t cardCapacity; /**< The standard card or the card with the high capacity. */
1501 uint32_t maxSectorNum; /**< The SD card maximum number of the sectors. */
1502 uint32_t RCA; /**< The relative card address. */
1503 cy_en_sd_host_card_type_t cardType; /**< The card type. */
1504 uint32_t csd[4]; /**< The Card-Specific Data register. */
1505 }cy_stc_sd_host_context_t;
1506
1507 /** \} group_sd_host_data_structures */
1508
1509
1510 /**
1511 * \addtogroup group_sd_host_high_level_functions
1512 * \{
1513 */
1514
1515 /******************************************************************************
1516 * Functions
1517 *******************************************************************************/
1518
1519 /* High level section */
1520
1521 cy_en_sd_host_status_t Cy_SD_Host_InitCard(SDHC_Type *base,
1522 cy_stc_sd_host_sd_card_config_t *config,
1523 cy_stc_sd_host_context_t *context);
1524 cy_en_sd_host_status_t Cy_SD_Host_Read(SDHC_Type *base,
1525 cy_stc_sd_host_write_read_config_t *config,
1526 cy_stc_sd_host_context_t const *context);
1527 cy_en_sd_host_status_t Cy_SD_Host_Write(SDHC_Type *base,
1528 cy_stc_sd_host_write_read_config_t *config,
1529 cy_stc_sd_host_context_t const *context);
1530 cy_en_sd_host_status_t Cy_SD_Host_Erase(SDHC_Type *base,
1531 uint32_t startAddr,
1532 uint32_t endAddr,
1533 cy_en_sd_host_erase_type_t eraseType,
1534 cy_stc_sd_host_context_t const *context);
1535
1536 /** \} group_sd_host_high_level_functions */
1537
1538 /**
1539 * \addtogroup group_sd_host_low_level_functions
1540 * \{
1541 */
1542
1543 cy_en_sd_host_status_t Cy_SD_Host_Init(SDHC_Type *base,
1544 const cy_stc_sd_host_init_config_t* config,
1545 cy_stc_sd_host_context_t *context);
1546 void Cy_SD_Host_DeInit(SDHC_Type *base);
1547 void Cy_SD_Host_Enable(SDHC_Type *base);
1548 void Cy_SD_Host_Disable(SDHC_Type *base);
1549 __STATIC_INLINE void Cy_SD_Host_EnableSdClk(SDHC_Type *base);
1550 __STATIC_INLINE void Cy_SD_Host_DisableSdClk(SDHC_Type *base);
1551 cy_en_sd_host_status_t Cy_SD_Host_SetSdClkDiv(SDHC_Type *base, uint16_t clkDiv);
1552 bool Cy_SD_Host_IsWpSet(SDHC_Type const *base);
1553 cy_en_sd_host_status_t Cy_SD_Host_SetHostBusWidth(SDHC_Type *base,
1554 cy_en_sd_host_bus_width_t width);
1555 cy_en_sd_host_status_t Cy_SD_Host_SetBusWidth(SDHC_Type *base,
1556 cy_en_sd_host_bus_width_t width,
1557 cy_stc_sd_host_context_t const *context);
1558 cy_en_sd_host_status_t Cy_SD_Host_SetHostSpeedMode(SDHC_Type *base,
1559 cy_en_sd_host_bus_speed_mode_t speedMode);
1560 cy_en_sd_host_status_t Cy_SD_Host_SetBusSpeedMode(SDHC_Type *base,
1561 cy_en_sd_host_bus_speed_mode_t speedMode,
1562 cy_stc_sd_host_context_t const *context);
1563 cy_en_sd_host_status_t Cy_SD_Host_SelBusVoltage(SDHC_Type *base,
1564 bool enable18VSignal,
1565 cy_stc_sd_host_context_t *context);
1566 void Cy_SD_Host_EnableCardVoltage(SDHC_Type *base);
1567 void Cy_SD_Host_DisableCardVoltage(SDHC_Type *base);
1568 cy_en_sd_host_status_t Cy_SD_Host_GetResponse(SDHC_Type const *base,
1569 uint32_t *responsePtr,
1570 bool largeResponse);
1571 cy_en_sd_host_status_t Cy_SD_Host_SendCommand(SDHC_Type *base,
1572 cy_stc_sd_host_cmd_config_t const *config);
1573 cy_en_sd_host_status_t Cy_SD_Host_InitDataTransfer(SDHC_Type *base,
1574 cy_stc_sd_host_data_config_t const *dataConfig);
1575 __STATIC_INLINE uint32_t Cy_SD_Host_BufferRead(SDHC_Type const *base);
1576 __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_BufferWrite(SDHC_Type *base, uint32_t data);
1577 void Cy_SD_Host_ChangeIoVoltage(SDHC_Type *base, cy_en_sd_host_io_voltage_t ioVoltage);
1578 __STATIC_INLINE void Cy_SD_Host_StopAtBlockGap(SDHC_Type *base);
1579 __STATIC_INLINE void Cy_SD_Host_ContinueFromBlockGap(SDHC_Type *base);
1580 __STATIC_INLINE uint32_t Cy_SD_Host_GetAutoCmdErrStatus(SDHC_Type const *base);
1581 __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_EnableAutoCmd23(SDHC_Type *base);
1582 __STATIC_INLINE void Cy_SD_Host_DisableAutoCmd23(SDHC_Type *base);
1583 __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_EnableAsyncInterrupt(SDHC_Type *base);
1584 __STATIC_INLINE void Cy_SD_Host_DisableAsyncInterrupt(SDHC_Type *base);
1585 __STATIC_INLINE uint32_t Cy_SD_Host_GetAdmaErrorStatus(SDHC_Type const *base);
1586 __STATIC_INLINE void Cy_SD_Host_EMMC_Reset(SDHC_Type *base);
1587 cy_en_sd_host_status_t Cy_SD_Host_AbortTransfer(SDHC_Type *base,
1588 cy_stc_sd_host_context_t const *context);
1589 cy_en_sd_host_status_t Cy_SD_Host_WriteProtect(SDHC_Type *base,
1590 cy_en_sd_host_write_protect_t writeProtect,
1591 cy_stc_sd_host_context_t *context);
1592 uint32_t Cy_SD_Host_GetCardStatus(SDHC_Type *base, cy_stc_sd_host_context_t const *context);
1593 cy_en_sd_host_status_t Cy_SD_Host_GetSdStatus(SDHC_Type *base,
1594 uint32_t *sdStatus,
1595 cy_stc_sd_host_context_t const *context);
1596 uint32_t Cy_SD_Host_GetOcr(SDHC_Type *base, cy_stc_sd_host_context_t const *context);
1597 cy_en_sd_host_status_t Cy_SD_Host_GetCid(SDHC_Type *base, uint32_t *cid);
1598 cy_en_sd_host_status_t Cy_SD_Host_GetCsd(SDHC_Type *base,
1599 uint32_t *csd,
1600 cy_stc_sd_host_context_t *context);
1601 cy_en_sd_host_status_t Cy_SD_Host_GetExtCsd(SDHC_Type *base,
1602 uint32_t *extCsd,
1603 cy_stc_sd_host_context_t *context);
1604 uint32_t Cy_SD_Host_GetRca(SDHC_Type *base);
1605 cy_en_sd_host_status_t Cy_SD_Host_GetScr(SDHC_Type *base,
1606 uint32_t *scr,
1607 cy_stc_sd_host_context_t const *context);
1608 uint32_t Cy_SD_Host_GetPresentState(SDHC_Type const *base);
1609 bool Cy_SD_Host_IsCardConnected(SDHC_Type const *base);
1610 void Cy_SD_Host_SoftwareReset(SDHC_Type *base, cy_en_sd_host_reset_t reset);
1611 cy_en_syspm_status_t Cy_SD_Host_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams,
1612 cy_en_syspm_callback_mode_t mode);
1613 cy_en_sd_host_status_t Cy_SD_Host_GetBlockCount(SDHC_Type *base,
1614 uint32_t *block_count,
1615 cy_stc_sd_host_context_t *context);
1616
1617
1618 /** \} group_sd_host_low_level_functions */
1619
1620 /**
1621 * \addtogroup group_sd_host_interrupt_functions
1622 * \{
1623 */
1624
1625 __STATIC_INLINE uint32_t Cy_SD_Host_GetNormalInterruptStatus(SDHC_Type const *base);
1626 __STATIC_INLINE void Cy_SD_Host_ClearNormalInterruptStatus(SDHC_Type *base, uint32_t status);
1627 __STATIC_INLINE void Cy_SD_Host_SetNormalInterruptEnable(SDHC_Type *base, uint32_t interrupt);
1628 __STATIC_INLINE uint32_t Cy_SD_Host_GetNormalInterruptEnable(SDHC_Type const *base);
1629 __STATIC_INLINE void Cy_SD_Host_SetNormalInterruptMask(SDHC_Type *base, uint32_t interruptMask);
1630 __STATIC_INLINE uint32_t Cy_SD_Host_GetNormalInterruptMask(SDHC_Type const *base);
1631 __STATIC_INLINE uint32_t Cy_SD_Host_GetErrorInterruptStatus(SDHC_Type const *base);
1632 __STATIC_INLINE void Cy_SD_Host_ClearErrorInterruptStatus(SDHC_Type *base, uint32_t status);
1633 __STATIC_INLINE void Cy_SD_Host_SetErrorInterruptEnable(SDHC_Type *base, uint32_t interrupt);
1634 __STATIC_INLINE uint32_t Cy_SD_Host_GetErrorInterruptEnable(SDHC_Type const *base);
1635 __STATIC_INLINE void Cy_SD_Host_SetErrorInterruptMask(SDHC_Type *base, uint32_t interruptMask);
1636 __STATIC_INLINE uint32_t Cy_SD_Host_GetErrorInterruptMask(SDHC_Type const *base);
1637
1638 /** \} group_sd_host_interrupt_functions */
1639
1640 /**
1641 * \addtogroup group_sd_host_low_level_functions
1642 * \{
1643 */
1644
1645
1646 /*******************************************************************************
1647 * Function Name: Cy_SD_Host_EnableSdClk
1648 ****************************************************************************//**
1649 *
1650 * Enables the SD clock (SD host drives the SDCLK line).
1651 *
1652 * \param *base
1653 * The SD host registers structure pointer.
1654 *
1655 *******************************************************************************/
Cy_SD_Host_EnableSdClk(SDHC_Type * base)1656 __STATIC_INLINE void Cy_SD_Host_EnableSdClk(SDHC_Type *base)
1657 {
1658 /* Check for NULL pointer */
1659 if (NULL != base)
1660 {
1661 SDHC_CORE_CLK_CTRL_R(base) = (uint16_t)((uint32_t)SDHC_CORE_CLK_CTRL_R(base) |
1662 SDHC_CORE_CLK_CTRL_R_SD_CLK_EN_Msk |
1663 SDHC_CORE_CLK_CTRL_R_PLL_ENABLE_Msk);
1664 }
1665 }
1666
1667
1668 /*******************************************************************************
1669 * Function Name: Cy_SD_Host_DisableSdClk
1670 ****************************************************************************//**
1671 *
1672 * Disables the SD clock (The SD Host doesn't drive the SDCLK line).
1673 *
1674 * \param *base
1675 * The SD host registers structure pointer.
1676 *
1677 *******************************************************************************/
Cy_SD_Host_DisableSdClk(SDHC_Type * base)1678 __STATIC_INLINE void Cy_SD_Host_DisableSdClk(SDHC_Type *base)
1679 {
1680 /* Check for NULL pointer */
1681 if (NULL != base)
1682 {
1683 /* Disable SD CLK */
1684 SDHC_CORE_CLK_CTRL_R(base) = _CLR_SET_FLD16U(SDHC_CORE_CLK_CTRL_R(base),
1685 SDHC_CORE_CLK_CTRL_R_SD_CLK_EN, 0UL);
1686
1687 /* Wait for at least 3 card clock periods */
1688 Cy_SysLib_DelayUs(CY_SD_HOST_3_PERIODS_US);
1689
1690 /* Disable PLL */
1691 SDHC_CORE_CLK_CTRL_R(base) = _CLR_SET_FLD16U(SDHC_CORE_CLK_CTRL_R(base),
1692 SDHC_CORE_CLK_CTRL_R_PLL_ENABLE, 0UL);
1693 }
1694 }
1695
1696
1697 /*******************************************************************************
1698 * Function Name: Cy_SD_Host_BufferRead
1699 ****************************************************************************//**
1700 *
1701 * Reads 32-bits of data from the read buffer.
1702 * Only use this function if not using SD block DMA to transfer data from buffer.
1703 *
1704 * \param *base
1705 * The SD host registers structure pointer.
1706 *
1707 * \return uint32_t
1708 * Data that is being read.
1709 *
1710 *******************************************************************************/
Cy_SD_Host_BufferRead(SDHC_Type const * base)1711 __STATIC_INLINE uint32_t Cy_SD_Host_BufferRead(SDHC_Type const *base)
1712 {
1713 /* Return the Buffer Data Port Register value */
1714 return SDHC_CORE_BUF_DATA_R(base);
1715 }
1716
1717
1718 /*******************************************************************************
1719 * Function Name: Cy_SD_Host_BufferWrite
1720 ****************************************************************************//**
1721 *
1722 * Writes 32-bits of data into the write buffer.
1723 * Only use this function if not using SD block DMA to transfer data to buffer.
1724 *
1725 * \param *base
1726 * The SD host registers structure pointer.
1727 *
1728 * \param data
1729 * Data to be written.
1730 *
1731 * \return \ref cy_en_sd_host_status_t
1732 *
1733 *******************************************************************************/
Cy_SD_Host_BufferWrite(SDHC_Type * base,uint32_t data)1734 __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_BufferWrite(SDHC_Type *base, uint32_t data)
1735 {
1736 cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_INVALID_PARAMETER;
1737
1738 /* Check for the NULL pointer */
1739 if (NULL != base)
1740 {
1741 SDHC_CORE_BUF_DATA_R(base) = data;
1742
1743 ret = CY_SD_HOST_SUCCESS;
1744 }
1745
1746 return ret;
1747 }
1748
1749
1750 /*******************************************************************************
1751 * Function Name: Cy_SD_Host_StopAtBlockGap
1752 ****************************************************************************//**
1753 *
1754 * Commands SD host to stop transmitting at the next block gap.
1755 *
1756 * \param *base
1757 * The SD host registers structure pointer.
1758 *
1759 *******************************************************************************/
Cy_SD_Host_StopAtBlockGap(SDHC_Type * base)1760 __STATIC_INLINE void Cy_SD_Host_StopAtBlockGap(SDHC_Type *base)
1761 {
1762 SDHC_CORE_BGAP_CTRL_R(base) = _CLR_SET_FLD8U(SDHC_CORE_BGAP_CTRL_R(base),
1763 SDHC_CORE_BGAP_CTRL_R_STOP_BG_REQ,
1764 1UL);
1765 }
1766
1767
1768 /*******************************************************************************
1769 * Function Name: Cy_SD_Host_ContinueFromBlockGap
1770 ****************************************************************************//**
1771 *
1772 * Commands SD host to continue transmitting after stopping at the block gap.
1773 *
1774 * \param *base
1775 * The SD host registers structure pointer.
1776 *
1777 *******************************************************************************/
Cy_SD_Host_ContinueFromBlockGap(SDHC_Type * base)1778 __STATIC_INLINE void Cy_SD_Host_ContinueFromBlockGap(SDHC_Type *base)
1779 {
1780 SDHC_CORE_BGAP_CTRL_R(base) = (uint8_t)(((uint32_t)SDHC_CORE_BGAP_CTRL_R(base) &
1781 ~SDHC_CORE_BGAP_CTRL_R_STOP_BG_REQ_Msk) | /* Clear the Stop At Block Gap Request bit. */
1782 SDHC_CORE_BGAP_CTRL_R_CONTINUE_REQ_Msk); /* Set the Continue Request bit. */
1783 }
1784
1785
1786 /*******************************************************************************
1787 * Function Name: Cy_SD_Host_GetAutoCmdErrStatus
1788 ****************************************************************************//**
1789 *
1790 * Gets the SD host error status of the auto command.
1791 *
1792 * \param *base
1793 * The SD host registers structure pointer.
1794 *
1795 * \return uint32_t
1796 * The bit mask of the Auto Command status.
1797 *
1798 *******************************************************************************/
Cy_SD_Host_GetAutoCmdErrStatus(SDHC_Type const * base)1799 __STATIC_INLINE uint32_t Cy_SD_Host_GetAutoCmdErrStatus(SDHC_Type const *base)
1800 {
1801 uint32_t ret;
1802
1803 ret = (uint32_t)SDHC_CORE_AUTO_CMD_STAT_R(base);
1804
1805 return ret;
1806 }
1807
1808
1809 /*******************************************************************************
1810 * Function Name: Cy_SD_Host_EnableAutoCmd23
1811 ****************************************************************************//**
1812 *
1813 * If the card supports AutoCmd23 call this function to enable it in the host.
1814 *
1815 * \param *base
1816 * The SD host registers structure pointer.
1817 *
1818 * \return \ref cy_en_sd_host_status_t.
1819 *
1820 *******************************************************************************/
Cy_SD_Host_EnableAutoCmd23(SDHC_Type * base)1821 __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_EnableAutoCmd23(SDHC_Type *base)
1822 {
1823 cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_INVALID_PARAMETER;
1824
1825 /* Check for the NULL pointer */
1826 if (NULL != base)
1827 {
1828 SDHC_CORE_XFER_MODE_R(base) = _CLR_SET_FLD16U(SDHC_CORE_XFER_MODE_R(base),
1829 SDHC_CORE_XFER_MODE_R_AUTO_CMD_ENABLE,
1830 2UL);
1831
1832 ret = CY_SD_HOST_SUCCESS;
1833 }
1834
1835 return ret;
1836 }
1837
1838
1839 /*******************************************************************************
1840 * Function Name: Cy_SD_Host_DisableAutoCmd23
1841 ****************************************************************************//**
1842 *
1843 * Removes support for AutoCmd23 if it was previously set.
1844 *
1845 * \param *base
1846 * The SD host registers structure pointer.
1847 *
1848 *******************************************************************************/
Cy_SD_Host_DisableAutoCmd23(SDHC_Type * base)1849 __STATIC_INLINE void Cy_SD_Host_DisableAutoCmd23(SDHC_Type *base)
1850 {
1851 SDHC_CORE_XFER_MODE_R(base) = _CLR_SET_FLD16U(SDHC_CORE_XFER_MODE_R(base),
1852 SDHC_CORE_XFER_MODE_R_AUTO_CMD_ENABLE,
1853 0UL);
1854 }
1855
1856
1857 /*******************************************************************************
1858 * Function Name: Cy_SD_Host_EnableAsyncInterrupt
1859 ****************************************************************************//**
1860 *
1861 * Enables the Asynchronous Interrupt for SDIO cards. Set this only
1862 * if the card supports this feature.
1863 *
1864 * \param *base
1865 * The SD host registers structure pointer.
1866 *
1867 * \return \ref cy_en_sd_host_status_t
1868 *
1869 *******************************************************************************/
Cy_SD_Host_EnableAsyncInterrupt(SDHC_Type * base)1870 __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_EnableAsyncInterrupt(SDHC_Type *base)
1871 {
1872 cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_INVALID_PARAMETER;
1873
1874 /* Check for the NULL pointer */
1875 if (NULL != base)
1876 {
1877 SDHC_CORE_HOST_CTRL2_R(base) = _CLR_SET_FLD16U(SDHC_CORE_HOST_CTRL2_R(base),
1878 SDHC_CORE_HOST_CTRL2_R_ASYNC_INT_ENABLE,
1879 1UL);
1880 }
1881
1882 return ret;
1883 }
1884
1885
1886
1887 /*******************************************************************************
1888 * Function Name: Cy_SD_Host_DisableAsyncInterrupt
1889 ****************************************************************************//**
1890 *
1891 * Removes the support for the Asynchronous Interrupt if it was previously set.
1892 *
1893 * \param *base
1894 * The SD host registers structure pointer.
1895 *
1896 *******************************************************************************/
Cy_SD_Host_DisableAsyncInterrupt(SDHC_Type * base)1897 __STATIC_INLINE void Cy_SD_Host_DisableAsyncInterrupt(SDHC_Type *base)
1898 {
1899 SDHC_CORE_HOST_CTRL2_R(base) = _CLR_SET_FLD16U(SDHC_CORE_HOST_CTRL2_R(base),
1900 SDHC_CORE_HOST_CTRL2_R_ASYNC_INT_ENABLE,
1901 0UL);
1902 }
1903
1904
1905 /*******************************************************************************
1906 * Function Name: Cy_SD_Host_GetAdmaErrorStatus
1907 ****************************************************************************//**
1908 *
1909 * Returns the ADMA Error Status register.
1910 *
1911 * \param *base
1912 * The SD host registers structure pointer.
1913 *
1914 * \return uint32_t
1915 * The bit mask of ADMA Error Status.
1916 *
1917 *******************************************************************************/
Cy_SD_Host_GetAdmaErrorStatus(SDHC_Type const * base)1918 __STATIC_INLINE uint32_t Cy_SD_Host_GetAdmaErrorStatus(SDHC_Type const *base)
1919 {
1920 uint32_t ret;
1921
1922 ret = (uint32_t)SDHC_CORE_ADMA_ERR_STAT_R(base);
1923
1924 return ret;
1925 }
1926
1927
1928 /*******************************************************************************
1929 * Function Name: Cy_SD_Host_EMMC_Reset
1930 ****************************************************************************//**
1931 *
1932 * Resets the eMMC card.
1933 *
1934 * \param *base
1935 * The SD host registers structure pointer.
1936 *
1937 *******************************************************************************/
Cy_SD_Host_EMMC_Reset(SDHC_Type * base)1938 __STATIC_INLINE void Cy_SD_Host_EMMC_Reset(SDHC_Type *base)
1939 {
1940 SDHC_CORE_EMMC_CTRL_R(base) = _CLR_SET_FLD16U(SDHC_CORE_EMMC_CTRL_R(base),
1941 SDHC_CORE_EMMC_CTRL_R_EMMC_RST_N,
1942 0UL);
1943
1944 /* Wait RST_n pulse width of 1 us */
1945 Cy_SysLib_DelayUs(CY_SD_HOST_EMMC_T_RSTW_US);
1946
1947 SDHC_CORE_EMMC_CTRL_R(base) = _CLR_SET_FLD16U(SDHC_CORE_EMMC_CTRL_R(base),
1948 SDHC_CORE_EMMC_CTRL_R_EMMC_RST_N,
1949 1UL);
1950
1951 /* Wait RST_n to Command time (74 cycles of clock signal required
1952 * before issuing CMD1 or CMD0 with argument 0xFFFFFFFA) - 200 us
1953 */
1954 Cy_SysLib_DelayUs(CY_SD_HOST_EMMC_T_RSCA_US);
1955 }
1956
1957 /** \} group_sd_host_low_level_functions */
1958
1959 /**
1960 * \addtogroup group_sd_host_interrupt_functions
1961 * \{
1962 */
1963
1964 /*******************************************************************************
1965 * Function Name: Cy_SD_Host_GetNormalInterruptStatus
1966 ****************************************************************************//**
1967 *
1968 * Returns the normal Int Status register.
1969 *
1970 * \param *base
1971 * The SD host registers structure pointer.
1972 *
1973 * \return uint32_t
1974 * The Bit mask of the normal Int Status.
1975 *
1976 *******************************************************************************/
Cy_SD_Host_GetNormalInterruptStatus(SDHC_Type const * base)1977 __STATIC_INLINE uint32_t Cy_SD_Host_GetNormalInterruptStatus(SDHC_Type const *base)
1978 {
1979 uint32_t ret;
1980
1981 ret = (uint32_t)SDHC_CORE_NORMAL_INT_STAT_R(base);
1982
1983 return ret;
1984 }
1985
1986
1987 /*******************************************************************************
1988 * Function Name: Cy_SD_Host_ClearNormalInterruptStatus
1989 ****************************************************************************//**
1990 *
1991 * Clears the selected SD host normal status.
1992 *
1993 * \param *base
1994 * The SD host registers structure pointer.
1995 *
1996 * \param status
1997 * The bitmask of statuses to clear.
1998 *
1999 *******************************************************************************/
Cy_SD_Host_ClearNormalInterruptStatus(SDHC_Type * base,uint32_t status)2000 __STATIC_INLINE void Cy_SD_Host_ClearNormalInterruptStatus(SDHC_Type *base, uint32_t status)
2001 {
2002 SDHC_CORE_NORMAL_INT_STAT_R(base) = (uint16_t)status;
2003 }
2004
2005
2006 /*******************************************************************************
2007 * Function Name: Cy_SD_Host_SetNormalInterruptEnable
2008 ****************************************************************************//**
2009 *
2010 * Sets the bit to be active in the Int status register.
2011 *
2012 * \param *base
2013 * The SD host registers structure pointer.
2014 *
2015 * \param interrupt
2016 * The Bit field of which normal interrupt status to enable.
2017 *
2018 *******************************************************************************/
Cy_SD_Host_SetNormalInterruptEnable(SDHC_Type * base,uint32_t interrupt)2019 __STATIC_INLINE void Cy_SD_Host_SetNormalInterruptEnable(SDHC_Type *base, uint32_t interrupt)
2020 {
2021 SDHC_CORE_NORMAL_INT_STAT_EN_R(base) = (uint16_t)interrupt;
2022 }
2023
2024
2025 /*******************************************************************************
2026 * Function Name: Cy_SD_Host_GetNormalInterruptEnable
2027 ****************************************************************************//**
2028 *
2029 * Returns which normal interrupts are enabled.
2030 *
2031 * \param *base
2032 * The SD host registers structure pointer.
2033 *
2034 * \return uint32_t
2035 * The Bit field of which normal interrupt statuses are enabled.
2036 *
2037 *******************************************************************************/
Cy_SD_Host_GetNormalInterruptEnable(SDHC_Type const * base)2038 __STATIC_INLINE uint32_t Cy_SD_Host_GetNormalInterruptEnable(SDHC_Type const *base)
2039 {
2040 uint32_t ret;
2041
2042 ret = (uint32_t)SDHC_CORE_NORMAL_INT_STAT_EN_R(base);
2043
2044 return ret;
2045 }
2046
2047
2048 /*******************************************************************************
2049 * Function Name: Cy_SD_Host_SetNormalInterruptMask
2050 ****************************************************************************//**
2051 *
2052 * Setting a bit in this register allows the enabled status to cause an interrupt.
2053 *
2054 * \param *base
2055 * The SD host registers structure pointer.
2056 *
2057 * \param interruptMask
2058 * The Bit field of which normal interrupts can cause an interrupt.
2059 *
2060 *******************************************************************************/
Cy_SD_Host_SetNormalInterruptMask(SDHC_Type * base,uint32_t interruptMask)2061 __STATIC_INLINE void Cy_SD_Host_SetNormalInterruptMask(SDHC_Type *base, uint32_t interruptMask)
2062 {
2063 SDHC_CORE_NORMAL_INT_SIGNAL_EN_R(base) = (uint16_t)interruptMask;
2064 }
2065
2066
2067 /*******************************************************************************
2068 * Function Name: Cy_SD_Host_GetNormalInterruptMask
2069 ****************************************************************************//**
2070 *
2071 * Returns which normal interrupts are masked to cause an interrupt.
2072 *
2073 * \param *base
2074 * The SD host registers structure pointer.
2075 *
2076 * \return uint32_t
2077 * The Bit field of which normal interrupts are masked to cause an interrupt.
2078 *
2079 *******************************************************************************/
Cy_SD_Host_GetNormalInterruptMask(SDHC_Type const * base)2080 __STATIC_INLINE uint32_t Cy_SD_Host_GetNormalInterruptMask(SDHC_Type const *base)
2081 {
2082 uint32_t ret;
2083
2084 ret = (uint32_t)SDHC_CORE_NORMAL_INT_SIGNAL_EN_R(base);
2085
2086 return ret;
2087 }
2088
2089
2090 /*******************************************************************************
2091 * Function Name: Cy_SD_Host_GetErrorInterruptStatus
2092 ****************************************************************************//**
2093 *
2094 * Returns the error Int Status register.
2095 *
2096 * \param *base
2097 * The SD host registers structure pointer.
2098 *
2099 * \return uint32_t
2100 * The bit mask of the error Int status.
2101 *
2102 *******************************************************************************/
Cy_SD_Host_GetErrorInterruptStatus(SDHC_Type const * base)2103 __STATIC_INLINE uint32_t Cy_SD_Host_GetErrorInterruptStatus(SDHC_Type const *base)
2104 {
2105 uint32_t ret;
2106
2107 ret = (uint32_t)SDHC_CORE_ERROR_INT_STAT_R(base);
2108
2109 return ret;
2110 }
2111
2112
2113 /*******************************************************************************
2114 * Function Name: Cy_SD_Host_ClearErrorInterruptStatus
2115 ****************************************************************************//**
2116 *
2117 * Clears the error interrupt status.
2118 *
2119 * \param *base
2120 * The SD host registers structure pointer.
2121 *
2122 * \param status
2123 * The bitmask of statuses to clear.
2124 *
2125 *******************************************************************************/
Cy_SD_Host_ClearErrorInterruptStatus(SDHC_Type * base,uint32_t status)2126 __STATIC_INLINE void Cy_SD_Host_ClearErrorInterruptStatus(SDHC_Type *base, uint32_t status)
2127 {
2128 SDHC_CORE_ERROR_INT_STAT_R(base) = (uint16_t)status;
2129 }
2130
2131
2132 /*******************************************************************************
2133 * Function Name: Cy_SD_Host_SetErrorInterruptEnable
2134 ****************************************************************************//**
2135 *
2136 * Setting a bit in this register allows for the bit to be active in
2137 * the Int status register.
2138 *
2139 * \param *base
2140 * The SD host registers structure pointer.
2141 *
2142 * \param interrupt
2143 * The Bit field of which error interrupt status to enable.
2144 *
2145 *******************************************************************************/
Cy_SD_Host_SetErrorInterruptEnable(SDHC_Type * base,uint32_t interrupt)2146 __STATIC_INLINE void Cy_SD_Host_SetErrorInterruptEnable(SDHC_Type *base, uint32_t interrupt)
2147 {
2148 SDHC_CORE_ERROR_INT_STAT_EN_R(base) = (uint16_t)interrupt;
2149 }
2150
2151
2152 /*******************************************************************************
2153 * Function Name: Cy_SD_Host_GetErrorInterruptEnable
2154 ****************************************************************************//**
2155 *
2156 * Returns which error interrupts are enabled.
2157 *
2158 * \param *base
2159 * The SD host registers structure pointer.
2160 *
2161 * \return uint32_t
2162 * The Bit field of which error interrupt statuses are enabled.
2163 *
2164 *******************************************************************************/
Cy_SD_Host_GetErrorInterruptEnable(SDHC_Type const * base)2165 __STATIC_INLINE uint32_t Cy_SD_Host_GetErrorInterruptEnable(SDHC_Type const *base)
2166 {
2167 uint32_t ret;
2168
2169 ret = (uint32_t)SDHC_CORE_ERROR_INT_STAT_EN_R(base);
2170
2171 return ret;
2172 }
2173
2174
2175 /*******************************************************************************
2176 * Function Name: Cy_SD_Host_SetErrorInterruptMask
2177 ****************************************************************************//**
2178 *
2179 * Setting a bit in this register allows the enabled status to cause an interrupt.
2180 *
2181 * \param *base
2182 * The SD host registers structure pointer.
2183 *
2184 * \param interruptMask
2185 * The Bit filed of which error interrupts can cause an interrupt.
2186 *
2187 *******************************************************************************/
Cy_SD_Host_SetErrorInterruptMask(SDHC_Type * base,uint32_t interruptMask)2188 __STATIC_INLINE void Cy_SD_Host_SetErrorInterruptMask(SDHC_Type *base, uint32_t interruptMask)
2189 {
2190 SDHC_CORE_ERROR_INT_SIGNAL_EN_R(base) = (uint16_t)interruptMask;
2191 }
2192
2193
2194 /*******************************************************************************
2195 * Function Name: Cy_SD_Host_GetErrorInterruptMask
2196 ****************************************************************************//**
2197 *
2198 * Returns which error interrupts are masked to cause an interrupt.
2199 *
2200 * \param *base
2201 * The SD host registers structure pointer.
2202 *
2203 * \return uint32_t
2204 * The Bit field of which error interrupts are masked to cause an interrupt.
2205 *
2206 *******************************************************************************/
Cy_SD_Host_GetErrorInterruptMask(SDHC_Type const * base)2207 __STATIC_INLINE uint32_t Cy_SD_Host_GetErrorInterruptMask(SDHC_Type const *base)
2208 {
2209 uint32_t ret;
2210
2211 ret = (uint32_t)SDHC_CORE_ERROR_INT_SIGNAL_EN_R(base);
2212
2213 return ret;
2214 }
2215
2216 /** \} group_sd_host_interrupt_functions */
2217
2218 #ifdef __cplusplus
2219 }
2220 #endif
2221
2222 /** \} group_sd_host */
2223
2224 #endif /* defined (CY_IP_MXSDHC) */
2225
2226 #endif /* CY_SD_HOST_PDL_H */
2227
2228
2229 /* [] END OF FILE */
2230
