1 /***************************************************************************//**
2 * \file cy_scb_ezi2c.h
3 * \version 3.10
4 *
5 * Provides EZI2C API declarations of the SCB driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2016-2021 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24
25 /**
26 * \addtogroup group_scb_ezi2c
27 * \{
28 * Driver API for EZI2C Slave Peripheral
29 *
30 * The functions and other declarations used in this part of the driver are in
31 * cy_scb_ezi2c.h. You can also include cy_pdl.h to get access
32 * to all functions and declarations in the PDL.
33 *
34 * I2C - The Inter-Integrated Circuit (I2C) bus is an industry-standard.
35 *
36 * The EZI2C slave peripheral driver provides an API to implement the I2C slave
37 * device based on the SCB hardware block. This slave device emulates a common
38 * I2C EEPROM interface that acts like dual-port memory between the external
39 * master and your code. I2C devices based on the SCB hardware are compatible
40 * with the I2C Standard mode, Fast mode, and Fast mode Plus specifications, as
41 * defined in the I2C bus specification.
42 *
43 * EZI2C slave is a special implementation of the I2C that handles all communication
44 * between the master and slave through ISR (interrupt service routine) and requires
45 * no interaction with the main program flow from the slave side. The EZI2C should be
46 * used when a shared memory model between the I2C master and I2C slave is needed.
47 *
48 * Features:
49 * * An industry-standard I2C bus interface
50 * * Supports standard data rates of 100/400/1000 kbps
51 * * Emulates a common I2C EEPROM Interface
52 * * Acts like dual-port memory between the external master and your code
53 * * Supports Hardware Address Match
54 * * Supports two hardware addresses with separate buffers
55 * * On deep sleep-capable SCB, it supports wake from deep sleep on address match
56 * * Simple to set up and use; does not require calling EZI2C API
57 * at run time.
58 *
59 ********************************************************************************
60 * \section group_scb_ezi2c_configuration Configuration Considerations
61 ********************************************************************************
62 * The EZI2C slave driver configuration can be divided to number of sequential
63 * steps listed below:
64 * * \ref group_scb_ezi2c_config
65 * * \ref group_scb_ezi2c_pins
66 * * \ref group_scb_ezi2c_clock
67 * * \ref group_scb_ezi2c_data_rate
68 * * \ref group_scb_ezi2c_intr
69 * * \ref group_scb_ezi2c_enable
70 *
71 * \note
72 * EZI2C slave driver is built on top of the SCB hardware block. The SCB3
73 * instance is used as an example for all code snippets. Modify the code to
74 * match your design.
75 *
76 ********************************************************************************
77 * \subsection group_scb_ezi2c_config Configure EZI2C slave
78 ********************************************************************************
79 * To set up the EZI2C slave driver, provide the configuration parameters in the
80 * \ref cy_stc_scb_ezi2c_config_t structure. The primary slave address
81 * slaveAddress1 must be provided. The other parameters are optional for
82 * operation. To initialize the driver, call \ref Cy_SCB_EZI2C_Init
83 * function providing a pointer to the populated \ref cy_stc_scb_ezi2c_config_t
84 * structure and the allocated \ref cy_stc_scb_ezi2c_context_t structure.
85 *
86 * \snippet scb/ezi2c_snippet/main.c EZI2C_CFG
87 *
88 * Set up the EZI2C slave buffer before enabling its
89 * operation by using \ref Cy_SCB_EZI2C_SetBuffer1 for the primary slave address
90 * and \ref Cy_SCB_EZI2C_SetBuffer2 for the secondary (if the secondary is enabled).
91 *
92 * \snippet scb/ezi2c_snippet/main.c EZI2C_CFG_BUFFER
93 *
94 ********************************************************************************
95 * \subsection group_scb_ezi2c_pins Assign and Configure Pins
96 ********************************************************************************
97 * Only dedicated SCB pins can be used for I2C operation. The HSIOM
98 * register must be configured to connect dedicated SCB I2C pins to the
99 * SCB block. Also the I2C pins must be configured in Open-Drain, Drives Low mode
100 * (this pin configuration implies usage of external pull-up resistors):
101 *
102 * \snippet scb/ezi2c_snippet/main.c EZI2C_CFG_PINS
103 *
104 * \note
105 * The alternative pins configuration is Resistive Pull-ups which implies usage
106 * internal pull-up resistors. This configuration is not recommended because
107 * resistor value is fixed and cannot be used for all supported data rates.
108 * Refer to device datasheet parameter RPULLUP for resistor value specifications.
109 *
110 ********************************************************************************
111 * \subsection group_scb_ezi2c_clock Assign Clock Divider
112 ********************************************************************************
113 * A clock source must be connected to the SCB block to oversample input and
114 * output signals, in this document this clock will be referred as clk_scb.
115 * You must use one of the 8-bit or 16-bit dividers. Use the \ref group_sysclk
116 * driver API to do this.
117 *
118 * \snippet scb/ezi2c_snippet/main.c EZI2C_CFG_ASSIGN_CLOCK
119 *
120 ********************************************************************************
121 * \subsection group_scb_ezi2c_data_rate Configure Data Rate
122 ********************************************************************************
123 * To get EZI2C slave to operate at the desired data rate, the clk_scb must be
124 * fast enough to provide sufficient oversampling. Use the
125 * \ref group_sysclk driver API to do this.
126 *
127 * <b>Refer to the technical reference manual (TRM) section I2C sub-section
128 * Oversampling and Bit Rate to get information about how to configure the
129 * I2C to run at the desired data rate</b>.
130 *
131 * \snippet scb/ezi2c_snippet/main.c EZI2C_CFG_DATA_RATE
132 *
133 ********************************************************************************
134 * \subsection group_scb_ezi2c_intr Configure Interrupt
135 ********************************************************************************
136 * The interrupt is mandatory for the EZI2C slave operation.
137 * The \ref Cy_SCB_EZI2C_Interrupt function must be called in the interrupt
138 * handler for the selected SCB instance. Also, this interrupt must be enabled
139 * in the NVIC or it will not work.
140 *
141 * \snippet scb/ezi2c_snippet/main.c EZI2C_INTR_A
142 * \snippet scb/ezi2c_snippet/main.c EZI2C_INTR_B
143 *
144 ********************************************************************************
145 * \subsection group_scb_ezi2c_enable Enable EZI2C slave
146 ********************************************************************************
147 * Finally, enable the EZI2C slave operation by calling \ref Cy_SCB_EZI2C_Enable.
148 * Now the I2C device responds to the assigned address.
149 * \snippet scb/ezi2c_snippet/main.c EZI2C_ENABLE
150 *
151 ********************************************************************************
152 * \section group_scb_ezi2c_use_cases Common Use Cases
153 ********************************************************************************
154 * The EZI2C slave operation might not require calling any EZI2C slave function
155 * because the I2C master is able to access the slave buffer. The application
156 * can directly access it as well. Note that this is an application-level task
157 * to ensure the buffer content integrity.
158 *
159 ********************************************************************************
160 * \subsection group_scb_ezi2c_master_wr Master Write operation
161 ********************************************************************************
162 * This operation starts with sending a base address that is one
163 * or two bytes, depending on the sub-address size configuration. This base
164 * address is retained and will be used for later read operations. Following
165 * the base address, there is a sequence of bytes written into the buffer
166 * starting from the base address location. The buffer index is incremented
167 * for each written byte, but this does not affect the base address that is
168 * retained. The length of a write operation is limited by the maximum buffer
169 * read/write region size.\n
170 * When a master attempts to write outside the read/write region or past the
171 * end of the buffer, the last byte is NACKed.
172 *
173 * \image html scb_ezi2c_write.png
174 *
175 ********************************************************************************
176 * \subsection group_scb_ezi2c_master_rd Master Read operation
177 ********************************************************************************
178 * This operation always starts from the base address set by the most
179 * recent write operation. The buffer index is incremented for each read byte.
180 * Two sequential read operations start from the same base address no matter
181 * how many bytes are read. The length of a read operation is not limited by
182 * the maximum size of the data buffer. The EZI2C slave returns 0xFF bytes
183 * if the read operation passes the end of the buffer.\n
184 * Typically, a read operation requires the base address to be updated before
185 * starting the read. In this case, the write and read operations must be
186 * combined together.
187 *
188 * \image html scb_ezi2c_read.png
189 *
190 * The I2C master may use the ReStart or Stop/Start conditions to combine the
191 * operations. The write operation sets only the base address and the following
192 * read operation will start from the new base address. In cases where the base
193 * address remains the same, there is no need for a write operation.
194 * \image html scb_ezi2c_set_ba_read.png
195 *
196 ********************************************************************************
197 * \section group_scb_ezi2c_lp Low Power Support
198 ********************************************************************************
199 * The EZI2C slave provides the callback functions to handle power mode
200 * transition. The callback \ref Cy_SCB_EZI2C_DeepSleepCallback must be called
201 * during execution of \ref Cy_SysPm_CpuEnterDeepSleep;
202 * \ref Cy_SCB_EZI2C_HibernateCallback must be called during execution of
203 * \ref Cy_SysPm_SystemEnterHibernate. To trigger the callback execution, the
204 * callback must be registered before calling the power mode transition function.
205 * Refer to \ref group_syspm driver for more information about power mode
206 * transitions and callback registration.
207 *
208 * The EZI2C configured to support two addresses can wakeup the device on
209 * address match to NACK not supported address. This happens because the
210 * hardware address-match-logic uses address bit masking to support to two
211 * addresses. The address mask defines which bits in the address are treated
212 * as non-significant while performing an address match. One non-significant
213 * bit results in two matching addresses; two bits will match 4 and so on.
214 * If the two addresses differ by more than a single bit, then the extra
215 * addresses that will pass the hardware match and wakeup the device from
216 * Deep Sleep mode. Then firmware address matching will to generate a NAK.
217 * Due to this reason, it is preferable to select a secondary address that
218 * is different from the primary by one bit. The address mask in this case
219 * makes one bit non-significant.
220 * For example:
221 * * Primary address = 0x24 and secondary address = 0x34, only one bit differs.
222 * Only the two addresses are treated as matching by the hardware.
223 * * Primary address = 0x24 and secondary address = 0x30, two bits differ.
224 * Four addresses are treated as matching by the hardware: 0x24, 0x34, 0x20
225 * and 0x30. Firmware is required to ACK only the primary and secondary
226 * addresses 0x24 and 0x30 and NAK all others 0x20 and 0x34.
227 *
228 * \note
229 * Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>.
230 * For proper operation, when the EZI2C slave is configured to be a wakeup
231 * source from Deep Sleep mode, the \ref Cy_SCB_EZI2C_DeepSleepCallback must
232 * be copied and modified. Refer to the function description to get the details.
233 *
234 * \defgroup group_scb_ezi2c_macros Macros
235 * \defgroup group_scb_ezi2c_functions Functions
236 * \{
237 * \defgroup group_scb_ezi2c_general_functions General
238 * \defgroup group_scb_ezi2c_slave_functions Slave
239 * \defgroup group_scb_ezi2c_low_power_functions Low Power Callbacks
240 * \}
241 * \defgroup group_scb_ezi2c_data_structures Data Structures
242 * \defgroup group_scb_ezi2c_enums Enumerated Types
243 */
244
245 #if !defined(CY_SCB_EZI2C_H)
246 #define CY_SCB_EZI2C_H
247
248 #include "cy_device.h"
249
250 #if (defined (CY_IP_MXSCB) || defined (CY_IP_MXS22SCB))
251
252 #include "cy_scb_common.h"
253
254 #if defined(__cplusplus)
255 extern "C" {
256 #endif
257
258 /*******************************************************************************
259 * Enumerated Types
260 *******************************************************************************/
261
262 /**
263 * \addtogroup group_scb_ezi2c_enums
264 * \{
265 */
266
267 /** EZI2C slave status codes */
268 typedef enum
269 {
270 /** Operation completed successfully */
271 CY_SCB_EZI2C_SUCCESS = 0U,
272
273 /** One or more of input parameters are invalid */
274 CY_SCB_EZI2C_BAD_PARAM = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_EZI2C_ID | 1U),
275 } cy_en_scb_ezi2c_status_t;
276
277 /** Number of Addresses */
278 typedef enum
279 {
280 CY_SCB_EZI2C_ONE_ADDRESS, /**< Only one address */
281 CY_SCB_EZI2C_TWO_ADDRESSES /**< Two addresses */
282 } cy_en_scb_ezi2c_num_of_addr_t;
283
284 /** Size of Sub-Address */
285 typedef enum
286 {
287 CY_SCB_EZI2C_SUB_ADDR8_BITS, /**< Sub-address is 8 bits */
288 CY_SCB_EZI2C_SUB_ADDR16_BITS /**< Sub-address is 16 bits */
289 } cy_en_scb_ezi2c_sub_addr_size_t;
290
291 /** \cond INTERNAL */
292 /** EZI2C slave FSM states */
293 typedef enum
294 {
295 CY_SCB_EZI2C_STATE_IDLE,
296 CY_SCB_EZI2C_STATE_ADDR,
297 CY_SCB_EZI2C_STATE_RX_OFFSET_MSB,
298 CY_SCB_EZI2C_STATE_RX_OFFSET_LSB,
299 CY_SCB_EZI2C_STATE_RX_DATA0,
300 CY_SCB_EZI2C_STATE_RX_DATA1,
301 CY_SCB_EZI2C_STATE_TX_DATA
302 } cy_en_scb_ezi2c_state_t;
303 /** \endcond */
304 /** \} group_scb_ezi2c_enums */
305
306
307 /*******************************************************************************
308 * Type Definitions
309 *******************************************************************************/
310
311 /**
312 * \addtogroup group_scb_ezi2c_data_structures
313 * \{
314 */
315
316 /** EZI2C slave configuration structure */
317 typedef struct cy_stc_scb_ezi2c_config
318 {
319 /** The number of supported addresses either */
320 cy_en_scb_ezi2c_num_of_addr_t numberOfAddresses;
321
322 /** The 7-bit right justified primary slave address */
323 uint8_t slaveAddress1;
324
325 /** The 7-bit right justified secondary slave address */
326 uint8_t slaveAddress2;
327
328 /** The size of the sub-address, can either be 8 or 16 bits */
329 cy_en_scb_ezi2c_sub_addr_size_t subAddressSize;
330
331 /**
332 * When set, the slave will wake the device from Deep Sleep on an address
333 * match (The device datasheet must be consulted to determine which SCBs
334 * support this mode)
335 */
336 bool enableWakeFromSleep;
337 } cy_stc_scb_ezi2c_config_t;
338
339 /** EZI2C slave context structure.
340 * All fields for the context structure are internal. Firmware never reads or
341 * writes these values. Firmware allocates the structure and provides the
342 * address of the structure to the driver in function calls. Firmware must
343 * ensure that the defined instance of this structure remains in scope
344 * while the drive is in use.
345 */
346 typedef struct cy_stc_scb_ezi2c_context
347 {
348 /** \cond INTERNAL */
349 volatile cy_en_scb_ezi2c_state_t state; /**< The driver state */
350 volatile uint32_t status; /**< The slave status */
351
352 uint8_t address1; /**< The primary slave address (7-bits right justified) */
353 uint8_t address2; /**< The secondary slave address (7-bits right justified) */
354 cy_en_scb_ezi2c_sub_addr_size_t subAddrSize; /**< The sub-address size */
355
356 uint32_t idx; /**< The index within the buffer during operation */
357 uint32_t baseAddr1; /**< The valid base address for the primary slave address */
358 uint32_t baseAddr2; /**< The valid base address for the secondary slave address */
359
360 bool addr1Active; /**< Defines whether the request is intended for the primary slave address */
361 uint8_t *curBuf; /**< The pointer to the current location in the buffer (while it is accessed) */
362 uint32_t bufSize; /**< Specifies how many bytes are left in the current buffer */
363
364 uint8_t *buf1; /**< The pointer to the buffer exposed on the request intended for the primary slave address */
365 uint32_t buf1Size; /**< The buffer size assigned to the primary slave address */
366 uint32_t buf1rwBondary; /**< The Read/Write boundary within the buffer assigned to the primary slave address */
367
368 uint8_t *buf2; /**< The pointer to the buffer exposed on the request intended for the secondary slave address */
369 uint32_t buf2Size; /**< The buffer size assigned to the secondary slave address */
370 uint32_t buf2rwBondary; /**< The Read/Write boundary within the buffer assigned for the secondary slave address */
371 /** \endcond */
372 } cy_stc_scb_ezi2c_context_t;
373 /** \} group_scb_ezi2c_data_structures */
374
375
376 /*******************************************************************************
377 * Function Prototypes
378 *******************************************************************************/
379
380 /**
381 * \addtogroup group_scb_ezi2c_general_functions
382 * \{
383 */
384 cy_en_scb_ezi2c_status_t Cy_SCB_EZI2C_Init(CySCB_Type *base, cy_stc_scb_ezi2c_config_t const *config,
385 cy_stc_scb_ezi2c_context_t *context);
386 void Cy_SCB_EZI2C_DeInit(CySCB_Type *base);
387 __STATIC_INLINE void Cy_SCB_EZI2C_Enable(CySCB_Type *base);
388 void Cy_SCB_EZI2C_Disable(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context);
389
390 void Cy_SCB_EZI2C_SetAddress1(CySCB_Type *base, uint8_t addr, cy_stc_scb_ezi2c_context_t *context);
391 uint32_t Cy_SCB_EZI2C_GetAddress1(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t const *context);
392
393 void Cy_SCB_EZI2C_SetAddress2(CySCB_Type *base, uint8_t addr, cy_stc_scb_ezi2c_context_t *context);
394 uint32_t Cy_SCB_EZI2C_GetAddress2(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t const *context);
395 /** \} group_scb_ezi2c_general_functions */
396
397 /**
398 * \addtogroup group_scb_ezi2c_slave_functions
399 * \{
400 */
401 void Cy_SCB_EZI2C_SetBuffer1(CySCB_Type const *base, uint8_t *buffer, uint32_t size, uint32_t rwBoundary,
402 cy_stc_scb_ezi2c_context_t *context);
403 void Cy_SCB_EZI2C_SetBuffer2(CySCB_Type const *base, uint8_t *buffer, uint32_t size, uint32_t rwBoundary,
404 cy_stc_scb_ezi2c_context_t *context);
405
406 uint32_t Cy_SCB_EZI2C_GetActivity(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t *context);
407
408 void Cy_SCB_EZI2C_Interrupt(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context);
409 /** \} group_scb_ezi2c_slave_functions */
410
411 /**
412 * \addtogroup group_scb_ezi2c_low_power_functions
413 * \{
414 */
415 cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
416 cy_en_syspm_status_t Cy_SCB_EZI2C_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
417 /** \} group_scb_ezi2c_low_power_functions */
418
419
420 /*******************************************************************************
421 * API Constants
422 *******************************************************************************/
423
424 /**
425 * \addtogroup group_scb_ezi2c_macros
426 * \{
427 */
428
429 /**
430 * \defgroup group_scb_ezi2c_macros_get_activity EZI2C Activity Status
431 * Macros to check current EZI2C activity slave status returned by
432 * \ref Cy_SCB_EZI2C_GetActivity function. Each EZI2C slave status is encoded
433 * in a separate bit, therefore multiple bits may be set to indicate the
434 * current status.
435 * \{
436 */
437
438 /**
439 * The Read transfer intended for the primary slave address is complete.
440 * The error condition status bit must be checked to ensure that the Read
441 * transfer was completed successfully.
442 */
443 #define CY_SCB_EZI2C_STATUS_READ1 (0x01UL)
444
445 /**
446 * The Write transfer intended for the primary slave address is complete.
447 * The buffer content was modified.
448 * The error condition status bit must be checked to ensure that the Write
449 * transfer was completed successfully.
450 */
451 #define CY_SCB_EZI2C_STATUS_WRITE1 (0x02UL)
452
453 /**
454 * The Read transfer intended for the secondary slave address is complete.
455 * The error condition status bit must be checked to ensure that the Read
456 * transfer was completed successfully.
457 */
458 #define CY_SCB_EZI2C_STATUS_READ2 (0x04UL)
459
460 /**
461 * The Write transfer intended for the secondary slave address is complete.
462 * The buffer content was modified.
463 * The error condition status bit must be checked to ensure that the Write
464 * transfer was completed successfully.
465 */
466 #define CY_SCB_EZI2C_STATUS_WRITE2 (0x08UL)
467
468 /**
469 * A transfer intended for the primary address or secondary address is in
470 * progress. The status bit is set after an address match and cleared
471 * on a Stop or ReStart condition.
472 */
473 #define CY_SCB_EZI2C_STATUS_BUSY (0x10UL)
474
475 /**
476 * An error occurred during a transfer intended for the primary or secondary
477 * slave address. The sources of the error are: a misplaced Start or Stop
478 * condition or lost arbitration while the slave drives SDA.
479 * When CY_SCB_EZI2C_STATUS_ERR is set, the slave buffer may contain an
480 * invalid byte. Discard the buffer content in this case.
481 */
482 #define CY_SCB_EZI2C_STATUS_ERR (0x20UL)
483 /** \} group_scb_ezi2c_macros_get_activity */
484
485 /**
486 * This value is returned by the slave when the buffer is not configured or
487 * the master requests more bytes than are available in the buffer.
488 */
489 #define CY_SCB_EZI2C_DEFAULT_TX (0xFFUL)
490
491
492 /*******************************************************************************
493 * Internal Constants
494 *******************************************************************************/
495
496 /** \cond INTERNAL */
497 /* Default registers values */
498 #if ((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB))
499 #define CY_SCB_EZI2C_I2C_CTRL (SCB_I2C_CTRL_S_GENERAL_IGNORE_Msk | SCB_I2C_CTRL_SLAVE_MODE_Msk | \
500 SCB_I2C_CTRL_S_READY_ADDR_ACK_Msk | SCB_I2C_CTRL_S_READY_DATA_ACK_Msk)
501 #elif (defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION==1))
502 #define CY_SCB_EZI2C_I2C_CTRL (SCB_I2C_CTRL_S_GENERAL_IGNORE_Msk | SCB_I2C_CTRL_SLAVE_MODE_Msk)
503 #endif /* CY_IP_MXSCB_VERSION */
504 #define CY_SCB_EZI2C_RX_CTRL (CY_SCB_I2C_RX_CTRL)
505 #define CY_SCB_EZI2C_TX_CTRL (CY_SCB_I2C_TX_CTRL)
506
507 #define CY_SCB_EZI2C_SLAVE_INTR (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH | CY_SCB_SLAVE_INTR_I2C_STOP | \
508 CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_I2C_ARB_LOST)
509 /* Error interrupt sources */
510 #define CY_SCB_EZI2C_SLAVE_INTR_ERROR (CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_I2C_ARB_LOST)
511
512 /* Disables Stop interrupt source */
513 #define CY_SCB_EZI2C_SLAVE_INTR_NO_STOP (CY_SCB_EZI2C_SLAVE_INTR & ((uint32_t) ~CY_SCB_SLAVE_INTR_I2C_STOP))
514
515 /* Disable Address interrupt source */
516 #define CY_SCB_EZI2C_SLAVE_INTR_NO_ADDR (CY_SCB_EZI2C_SLAVE_INTR & ((uint32_t) ~CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH))
517
518 /* FIFO size */
519 #define CY_SCB_EZI2C_FIFO_SIZE CY_SCB_FIFO_SIZE
520 #define CY_SCB_EZI2C_HALF_FIFO_SIZE (CY_SCB_FIFO_SIZE / 2UL)
521
522 #define CY_SCB_EZI2C_ONE_ADDRESS_MASK (0xFFUL)
523
524 #define CY_SCB_EZI2C_IS_NUM_OF_ADDR_VALID(numAddr) ( (CY_SCB_EZI2C_ONE_ADDRESS == (numAddr)) || \
525 (CY_SCB_EZI2C_TWO_ADDRESSES == (numAddr)) )
526
527 #define CY_SCB_EZI2C_IS_SUB_ADDR_SIZE_VALID(subAddrSize) ( (CY_SCB_EZI2C_SUB_ADDR8_BITS == (subAddrSize)) || \
528 (CY_SCB_EZI2C_SUB_ADDR16_BITS == (subAddrSize)) )
529 /** \endcond */
530 /** \} group_scb_ezi2c_macros */
531
532
533 /*******************************************************************************
534 * In-line Function Implementation
535 *******************************************************************************/
536
537 /**
538 * \addtogroup group_scb_ezi2c_general_functions
539 * \{
540 */
541 /*******************************************************************************
542 * Function Name: Cy_SCB_EZI2C_Enable
543 ****************************************************************************//**
544 *
545 * Enables the SCB block for the EZI2C operation
546 *
547 * \param base
548 * The pointer to the EZI2C SCB instance.
549 *
550 *******************************************************************************/
Cy_SCB_EZI2C_Enable(CySCB_Type * base)551 __STATIC_INLINE void Cy_SCB_EZI2C_Enable(CySCB_Type *base)
552 {
553 SCB_CTRL(base) |= SCB_CTRL_ENABLED_Msk;
554 }
555
556 /*******************************************************************************
557 * Function Name: Cy_SCB_SetEzI2CMode
558 ****************************************************************************//**
559 *
560 * Sets EZ mode for I2C protocol.
561 * EZ mode is only used for synchronous serial interface protocols.
562 * This mode is only applicable to slave functionality.
563 * In EZ mode, the slave can read from and write to an addressable memory.
564 *
565 * \param base
566 * The pointer to the EZI2C SCB instance.
567 *
568 * \param ezMode
569 * If true, HW EZ mode is enabled. If false, HW EZ mode is disabled.
570 *
571 *******************************************************************************/
Cy_SCB_SetEzI2CMode(CySCB_Type * base,bool ezMode)572 __STATIC_INLINE void Cy_SCB_SetEzI2CMode(CySCB_Type *base, bool ezMode)
573 {
574 if(ezMode)
575 {
576 SCB_CTRL(base) |= SCB_CTRL_EZ_MODE_Msk;
577 }
578 else
579 {
580 SCB_CTRL(base) &= ~(SCB_CTRL_EZ_MODE_Msk);
581 }
582 }
583
584
585 /** \} group_scb_ezi2c_general_functions */
586
587 #if defined(__cplusplus)
588 }
589 #endif
590
591 /** \} group_scb_ezi2c */
592
593 #endif /* (defined (CY_IP_MXSCB) || defined (CY_IP_MXS22SCB)) */
594
595 #endif /* (CY_SCB_EZI2C_H) */
596 /* [] END OF FILE */
597
