1 /***************************************************************************//**
2 * \file cy_pra_cfg.c
3 * \version 2.40.1
4 *
5 * \brief The source code file for the PRA driver. The API is not intended to
6 * be used directly by user application.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2020 Cypress Semiconductor Corporation
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_device.h"
27
28 #if defined (CY_IP_MXS40SRSS)
29
30 #include "cy_pra_cfg.h"
31 #include "cy_device.h"
32 #include "cy_gpio.h"
33 #include "cy_wdt.h"
34
35 #if defined (CY_DEVICE_SECURE) || defined (CY_DOXYGEN)
36
37 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 17.2', 15, \
38 'Checked manually. All the recursive cycles are handled properly.')
39
40 #if (CY_CPU_CORTEX_M0P)
41 #include "cy_prot.h"
42 #endif /* (CY_CPU_CORTEX_M0P) */
43
44 #if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
45
46 /*******************************************************************************
47 * Function Prototypes
48 *******************************************************************************/
49 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_IloEnable(void);
50 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_IloDisable(void);
51 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_IloHibernateOn(bool hibernateEnable);
52 __STATIC_INLINE void Cy_PRA_ClkPumpInit(cy_en_clkpump_in_sources_t source, cy_en_clkpump_divide_t divider);
53 __STATIC_INLINE void Cy_PRA_ClkTimerInit(cy_en_clktimer_in_sources_t source, uint8_t divider);
54 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_PllInit(uint32_t clkPath, const cy_stc_pll_manual_config_t *pllConfig);
55 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_ClkHfInit( uint32_t clkHf, cy_en_clkhf_in_sources_t hfClkPath, cy_en_clkhf_dividers_t divider);
56 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_FllInit(const cy_stc_pra_system_config_t *devConfig);
57 __STATIC_INLINE void Cy_PRA_ExtClkInit( const cy_stc_pra_system_config_t *devConfig );
58 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_EcoInit(const cy_stc_pra_system_config_t *devConfig);
59 #if defined(CY_IP_MXBLESS)
60 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_AltHfInit(const cy_stc_pra_system_config_t *devConfig);
61 static cy_en_pra_status_t Cy_PRA_ValidateAltHf(const cy_stc_pra_system_config_t *devConfig);
62 #endif
63 __STATIC_INLINE void Cy_PRA_PiloInit(void);
64 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_ClkLfInit(cy_en_clklf_in_sources_t clkLfSource);
65 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_WcoInit(const cy_stc_pra_system_config_t *devConfig);
66 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_PowerInit(const cy_stc_pra_system_config_t *devConfig);
67 static uint32_t Cy_PRA_GetInputPathMuxFrq(cy_en_clkpath_in_sources_t pathMuxSrc, const cy_stc_pra_system_config_t *devConfig);
68 static cy_en_pra_status_t Cy_PRA_GetInputSourceFreq(uint32_t clkPath, const cy_stc_pra_system_config_t *devConfig, uint32_t *srcFreq );
69 static uint32_t Cy_PRA_GetHF0FreqHz(const cy_stc_pra_system_config_t *devConfig);
70 static uint32_t Cy_PRA_GetClkLfFreq(const cy_stc_pra_system_config_t *devConfig);
71 static uint32_t Cy_PRA_GetClkBakFreq(const cy_stc_pra_system_config_t *devConfig);
72 static cy_en_clkpath_in_sources_t Cy_PRA_GetInputSourceClock(uint32_t clkPath, const cy_stc_pra_system_config_t *devConfig, cy_en_pra_status_t *status);
73 static cy_en_pra_status_t Cy_PRA_ValidateECO(const cy_stc_pra_system_config_t *devConfig);
74 static cy_en_pra_status_t Cy_PRA_ValidateExtClkConfig(const cy_stc_pra_system_config_t *devConfig);
75 static cy_en_pra_status_t Cy_PRA_ValidateEXTClk(const cy_stc_pra_system_config_t *devConfig);
76 static cy_en_pra_status_t Cy_PRA_ValidateFLL(const cy_stc_pra_system_config_t *devConfig);
77 static cy_en_pra_status_t Cy_PRA_ValidatePLL(const cy_stc_pra_system_config_t *devConfig, uint8_t pll);
78 static cy_en_pra_status_t Cy_PRA_ValidateAllPLL(const cy_stc_pra_system_config_t *devConfig);
79 static cy_en_pra_status_t Cy_PRA_ValidateClkLf(const cy_stc_pra_system_config_t *devConfig);
80 static cy_en_pra_status_t Cy_PRA_ValidateClkPathMux(cy_en_clkpath_in_sources_t pathSrc, const cy_stc_pra_system_config_t *devConfig);
81 static cy_en_pra_status_t Cy_PRA_ValidateClkPath(uint32_t clkPath, const cy_stc_pra_system_config_t *devConfig);
82 static cy_en_pra_status_t Cy_PRA_ValidateAllClkPathMux(const cy_stc_pra_system_config_t *devConfig);
83 static cy_en_pra_status_t Cy_PRA_ValidateClkHfFreqDiv(uint32_t outFreqMHz, cy_en_clkhf_dividers_t divider);
84 static cy_en_pra_status_t Cy_PRA_ValidateClkHFs(const cy_stc_pra_system_config_t *devConfig);
85 static cy_en_pra_status_t Cy_PRA_ValidateClkPump(const cy_stc_pra_system_config_t *devConfig);
86 static cy_en_pra_status_t Cy_PRA_ValidateClkBak(const cy_stc_pra_system_config_t *devConfig);
87 static cy_en_pra_status_t Cy_PRA_ValidateClkFast(const cy_stc_pra_system_config_t *devConfig);
88 static cy_en_pra_status_t Cy_PRA_ValidateClkPeri(const cy_stc_pra_system_config_t *devConfig);
89 static cy_en_pra_status_t Cy_PRA_ValidateClkTimer(const cy_stc_pra_system_config_t *devConfig);
90 static cy_en_pra_status_t Cy_PRA_ValidateClkSlow(const cy_stc_pra_system_config_t *devConfig);
91 static cy_en_pra_status_t Cy_PRA_ValidateSystemConfig(const cy_stc_pra_system_config_t *devConfig);
92
93
94 /*******************************************************************************
95 * Global variables
96 *******************************************************************************/
97 /* External clock provisioned configuration */
98 cy_stc_pra_extclk_policy_t *extClkPolicyPtr = NULL;
99
100
101
102 /*******************************************************************************
103 * Function Name: Cy_PRA_IloEnable
104 ****************************************************************************//**
105 *
106 * Enables ILO Clock
107 *
108 * \return
109 * CY_PRA_STATUS_SUCCESS when success.
110 * CY_PRA_STATUS_ERROR_PROCESSING_ILO when failure.
111 *******************************************************************************/
Cy_PRA_IloEnable(void)112 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_IloEnable(void)
113 {
114 cy_en_pra_status_t retStatus = CY_PRA_STATUS_ERROR_PROCESSING_ILO;
115
116 if (Cy_SysClk_IloIsEnabled()) /* No change in ILO configuration */
117 {
118 retStatus = CY_PRA_STATUS_SUCCESS;
119 }
120 else
121 {
122 /* ILO cannot be enabled when WDT is locked */
123 if (!Cy_WDT_Locked())
124 {
125 Cy_SysClk_IloEnable();
126 retStatus = CY_PRA_STATUS_SUCCESS;
127 }
128 }
129 return retStatus;
130 }
131
132 /*******************************************************************************
133 * Function Name: Cy_PRA_IloDisable
134 ****************************************************************************//**
135 *
136 * Disables ILO Clock
137 *
138 * \return
139 * CY_PRA_STATUS_SUCCESS when success.
140 * CY_PRA_STATUS_ERROR_PROCESSING_ILO when failure.
141 *******************************************************************************/
Cy_PRA_IloDisable(void)142 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_IloDisable(void)
143 {
144 cy_en_pra_status_t retStatus = CY_PRA_STATUS_ERROR_PROCESSING_ILO;
145
146 if (!Cy_SysClk_IloIsEnabled()) /* No change in ILO configuration */
147 {
148 retStatus = CY_PRA_STATUS_SUCCESS;
149 }
150 else
151 {
152 /* ILO cannot be disabled when WDT is locked */
153 if (!Cy_WDT_Locked())
154 {
155 if (CY_SYSCLK_SUCCESS == Cy_SysClk_IloDisable())
156 {
157 retStatus = CY_PRA_STATUS_SUCCESS;
158 }
159 }
160 }
161 return retStatus;
162 }
163
164 /*******************************************************************************
165 * Function Name: Cy_PRA_IloHibernateOn
166 ****************************************************************************//**
167 *
168 * Controls whether the ILO stays on during a hibernate, or through an XRES or
169 * a brown-out detect (BOD) event.
170 *
171 * \param hibernateEnable
172 * true = ILO stays on during hibernate or across XRES/BOD. \n
173 * false = ILO turns off for hibernate or XRES/BOD.
174 *
175 * \return
176 * CY_PRA_STATUS_SUCCESS when success.
177 * CY_PRA_STATUS_ERROR_PROCESSING_ILO when failure.
178 *******************************************************************************/
Cy_PRA_IloHibernateOn(bool hibernateEnable)179 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_IloHibernateOn(bool hibernateEnable)
180 {
181 cy_en_pra_status_t retStatus = CY_PRA_STATUS_ERROR_PROCESSING_ILO;
182 static bool hibernateOn = false; /* Default hibernate state is false */
183
184 if (hibernateOn == hibernateEnable) /* No change in ILO configuration */
185 {
186 retStatus = CY_PRA_STATUS_SUCCESS;
187 }
188 else
189 {
190 /* ILO hibernate cannot be ON when WDT is locked */
191 if (!Cy_WDT_Locked())
192 {
193 Cy_SysClk_IloHibernateOn(hibernateEnable);
194 hibernateOn = hibernateEnable;
195 retStatus = CY_PRA_STATUS_SUCCESS;
196 }
197 }
198 return retStatus;
199 }
200
201 /*******************************************************************************
202 * Function Name: Cy_PRA_ClkPumpInit
203 ****************************************************************************//**
204 *
205 * Initializes PUMP Clock.
206 *
207 * \param source \ref cy_en_clkpump_in_sources_t
208 * \param divider \ref cy_en_clkpump_divide_t
209 *
210 *******************************************************************************/
Cy_PRA_ClkPumpInit(cy_en_clkpump_in_sources_t source,cy_en_clkpump_divide_t divider)211 __STATIC_INLINE void Cy_PRA_ClkPumpInit(cy_en_clkpump_in_sources_t source, cy_en_clkpump_divide_t divider)
212 {
213 Cy_SysClk_ClkPumpDisable();
214 Cy_SysClk_ClkPumpSetSource(source);
215 Cy_SysClk_ClkPumpSetDivider(divider);
216 Cy_SysClk_ClkPumpEnable();
217 }
218
219
220 /*******************************************************************************
221 * Function Name: Cy_PRA_ClkTimerInit
222 ****************************************************************************//**
223 *
224 * Initializes Timer Clock.
225 *
226 * \param source \ref cy_en_clktimer_in_sources_t
227 * \param divider Divider value; valid range is 0 to 255. Divides the selected
228 * source (\ref Cy_SysClk_ClkTimerSetSource) by the (value + 1).
229 *
230 *******************************************************************************/
Cy_PRA_ClkTimerInit(cy_en_clktimer_in_sources_t source,uint8_t divider)231 __STATIC_INLINE void Cy_PRA_ClkTimerInit(cy_en_clktimer_in_sources_t source, uint8_t divider)
232 {
233 Cy_SysClk_ClkTimerDisable();
234 Cy_SysClk_ClkTimerSetSource(source);
235 Cy_SysClk_ClkTimerSetDivider(divider);
236 Cy_SysClk_ClkTimerEnable();
237 }
238
239
240 /*******************************************************************************
241 * Function Name: Cy_PRA_PllInit
242 ****************************************************************************//**
243 *
244 * Initializes Phase Locked Loop. This function configures and enables PLL.
245 *
246 * \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid.
247 * \param pllConfig \ref cy_stc_pll_manual_config_t
248 *
249 * \return
250 * CY_PRA_STATUS_SUCCESS PLL init is success.
251 * CY_PRA_STATUS_ERROR_PROCESSING PLL init is failure.
252 *
253 *******************************************************************************/
Cy_PRA_PllInit(uint32_t clkPath,const cy_stc_pll_manual_config_t * pllConfig)254 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_PllInit(uint32_t clkPath, const cy_stc_pll_manual_config_t *pllConfig)
255 {
256 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(clkPath, pllConfig))
257 {
258 return CY_PRA_STATUS_ERROR_PROCESSING;
259 }
260 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(clkPath, 10000u))
261 {
262 return CY_PRA_STATUS_ERROR_PROCESSING;
263 }
264
265 return CY_PRA_STATUS_SUCCESS;
266 }
267
268
269 /*******************************************************************************
270 * Function Name: Cy_PRA_ClkHfInit
271 ****************************************************************************//**
272 *
273 * Initializes High Frequency Clock.
274 *
275 * \param clkHf selects which clkHf mux to configure.
276 * \param hfClkPath \ref cy_en_clkhf_in_sources_t
277 * \param divider \ref cy_en_clkhf_dividers_t
278 *
279 * \return
280 * CY_PRA_STATUS_SUCCESS CLK_HF init is success.
281 * CY_PRA_STATUS_ERROR_PROCESSING CLK_HF init is failure.
282 *
283 * \note
284 * There is no separate PRA function for CLK_HF set, divide, and enable.
285 * They are wrapped into a single PRA function.
286 *******************************************************************************/
Cy_PRA_ClkHfInit(uint32_t clkHf,cy_en_clkhf_in_sources_t hfClkPath,cy_en_clkhf_dividers_t divider)287 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_ClkHfInit( uint32_t clkHf, cy_en_clkhf_in_sources_t hfClkPath, cy_en_clkhf_dividers_t divider)
288 {
289 if (CY_SYSCLK_SUCCESS != Cy_SysClk_ClkHfSetSource(clkHf, hfClkPath))
290 {
291 return CY_PRA_STATUS_ERROR_PROCESSING;
292 }
293 if (CY_SYSCLK_SUCCESS != Cy_SysClk_ClkHfSetDivider(clkHf, divider))
294 {
295 return CY_PRA_STATUS_ERROR_PROCESSING;
296 }
297 if (CY_SYSCLK_SUCCESS != Cy_SysClk_ClkHfEnable(clkHf))
298 {
299 return CY_PRA_STATUS_ERROR_PROCESSING;
300 }
301
302 return CY_PRA_STATUS_SUCCESS;
303 }
304
305
306 /*******************************************************************************
307 * Function Name: Cy_PRA_FllInit
308 ****************************************************************************//**
309 *
310 * Initializes Frequency Locked Loop. This function configures FLL manually
311 * and enables FLL.
312 *
313 * \param devConfig
314 *
315 * \return
316 * CY_PRA_STATUS_SUCCESS FLL init is success
317 * CY_PRA_STATUS_ERROR_PROCESSING_FLL0 FLL init fails
318 *
319 *******************************************************************************/
Cy_PRA_FllInit(const cy_stc_pra_system_config_t * devConfig)320 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_FllInit(const cy_stc_pra_system_config_t *devConfig)
321 {
322 const cy_stc_fll_manual_config_t fllconfig =
323 {
324 .ccoRange = devConfig->fllCcoRange,
325 .cco_Freq = devConfig->ccoFreq,
326 .enableOutputDiv = devConfig->enableOutputDiv,
327 .fllMult = devConfig->fllMult,
328 .igain = devConfig->igain,
329 .lockTolerance = devConfig->lockTolerance,
330 .outputMode = devConfig->outputMode,
331 .pgain = devConfig->pgain,
332 .refDiv = devConfig->fllRefDiv,
333 .settlingCount = devConfig->settlingCount,
334 };
335
336 if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&fllconfig))
337 {
338 return CY_PRA_STATUS_ERROR_PROCESSING_FLL0;
339 }
340 if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(CY_PRA_FLL_ENABLE_TIMEOUT))
341 {
342 return CY_PRA_STATUS_ERROR_PROCESSING_FLL0;
343 }
344
345 return CY_PRA_STATUS_SUCCESS;
346 }
347
348
349 /*******************************************************************************
350 * Function Name: Cy_PRA_ExtClkInit
351 ****************************************************************************//**
352 *
353 * Initializes External Clock Source. This function initializes external pin and
354 * sets EXT_CLK frequency.
355 * The drive mode of the pin is hardcoded to \ref CY_GPIO_DM_HIGHZ. So User has to
356 * make sure this drive mode is not overwritten in application.
357 *
358 * \param devConfig
359 *
360 *******************************************************************************/
Cy_PRA_ExtClkInit(const cy_stc_pra_system_config_t * devConfig)361 __STATIC_INLINE void Cy_PRA_ExtClkInit( const cy_stc_pra_system_config_t *devConfig )
362 {
363 if (devConfig->extClkPort != NULL)
364 {
365 Cy_GPIO_Pin_FastInit(devConfig->extClkPort, devConfig->extClkPinNum, CY_GPIO_DM_HIGHZ, 0UL, devConfig->extClkHsiom);
366 }
367 Cy_SysClk_ExtClkSetFrequency(devConfig->extClkFreqHz);
368 }
369
370
371 /*******************************************************************************
372 * Function Name: Cy_PRA_EcoInit
373 ****************************************************************************//**
374 *
375 * Initializes External Crystal Oscillator. This function initializes input and
376 * output pins. Also configures and Enables ECO.
377 *
378 * \param devConfig
379 *
380 * \return
381 * CY_PRA_STATUS_SUCCESS CLK_ECO init is success.
382 * CY_PRA_STATUS_ERROR_PROCESSING_ECO CLK_ECO init is failure.
383 *
384 *******************************************************************************/
Cy_PRA_EcoInit(const cy_stc_pra_system_config_t * devConfig)385 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_EcoInit(const cy_stc_pra_system_config_t *devConfig)
386 {
387 if ((devConfig->ecoInPort != NULL) && (devConfig->ecoOutPort != NULL))
388 {
389 Cy_GPIO_Pin_FastInit(devConfig->ecoInPort, devConfig->ecoInPinNum, CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO);
390 Cy_GPIO_Pin_FastInit(devConfig->ecoOutPort, devConfig->ecoOutPinNum, CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO);
391 }
392 if (CY_SYSCLK_SUCCESS != Cy_SysClk_EcoConfigure(devConfig->ecoFreqHz, devConfig->ecoLoad, devConfig->ecoEsr, devConfig->ecoDriveLevel))
393 {
394 return CY_PRA_STATUS_ERROR_PROCESSING_ECO;
395 }
396 if (CY_SYSCLK_SUCCESS != Cy_SysClk_EcoEnable(CY_PRA_ECO_ENABLE_TIMEOUT))
397 {
398 return CY_PRA_STATUS_ERROR_PROCESSING_ECO;
399 }
400
401 return CY_PRA_STATUS_SUCCESS;
402 }
403
404
405 /*******************************************************************************
406 * Function Name: Cy_PRA_PiloInit
407 ****************************************************************************//**
408 *
409 * Initializes PILO.
410 *
411 *******************************************************************************/
Cy_PRA_PiloInit(void)412 __STATIC_INLINE void Cy_PRA_PiloInit(void)
413 {
414 Cy_SysClk_PiloEnable();
415 }
416
417
418 #if defined(CY_IP_MXBLESS)
419 /*******************************************************************************
420 * Function Name: Cy_PRA_AltHfInit
421 ****************************************************************************//**
422 *
423 * Initializes Alternative High-Frequency Clock.
424 *
425 * \param devConfig
426 *
427 * \return
428 * CY_PRA_STATUS_SUCCESS AltHF init is success
429 * CY_PRA_STATUS_ERROR_PROCESSING_ALTHF AltHF init failed
430 *
431 *******************************************************************************/
Cy_PRA_AltHfInit(const cy_stc_pra_system_config_t * devConfig)432 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_AltHfInit(const cy_stc_pra_system_config_t *devConfig)
433 {
434 cy_en_ble_eco_status_t status;
435 status = Cy_BLE_EcoConfigure((cy_en_ble_eco_freq_t)devConfig->altHFclkFreq, (cy_en_ble_eco_sys_clk_div_t)devConfig->altHFsysClkDiv, devConfig->altHFcLoad, devConfig->altHFxtalStartUpTime, (cy_en_ble_eco_voltage_reg_t)devConfig->altHFvoltageReg);
436 if ((CY_BLE_ECO_SUCCESS != status) && (CY_BLE_ECO_ALREADY_STARTED !=status))
437 {
438 return CY_PRA_STATUS_ERROR_PROCESSING_ALTHF;
439 }
440
441 return CY_PRA_STATUS_SUCCESS;
442 }
443
444 #endif /* CY_IP_MXBLESS */
445
446
447 /*******************************************************************************
448 * Function Name: Cy_PRA_ClkLfInit
449 ****************************************************************************//**
450 *
451 * Initializes Low-Frequency Clock.
452 *
453 * \param clkLfSource \ref cy_en_clklf_in_sources_t
454 *
455 * \return
456 * CY_PRA_STATUS_SUCCESS LF init is success.
457 * CY_PRA_STATUS_ERROR_PROCESSING_CLKLF LF init is failure.
458 *
459 *******************************************************************************/
Cy_PRA_ClkLfInit(cy_en_clklf_in_sources_t clkLfSource)460 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_ClkLfInit(cy_en_clklf_in_sources_t clkLfSource)
461 {
462 cy_en_pra_status_t retStatus = CY_PRA_STATUS_ERROR_PROCESSING_CLKLF;
463
464 if (clkLfSource == Cy_SysClk_ClkLfGetSource()) /* No change in CLK_LF */
465 {
466 retStatus = CY_PRA_STATUS_SUCCESS;
467 }
468 else
469 {
470 /* Cannot set an LF source when WDT is locked */
471 if (!Cy_WDT_Locked())
472 {
473 Cy_SysClk_ClkLfSetSource(clkLfSource);
474 retStatus = CY_PRA_STATUS_SUCCESS;
475 }
476 }
477 return retStatus;
478 }
479
480
481 /*******************************************************************************
482 * Function Name: Cy_PRA_WcoInit
483 ****************************************************************************//**
484 *
485 * Initializes Watch Crystal Oscillator.
486 *
487 * \param devConfig
488 *
489 * \return
490 * CY_PRA_STATUS_SUCCESS WCO init is success.
491 * CY_PRA_STATUS_ERROR_PROCESSING_WCO WCO init is failure.
492 *
493 *******************************************************************************/
Cy_PRA_WcoInit(const cy_stc_pra_system_config_t * devConfig)494 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_WcoInit(const cy_stc_pra_system_config_t *devConfig)
495 {
496 if ((devConfig->wcoInPort != NULL) && (devConfig->wcoOutPort != NULL))
497 {
498 Cy_GPIO_Pin_FastInit(devConfig->wcoInPort , devConfig->wcoInPinNum, 0x00U, 0x00U, HSIOM_SEL_GPIO);
499 Cy_GPIO_Pin_FastInit(devConfig->wcoOutPort , devConfig->wcoOutPinNum, 0x00U, 0x00U, HSIOM_SEL_GPIO);
500 }
501 if (devConfig->bypassEnable)
502 {
503 Cy_SysClk_WcoBypass(CY_SYSCLK_WCO_BYPASSED);
504 }
505 else
506 {
507 Cy_SysClk_WcoBypass(CY_SYSCLK_WCO_NOT_BYPASSED);
508 }
509
510 if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(CY_PRA_WCO_ENABLE_TIMEOUT))
511 {
512 return CY_PRA_STATUS_ERROR_PROCESSING_WCO;
513 }
514
515 return CY_PRA_STATUS_SUCCESS;
516 }
517
518
519 /*******************************************************************************
520 * Function Name: Cy_PRA_PowerInit
521 ****************************************************************************//**
522 *
523 * Initializes Power
524 *
525 * \param devConfig
526 *
527 * \return
528 * CY_PRA_STATUS_SUCCESS Power init is success.
529 * CY_PRA_STATUS_ERROR_PROCESSING_PWR Power init is failure.
530 *
531 *******************************************************************************/
Cy_PRA_PowerInit(const cy_stc_pra_system_config_t * devConfig)532 __STATIC_INLINE cy_en_pra_status_t Cy_PRA_PowerInit(const cy_stc_pra_system_config_t *devConfig)
533 {
534 if (devConfig->ldoEnable)
535 {
536 /* LDO valid voltage */
537 if ((devConfig->ldoVoltage == CY_SYSPM_LDO_VOLTAGE_0_9V) ||
538 (devConfig->ldoVoltage == CY_SYSPM_LDO_VOLTAGE_1_1V))
539 {
540 if (CY_SYSPM_SUCCESS != Cy_SysPm_LdoSetVoltage(devConfig->ldoVoltage))
541 {
542 return CY_PRA_STATUS_ERROR_PROCESSING_PWR;
543 }
544 }
545 }
546 else
547 {
548 if ((devConfig->buckVoltage == CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V) ||
549 (devConfig->buckVoltage == CY_SYSPM_BUCK_OUT1_VOLTAGE_1_1V))
550 {
551 if (CY_SYSPM_SUCCESS != Cy_SysPm_BuckEnable(devConfig->buckVoltage))
552 {
553 return CY_PRA_STATUS_ERROR_PROCESSING_PWR;
554 }
555 }
556 }
557
558 if (devConfig->pwrCurrentModeMin)
559 {
560 /* Sets the system into Minimum current mode of the core regulator */
561 if (CY_SYSPM_SUCCESS != Cy_SysPm_SystemSetMinRegulatorCurrent())
562 {
563 return CY_PRA_STATUS_ERROR_PROCESSING_PWR;
564 }
565 }
566 else
567 {
568 /* Sets the system into Normal current mode of the core regulator */
569 if (CY_SYSPM_SUCCESS != Cy_SysPm_SystemSetNormalRegulatorCurrent())
570 {
571 return CY_PRA_STATUS_ERROR_PROCESSING_PWR;
572 }
573 }
574
575 /* Configures PMIC */
576 Cy_SysPm_UnlockPmic();
577 if (devConfig->pmicEnable)
578 {
579 Cy_SysPm_PmicEnableOutput();
580 }
581 else
582 {
583 Cy_SysPm_PmicDisableOutput();
584 }
585
586 return CY_PRA_STATUS_SUCCESS;
587 }
588
589 /*******************************************************************************
590 * Function Name: Cy_PRA_GetInputPathMuxFrq
591 ****************************************************************************//**
592 *
593 * Gets Source clock frequency for the path mux.
594 *
595 * \param pathMuxSrc The source clock for PATH_MUX.
596 * \param devConfig System Configuration Parameter
597 *
598 * \return
599 * Returns the source frequency of the path mux.
600 *
601 *******************************************************************************/
Cy_PRA_GetInputPathMuxFrq(cy_en_clkpath_in_sources_t pathMuxSrc,const cy_stc_pra_system_config_t * devConfig)602 static uint32_t Cy_PRA_GetInputPathMuxFrq(cy_en_clkpath_in_sources_t pathMuxSrc, const cy_stc_pra_system_config_t *devConfig)
603 {
604 uint32_t srcFreq = CY_PRA_DEFAULT_SRC_FREQUENCY; /* Hz */
605
606 switch (pathMuxSrc)
607 {
608 case CY_SYSCLK_CLKPATH_IN_IMO:
609 {
610 srcFreq = CY_PRA_IMO_SRC_FREQUENCY; /* IMO Freq = 8 MHz */
611 }
612 break;
613 case CY_SYSCLK_CLKPATH_IN_EXT:
614 {
615 srcFreq = devConfig->extClkFreqHz;
616 }
617 break;
618 case CY_SYSCLK_CLKPATH_IN_ECO:
619 {
620 srcFreq = devConfig->ecoFreqHz;
621 }
622 break;
623 #if defined(CY_IP_MXBLESS)
624 case CY_SYSCLK_CLKPATH_IN_ALTHF:
625 {
626 (devConfig->altHFclkFreq == (uint32_t)CY_BLE_BLESS_ECO_FREQ_32MHZ) ? (srcFreq = CY_PRA_ALTHF_FREQ_32MHZ) : (srcFreq = CY_PRA_ALTHF_FREQ_16MHZ);
627 }
628 break;
629 #endif
630 case CY_SYSCLK_CLKPATH_IN_ILO:
631 {
632 srcFreq = CY_PRA_ILO_SRC_FREQUENCY; /* ILO Freq = 32 KHz */
633 }
634 break;
635 case CY_SYSCLK_CLKPATH_IN_WCO:
636 {
637 srcFreq = CY_PRA_WCO_SRC_FREQUENCY; /* WCO Freq = 32.768 KHz */
638 }
639 break;
640 case CY_SYSCLK_CLKPATH_IN_PILO:
641 {
642 if(CY_SRSS_PILO_PRESENT)
643 {
644 srcFreq = CY_PRA_PILO_SRC_FREQUENCY; /* PILO Freq = 32.768 KHz */
645 }
646 }
647 break;
648 default:
649 {
650 srcFreq = CY_PRA_DEFAULT_SRC_FREQUENCY;
651 }
652 break;
653 } /* End Switch */
654
655 return srcFreq;
656 }
657
658 /*******************************************************************************
659 * Function Name: Cy_PRA_GetInputSourceFreq
660 ****************************************************************************//**
661 *
662 * Gets the source clock frequency for the clock path. This function is called from the HF
663 * level.
664 *
665 * \param clkPath Clock Path
666 * \param devConfig System Configuration Parameter
667 * \param srcFreq The source frequency of the clock path which is updated in this function.
668 *
669 * \return
670 * CY_PRA_STATUS_SUCCESS If the frequency is updated.
671 * CY_PRA_STATUS_INVALID_PARAM If clkpath is not the valid path.
672 *
673 *******************************************************************************/
Cy_PRA_GetInputSourceFreq(uint32_t clkPath,const cy_stc_pra_system_config_t * devConfig,uint32_t * srcFreq)674 static cy_en_pra_status_t Cy_PRA_GetInputSourceFreq(uint32_t clkPath, const cy_stc_pra_system_config_t *devConfig, uint32_t *srcFreq )
675 {
676 cy_en_pra_status_t status = CY_PRA_STATUS_INVALID_PARAM;
677 *srcFreq = CY_PRA_DEFAULT_SRC_FREQUENCY;
678
679 if(clkPath >= CY_SRSS_NUM_CLKPATH)
680 {
681 return status;
682 }
683
684 switch (clkPath)
685 {
686 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0: /* CLK_PATH0 */
687 {
688 if (devConfig->path0Enable)
689 {
690 /* Checks for FLL, if FLL is enabled, returns the FLL output frequency */
691 if ((devConfig->fllEnable) && (devConfig->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT))
692 {
693 *srcFreq = devConfig->fllOutFreqHz;
694 status = CY_PRA_STATUS_SUCCESS;
695 }
696 else
697 {
698 *srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path0Src, devConfig);
699 status = CY_PRA_STATUS_SUCCESS;
700 }
701 }
702 }
703 break;
704 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH1: /* CLK_PATH1 */
705 {
706 if (devConfig->path1Enable)
707 {
708 /* Checks for PLL0, if PLL0 is enabled, returns the PLL0 output frequency */
709 if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_1) && (devConfig->pll0Enable) && (devConfig->pll0OutputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT))
710 {
711 *srcFreq = devConfig->pll0OutFreqHz;
712 status = CY_PRA_STATUS_SUCCESS;
713 }
714 else
715 {
716 *srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path1Src, devConfig);
717 status = CY_PRA_STATUS_SUCCESS;
718 }
719 }
720 }
721 break;
722 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH2: /* CLK_PATH2 */
723 {
724 if (devConfig->path2Enable)
725 {
726 /* Checks for PLL1, if PLL1 is enabled, returns the PLL1 output frequency */
727 if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_2) && (devConfig->pll1Enable) && (devConfig->pll1OutputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT))
728 {
729 *srcFreq = devConfig->pll1OutFreqHz;
730 status = CY_PRA_STATUS_SUCCESS;
731 }
732 else
733 {
734 *srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path2Src, devConfig);
735 status = CY_PRA_STATUS_SUCCESS;
736 }
737 }
738 }
739 break;
740 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH3: /* CLK_PATH3 */
741 {
742 if (devConfig->path3Enable)
743 {
744 *srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path3Src, devConfig);
745 status = CY_PRA_STATUS_SUCCESS;
746 }
747 }
748 break;
749 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH4: /* CLK_PATH4 */
750 {
751 if (devConfig->path4Enable)
752 {
753 *srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path4Src, devConfig);
754 status = CY_PRA_STATUS_SUCCESS;
755 }
756 }
757 break;
758 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH5: /* CLK_PATH5 */
759 {
760 if (devConfig->path5Enable)
761 {
762 *srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path5Src, devConfig);
763 status = CY_PRA_STATUS_SUCCESS;
764 }
765 }
766 break;
767 default:
768 {
769 *srcFreq = CY_PRA_DEFAULT_SRC_FREQUENCY;
770 }
771 break;
772 }
773
774 return status;
775 }
776
777 /*******************************************************************************
778 * Function Name: Cy_PRA_GetHF0FreqHz
779 ****************************************************************************//**
780 *
781 * Get HF0 frequency in Hz. When HF0 is sourced from LF clocks then the output
782 * frequency of HF0 is "0" in MHz. So HF0 output frequency has to be calculated
783 * and returned in Hz.
784 *
785 * \param devConfig System Configuration Parameter
786 *
787 * \return HF0 frequency in Hz
788 *
789 *******************************************************************************/
Cy_PRA_GetHF0FreqHz(const cy_stc_pra_system_config_t * devConfig)790 static uint32_t Cy_PRA_GetHF0FreqHz(const cy_stc_pra_system_config_t *devConfig)
791 {
792 uint32_t retFreq;
793 /* if HF0 output frequency is 0, then calculate HF0 output frequency from HF_PATH frequency */
794 if (devConfig->hf0OutFreqMHz != 0UL)
795 {
796 retFreq = (devConfig->hf0OutFreqMHz * CY_PRA_FREQUENCY_HZ_CONVERSION);
797 }
798 else
799 {
800 retFreq = CY_SYSLIB_DIV_ROUND(Cy_SysClk_ClkPathGetFrequency((uint32_t) devConfig->hf0Source),(1UL << ((uint32_t)devConfig->hf0Divider)));
801 }
802
803 return retFreq;
804 }
805
806 /*******************************************************************************
807 * Function Name: Cy_PRA_GetClkLfFreq
808 ****************************************************************************//**
809 *
810 * Gets Low-Frequency Clock (CLK_LF).
811 *
812 * \param devConfig System Configuration Parameter
813 *
814 * \return CLK_LF The frequency.
815 *
816 *******************************************************************************/
Cy_PRA_GetClkLfFreq(const cy_stc_pra_system_config_t * devConfig)817 static uint32_t Cy_PRA_GetClkLfFreq(const cy_stc_pra_system_config_t *devConfig)
818 {
819 uint32_t freq = CY_PRA_DEFAULT_SRC_FREQUENCY;
820
821 if (devConfig->clkLFEnable)
822 {
823 switch (devConfig->clkLfSource)
824 {
825 case CY_SYSCLK_CLKLF_IN_ILO:
826 {
827 if (devConfig->iloEnable)
828 {
829 freq = CY_PRA_ILO_SRC_FREQUENCY;
830 }
831 }
832 break;
833 case CY_SYSCLK_CLKLF_IN_WCO:
834 {
835 if (devConfig->wcoEnable)
836 {
837 freq = CY_PRA_WCO_SRC_FREQUENCY;
838 }
839 }
840 break;
841 case CY_SYSCLK_CLKLF_IN_PILO:
842 {
843 if ((devConfig->piloEnable) && (CY_SRSS_PILO_PRESENT))
844 {
845 freq = CY_PRA_PILO_SRC_FREQUENCY;
846 }
847 }
848 break;
849 default:
850 {
851 freq = CY_PRA_DEFAULT_SRC_FREQUENCY;
852 }
853 break;
854 } /* End Switch */
855 }
856
857 return freq;
858 }
859
860 /*******************************************************************************
861 * Function Name: Cy_PRA_GetClkBakFreq
862 ****************************************************************************//**
863 *
864 * Gets the BAK Clock (CLK_BAK) frequency.
865 *
866 * \param devConfig System Configuration Parameter
867 *
868 * \return CLK_LF The frequency.
869 *
870 *******************************************************************************/
Cy_PRA_GetClkBakFreq(const cy_stc_pra_system_config_t * devConfig)871 static uint32_t Cy_PRA_GetClkBakFreq(const cy_stc_pra_system_config_t *devConfig)
872 {
873 uint32_t freq = CY_PRA_DEFAULT_SRC_FREQUENCY;
874
875 if (devConfig->clkBakEnable)
876 {
877 switch (devConfig->clkBakSource)
878 {
879 case CY_SYSCLK_BAK_IN_WCO:
880 {
881 if (devConfig->wcoEnable)
882 {
883 freq = CY_PRA_WCO_SRC_FREQUENCY;
884 }
885 }
886 break;
887 case CY_SYSCLK_BAK_IN_CLKLF:
888 {
889 if (devConfig->clkLFEnable)
890 {
891 freq = Cy_PRA_GetClkLfFreq(devConfig);
892 }
893 }
894 break;
895 default:
896 {
897 freq = CY_PRA_DEFAULT_SRC_FREQUENCY;
898 }
899 break;
900 } /* End Switch */
901 }
902
903 return freq;
904 }
905
906 /*******************************************************************************
907 * Function Name: Cy_PRA_GetInputSourceClock
908 ****************************************************************************//**
909 *
910 * Gets the source clock for the clock path.
911 *
912 * \param clkPath Clock Path
913 * \param devConfig System Configuration Parameter
914 * \param status
915 * CY_PRA_STATUS_SUCCESS for valid input configuration
916 * CY_PRA_STATUS_INVALID_PARAM for bad parameter
917 *
918 * \return
919 * Returns the source clock.
920 *
921 *******************************************************************************/
Cy_PRA_GetInputSourceClock(uint32_t clkPath,const cy_stc_pra_system_config_t * devConfig,cy_en_pra_status_t * status)922 static cy_en_clkpath_in_sources_t Cy_PRA_GetInputSourceClock(uint32_t clkPath, const cy_stc_pra_system_config_t *devConfig, cy_en_pra_status_t *status)
923 {
924 cy_en_clkpath_in_sources_t srcClock = CY_SYSCLK_CLKPATH_IN_IMO;
925
926 if(clkPath >= CY_SRSS_NUM_CLKPATH)
927 {
928 *status = CY_PRA_STATUS_INVALID_PARAM;
929 return srcClock;
930 }
931
932 *status = CY_PRA_STATUS_INVALID_PARAM;
933
934 switch (clkPath)
935 {
936 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0: /* CLK_PATH0 */
937 {
938 if (devConfig->path0Enable) /* Checks for PATH_MUX0 enable/disable */
939 {
940 srcClock = devConfig->path0Src;
941 *status = CY_PRA_STATUS_SUCCESS;
942 }
943 }
944 break;
945 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH1: /* CLK_PATH1 */
946 {
947 if (devConfig->path1Enable) /* Checks for PATH_MUX1 enable/disable */
948 {
949 srcClock = devConfig->path1Src;
950 *status = CY_PRA_STATUS_SUCCESS;
951 }
952 }
953 break;
954 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH2: /* CLK_PATH2 */
955 {
956 if (devConfig->path2Enable) /* Checks for PATH_MUX2 enable/disable */
957 {
958 srcClock = devConfig->path2Src;
959 *status = CY_PRA_STATUS_SUCCESS;
960 }
961 }
962 break;
963 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH3: /* CLK_PATH3 */
964 {
965 if (devConfig->path3Enable) /* Checks for PATH_MUX3 enable/disable */
966 {
967 srcClock = devConfig->path3Src;
968 *status = CY_PRA_STATUS_SUCCESS;
969 }
970 }
971 break;
972 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH4: /* CLK_PATH4 */
973 {
974 if (devConfig->path4Enable) /* Checks for PATH_MUX4 enable/disable */
975 {
976 srcClock = devConfig->path4Src;
977 *status = CY_PRA_STATUS_SUCCESS;
978 }
979 }
980 break;
981 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH5: /* CLK_PATH5 */
982 {
983 if (devConfig->path5Enable) /* Checks for PATH_MUX5 enable/disable */
984 {
985 srcClock = devConfig->path5Src;
986 *status = CY_PRA_STATUS_SUCCESS;
987 }
988 }
989 break;
990 default:
991 {
992 /* Returns CY_PRA_STATUS_INVALID_PARAM */
993 }
994 break;
995 }
996
997 return srcClock;
998 }
999
1000 /*******************************************************************************
1001 * Function Name: Cy_PRA_ValidateECO
1002 ****************************************************************************//**
1003 *
1004 * Validates the ECO.
1005 *
1006 * \param devConfig System Configuration Parameter
1007 *
1008 * \return
1009 * CY_PRA_STATUS_SUCCESS For valid input configuration.
1010 * CY_PRA_STATUS_INVALID_PARAM_ECO For the invalid parameter.
1011 *
1012 *******************************************************************************/
Cy_PRA_ValidateECO(const cy_stc_pra_system_config_t * devConfig)1013 static cy_en_pra_status_t Cy_PRA_ValidateECO(const cy_stc_pra_system_config_t *devConfig)
1014 {
1015 cy_en_pra_status_t retStatus = CY_PRA_STATUS_SUCCESS;
1016
1017 if ((CY_SYSCLK_ECOSTAT_STABLE != Cy_SysClk_EcoGetStatus()) && (devConfig->ecoEnable))
1018 {
1019 if (((devConfig->ecoFreqHz >= CY_PRA_ECO_FREQ_MIN) && (devConfig->ecoFreqHz <= CY_PRA_ECO_FREQ_MAX)) /* legal range of ECO frequency is [16.0000-35.0000] */
1020 && ((devConfig->ecoLoad >= CY_PRA_ECO_CSM_MIN) && (devConfig->ecoLoad <= CY_PRA_ECO_CSM_MAX)) /* ECO cLoad range [1 - 100] */
1021 && ((devConfig->ecoEsr >= CY_PRA_ECO_ESR_MIN) && (devConfig->ecoEsr <= CY_PRA_ECO_ESR_MAX)) /* ECO ESR range [1 - 1000] */
1022 && ((devConfig->ecoDriveLevel >= CY_PRA_ECO_DRV_MIN) && (devConfig->ecoDriveLevel <= CY_PRA_ECO_DRV_MAX))) /* ECO Drive Level range [1 - 1000] */
1023 {
1024 retStatus = CY_PRA_STATUS_SUCCESS;
1025 }
1026 else
1027 {
1028 retStatus = CY_PRA_STATUS_INVALID_PARAM_ECO;
1029 }
1030 }
1031
1032 return retStatus;
1033 }
1034
1035 /*******************************************************************************
1036 * Function Name: Cy_PRA_ValidateExtClkConfig
1037 ****************************************************************************//**
1038 *
1039 * Validate External Clocks in respect to provisioned data
1040 *
1041 * \param devConfig System Configuration Parameter
1042 *
1043 * \return
1044 * CY_PRA_STATUS_SUCCESS for valid input configuration.
1045 * CY_PRA_STATUS_INVALID_EXTCLK_PROVISION for invalid EXTCLK input configuration.
1046 * CY_PRA_STATUS_INVALID_ECO_PROVISION for invalid ECO input configuration.
1047 * CY_PRA_STATUS_INVALID_WCO_PROVISION for invalid WCO input configuration.
1048 * CY_PRA_STATUS_ERROR_PROCESSING_EXTCLK_PROVISION if failed to process provisioned data
1049 * or devConfig is NULL.
1050 *
1051 *******************************************************************************/
Cy_PRA_ValidateExtClkConfig(const cy_stc_pra_system_config_t * devConfig)1052 static cy_en_pra_status_t Cy_PRA_ValidateExtClkConfig(const cy_stc_pra_system_config_t *devConfig)
1053 {
1054 cy_en_pra_status_t clkStatus, retStatus = CY_PRA_STATUS_SUCCESS;
1055 cy_en_clkpath_in_sources_t hf0SourceClk;
1056
1057 hf0SourceClk = Cy_PRA_GetInputSourceClock((uint32_t) devConfig->hf0Source, devConfig, &clkStatus);
1058 if (clkStatus != CY_PRA_STATUS_SUCCESS)
1059 {
1060 retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKHF0;
1061 }
1062 else
1063 {
1064 /* check for provision data only if External clock source to HF0 */
1065 switch (hf0SourceClk)
1066 {
1067 case CY_SYSCLK_CLKPATH_IN_EXT:
1068 {
1069 if ((NULL == extClkPolicyPtr) ||
1070 (!((extClkPolicyPtr->extClkEnable) &&
1071 (extClkPolicyPtr->extClkFreqHz == devConfig->extClkFreqHz) &&
1072 (extClkPolicyPtr->extClkPort == devConfig->extClkPort) &&
1073 (extClkPolicyPtr->extClkPinNum == devConfig->extClkPinNum) &&
1074 (HSIOM_SEL_ACT_4 == devConfig->extClkHsiom)))) /* HSIOM_SEL_ACT_4 is Digital Active
1075 * port settings for srss.ext_clk, equals to
1076 * P0_0_SRSS_EXT_CLK or P0_5_SRSS_EXT_CLK
1077 */
1078 {
1079 retStatus = CY_PRA_STATUS_ERROR_PROCESSING_EXTCLK_PROVISION;
1080 }
1081 }
1082 break;
1083 case CY_SYSCLK_CLKPATH_IN_ECO:
1084 {
1085 if ((NULL == extClkPolicyPtr) ||
1086 (!((extClkPolicyPtr->ecoEnable) &&
1087 (extClkPolicyPtr->ecoFreqHz == devConfig->ecoFreqHz) &&
1088 (extClkPolicyPtr->ecoLoad == devConfig->ecoLoad) &&
1089 (extClkPolicyPtr->ecoEsr == devConfig->ecoEsr) &&
1090 (extClkPolicyPtr->ecoDriveLevel == devConfig->ecoDriveLevel) &&
1091 (extClkPolicyPtr->ecoInPort == devConfig->ecoInPort) &&
1092 (extClkPolicyPtr->ecoOutPort == devConfig->ecoOutPort) &&
1093 (extClkPolicyPtr->ecoInPinNum == devConfig->ecoInPinNum) &&
1094 (extClkPolicyPtr->ecoOutPinNum == devConfig->ecoOutPinNum))))
1095 {
1096 retStatus = CY_PRA_STATUS_ERROR_PROCESSING_ECO_PROVISION;
1097 }
1098 }
1099 break;
1100 case CY_SYSCLK_CLKPATH_IN_WCO:
1101 {
1102 if ((NULL == extClkPolicyPtr) ||
1103 (!((extClkPolicyPtr->wcoEnable) &&
1104 (extClkPolicyPtr->bypassEnable == devConfig->bypassEnable) &&
1105 (extClkPolicyPtr->wcoInPort == devConfig->wcoInPort) &&
1106 (extClkPolicyPtr->wcoOutPort == devConfig->wcoOutPort) &&
1107 (extClkPolicyPtr->wcoInPinNum == devConfig->wcoInPinNum) &&
1108 (extClkPolicyPtr->wcoOutPinNum == devConfig->wcoOutPinNum))))
1109 {
1110 retStatus = CY_PRA_STATUS_ERROR_PROCESSING_WCO_PROVISION;
1111 }
1112 }
1113 break;
1114 default:
1115 /* None of the external clocks are source to HF0. So skipping validation for provisioning */
1116 break;
1117 } /* end switch case */
1118 } /* end if (clkStatus != CY_PRA_STATUS_SUCCESS) */
1119
1120 return retStatus;
1121 }
1122
1123 /*******************************************************************************
1124 * Function Name: Cy_PRA_ValidateEXTClk
1125 ****************************************************************************//**
1126 *
1127 * Validates External Clock Source.
1128 *
1129 * \param devConfig System Configuration Parameter
1130 *
1131 * \return
1132 * CY_PRA_STATUS_SUCCESS For valid input configuration.
1133 * CY_PRA_STATUS_INVALID_PARAM_EXTCLK For the invalid parameter.
1134 *
1135 *******************************************************************************/
Cy_PRA_ValidateEXTClk(const cy_stc_pra_system_config_t * devConfig)1136 static cy_en_pra_status_t Cy_PRA_ValidateEXTClk(const cy_stc_pra_system_config_t *devConfig)
1137 {
1138 uint32_t maxFreq;
1139
1140 /* For ULP mode, Fextclk_max = 50 MHz. For LP mode, Fextclk_max = 100 MHz or Fcpu_max (if Fcpu_max < 100 MHz) */
1141 if (devConfig->extClkEnable)
1142 {
1143 if (devConfig->ulpEnable)
1144 {
1145 if (devConfig->extClkFreqHz > CY_PRA_ULP_MODE_MAX_FREQUENCY)
1146 {
1147 return CY_PRA_STATUS_INVALID_PARAM_EXTCLK;
1148 }
1149 }
1150 else
1151 {
1152 CY_MISRA_FP_LINE('MISRA C-2012 Rule 14.3','CY_HF_CLK_MAX_FREQ varies based on target device and this statement may not be always true.');
1153 (CY_HF_CLK_MAX_FREQ > CY_PRA_LP_MODE_MAX_FREQUENCY) ? (maxFreq = CY_PRA_LP_MODE_MAX_FREQUENCY) : (maxFreq = CY_HF_CLK_MAX_FREQ);
1154 if (devConfig->extClkFreqHz > maxFreq)
1155 {
1156 return CY_PRA_STATUS_INVALID_PARAM_EXTCLK;
1157 }
1158 } /*usingULP*/
1159
1160 /* GPIO port cannot be NULL */
1161 if (devConfig->extClkPort == NULL)
1162 {
1163 return CY_PRA_STATUS_INVALID_PARAM_EXTCLK;
1164 }
1165 }
1166
1167 return CY_PRA_STATUS_SUCCESS;
1168 }
1169
1170 #if defined(CY_IP_MXBLESS)
1171
1172 /*******************************************************************************
1173 * Function Name: Cy_PRA_ValidateAltHf
1174 ****************************************************************************//**
1175 *
1176 * Validates Alternative High-Frequency Clock.
1177 *
1178 * \param devConfig System Configuration Parameter
1179 *
1180 * \return
1181 * CY_PRA_STATUS_SUCCESS For the valid input configuration.
1182 * CY_PRA_STATUS_INVALID_PARAM_ALTHF For the invalid parameter.
1183 *
1184 *******************************************************************************/
Cy_PRA_ValidateAltHf(const cy_stc_pra_system_config_t * devConfig)1185 static cy_en_pra_status_t Cy_PRA_ValidateAltHf(const cy_stc_pra_system_config_t *devConfig)
1186 {
1187
1188 if (devConfig->clkAltHfEnable)
1189 {
1190 uint32_t startupTime;
1191 /* Validates the frequency */
1192 if (devConfig->altHFclkFreq > (uint32_t)CY_BLE_BLESS_ECO_FREQ_32MHZ)
1193 {
1194 return CY_PRA_STATUS_INVALID_PARAM_ALTHF;
1195 }
1196 /* Startup Time */
1197 startupTime = devConfig->altHFxtalStartUpTime << 5U;
1198 if ((startupTime < CY_PRA_ALTHF_MIN_STARTUP_TIME) || (startupTime > CY_PRA_ALTHF_MAX_STARTUP_TIME))
1199 {
1200 return CY_PRA_STATUS_INVALID_PARAM_ALTHF;
1201 }
1202 /* Load Cap Range min="7.5 -> 0U" max="26.325 -> 251U" */
1203 if (devConfig->altHFcLoad > ((uint32_t)CY_PRA_ALTHF_MAX_LOAD))
1204 {
1205 return CY_PRA_STATUS_INVALID_PARAM_ALTHF;
1206 }
1207 /* Validates the clock divider */
1208 if (devConfig->altHFsysClkDiv > ((uint32_t)CY_BLE_SYS_ECO_CLK_DIV_8))
1209 {
1210 return CY_PRA_STATUS_INVALID_PARAM_ALTHF;
1211 }
1212 }
1213 return CY_PRA_STATUS_SUCCESS;
1214 }
1215 #endif /* CY_IP_MXBLESS */
1216
1217 /*******************************************************************************
1218 * Function Name: Cy_PRA_ValidateFLL
1219 ****************************************************************************//**
1220 *
1221 * Validates the Frequency Locked Loop (FLL).
1222 *
1223 * \param devConfig System Configuration Parameter
1224 *
1225 * \return
1226 * CY_PRA_STATUS_SUCCESS For the valid input configuration.
1227 * CY_PRA_STATUS_INVALID_PARAM_FLL For the invalid parameter.
1228 *
1229 *******************************************************************************/
Cy_PRA_ValidateFLL(const cy_stc_pra_system_config_t * devConfig)1230 static cy_en_pra_status_t Cy_PRA_ValidateFLL(const cy_stc_pra_system_config_t *devConfig)
1231 {
1232 uint32_t srcFreq;
1233
1234 /* Validates FLL only when its state changes Disable -> Enable */
1235 if ((!Cy_SysClk_FllIsEnabled()) && (devConfig->fllEnable))
1236 {
1237 /* FLL is always sourced from PATH_MUX0 */
1238 /* If FLL is sourced from ILO, PILO or any external clock, then FLL output cannot source
1239 * to HF0. HF0 validation will check that. */
1240 if (devConfig->path0Enable)
1241 {
1242 /* The source clock for the FLL valid range is 1 kHz - 100 MHz */
1243 srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path0Src, devConfig);
1244 if ((srcFreq < CY_PRA_FLL_SRC_MIN_FREQUENCY) || (srcFreq > CY_PRA_FLL_SRC_MAX_FREQUENCY))
1245 {
1246 return CY_PRA_STATUS_INVALID_PARAM_FLL0;
1247 }
1248
1249 /* For ULP mode, the out frequency range is 24 - 50 MHz */
1250 /* For LP mode, theout frequency range is 24 - 100 MHz */
1251 if (devConfig->ulpEnable)
1252 {
1253 if ((devConfig->fllOutFreqHz < CY_PRA_FLL_OUT_MIN_FREQUENCY) || (devConfig->fllOutFreqHz > CY_PRA_FLL_ULP_OUT_MAX_FREQUENCY))
1254 {
1255 return CY_PRA_STATUS_INVALID_PARAM_FLL0;
1256 }
1257 }
1258 else
1259 {
1260 CY_MISRA_FP_LINE('MISRA C-2012 Rule 14.3','CY_HF_CLK_MAX_FREQ varies based on target device and this statement may not be always true.');
1261 if ((devConfig->fllOutFreqHz < CY_PRA_FLL_OUT_MIN_FREQUENCY) || (devConfig->fllOutFreqHz > CY_PRA_FLL_OUT_MAX_FREQUENCY))
1262 {
1263 return CY_PRA_STATUS_INVALID_PARAM_FLL0;
1264 }
1265 } /*usingULP*/
1266
1267 /* Validates multiplier min="1" max="262143" */
1268 if ((devConfig->fllMult < CY_PRA_FLL_MIN_MULTIPLIER) || (devConfig->fllMult > CY_PRA_FLL_MAX_MULTIPLIER))
1269 {
1270 return CY_PRA_STATUS_INVALID_PARAM_FLL0;
1271 }
1272 /* Validates reference min="1" max="8191" */
1273 if ((devConfig->fllRefDiv < CY_PRA_FLL_MIN_REFDIV) || (devConfig->fllRefDiv > CY_PRA_FLL_MAX_REFDIV))
1274 {
1275 return CY_PRA_STATUS_INVALID_PARAM_FLL0;
1276 }
1277 /* ccoRange */
1278 if (devConfig->fllCcoRange > CY_SYSCLK_FLL_CCO_RANGE4)
1279 {
1280 return CY_PRA_STATUS_INVALID_PARAM_FLL0;
1281 }
1282 /* lockTolerance min="0" max="511" */
1283 if (devConfig->lockTolerance > CY_PRA_FLL_MAX_LOCK_TOLERENCE)
1284 {
1285 return CY_PRA_STATUS_INVALID_PARAM_FLL0;
1286 }
1287 if (devConfig->igain > (SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk >> SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos))
1288 {
1289 return CY_PRA_STATUS_INVALID_PARAM_FLL0;
1290 }
1291 if (devConfig->pgain > (SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk >> SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos))
1292 {
1293 return CY_PRA_STATUS_INVALID_PARAM_FLL0;
1294 }
1295 if (devConfig->settlingCount > (SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk >> SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos))
1296 {
1297 return CY_PRA_STATUS_INVALID_PARAM_FLL0;
1298 }
1299 if (devConfig->ccoFreq > (SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk >> SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos))
1300 {
1301 return CY_PRA_STATUS_INVALID_PARAM_FLL0;
1302 }
1303
1304 /* devConfig->fllOutFreqHz can be compared with calculated FLL output value with % of accuracy - DRIVERS-3751 */
1305
1306 return CY_PRA_STATUS_SUCCESS;
1307 }
1308 else
1309 {
1310 return CY_PRA_STATUS_INVALID_PARAM_FLL0;
1311 }
1312 }
1313
1314 return CY_PRA_STATUS_SUCCESS;
1315 }
1316
1317 /*******************************************************************************
1318 * Function Name: Cy_PRA_ValidatePLL
1319 ****************************************************************************//**
1320 *
1321 * Validates Phase Locked Loop (PLL).
1322 *
1323 * \param devConfig System Configuration Parameter
1324 * \param pll The PLL number.
1325 *
1326 * \return
1327 * CY_PRA_STATUS_SUCCESS For the valid input configuration.
1328 * CY_PRA_STATUS_INVALID_PARAM For the invalid parameter.
1329 *
1330 *******************************************************************************/
Cy_PRA_ValidatePLL(const cy_stc_pra_system_config_t * devConfig,uint8_t pll)1331 static cy_en_pra_status_t Cy_PRA_ValidatePLL(const cy_stc_pra_system_config_t *devConfig, uint8_t pll)
1332 {
1333 uint32_t srcFreq, outFreq, minDesiredOutFreq;
1334 bool pllEnable, pathEnable, lowFreqMode;
1335 cy_en_clkpath_in_sources_t pathSrc;
1336
1337 if ((pll == CY_PRA_DEFAULT_ZERO) || (pll > CY_SRSS_NUM_PLL))
1338 {
1339 return CY_PRA_STATUS_INVALID_PARAM;
1340 }
1341
1342 if (pll == CY_PRA_CLKPLL_1)
1343 {
1344 pllEnable = devConfig->pll0Enable;
1345 pathEnable = devConfig->path1Enable;
1346 pathSrc = devConfig->path1Src;
1347 outFreq = devConfig->pll0OutFreqHz;
1348 lowFreqMode = devConfig->pll0LfMode;
1349 }
1350 else if (pll == CY_PRA_CLKPLL_2)
1351 {
1352 pllEnable = devConfig->pll1Enable;
1353 pathEnable = devConfig->path2Enable;
1354 pathSrc = devConfig->path2Src;
1355 outFreq = devConfig->pll1OutFreqHz;
1356 lowFreqMode = devConfig->pll1LfMode;
1357 }
1358 else
1359 {
1360 return CY_PRA_STATUS_INVALID_PARAM;
1361 }
1362
1363 /* If PLL is sourced from ILO, PILO, or any external clock, then the PLL output cannot source
1364 * to HF0. This check is performed at HF0 validation */
1365 if (pllEnable)
1366 {
1367 if (pathEnable)
1368 {
1369 /* The PLL source clock valid range is 4 MHz - 64 MHz */
1370 srcFreq = Cy_PRA_GetInputPathMuxFrq(pathSrc, devConfig);
1371 if ((srcFreq < CY_PRA_PLL_SRC_MIN_FREQUENCY) || (srcFreq > CY_PRA_PLL_SRC_MAX_FREQUENCY))
1372 {
1373 return CY_PRA_STATUS_INVALID_PARAM;
1374 }
1375
1376 /* If Low frequency mode is enabled, the PLL minimum output frequency is 10.625 MHz otherwise 12.5 MHz */
1377 (lowFreqMode) ? (minDesiredOutFreq = CY_PRA_PLL_LOW_OUT_MIN_FREQUENCY) : (minDesiredOutFreq = CY_PRA_PLL_OUT_MIN_FREQUENCY);
1378 /* For ULP mode, the out frequency is < 50 MHz */
1379 /* For LP mode, the out frequency is < CY_HF_CLK_MAX_FREQ */
1380 if (devConfig->ulpEnable)
1381 {
1382 if ((outFreq < minDesiredOutFreq) || (outFreq > CY_PRA_PLL_ULP_OUT_MAX_FREQUENCY))
1383 {
1384 return CY_PRA_STATUS_INVALID_PARAM;
1385 }
1386 }
1387 else
1388 {
1389 if ((outFreq < minDesiredOutFreq) || (outFreq > CY_PRA_PLL_OUT_MAX_FREQUENCY))
1390 {
1391 return CY_PRA_STATUS_INVALID_PARAM;
1392 }
1393 } /*usingULP*/
1394
1395 /* Checks the PLL output frequency */
1396 if (outFreq != Cy_PRA_CalculatePLLOutFreq(pll, devConfig))
1397 {
1398 return CY_PRA_STATUS_INVALID_PARAM;
1399 }
1400 }
1401 else
1402 {
1403 return CY_PRA_STATUS_INVALID_PARAM;
1404 }
1405 }
1406
1407 return CY_PRA_STATUS_SUCCESS;
1408 }
1409
1410 /*******************************************************************************
1411 * Function Name: Cy_PRA_ValidateAllPLL
1412 ****************************************************************************//**
1413 *
1414 * Validates All Phase Locked Loop (PLL).
1415 *
1416 * \param devConfig System Configuration Parameter
1417 *
1418 * \return
1419 * CY_PRA_STATUS_SUCCESS For the valid input configuration.
1420 * CY_PRA_STATUS_INVALID_PARAM_PLL0 For the PLLO invalid parameter.
1421 * CY_PRA_STATUS_INVALID_PARAM_PLL1 For the PLL1 invalid parameter.
1422 *
1423 *******************************************************************************/
Cy_PRA_ValidateAllPLL(const cy_stc_pra_system_config_t * devConfig)1424 static cy_en_pra_status_t Cy_PRA_ValidateAllPLL(const cy_stc_pra_system_config_t *devConfig)
1425 {
1426 cy_en_pra_status_t retStatus = CY_PRA_STATUS_SUCCESS;
1427
1428 /* PLL0 is always sourced from PATH_MUX1 */
1429 if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_1) && (devConfig->pll0Enable))
1430 {
1431 /* Validates PLL1 only when its state changes Disable -> Enable */
1432 if (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_1))
1433 {
1434 retStatus = Cy_PRA_ValidatePLL(devConfig, CY_PRA_CLKPLL_1);
1435 }
1436
1437 if (CY_PRA_STATUS_SUCCESS != retStatus)
1438 {
1439 retStatus = CY_PRA_STATUS_INVALID_PARAM_PLL0;
1440 }
1441 }
1442 /* PLL1 is always sourced from PATH_MUX2 */
1443 if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_2) && (devConfig->pll1Enable) && (retStatus == CY_PRA_STATUS_SUCCESS))
1444 {
1445 /* Validates PLL2 only when its state changes Disable -> Enable */
1446 if (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_2))
1447 {
1448 retStatus = Cy_PRA_ValidatePLL(devConfig, CY_PRA_CLKPLL_2);
1449 }
1450
1451 if (CY_PRA_STATUS_SUCCESS != retStatus)
1452 {
1453 retStatus = CY_PRA_STATUS_INVALID_PARAM_PLL1;
1454 }
1455 }
1456 return retStatus;
1457 }
1458
1459 /*******************************************************************************
1460 * Function Name: Cy_PRA_ValidateClkLf
1461 ****************************************************************************//**
1462 *
1463 * Validates Low-Frequency Clock (CLK_LF).
1464 *
1465 * \param devConfig System Configuration Parameter
1466 *
1467 * \return
1468 * CY_PRA_STATUS_SUCCESS For the valid input configuration.
1469 * CY_PRA_STATUS_INVALID_PARAM_CLKLF For the invalid parameter.
1470 *
1471 *******************************************************************************/
Cy_PRA_ValidateClkLf(const cy_stc_pra_system_config_t * devConfig)1472 static cy_en_pra_status_t Cy_PRA_ValidateClkLf(const cy_stc_pra_system_config_t *devConfig)
1473 {
1474 cy_en_pra_status_t retStatus = CY_PRA_STATUS_SUCCESS;
1475
1476 /* output frequency = input frequency [range min="0" max="100000"] */
1477 if (devConfig->clkLFEnable)
1478 {
1479 switch (devConfig->clkLfSource)
1480 {
1481 case CY_SYSCLK_CLKLF_IN_ILO:
1482 {
1483 (devConfig->iloEnable) ? (retStatus = CY_PRA_STATUS_SUCCESS) : (retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKLF);
1484 }
1485 break;
1486 case CY_SYSCLK_CLKLF_IN_WCO:
1487 {
1488 (devConfig->wcoEnable) ? (retStatus = CY_PRA_STATUS_SUCCESS) : (retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKLF);
1489 }
1490 break;
1491 case CY_SYSCLK_CLKLF_IN_PILO:
1492 {
1493 ((devConfig->piloEnable) && (CY_SRSS_PILO_PRESENT)) ? (retStatus = CY_PRA_STATUS_SUCCESS) : (retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKLF);
1494 }
1495 break;
1496 default:
1497 {
1498 retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKLF;
1499 }
1500 break;
1501 } /* End of Switch */
1502 }
1503
1504 return retStatus;
1505 }
1506
1507 /*******************************************************************************
1508 * Function Name: Cy_PRA_ValidateClkPathMux
1509 ****************************************************************************//**
1510 *
1511 * Returns an error if the specified path source is disabled.
1512 *
1513 * \param pathSrc Source clock for the PATH_MUX
1514 * \param devConfig System Configuration Parameter
1515 *
1516 * \return
1517 * CY_PRA_STATUS_SUCCESS For the valid input configuration.
1518 * CY_PRA_STATUS_INVALID_PARAM For the invalid parameter.
1519 *
1520 *******************************************************************************/
Cy_PRA_ValidateClkPathMux(cy_en_clkpath_in_sources_t pathSrc,const cy_stc_pra_system_config_t * devConfig)1521 static cy_en_pra_status_t Cy_PRA_ValidateClkPathMux(cy_en_clkpath_in_sources_t pathSrc, const cy_stc_pra_system_config_t *devConfig)
1522 {
1523 cy_en_pra_status_t status;
1524
1525 /* The Check Source clock is enabled */
1526 switch (pathSrc)
1527 {
1528 case CY_SYSCLK_CLKPATH_IN_IMO:
1529 {
1530 status = CY_PRA_STATUS_SUCCESS;
1531 }
1532 break;
1533 case CY_SYSCLK_CLKPATH_IN_EXT:
1534 {
1535 (devConfig->extClkEnable) ? (status = CY_PRA_STATUS_SUCCESS) : (status = CY_PRA_STATUS_INVALID_PARAM);
1536 }
1537 break;
1538 case CY_SYSCLK_CLKPATH_IN_ECO:
1539 {
1540 (devConfig->ecoEnable) ? (status = CY_PRA_STATUS_SUCCESS) : (status = CY_PRA_STATUS_INVALID_PARAM);
1541 }
1542 break;
1543 case CY_SYSCLK_CLKPATH_IN_ALTHF:
1544 {
1545 (devConfig->clkAltHfEnable) ? (status = CY_PRA_STATUS_SUCCESS) : (status = CY_PRA_STATUS_INVALID_PARAM);
1546 }
1547 break;
1548 case CY_SYSCLK_CLKPATH_IN_ILO:
1549 {
1550 (devConfig->iloEnable) ? (status = CY_PRA_STATUS_SUCCESS) : (status = CY_PRA_STATUS_INVALID_PARAM);
1551 }
1552 break;
1553 case CY_SYSCLK_CLKPATH_IN_WCO:
1554 {
1555 (devConfig->wcoEnable) ? (status = CY_PRA_STATUS_SUCCESS) : (status = CY_PRA_STATUS_INVALID_PARAM);
1556 }
1557 break;
1558 case CY_SYSCLK_CLKPATH_IN_PILO:
1559 {
1560 ((devConfig->piloEnable) && (CY_SRSS_PILO_PRESENT)) ? (status = CY_PRA_STATUS_SUCCESS) : (status = CY_PRA_STATUS_INVALID_PARAM);
1561 }
1562 break;
1563 default:
1564 {
1565 status = CY_PRA_STATUS_INVALID_PARAM;
1566 }
1567 break;
1568 }
1569
1570 return status;
1571 }
1572
1573
1574 /*******************************************************************************
1575 * Function Name: Cy_PRA_ValidateClkPath
1576 ****************************************************************************//**
1577 *
1578 * Validates the clock path. Checks whether the source clock of the clock path
1579 * is enabled.
1580 *
1581 * \param clkPath Clock path
1582 * \param devConfig System Configuration Parameter
1583 *
1584 * \return
1585 * CY_PRA_STATUS_SUCCESS For the valid input configuration.
1586 * CY_PRA_STATUS_INVALID_PARAM For the invalid parameter.
1587 *
1588 *******************************************************************************/
Cy_PRA_ValidateClkPath(uint32_t clkPath,const cy_stc_pra_system_config_t * devConfig)1589 static cy_en_pra_status_t Cy_PRA_ValidateClkPath(uint32_t clkPath, const cy_stc_pra_system_config_t *devConfig)
1590 {
1591 cy_en_pra_status_t retStatus = CY_PRA_STATUS_INVALID_PARAM;
1592 if(clkPath >= CY_SRSS_NUM_CLKPATH)
1593 {
1594 return retStatus;
1595 }
1596
1597 switch (clkPath)
1598 {
1599 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0: /* CLK_PATH0 */
1600 {
1601 /* PATH_MUX0 must be enabled */
1602 if (devConfig->path0Enable)
1603 {
1604 retStatus = Cy_PRA_ValidateClkPathMux(devConfig->path0Src, devConfig);
1605 }
1606 }
1607 break;
1608 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH1: /* CLK_PATH1 */
1609 {
1610 /* PATH_MUX1 must be enabled */
1611 if (devConfig->path1Enable)
1612 {
1613 retStatus = Cy_PRA_ValidateClkPathMux(devConfig->path1Src, devConfig);
1614 }
1615 }
1616 break;
1617 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH2: /* CLK_PATH2 */
1618 {
1619 /* PATH_MUX2 must be enabled */
1620 if (devConfig->path2Enable)
1621 {
1622 retStatus = Cy_PRA_ValidateClkPathMux(devConfig->path2Src, devConfig);
1623 }
1624 }
1625 break;
1626 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH3: /* CLK_PATH3 */
1627 {
1628 /* PATH_MUX3 must be enabled */
1629 if (devConfig->path3Enable)
1630 {
1631 retStatus = Cy_PRA_ValidateClkPathMux(devConfig->path3Src, devConfig);
1632 }
1633 }
1634 break;
1635 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH4: /* CLK_PATH4 */
1636 {
1637 /* PATH_MUX4 must be enabled */
1638 if (devConfig->path4Enable)
1639 {
1640 retStatus = Cy_PRA_ValidateClkPathMux(devConfig->path4Src, devConfig);
1641 }
1642 }
1643 break;
1644 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH5: /* CLK_PATH5 */
1645 {
1646 /* PATH_MUX5 must be enabled */
1647 if (devConfig->path5Enable)
1648 {
1649 retStatus = Cy_PRA_ValidateClkPathMux(devConfig->path5Src, devConfig);
1650 }
1651 }
1652 break;
1653 default:
1654 {
1655 retStatus = CY_PRA_STATUS_INVALID_PARAM;
1656 }
1657 break;
1658 }
1659
1660 return retStatus;
1661 }
1662
1663 /*******************************************************************************
1664 * Function Name: Cy_PRA_ValidateAllClkPathMux
1665 ****************************************************************************//**
1666 *
1667 * Validates All PATH MUXes.
1668 *
1669 * \param devConfig System Configuration Parameter
1670 *
1671 * \return
1672 * CY_PRA_STATUS_SUCCESS For the valid input configuration.
1673 * CY_PRA_STATUS_INVALID_PARAM_PATHMUX0 For the path-mux0 invalid parameter.
1674 * CY_PRA_STATUS_INVALID_PARAM_PATHMUX1 For the path-mux1 invalid parameter.
1675 * CY_PRA_STATUS_INVALID_PARAM_PATHMUX2 For the path-mux2 invalid parameter.
1676 * CY_PRA_STATUS_INVALID_PARAM_PATHMUX3 For the path-mux3 invalid parameter.
1677 * CY_PRA_STATUS_INVALID_PARAM_PATHMUX4 For the path-mux4 invalid parameter.
1678 * CY_PRA_STATUS_INVALID_PARAM_PATHMUX5 For the path-mux5 invalid parameter.
1679 *
1680 *******************************************************************************/
Cy_PRA_ValidateAllClkPathMux(const cy_stc_pra_system_config_t * devConfig)1681 static cy_en_pra_status_t Cy_PRA_ValidateAllClkPathMux(const cy_stc_pra_system_config_t *devConfig)
1682 {
1683
1684 if ((devConfig->path0Enable) && (CY_PRA_CLKPATH_0 < CY_SRSS_NUM_CLKPATH)) /* path_mux0 is enabled */
1685 {
1686 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPathMux(devConfig->path0Src, devConfig))
1687 {
1688 return CY_PRA_STATUS_INVALID_PARAM_PATHMUX0;
1689 }
1690 }
1691 if ((devConfig->path1Enable) && (CY_PRA_CLKPATH_1 < CY_SRSS_NUM_CLKPATH)) /* path_mux1 is enabled */
1692 {
1693 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPathMux(devConfig->path1Src, devConfig))
1694 {
1695 return CY_PRA_STATUS_INVALID_PARAM_PATHMUX1;
1696 }
1697 }
1698 if ((devConfig->path2Enable) && (CY_PRA_CLKPATH_2 < CY_SRSS_NUM_CLKPATH)) /* path_mux2 is enabled */
1699 {
1700 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPathMux(devConfig->path2Src, devConfig))
1701 {
1702 return CY_PRA_STATUS_INVALID_PARAM_PATHMUX2;
1703 }
1704 }
1705 if ((devConfig->path3Enable) && (CY_PRA_CLKPATH_3 < CY_SRSS_NUM_CLKPATH)) /* path_mux3 is enabled */
1706 {
1707 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPathMux(devConfig->path3Src, devConfig))
1708 {
1709 return CY_PRA_STATUS_INVALID_PARAM_PATHMUX3;
1710 }
1711 }
1712 if ((devConfig->path4Enable) && (CY_PRA_CLKPATH_4 < CY_SRSS_NUM_CLKPATH)) /* path_mux4 is enabled */
1713 {
1714 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPathMux(devConfig->path4Src, devConfig))
1715 {
1716 return CY_PRA_STATUS_INVALID_PARAM_PATHMUX4;
1717 }
1718 }
1719 if ((devConfig->path5Enable) && (CY_PRA_CLKPATH_5 < CY_SRSS_NUM_CLKPATH))/* path_mux5 is enabled */
1720 {
1721 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPathMux(devConfig->path5Src, devConfig))
1722 {
1723 return CY_PRA_STATUS_INVALID_PARAM_PATHMUX5;
1724 }
1725 }
1726
1727 return CY_PRA_STATUS_SUCCESS;
1728 }
1729
1730 /*******************************************************************************
1731 * Function Name: Cy_PRA_ValidateClkHfFreqDiv
1732 ****************************************************************************//**
1733 *
1734 * Validates the High Frequency Clock's output frequency and divider.
1735 *
1736 * \param outFreqMHz Output frequency
1737 * \param divider Frequency divider
1738 *
1739 * \return
1740 * CY_PRA_STATUS_SUCCESS For the valid input configuration.
1741 * CY_PRA_STATUS_INVALID_PARAM For the invalid parameter.
1742 *
1743 *******************************************************************************/
Cy_PRA_ValidateClkHfFreqDiv(uint32_t outFreqMHz,cy_en_clkhf_dividers_t divider)1744 static cy_en_pra_status_t Cy_PRA_ValidateClkHfFreqDiv(uint32_t outFreqMHz, cy_en_clkhf_dividers_t divider)
1745 {
1746 /* min="1" max="CY_HF_CLK_MAX_FREQ" */
1747 if ((outFreqMHz*CY_PRA_FREQUENCY_HZ_CONVERSION) > CY_HF_CLK_MAX_FREQ)
1748 {
1749 return CY_PRA_STATUS_INVALID_PARAM;
1750 }
1751 if (divider > CY_SYSCLK_CLKHF_DIVIDE_BY_8)
1752 {
1753 return CY_PRA_STATUS_INVALID_PARAM;
1754 }
1755
1756 return CY_PRA_STATUS_SUCCESS;
1757 }
1758
1759 /*******************************************************************************
1760 * Function Name: Cy_PRA_ValidateClkHFs
1761 ****************************************************************************//**
1762 *
1763 * Validates All High Frequency Clocks.
1764 *
1765 * \param devConfig System Configuration Parameter
1766 *
1767 * \return
1768 * CY_PRA_STATUS_SUCCESS for valid input configuration
1769 * CY_PRA_STATUS_INVALID_PARAM_CLKHF0 for bad parameter for HF0
1770 * CY_PRA_STATUS_INVALID_PARAM_CLKHF1 for bad parameter for HF1
1771 * CY_PRA_STATUS_INVALID_PARAM_CLKHF2 for bad parameter for HF2
1772 * CY_PRA_STATUS_INVALID_PARAM_CLKHF3 for bad parameter for HF3
1773 * CY_PRA_STATUS_INVALID_PARAM_CLKHF4 for bad parameter for HF4
1774 * CY_PRA_STATUS_INVALID_PARAM_CLKHF5 for bad parameter for HF5
1775 *
1776 *******************************************************************************/
Cy_PRA_ValidateClkHFs(const cy_stc_pra_system_config_t * devConfig)1777 static cy_en_pra_status_t Cy_PRA_ValidateClkHFs(const cy_stc_pra_system_config_t *devConfig)
1778 {
1779 cy_en_clkpath_in_sources_t clkSource;
1780 cy_en_pra_status_t status;
1781 uint32_t freq;
1782
1783 /* Validates HF0 */
1784 if ((devConfig->clkHF0Enable) && (CY_PRA_CLKHF_0 < CY_SRSS_NUM_HFROOT))
1785 {
1786 /* The input source clock should be enabled */
1787 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPath((uint32_t)(devConfig->hf0Source), devConfig))
1788 {
1789 return CY_PRA_STATUS_INVALID_PARAM_CLKHF0;
1790 }
1791
1792 /* ILO, PILO and ALTHF can't be source to HF0 */
1793 clkSource = Cy_PRA_GetInputSourceClock((uint32_t) devConfig->hf0Source, devConfig, &status);
1794 if ((clkSource == CY_SYSCLK_CLKPATH_IN_ILO) ||
1795 (clkSource == CY_SYSCLK_CLKPATH_IN_PILO) ||
1796 (clkSource == CY_SYSCLK_CLKPATH_IN_ALTHF) ||
1797 (status != CY_PRA_STATUS_SUCCESS))
1798 {
1799 return CY_PRA_STATUS_INVALID_PARAM_CLKHF0;
1800 }
1801
1802 /* HF0: the input source cannot be slower than legal min 200 kHz */
1803 status = Cy_PRA_GetInputSourceFreq((uint32_t) devConfig->hf0Source, devConfig, &freq);
1804 if ((freq < CY_PRA_HF0_MIN_FREQUENCY) || (status != CY_PRA_STATUS_SUCCESS))
1805 {
1806 return CY_PRA_STATUS_INVALID_PARAM_CLKHF0;
1807 }
1808
1809 /* Validates the output frequency and divider */
1810 /* The HF0 output frequency cannot be 0 MHz because the current LF
1811 * clocks are not allowed to source HF0 */
1812 if ((devConfig->hf0OutFreqMHz == 0UL) || (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkHfFreqDiv(devConfig->hf0OutFreqMHz, devConfig->hf0Divider)))
1813 {
1814 return CY_PRA_STATUS_INVALID_PARAM_CLKHF0;
1815 }
1816 }
1817 else
1818 {
1819 /* This cannot be disabled */
1820 return CY_PRA_STATUS_INVALID_PARAM_CLKHF0;
1821 }
1822
1823 /* Validates HF1 */
1824 if ((devConfig->clkHF1Enable) && (CY_PRA_CLKHF_1 < CY_SRSS_NUM_HFROOT))
1825 {
1826 /* The input source clock should be enabled */
1827 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPath((uint32_t)(devConfig->hf1Source), devConfig))
1828 {
1829 return CY_PRA_STATUS_INVALID_PARAM_CLKHF1;
1830 }
1831 /* Validates the output frequency and divider */
1832 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkHfFreqDiv(devConfig->hf1OutFreqMHz, devConfig->hf1Divider))
1833 {
1834 return CY_PRA_STATUS_INVALID_PARAM_CLKHF1;
1835 }
1836 }
1837
1838 /* Validates HF2 */
1839 if ((devConfig->clkHF2Enable) && (CY_PRA_CLKHF_2 < CY_SRSS_NUM_HFROOT))
1840 {
1841 /* The input source clock should be enabled */
1842 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPath((uint32_t)(devConfig->hf2Source), devConfig))
1843 {
1844 return CY_PRA_STATUS_INVALID_PARAM_CLKHF2;
1845 }
1846
1847 /* Validates the output frequency and divider */
1848 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkHfFreqDiv(devConfig->hf2OutFreqMHz, devConfig->hf2Divider))
1849 {
1850 return CY_PRA_STATUS_INVALID_PARAM_CLKHF2;
1851 }
1852 }
1853
1854 /* Validates HF3 */
1855 if ((devConfig->clkHF3Enable) && (CY_PRA_CLKHF_3 < CY_SRSS_NUM_HFROOT))
1856 {
1857 /* The input source clock should be enabled */
1858 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPath((uint32_t) devConfig->hf3Source, devConfig))
1859 {
1860 return CY_PRA_STATUS_INVALID_PARAM_CLKHF3;
1861 }
1862
1863 /* Validates the output frequency and divider */
1864 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkHfFreqDiv(devConfig->hf3OutFreqMHz, devConfig->hf3Divider))
1865 {
1866 return CY_PRA_STATUS_INVALID_PARAM_CLKHF3;
1867 }
1868 }
1869
1870 /* Validates HF4 */
1871 if ((devConfig->clkHF4Enable) && (CY_PRA_CLKHF_4 < CY_SRSS_NUM_HFROOT))
1872 {
1873 /* The input source clock should be enabled */
1874 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPath((uint32_t) devConfig->hf4Source, devConfig))
1875 {
1876 return CY_PRA_STATUS_INVALID_PARAM_CLKHF4;
1877 }
1878
1879 /* Validates the output frequency and divider */
1880 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkHfFreqDiv(devConfig->hf4OutFreqMHz, devConfig->hf4Divider))
1881 {
1882 return CY_PRA_STATUS_INVALID_PARAM_CLKHF4;
1883 }
1884 }
1885
1886 /* Validates HF5 */
1887 if ((devConfig->clkHF5Enable) && (CY_PRA_CLKHF_5 < CY_SRSS_NUM_HFROOT))
1888 {
1889 /* The input source clock should be enabled */
1890 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPath((uint32_t) devConfig->hf5Source, devConfig))
1891 {
1892 return CY_PRA_STATUS_INVALID_PARAM_CLKHF5;
1893 }
1894
1895 /* Validates the output frequency and divider */
1896 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkHfFreqDiv(devConfig->hf5OutFreqMHz, devConfig->hf5Divider))
1897 {
1898 return CY_PRA_STATUS_INVALID_PARAM_CLKHF5;
1899 }
1900 }
1901
1902 return CY_PRA_STATUS_SUCCESS;
1903 }
1904
1905 /*******************************************************************************
1906 * Function Name: Cy_PRA_ValidateClkPump
1907 ****************************************************************************//**
1908 *
1909 * Validates the PUMP Clock.
1910 *
1911 * \param devConfig System Configuration Parameter
1912 *
1913 * \return
1914 * CY_PRA_STATUS_SUCCESS For the valid input configuration.
1915 * CY_PRA_STATUS_INVALID_PARAM_CLKPUMP For the invalid parameter.
1916 *
1917 *******************************************************************************/
Cy_PRA_ValidateClkPump(const cy_stc_pra_system_config_t * devConfig)1918 static cy_en_pra_status_t Cy_PRA_ValidateClkPump(const cy_stc_pra_system_config_t *devConfig)
1919 {
1920 uint32_t freq;
1921 cy_en_pra_status_t status = CY_PRA_STATUS_SUCCESS;
1922 /* Validates PUMP */
1923 if (devConfig->clkPumpEnable)
1924 {
1925 /* The input source clock should be enabled */
1926 if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPath((uint32_t) devConfig->pumpSource, devConfig))
1927 {
1928 return CY_PRA_STATUS_INVALID_PARAM_CLKPUMP;
1929 }
1930
1931 /* Validates the divider */
1932 if (devConfig->pumpDivider > CY_SYSCLK_PUMP_DIV_16)
1933 {
1934 return CY_PRA_STATUS_INVALID_PARAM_CLKPUMP;
1935 }
1936
1937 /* the output frequency range is min="0" max="400000000" */
1938 status = Cy_PRA_GetInputSourceFreq((uint32_t) devConfig->pumpSource,devConfig, &freq);
1939 if( status == CY_PRA_STATUS_SUCCESS )
1940 {
1941 freq = freq / (1UL << ((uint32_t)devConfig->pumpDivider)); /* Calculates the output frequency */
1942 if (freq > CY_PRA_PUMP_OUT_MAX_FREQUENCY)
1943 {
1944 return CY_PRA_STATUS_INVALID_PARAM_CLKPUMP;
1945 }
1946 }
1947 else
1948 {
1949 status = CY_PRA_STATUS_INVALID_PARAM_CLKPUMP;
1950 }
1951 }
1952
1953 return status;
1954 }
1955
1956 /*******************************************************************************
1957 * Function Name: Cy_PRA_ValidateClkBak
1958 ****************************************************************************//**
1959 *
1960 * Validates Backup Domain Clock.
1961 *
1962 * \param devConfig System Configuration Parameter
1963 *
1964 * \return
1965 * CY_PRA_STATUS_SUCCESS for valid input configuration
1966 * CY_PRA_STATUS_INVALID_PARAM_CLKBAK for bad parameter
1967 *
1968 *******************************************************************************/
Cy_PRA_ValidateClkBak(const cy_stc_pra_system_config_t * devConfig)1969 static cy_en_pra_status_t Cy_PRA_ValidateClkBak(const cy_stc_pra_system_config_t *devConfig)
1970 {
1971 cy_en_pra_status_t retStatus = CY_PRA_STATUS_SUCCESS;
1972 uint32_t freq;
1973
1974 if (devConfig->clkBakEnable)
1975 {
1976 /* If CLK_BAK is enabled, the source clock, either CLK_LF or CLK_WCO,
1977 * must be enabled */
1978 switch (devConfig->clkBakSource)
1979 {
1980 case CY_SYSCLK_BAK_IN_WCO:
1981 {
1982 (devConfig->wcoEnable) ? (retStatus = CY_PRA_STATUS_SUCCESS) : (retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKBAK);
1983 }
1984 break;
1985 case CY_SYSCLK_BAK_IN_CLKLF:
1986 {
1987 (devConfig->clkLFEnable) ? (retStatus = CY_PRA_STATUS_SUCCESS) : (retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKBAK);
1988 }
1989 break;
1990 default:
1991 {
1992 retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKBAK;
1993 }
1994 break;
1995 }
1996
1997 if (CY_PRA_STATUS_SUCCESS != retStatus)
1998 {
1999 return retStatus;
2000 }
2001
2002 /* Validates Output Frequency min="0" max="100000" */
2003 /* There is no divider for CLK_BAK. So, output frequency = input frequency */
2004 freq = Cy_PRA_GetClkBakFreq(devConfig);
2005 if (freq > CY_PRA_BAK_OUT_MAX_FREQUENCY)
2006 {
2007 retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKBAK;
2008 }
2009 }
2010
2011 return retStatus;
2012 }
2013
2014 /*******************************************************************************
2015 * Function Name: Cy_PRA_ValidateClkFast
2016 ****************************************************************************//**
2017 *
2018 * Validate Fast Clock.
2019 *
2020 * \param devConfig System Configuration Parameter
2021 *
2022 * \return
2023 * CY_PRA_STATUS_SUCCESS For the valid input configuration.
2024 * CY_PRA_STATUS_INVALID_PARAM_CLKFAST For the invalid parameter.
2025 *
2026 *******************************************************************************/
Cy_PRA_ValidateClkFast(const cy_stc_pra_system_config_t * devConfig)2027 static cy_en_pra_status_t Cy_PRA_ValidateClkFast(const cy_stc_pra_system_config_t *devConfig)
2028 {
2029 uint32_t freq;
2030
2031 /* The HF0 source clock must be enabled */
2032 if (devConfig->clkFastEnable)
2033 {
2034 if (!(devConfig->clkHF0Enable))
2035 {
2036 return CY_PRA_STATUS_INVALID_PARAM_CLKFAST;
2037 }
2038
2039 /* Validates the frequency range. min="0" max="400000000" */
2040 freq = Cy_PRA_GetHF0FreqHz(devConfig); /* input frequency */
2041 freq = freq / (devConfig->clkFastDiv+1UL); /* Calculate Output frequency */
2042 if (freq > CY_PRA_FAST_OUT_MAX_FREQUENCY)
2043 {
2044 return CY_PRA_STATUS_INVALID_PARAM_CLKFAST;
2045 }
2046
2047 /* Validates divider min="1" max="256". The user must pass actual divider-1 */
2048 /* No need to validate the divider because the max value input cannot be more than 255 */
2049 }
2050
2051 return CY_PRA_STATUS_SUCCESS;
2052 }
2053
2054 /*******************************************************************************
2055 * Function Name: Cy_PRA_ValidateClkPeri
2056 ****************************************************************************//**
2057 *
2058 * Validate Peripheral Clock
2059 *
2060 * \param devConfig System Configuration Parameter
2061 *
2062 * \return
2063 * CY_PRA_STATUS_SUCCESS for valid input configuration
2064 * CY_PRA_STATUS_INVALID_PARAM_CLKPERI for bad parameter
2065 *
2066 *******************************************************************************/
Cy_PRA_ValidateClkPeri(const cy_stc_pra_system_config_t * devConfig)2067 static cy_en_pra_status_t Cy_PRA_ValidateClkPeri(const cy_stc_pra_system_config_t *devConfig)
2068 {
2069 uint32_t freq;
2070
2071 /* The HF0 source clock must be enabled */
2072 if (devConfig->clkPeriEnable)
2073 {
2074 if (!(devConfig->clkHF0Enable))
2075 {
2076 return CY_PRA_STATUS_INVALID_PARAM_CLKPERI;
2077 }
2078
2079 freq = Cy_PRA_GetHF0FreqHz(devConfig); /* input frequency */
2080 if (freq > CY_HF_CLK_MAX_FREQ)
2081 {
2082 return CY_PRA_STATUS_INVALID_PARAM_CLKPERI;
2083 }
2084
2085 freq = freq / (devConfig->clkPeriDiv+1UL); /* Calculate Output frequency */
2086
2087 /* Maximum 25 MHz for ULP mode and 100 MHz for LP mode */
2088 if (devConfig->ulpEnable)
2089 {
2090 if (freq > CY_PRA_ULP_MODE_HF0_MAX_FREQUENCY)
2091 {
2092 return CY_PRA_STATUS_INVALID_PARAM_CLKPERI;
2093 }
2094 }
2095 else
2096 {
2097 if (freq > CY_PRA_LP_MODE_MAX_FREQUENCY)
2098 {
2099 return CY_PRA_STATUS_INVALID_PARAM_CLKPERI;
2100 }
2101 }
2102
2103 /* Validates divider min="1" max="256". The user must pass actual divider-1 */
2104 /* No need to validate the divider because the max value input cannot be more than 255 */
2105 }
2106 else
2107 {
2108 /* Checks if this clock is always on */
2109 return CY_PRA_STATUS_INVALID_PARAM_CLKPERI;
2110 }
2111
2112 return CY_PRA_STATUS_SUCCESS;
2113 }
2114
2115 /*******************************************************************************
2116 * Function Name: Cy_PRA_ValidateClkTimer
2117 ****************************************************************************//**
2118 *
2119 * Validates Timer Clock.
2120 *
2121 * \param devConfig System Configuration Parameter
2122 *
2123 * \return
2124 * CY_PRA_STATUS_SUCCESS For the valid input configuration.
2125 * CY_PRA_STATUS_INVALID_PARAM For the invalid parameter.
2126 *
2127 *******************************************************************************/
Cy_PRA_ValidateClkTimer(const cy_stc_pra_system_config_t * devConfig)2128 static cy_en_pra_status_t Cy_PRA_ValidateClkTimer(const cy_stc_pra_system_config_t *devConfig)
2129 {
2130 uint32_t freq;
2131 uint8_t srcDiv;
2132 cy_en_pra_status_t ret = CY_PRA_STATUS_SUCCESS;
2133
2134 /* The source clock must be enabled */
2135 if (devConfig->clkTimerEnable)
2136 {
2137 /* Calculates the source frequency and divider */
2138 switch (devConfig->clkTimerSource)
2139 {
2140 case CY_SYSCLK_CLKTIMER_IN_IMO:
2141 {
2142 /* IMO is always on */
2143 freq = CY_PRA_IMO_SRC_FREQUENCY; /* 8 MHz */
2144 srcDiv = CY_PRA_DIVIDER_1;
2145 break;
2146 }
2147 case CY_SYSCLK_CLKTIMER_IN_HF0_NODIV:
2148 case CY_SYSCLK_CLKTIMER_IN_HF0_DIV2:
2149 case CY_SYSCLK_CLKTIMER_IN_HF0_DIV4:
2150 case CY_SYSCLK_CLKTIMER_IN_HF0_DIV8:
2151 {
2152 if ( devConfig->clkHF0Enable )
2153 {
2154 srcDiv = CY_PRA_DIVIDER_1;
2155 if (devConfig->clkTimerSource == CY_SYSCLK_CLKTIMER_IN_HF0_DIV2)
2156 {
2157 srcDiv = CY_PRA_DIVIDER_2;
2158 }
2159 if (devConfig->clkTimerSource == CY_SYSCLK_CLKTIMER_IN_HF0_DIV4)
2160 {
2161 srcDiv = CY_PRA_DIVIDER_4;
2162 }
2163 if (devConfig->clkTimerSource == CY_SYSCLK_CLKTIMER_IN_HF0_DIV8)
2164 {
2165 srcDiv = CY_PRA_DIVIDER_8;
2166 }
2167 freq = Cy_PRA_GetHF0FreqHz(devConfig);
2168 }
2169 else
2170 {
2171 ret = CY_PRA_STATUS_INVALID_PARAM_CLKTIMER;
2172 }
2173 break;
2174 }
2175 default:
2176 {
2177 ret = CY_PRA_STATUS_INVALID_PARAM_CLKTIMER;
2178 break;
2179 }
2180 }
2181
2182 if(ret != CY_PRA_STATUS_SUCCESS)
2183 {
2184 return ret;
2185 }
2186
2187 /* Output frequency = source frequency / divider */
2188 freq = (freq / (devConfig->clkTimerDivider + 1UL)) / srcDiv;
2189 /* Output frequency range min="0" max="400000000" */
2190 if (freq > CY_PRA_TIMER_OUT_MAX_FREQUENCY)
2191 {
2192 return CY_PRA_STATUS_INVALID_PARAM_CLKTIMER;
2193 }
2194 }
2195
2196 return CY_PRA_STATUS_SUCCESS;
2197 }
2198
2199 /*******************************************************************************
2200 * Function Name: Cy_PRA_ValidateClkSlow
2201 ****************************************************************************//**
2202 *
2203 * Validates Slow Clock.
2204 *
2205 * \param devConfig System Configuration Parameter
2206 *
2207 * \return
2208 * CY_PRA_STATUS_SUCCESS For the valid input configuration.
2209 * CY_PRA_STATUS_INVALID_PARAM_CLKPERI For the invalid parameter.
2210 *
2211 *******************************************************************************/
Cy_PRA_ValidateClkSlow(const cy_stc_pra_system_config_t * devConfig)2212 static cy_en_pra_status_t Cy_PRA_ValidateClkSlow(const cy_stc_pra_system_config_t *devConfig)
2213 {
2214 uint32_t freq;
2215
2216 /* The source clock must be enabled */
2217 if (devConfig->clkSlowEnable)
2218 {
2219 if (!(devConfig->clkPeriEnable))
2220 {
2221 return CY_PRA_STATUS_INVALID_PARAM_CLKSLOW;
2222 }
2223
2224 /* outFreq = (sourceFreq / divider) range is min="0" max="400000000" */
2225 freq = Cy_PRA_GetHF0FreqHz(devConfig); /* input frequency */
2226 if (freq > CY_HF_CLK_MAX_FREQ)
2227 {
2228 return CY_PRA_STATUS_INVALID_PARAM_CLKPERI;
2229 }
2230
2231 freq = freq / (devConfig->clkPeriDiv+1UL); /* Calculates the output frequency for PERI and input frequency for SLOW_CLK */
2232
2233 freq = freq / (devConfig->clkSlowDiv+1UL); /* Output CLK_SLOW frequency */
2234
2235 if (freq > CY_PRA_SLOW_OUT_MAX_FREQUENCY)
2236 {
2237 return CY_PRA_STATUS_INVALID_PARAM_CLKSLOW;
2238 }
2239 }
2240 else
2241 {
2242 /* Checks if this clock is always on */
2243 return CY_PRA_STATUS_INVALID_PARAM_CLKSLOW;
2244 }
2245
2246 return CY_PRA_STATUS_SUCCESS;
2247 }
2248
2249 /*******************************************************************************
2250 * Function Name: Cy_PRA_ValidateSystemConfig
2251 ****************************************************************************//**
2252 *
2253 * Validate System Configuration
2254 *
2255 * \param devConfig System Configuration Parameter
2256 *
2257 * \return
2258 * CY_PRA_STATUS_SUCCESS For the valid input configuration.
2259 * CY_PRA_STATUS_INVALID_PARAM Generic failure in validation.
2260 * CY_PRA_STATUS_INVALID_PARAM_ECO Error in ECO validation.
2261 * CY_PRA_STATUS_INVALID_PARAM_EXTCLK Error in EXTCLK validation.
2262 * CY_PRA_STATUS_INVALID_PARAM_ALTHF Error in ALTHF validation.
2263 * CY_PRA_STATUS_INVALID_PARAM_ILO Error in ILO validation.
2264 * CY_PRA_STATUS_INVALID_PARAM_PILO Error in PILO validation.
2265 * CY_PRA_STATUS_INVALID_PARAM_WCO Error in WCO validation.
2266 * CY_PRA_STATUS_INVALID_PARAM_PATHMUX0 Error in PATHMUX0 validation.
2267 * CY_PRA_STATUS_INVALID_PARAM_PATHMUX1 Error in PATHMUX1 validation.
2268 * CY_PRA_STATUS_INVALID_PARAM_PATHMUX2 Error in PATHMUX2 validation.
2269 * CY_PRA_STATUS_INVALID_PARAM_PATHMUX3 Error in PATHMUX3 validation.
2270 * CY_PRA_STATUS_INVALID_PARAM_PATHMUX4 Error in PATHMUX4 validation.
2271 * CY_PRA_STATUS_INVALID_PARAM_PATHMUX5 Error in PATHMUX5 validation.
2272 * CY_PRA_STATUS_INVALID_PARAM_FLL0 Error in FLL validation.
2273 * CY_PRA_STATUS_INVALID_PARAM_PLL0 Error in PLL0 validation.
2274 * CY_PRA_STATUS_INVALID_PARAM_PLL1 Error in PLL1 validation.
2275 * CY_PRA_STATUS_INVALID_PARAM_CLKLF Error in CLKLF validation.
2276 * CY_PRA_STATUS_INVALID_PARAM_CLKHF0 Error in CLKHF0 validation.
2277 * CY_PRA_STATUS_INVALID_PARAM_CLKHF1 Error in CLKHF1 validation.
2278 * CY_PRA_STATUS_INVALID_PARAM_CLKHF2 Error in CLKHF2 validation.
2279 * CY_PRA_STATUS_INVALID_PARAM_CLKHF3 Error in CLKHF3 validation.
2280 * CY_PRA_STATUS_INVALID_PARAM_CLKHF4 Error in CLKHF4 validation.
2281 * CY_PRA_STATUS_INVALID_PARAM_CLKHF5 Error in CLKHF5 validation.
2282 * CY_PRA_STATUS_INVALID_PARAM_CLKPUMP Error in CLKPUMP validation.
2283 * CY_PRA_STATUS_INVALID_PARAM_CLKBAK Error in CLKBAK validation.
2284 * CY_PRA_STATUS_INVALID_PARAM_CLKFAST Error in CLKFAST validation.
2285 * CY_PRA_STATUS_INVALID_PARAM_CLKPERI Error in CLKPERI validation.
2286 * CY_PRA_STATUS_INVALID_PARAM_CLKSLOW Error in CLKSLOW validation.
2287 * CY_PRA_STATUS_INVALID_PARAM_CLKTIMER Error in CLKTIMER validation.
2288 *
2289 *******************************************************************************/
Cy_PRA_ValidateSystemConfig(const cy_stc_pra_system_config_t * devConfig)2290 static cy_en_pra_status_t Cy_PRA_ValidateSystemConfig(const cy_stc_pra_system_config_t *devConfig)
2291 {
2292
2293 cy_en_pra_status_t retStatus;
2294
2295 if (devConfig == NULL )
2296 {
2297 return CY_PRA_STATUS_INVALID_PARAM;
2298 }
2299
2300 /* Validates IMO */
2301 /* Enables IMO for proper chip operation. So, the user option is not given for IMO.
2302 * The output frequency of IMO is fixed to 8MHz.
2303 */
2304
2305 /* Validate external clock with provisioned data */
2306 retStatus = Cy_PRA_ValidateExtClkConfig(devConfig);
2307 if (CY_PRA_STATUS_SUCCESS != retStatus)
2308 {
2309 return retStatus;
2310 }
2311
2312 /* Validates ECO */
2313 retStatus = Cy_PRA_ValidateECO(devConfig);
2314 if (CY_PRA_STATUS_SUCCESS != retStatus)
2315 {
2316 return retStatus;
2317 }
2318
2319 /* Validates EXTCLK */
2320 retStatus = Cy_PRA_ValidateEXTClk(devConfig);
2321 if (CY_PRA_STATUS_SUCCESS != retStatus)
2322 {
2323 return retStatus;
2324 }
2325
2326 /* Validates ALTHF (BLE ECO) */
2327 #if defined(CY_IP_MXBLESS)
2328 retStatus = Cy_PRA_ValidateAltHf(devConfig);
2329 if (CY_PRA_STATUS_SUCCESS != retStatus)
2330 {
2331 return retStatus;
2332 }
2333 #endif
2334
2335 /* Validates ILO */
2336 /* ILO frequency fixed to 32KHz */
2337
2338 /* Validate PILO */
2339 /* The PILO frequency is fixed to 32.768KHz */
2340
2341 /* Validates WCO */
2342 /* The WCO frequency is fixed to 32.768KHz */
2343
2344 /* Validates Path Mux */
2345 retStatus = Cy_PRA_ValidateAllClkPathMux(devConfig);
2346 if (CY_PRA_STATUS_SUCCESS != retStatus)
2347 {
2348 return retStatus;
2349 }
2350
2351 /* Validates FLL */
2352 /* For ULP mode, Ffll_max = 50 MHz. For LP mode, Ffll_max = 100 MHz or Fcpu_max (if Fcpu_max < 100 MHz) */
2353 retStatus = Cy_PRA_ValidateFLL(devConfig);
2354 if (CY_PRA_STATUS_SUCCESS != retStatus)
2355 {
2356 return retStatus;
2357 }
2358
2359 /* Validates PLLs */
2360 retStatus = Cy_PRA_ValidateAllPLL(devConfig);
2361 if (CY_PRA_STATUS_SUCCESS != retStatus)
2362 {
2363 return retStatus;
2364 }
2365
2366 /* Validates CLK_LF */
2367 retStatus = Cy_PRA_ValidateClkLf(devConfig);
2368 if (CY_PRA_STATUS_SUCCESS != retStatus)
2369 {
2370 return retStatus;
2371 }
2372
2373 /* Validates CLK_HF */
2374 retStatus = Cy_PRA_ValidateClkHFs(devConfig);
2375 if (CY_PRA_STATUS_SUCCESS != retStatus)
2376 {
2377 return retStatus;
2378 }
2379
2380 /* Validates CLK_PUMP */
2381 retStatus = Cy_PRA_ValidateClkPump(devConfig);
2382 if (CY_PRA_STATUS_SUCCESS != retStatus)
2383 {
2384 return retStatus;
2385 }
2386
2387 /* Validates CLK_BAK */
2388 retStatus = Cy_PRA_ValidateClkBak(devConfig);
2389 if (CY_PRA_STATUS_SUCCESS != retStatus)
2390 {
2391 return retStatus;
2392 }
2393
2394 /* Validates CLK_FAST */
2395 retStatus = Cy_PRA_ValidateClkFast(devConfig);
2396 if (CY_PRA_STATUS_SUCCESS != retStatus)
2397 {
2398 return retStatus;
2399 }
2400
2401 /* Validate CLK_PERI */
2402 retStatus = Cy_PRA_ValidateClkPeri(devConfig);
2403 if (CY_PRA_STATUS_SUCCESS != retStatus)
2404 {
2405 return retStatus;
2406 }
2407
2408 /* Validates CLK_TIMER */
2409 retStatus = Cy_PRA_ValidateClkTimer(devConfig);
2410 if (CY_PRA_STATUS_SUCCESS != retStatus)
2411 {
2412 return retStatus;
2413 }
2414
2415 /* Validate CLK_SLOW */
2416 retStatus = Cy_PRA_ValidateClkSlow(devConfig);
2417 if (CY_PRA_STATUS_SUCCESS != retStatus)
2418 {
2419 return retStatus;
2420 }
2421
2422 return CY_PRA_STATUS_SUCCESS;
2423 }
2424
2425
2426 /*******************************************************************************
2427 * Function Name: Cy_PRA_CalculateFLLOutFreq
2428 ****************************************************************************//**
2429 *
2430 * Calculates and returns the FLL output frequency.
2431 *
2432 * \param devConfig System Configuration Parameter
2433 *
2434 * \return
2435 * The FLL output frequency.
2436 *
2437 *******************************************************************************/
Cy_PRA_CalculateFLLOutFreq(const cy_stc_pra_system_config_t * devConfig)2438 uint32_t Cy_PRA_CalculateFLLOutFreq(const cy_stc_pra_system_config_t *devConfig)
2439 {
2440 uint32_t srcFreq;
2441 uint32_t outFreq=0UL;
2442
2443 /* Gets the input source frequency to FLL */
2444 srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path0Src, devConfig);
2445 if ((srcFreq != CY_PRA_DEFAULT_SRC_FREQUENCY) && (devConfig->fllRefDiv != 0UL))
2446 {
2447 outFreq = ((srcFreq * devConfig->fllMult) / devConfig->fllRefDiv) / (devConfig->enableOutputDiv ? 2UL : 1UL);
2448 }
2449
2450 return outFreq;
2451 }
2452
2453 /*******************************************************************************
2454 * Function Name: Cy_PRA_CalculatePLLOutFreq
2455 ****************************************************************************//**
2456 *
2457 * Calculates and returns the PLL output frequency.
2458 *
2459 * \param pll PLL number
2460 * \param devConfig System Configuration Parameter
2461 *
2462 * \return
2463 * The PLL output frequency.
2464 *
2465 *******************************************************************************/
Cy_PRA_CalculatePLLOutFreq(uint8_t pll,const cy_stc_pra_system_config_t * devConfig)2466 uint32_t Cy_PRA_CalculatePLLOutFreq(uint8_t pll, const cy_stc_pra_system_config_t *devConfig)
2467 {
2468 uint32_t srcFreq;
2469 uint32_t outFreq;
2470 uint32_t feedback;
2471 uint32_t reference;
2472 uint32_t pllOutputDiv;
2473
2474 if ((pll > CY_PRA_DEFAULT_ZERO) && (pll <= CY_SRSS_NUM_PLL)) /* 0 is invalid pll number */
2475 {
2476 if (pll == CY_PRA_CLKPLL_1)
2477 {
2478 /* Gets the input source frequency to PLL1 */
2479 srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path1Src, devConfig);
2480 feedback = devConfig->pll0FeedbackDiv;
2481 reference = devConfig->pll0ReferenceDiv;
2482 pllOutputDiv = devConfig->pll0OutputDiv;
2483 }
2484 else if (pll == CY_PRA_CLKPLL_2)
2485 {
2486 /* Gets the input source frequency to PLL2 */
2487 srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path2Src, devConfig);
2488 feedback = devConfig->pll1FeedbackDiv;
2489 reference = devConfig->pll1ReferenceDiv;
2490 pllOutputDiv = devConfig->pll1OutputDiv;
2491 }
2492 else
2493 {
2494 srcFreq = CY_PRA_DEFAULT_SRC_FREQUENCY;
2495 }
2496
2497 if ((srcFreq != CY_PRA_DEFAULT_SRC_FREQUENCY) && (reference != CY_PRA_DIVIDER_0) && (pllOutputDiv != CY_PRA_DIVIDER_0))
2498 {
2499 outFreq = ((srcFreq * feedback) / reference) / pllOutputDiv;
2500 }
2501 else
2502 {
2503 outFreq = CY_PRA_DEFAULT_ZERO;
2504 }
2505 }
2506 else
2507 {
2508 outFreq = CY_PRA_DEFAULT_ZERO;
2509 }
2510
2511 return outFreq;
2512 }
2513
2514 #endif /* (CY_CPU_CORTEX_M0P) */
2515
2516 /*
2517 * Delay of 4 WCO clock cycles. This delay is used before the WCO is disabled.
2518 * 1 WCO cycle is 30.5 uS.
2519 */
2520 #define WCO_DISABLE_DELAY_US (123U)
2521
2522 /*
2523 * Delay of 4 ILO clock cycles. This delay is used before the ILO is disabled.
2524 * 1 ILO cycle is 40.6 uS. This is a worst case for ILO which is 32 kHz +/- 30%.
2525 */
2526 #define ILO_DISABLE_DELAY_US (163U)
2527
2528 /*******************************************************************************
2529 * Function Name: Cy_PRA_SystemConfig
2530 ****************************************************************************//**
2531 *
2532 * Validates \ref cy_stc_pra_system_config_t and applies the provided
2533 * settings.
2534 *
2535 * \param devConfig The device configuration structure initialized with
2536 * Device Configurator.
2537 *
2538 * \return \ref cy_en_pra_status_t
2539 *
2540 * \funcusage
2541 * \snippet pra/snippet/main.c snippet_Cy_PRA_SystemConfig
2542 *
2543 *******************************************************************************/
Cy_PRA_SystemConfig(const cy_stc_pra_system_config_t * devConfig)2544 cy_en_pra_status_t Cy_PRA_SystemConfig(const cy_stc_pra_system_config_t *devConfig)
2545 {
2546 cy_en_pra_status_t status;
2547
2548 #if (CY_CPU_CORTEX_M4)
2549 (void) devConfig;
2550 status = CY_PRA_STATUS_SUCCESS;
2551 #else
2552
2553 cy_en_sysclk_status_t sysClkStatus;
2554
2555 /* Validates the input parameters */
2556 status = Cy_PRA_ValidateSystemConfig(devConfig);
2557 if (CY_PRA_STATUS_SUCCESS != status)
2558 {
2559 return status;
2560 }
2561
2562 /* Sets the worst case memory wait states (! ultra low power, 150 MHz), update - at the end */
2563 Cy_SysLib_SetWaitStates(false, CY_PRA_150MHZ_FREQUENCY);
2564
2565 if (devConfig->powerEnable)
2566 {
2567 status = Cy_PRA_PowerInit(devConfig);
2568 if (CY_PRA_STATUS_SUCCESS != status)
2569 {
2570 return status;
2571 }
2572 }
2573
2574 if(CY_SRSS_PILO_PRESENT)
2575 {
2576 /* Enables all source clocks */
2577 if (Cy_SysClk_PiloIsEnabled())
2578 {
2579 if (!devConfig->piloEnable)
2580 {
2581 Cy_SysClk_PiloDisable();
2582 }
2583 }
2584 /* When the PILO state changes DISABLE -> ENABLE, enable only PILO.
2585 * Ignore, if PILO is already enabled */
2586 else
2587 {
2588 if (devConfig->piloEnable)
2589 {
2590 SystemCoreClockUpdate();
2591 Cy_PRA_PiloInit();
2592 }
2593 }
2594 }
2595
2596 if (_FLD2BOOL(BACKUP_CTL_WCO_EN, BACKUP_CTL))
2597 {
2598 if (!devConfig->wcoEnable)
2599 {
2600 /* Wait 4 WCO cycles before it is disabled */
2601 Cy_SysLib_DelayUs(WCO_DISABLE_DELAY_US);
2602 Cy_SysClk_WcoDisable();
2603 }
2604 }
2605 /* When the WCO state changes DISABLE -> ENABLE, enable only WCO.
2606 * Ignore, if WCO is already enabled */
2607 else
2608 {
2609 if (devConfig->wcoEnable)
2610 {
2611 SystemCoreClockUpdate();
2612 status = Cy_PRA_WcoInit(devConfig);
2613 if (CY_PRA_STATUS_SUCCESS != status)
2614 {
2615 return status;
2616 }
2617 }
2618 }
2619
2620 if (devConfig->clkLFEnable)
2621 {
2622 status = Cy_PRA_ClkLfInit(devConfig->clkLfSource);
2623 if (CY_PRA_STATUS_SUCCESS != status)
2624 {
2625 return status;
2626 }
2627 }
2628
2629 #if defined(CY_IP_MXBLESS)
2630 if (Cy_BLE_EcoIsEnabled())
2631 {
2632 if (!devConfig->clkAltHfEnable)
2633 {
2634 Cy_BLE_EcoReset();
2635 }
2636 }
2637 /* When the BLE_ECO state changes DISABLE -> ENABLE, enable only BLE_ECO.
2638 * Ignore, if BLE_ECO is already enabled */
2639 else
2640 {
2641 if (devConfig->clkAltHfEnable)
2642 {
2643 SystemCoreClockUpdate();
2644 status = Cy_PRA_AltHfInit(devConfig);
2645 if (CY_PRA_STATUS_SUCCESS != status)
2646 {
2647 return status;
2648 }
2649 }
2650 }
2651 #endif /* CY_IP_MXBLESS */
2652
2653 if(CY_SYSCLK_ECOSTAT_STABLE == Cy_SysClk_EcoGetStatus())
2654 {
2655 if (!devConfig->ecoEnable)
2656 {
2657 Cy_SysClk_EcoDisable();
2658 }
2659 }
2660 /* When the ECO state changes DISABLE -> ENABLE, enable only ECO.
2661 * Ignore, if ECO is already enabled */
2662 else
2663 {
2664 if (devConfig->ecoEnable)
2665 {
2666 SystemCoreClockUpdate();
2667 status = Cy_PRA_EcoInit(devConfig);
2668 if (CY_PRA_STATUS_SUCCESS != status)
2669 {
2670 return status;
2671 }
2672 }
2673 }
2674
2675 if (devConfig->extClkEnable)
2676 {
2677 Cy_PRA_ExtClkInit(devConfig);
2678 }
2679
2680 if (devConfig->clkFastEnable)
2681 {
2682 Cy_SysClk_ClkFastSetDivider(devConfig->clkFastDiv);
2683 }
2684
2685 if (devConfig->clkPeriEnable)
2686 {
2687 Cy_SysClk_ClkPeriSetDivider(devConfig->clkPeriDiv);
2688 }
2689
2690 if (devConfig->clkSlowEnable)
2691 {
2692 Cy_SysClk_ClkSlowSetDivider(devConfig->clkSlowDiv);
2693 }
2694
2695 if ((devConfig->path0Src == CY_SYSCLK_CLKPATH_IN_WCO) &&
2696 (devConfig->hf0Source == CY_SYSCLK_CLKHF_IN_CLKPATH0))
2697 {
2698 /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
2699 sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_1, CY_SYSCLK_CLKPATH_IN_IMO);
2700 if (CY_SYSCLK_SUCCESS != sysClkStatus)
2701 {
2702 return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX1;
2703 }
2704 sysClkStatus = Cy_SysClk_ClkHfSetSource(CY_PRA_CLKHF_0, CY_SYSCLK_CLKHF_IN_CLKPATH1);
2705 if (CY_SYSCLK_SUCCESS != sysClkStatus)
2706 {
2707 return CY_PRA_STATUS_ERROR_PROCESSING_CLKHF0;
2708 }
2709 }
2710 else
2711 {
2712 sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_1, devConfig->path1Src);
2713 if (CY_SYSCLK_SUCCESS != sysClkStatus)
2714 {
2715 return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX1;
2716 }
2717 }
2718
2719 /* Configures Path Clocks */
2720
2721 if (devConfig->path0Enable)
2722 {
2723 sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_0, devConfig->path0Src);
2724 if (CY_SYSCLK_SUCCESS != sysClkStatus)
2725 {
2726 return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX0;
2727 }
2728 }
2729
2730 if (devConfig->path2Enable)
2731 {
2732 sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_2, devConfig->path2Src);
2733 if (CY_SYSCLK_SUCCESS != sysClkStatus)
2734 {
2735 return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX2;
2736 }
2737 }
2738
2739 if ((devConfig->path3Enable) && (CY_PRA_CLKPATH_3 < CY_SRSS_NUM_CLKPATH))
2740 {
2741 sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_3, devConfig->path3Src);
2742 if (CY_SYSCLK_SUCCESS != sysClkStatus)
2743 {
2744 return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX3;
2745 }
2746 }
2747
2748 if ((devConfig->path4Enable) && (CY_PRA_CLKPATH_4 < CY_SRSS_NUM_CLKPATH))
2749 {
2750 sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_4, devConfig->path4Src);
2751 if (CY_SYSCLK_SUCCESS != sysClkStatus)
2752 {
2753 return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX4;
2754 }
2755 }
2756
2757 if ((devConfig->path5Enable) && (CY_PRA_CLKPATH_5 < CY_SRSS_NUM_CLKPATH))
2758 {
2759 sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_5, devConfig->path5Src);
2760 if (CY_SYSCLK_SUCCESS != sysClkStatus)
2761 {
2762 return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX5;
2763 }
2764 }
2765
2766 if(Cy_SysClk_FllIsEnabled())
2767 {
2768 uint32_t oldFreq, newFreq;
2769 oldFreq = Cy_SysClk_FllGetFrequency();
2770 newFreq = Cy_PRA_CalculateFLLOutFreq(devConfig);
2771 /* Disables FLL when its state changes ENABLE -> DISABLE or FLL configuration changed */
2772 if ((!(devConfig->fllEnable)) || /* state change from ENABLE -> DISABLE */
2773 (oldFreq != newFreq)) /* fll configuration is changed */
2774 {
2775 sysClkStatus = Cy_SysClk_FllDisable();
2776
2777 if (CY_SYSCLK_SUCCESS != sysClkStatus)
2778 {
2779 return CY_PRA_STATUS_ERROR_PROCESSING_FLL0;
2780 }
2781 }
2782 }
2783
2784 /* When the FLL state changes DISABLE -> ENABLE, then only enable FLL.
2785 * Ignore, if FLL is already enabled
2786 */
2787 if((devConfig->fllEnable) && (!Cy_SysClk_FllIsEnabled()))
2788 {
2789 SystemCoreClockUpdate();
2790 status = Cy_PRA_FllInit(devConfig);
2791
2792 if (CY_PRA_STATUS_SUCCESS != status)
2793 {
2794 return status;
2795 }
2796 }
2797
2798
2799 /* CLK_HF0 Init */
2800 sysClkStatus = Cy_SysClk_ClkHfSetSource(CY_PRA_CLKHF_0, devConfig->hf0Source);
2801 if (CY_SYSCLK_SUCCESS != sysClkStatus)
2802 {
2803 return CY_PRA_STATUS_ERROR_PROCESSING_CLKHF0;
2804 }
2805 sysClkStatus = Cy_SysClk_ClkHfSetDivider(CY_PRA_CLKHF_0, devConfig->hf0Divider);
2806 if (CY_SYSCLK_SUCCESS != sysClkStatus)
2807 {
2808 return CY_PRA_STATUS_ERROR_PROCESSING_CLKHF0;
2809 }
2810
2811 if ((devConfig->path0Src == CY_SYSCLK_CLKPATH_IN_WCO) && (devConfig->hf0Source == CY_SYSCLK_CLKHF_IN_CLKPATH0))
2812 {
2813 if (devConfig->path1Enable)
2814 {
2815 sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_1, devConfig->path1Src);
2816 if (CY_SYSCLK_SUCCESS != sysClkStatus)
2817 {
2818 return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX1;
2819 }
2820 }
2821 else
2822 {
2823 return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX1;
2824 }
2825
2826 }
2827
2828 if (CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_1)
2829 {
2830 if(Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_1))
2831 {
2832 uint32_t oldFreq, newFreq;
2833 oldFreq = Cy_SysClk_PllGetFrequency(CY_PRA_CLKPLL_1);
2834 newFreq = Cy_PRA_CalculatePLLOutFreq(CY_PRA_CLKPLL_1, devConfig);
2835 /* Disables PLL0 when its state changes ENABLE -> DISABLE or PLL configuration changed */
2836 if ((!devConfig->pll0Enable) || /* state change from ENABLE -> DISABLE */
2837 (oldFreq != newFreq)) /* pll1 configuration is changed */
2838 {
2839 SystemCoreClockUpdate();
2840 sysClkStatus = Cy_SysClk_PllDisable(CY_PRA_CLKPLL_1);
2841
2842 if (CY_SYSCLK_SUCCESS != sysClkStatus)
2843 {
2844 return CY_PRA_STATUS_ERROR_PROCESSING_PLL0;
2845 }
2846 }
2847 }
2848 /* When the PLL0 state changes DISABLE -> ENABLE, enable only PLL0.
2849 * Ignore, if PLL0 is already enabled */
2850
2851 if((devConfig->pll0Enable) && (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_1)))
2852 {
2853 const cy_stc_pll_manual_config_t pll0Config =
2854 {
2855 .feedbackDiv = devConfig->pll0FeedbackDiv,
2856 .referenceDiv = devConfig->pll0ReferenceDiv,
2857 .outputDiv = devConfig->pll0OutputDiv,
2858 .lfMode = devConfig->pll0LfMode,
2859 .outputMode = devConfig->pll0OutputMode,
2860 };
2861
2862 SystemCoreClockUpdate();
2863 status = Cy_PRA_PllInit(CY_PRA_CLKPLL_1, &pll0Config);
2864
2865 if (CY_PRA_STATUS_SUCCESS != status)
2866 {
2867 return CY_PRA_STATUS_ERROR_PROCESSING_PLL0;
2868 }
2869 }
2870 }
2871
2872 if (CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_2)
2873 {
2874 if(Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_2))
2875 {
2876 uint32_t oldFreq, newFreq;
2877 oldFreq = Cy_SysClk_PllGetFrequency(CY_PRA_CLKPLL_2);
2878 newFreq = Cy_PRA_CalculatePLLOutFreq(CY_PRA_CLKPLL_2, devConfig);
2879 /* Disables PLL0 when its state changes ENABLE -> DISABLE or PLL configuration changed */
2880 if ((!devConfig->pll1Enable) || /* state change from ENABLE -> DISABLE */
2881 (oldFreq != newFreq)) /* pll2 configuration is changed */
2882 {
2883 SystemCoreClockUpdate();
2884 sysClkStatus = Cy_SysClk_PllDisable(CY_PRA_CLKPLL_2);
2885
2886 if (CY_SYSCLK_SUCCESS != sysClkStatus)
2887 {
2888 return CY_PRA_STATUS_ERROR_PROCESSING_PLL1;
2889 }
2890 }
2891 }
2892 /* When the PLL1 state changes DISABLE -> ENABLE, enable only PLL1.
2893 * Ignore, if PLL1 is already enabled */
2894
2895 if((devConfig->pll1Enable) && (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_2)))
2896 {
2897 const cy_stc_pll_manual_config_t pll1Config =
2898 {
2899 .feedbackDiv = devConfig->pll1FeedbackDiv,
2900 .referenceDiv = devConfig->pll1ReferenceDiv,
2901 .outputDiv = devConfig->pll1OutputDiv,
2902 .lfMode = devConfig->pll1LfMode,
2903 .outputMode = devConfig->pll1OutputMode,
2904 };
2905
2906 SystemCoreClockUpdate();
2907 status = Cy_PRA_PllInit(CY_PRA_CLKPLL_2, &pll1Config);
2908
2909 if (CY_PRA_STATUS_SUCCESS != status)
2910 {
2911 return CY_PRA_STATUS_ERROR_PROCESSING_PLL1;
2912 }
2913 }
2914 }
2915
2916 /* Configures the HF clocks */
2917 if (Cy_SysClk_ClkHfIsEnabled(CY_PRA_CLKHF_1))
2918 {
2919 if (!devConfig->clkHF1Enable)
2920 {
2921 status = (cy_en_pra_status_t)Cy_SysClk_ClkHfDisable(CY_PRA_CLKHF_1);
2922 if (CY_PRA_STATUS_SUCCESS != status)
2923 {
2924 return CY_PRA_STATUS_INVALID_PARAM_CLKHF1;
2925 }
2926 }
2927 }
2928 else
2929 {
2930 if (devConfig->clkHF1Enable)
2931 {
2932 status = Cy_PRA_ClkHfInit(CY_PRA_CLKHF_1, devConfig->hf1Source, devConfig->hf1Divider);
2933 if (CY_PRA_STATUS_SUCCESS != status)
2934 {
2935 return CY_PRA_STATUS_INVALID_PARAM_CLKHF1;
2936 }
2937 }
2938 }
2939
2940 if (Cy_SysClk_ClkHfIsEnabled(CY_PRA_CLKHF_2))
2941 {
2942 if (!devConfig->clkHF2Enable)
2943 {
2944 status = (cy_en_pra_status_t)Cy_SysClk_ClkHfDisable(CY_PRA_CLKHF_2);
2945 if (CY_PRA_STATUS_SUCCESS != status)
2946 {
2947 return CY_PRA_STATUS_INVALID_PARAM_CLKHF2;
2948 }
2949 }
2950 }
2951 else
2952 {
2953 if (devConfig->clkHF2Enable)
2954 {
2955 status = Cy_PRA_ClkHfInit(CY_PRA_CLKHF_2, devConfig->hf2Source, devConfig->hf2Divider);
2956 if (CY_PRA_STATUS_SUCCESS != status)
2957 {
2958 return CY_PRA_STATUS_INVALID_PARAM_CLKHF2;
2959 }
2960 }
2961 }
2962
2963 if(CY_PRA_CLKHF_3 < CY_SRSS_NUM_HFROOT)
2964 {
2965 if (Cy_SysClk_ClkHfIsEnabled(CY_PRA_CLKHF_3))
2966 {
2967 if (!devConfig->clkHF3Enable)
2968 {
2969 status = (cy_en_pra_status_t)Cy_SysClk_ClkHfDisable(CY_PRA_CLKHF_3);
2970 if (CY_PRA_STATUS_SUCCESS != status)
2971 {
2972 return CY_PRA_STATUS_INVALID_PARAM_CLKHF3;
2973 }
2974 }
2975 }
2976 else
2977 {
2978 if (devConfig->clkHF3Enable)
2979 {
2980 status = Cy_PRA_ClkHfInit(CY_PRA_CLKHF_3, devConfig->hf3Source, devConfig->hf3Divider);
2981 if (CY_PRA_STATUS_SUCCESS != status)
2982 {
2983 return CY_PRA_STATUS_INVALID_PARAM_CLKHF3;
2984 }
2985 }
2986 }
2987 }
2988
2989 if (CY_PRA_CLKHF_4 < CY_SRSS_NUM_HFROOT)
2990 {
2991 if (Cy_SysClk_ClkHfIsEnabled(CY_PRA_CLKHF_4))
2992 {
2993 if (!devConfig->clkHF4Enable)
2994 {
2995 status = (cy_en_pra_status_t)Cy_SysClk_ClkHfDisable(CY_PRA_CLKHF_4);
2996 if (CY_PRA_STATUS_SUCCESS != status)
2997 {
2998 return CY_PRA_STATUS_INVALID_PARAM_CLKHF4;
2999 }
3000 }
3001 }
3002 else
3003 {
3004 if (devConfig->clkHF4Enable)
3005 {
3006 status = Cy_PRA_ClkHfInit(CY_PRA_CLKHF_4, devConfig->hf4Source, devConfig->hf4Divider);
3007 if (CY_PRA_STATUS_SUCCESS != status)
3008 {
3009 return CY_PRA_STATUS_INVALID_PARAM_CLKHF4;
3010 }
3011 }
3012 }
3013 }
3014
3015 if (CY_PRA_CLKHF_5 < CY_SRSS_NUM_HFROOT)
3016 {
3017 if (Cy_SysClk_ClkHfIsEnabled(CY_PRA_CLKHF_5))
3018 {
3019 if (!devConfig->clkHF5Enable)
3020 {
3021 status = (cy_en_pra_status_t)Cy_SysClk_ClkHfDisable(CY_PRA_CLKHF_5);
3022 if (CY_PRA_STATUS_SUCCESS != status)
3023 {
3024 return CY_PRA_STATUS_INVALID_PARAM_CLKHF5;
3025 }
3026 }
3027 }
3028 else
3029 {
3030 if (devConfig->clkHF5Enable)
3031 {
3032 status = Cy_PRA_ClkHfInit(CY_PRA_CLKHF_5, devConfig->hf5Source, devConfig->hf5Divider);
3033 if (CY_PRA_STATUS_SUCCESS != status)
3034 {
3035 return CY_PRA_STATUS_INVALID_PARAM_CLKHF5;
3036 }
3037 }
3038 }
3039 }
3040
3041 /* Configures miscellaneous clocks */
3042 if (Cy_SysClk_ClkTimerIsEnabled())
3043 {
3044 if (!devConfig->clkTimerEnable)
3045 {
3046 Cy_SysClk_ClkTimerDisable();
3047 }
3048 }
3049 /* When the TIMER state changes DISABLE -> ENABLE, enable only TIMER.
3050 * Ignore, if TIMER is already enabled */
3051 else
3052 {
3053 if (devConfig->clkTimerEnable)
3054 {
3055 Cy_PRA_ClkTimerInit(devConfig->clkTimerSource, devConfig->clkTimerDivider);
3056 }
3057 }
3058
3059 if (Cy_SysClk_ClkPumpIsEnabled())
3060 {
3061 if (!devConfig->clkPumpEnable)
3062 {
3063 Cy_SysClk_ClkPumpDisable();
3064 }
3065 }
3066 /* When the PUMP state changes DISABLE -> ENABLE, enable only PUMP.
3067 * Ignore, if PUMP is already enabled */
3068 else
3069 {
3070 if (devConfig->clkPumpEnable)
3071 {
3072 Cy_PRA_ClkPumpInit(devConfig->pumpSource, devConfig->pumpDivider);
3073 }
3074 }
3075
3076 if (devConfig->clkBakEnable)
3077 {
3078 Cy_SysClk_ClkBakSetSource(devConfig->clkBakSource);
3079 }
3080
3081 status = Cy_PRA_IloHibernateOn(devConfig->iloHibernateON);
3082 if (CY_PRA_STATUS_SUCCESS != status)
3083 {
3084 return status;
3085 }
3086
3087 /* Configures the default-enabled clocks */
3088 if (Cy_SysClk_IloIsEnabled())
3089 {
3090 if (!devConfig->iloEnable)
3091 {
3092 /* Wait 4 ILO cycles before it is disabled */
3093 Cy_SysLib_DelayUs(ILO_DISABLE_DELAY_US);
3094
3095 status = Cy_PRA_IloDisable();
3096 if (CY_PRA_STATUS_SUCCESS != status)
3097 {
3098 return status;
3099 }
3100 }
3101 }
3102 /* When the ILO state changes DISABLE -> ENABLE, enable only ILO.
3103 * Ignore, if ILO is already enabled */
3104 else
3105 {
3106 if (devConfig->iloEnable)
3107 {
3108 status = Cy_PRA_IloEnable();
3109 if (CY_PRA_STATUS_SUCCESS != status)
3110 {
3111 return status;
3112 }
3113 }
3114 }
3115
3116 /* SYSCLK MFO INIT */
3117 /* SYSCLK MF INIT */
3118
3119 /* Sets accurate flash wait states */
3120 if ((devConfig->powerEnable) && (devConfig->clkHF0Enable))
3121 {
3122 Cy_SysLib_SetWaitStates(devConfig->ulpEnable, devConfig->hf0OutFreqMHz);
3123 }
3124
3125 /* Updates the System Core Clock values for the correct Cy_SysLib_Delay functioning.
3126 * This function is called before every PDL function where the Cy_SysLib_Delay
3127 * function is used.
3128 */
3129 SystemCoreClockUpdate();
3130
3131 #endif /* (CY_CPU_CORTEX_M4) */
3132
3133 return (status);
3134 }
3135
3136
3137 #if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
3138 /*******************************************************************************
3139 * Function Name: Cy_PRA_CloseSrssMain2
3140 ****************************************************************************//**
3141 *
3142 * Restricts the access to the SRSS_MAIN2 region, which includes the following
3143 * registers: SRSS_TST_DDFT_SLOW_CTL_REG and SRSS_TST_DDFT_FAST_CTL_REG.
3144 *
3145 * The function is called from \ref Cy_SysPm_CpuEnterDeepSleep() only for
3146 * the PSOC6ABLE2 devices.
3147 *
3148 *******************************************************************************/
3149 #if defined(CY_DEVICE_PSOC6ABLE2)
3150 CY_SECTION_RAMFUNC_BEGIN
3151 #if !defined (__ICCARM__)
3152 CY_NOINLINE
3153 #endif
3154 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
Cy_PRA_CloseSrssMain2(void)3155 void Cy_PRA_CloseSrssMain2(void)
3156 {
3157 #if defined(CY_DEVICE_PSOC6ABLE2)
3158 /* Turn off PC_MATCH for SRSS fixed PPU */
3159 uint32_t slaveAtt = PERI_GR_PPU_SL_SRSS->ATT0;
3160 slaveAtt &= ~PERI_GR_PPU_SL_ATT0_PC_MATCH_Msk;
3161 PERI_GR_PPU_SL_SRSS->ATT0 = slaveAtt;
3162
3163 /* Disable programmable PPUs #2 and #3 */
3164 PERI_PPU_PR_ATT0(PERI_PPU_PR2) &= ~_VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
3165 PERI_PPU_PR_ATT0(PERI_PPU_PR3) &= ~_VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
3166 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
3167 }
3168 #if defined(CY_DEVICE_PSOC6ABLE2)
3169 CY_SECTION_RAMFUNC_END
3170 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
3171
3172
3173 /*******************************************************************************
3174 * Function Name: Cy_PRA_OpenSrssMain2
3175 ****************************************************************************//**
3176 *
3177 * Restores the access to the SRSS_MAIN2 region, which was restricted by
3178 * Cy_PRA_CloseSrssMain2.
3179 *
3180 * The function is called from \ref Cy_SysPm_CpuEnterDeepSleep() only for
3181 * the CYB06xx7 devices.
3182 *
3183 *******************************************************************************/
3184 #if defined(CY_DEVICE_PSOC6ABLE2)
3185 CY_SECTION_RAMFUNC_BEGIN
3186 #if !defined (__ICCARM__)
3187 CY_NOINLINE
3188 #endif
3189 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
Cy_PRA_OpenSrssMain2(void)3190 void Cy_PRA_OpenSrssMain2(void)
3191 {
3192 #if defined(CY_DEVICE_PSOC6ABLE2)
3193 /* Turn on PC_MATCH for SRSS fixed PPU */
3194 uint32_t slaveAtt = PERI_GR_PPU_SL_SRSS->ATT0;
3195 slaveAtt |= PERI_GR_PPU_SL_ATT0_PC_MATCH_Msk;
3196 PERI_GR_PPU_SL_SRSS->ATT0 = slaveAtt;
3197
3198 /* Enable programmable PPUs #2 and #3 */
3199 PERI_PPU_PR_ATT0(PERI_PPU_PR2) |= _VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
3200 PERI_PPU_PR_ATT0(PERI_PPU_PR3) |= _VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
3201 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
3202 }
3203 #if defined(CY_DEVICE_PSOC6ABLE2)
3204 CY_SECTION_RAMFUNC_END
3205 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
3206
3207 #endif /* (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) */
3208
3209 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 17.2')
3210
3211 #endif /* (CY_DEVICE_SECURE) */
3212
3213 #endif /* defined (CY_IP_MXS40SRSS) */
3214
3215 /* [] END OF FILE */
3216
