1 /***************************************************************************//**
2 * \file cy_mcwdt_b.c
3 * \version 1.70
4 *
5 * Description:
6 * Provides a system API for the MCWDT driver.
7 *
8 ********************************************************************************
9 * Copyright 2016-2021 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24
25 #include "cy_device.h"
26
27 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined(CY_DOXYGEN)
28
29 #include "cy_mcwdt.h"
30
31 #if defined(__cplusplus)
32 extern "C" {
33 #endif
34
35 /*******************************************************************************
36 * Function Name: Cy_MCWDT_Init
37 ****************************************************************************//**
38 *
39 * Initializes the MCWDT_B block.
40 *
41 * \param base
42 * The base pointer to a structure that describes the registers.
43 *
44 * \param config
45 * The pointer to a structure that contains component configuration data.
46 *
47 * \return cy_en_mcwdt_status_t
48 * *base checking result. If the pointer is NULL, returns error.
49 *
50 * \note
51 * This API should not be called when the counters are running. Prior to calling
52 * this API the counter should be disabled.
53 *
54 *******************************************************************************/
Cy_MCWDT_Init(MCWDT_Type * base,cy_stc_mcwdt_config_t const * config)55 cy_en_mcwdt_status_t Cy_MCWDT_Init(MCWDT_Type *base, cy_stc_mcwdt_config_t const *config)
56 {
57 cy_en_mcwdt_status_t ret = CY_MCWDT_BAD_PARAM;
58 if ((base != NULL) && (config != NULL))
59 {
60 Cy_MCWDT_Unlock(base);
61
62 Cy_MCWDT_CpuSelectForDpSlpPauseAction(base, config->coreSelect);
63
64 Cy_MCWDT_SetLowerLimit(base, CY_MCWDT_COUNTER0, config->c0LowerLimit, 0);
65 Cy_MCWDT_SetUpperLimit(base, CY_MCWDT_COUNTER0, config->c0UpperLimit, 0);
66 Cy_MCWDT_SetWarnLimit(base, CY_MCWDT_COUNTER0, config->c0WarnLimit, 0);
67
68 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0) = _VAL2FLD(MCWDT_CTR_CONFIG_LOWER_ACTION, config->c0LowerAction) |
69 _VAL2FLD(MCWDT_CTR_CONFIG_UPPER_ACTION, config->c0UpperAction) |
70 _VAL2FLD(MCWDT_CTR_CONFIG_WARN_ACTION, config->c0WarnAction) |
71 _VAL2FLD(MCWDT_CTR_CONFIG_AUTO_SERVICE, config->c0AutoService) |
72 _VAL2FLD(MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE, config->c0SleepDeepPause) |
73 _VAL2FLD(MCWDT_CTR_CONFIG_DEBUG_RUN, config->c0DebugRun);
74
75
76 Cy_MCWDT_SetLowerLimit(base, CY_MCWDT_COUNTER1, config->c1LowerLimit, 0);
77 Cy_MCWDT_SetUpperLimit(base, CY_MCWDT_COUNTER1, config->c1UpperLimit, 0);
78 Cy_MCWDT_SetWarnLimit(base, CY_MCWDT_COUNTER1, config->c1WarnLimit, 0);
79
80 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1) = _VAL2FLD(MCWDT_CTR_CONFIG_LOWER_ACTION, config->c1LowerAction) |
81 _VAL2FLD(MCWDT_CTR_CONFIG_UPPER_ACTION, config->c1UpperAction) |
82 _VAL2FLD(MCWDT_CTR_CONFIG_WARN_ACTION, config->c1WarnAction) |
83 _VAL2FLD(MCWDT_CTR_CONFIG_AUTO_SERVICE, config->c1AutoService) |
84 _VAL2FLD(MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE, config->c1SleepDeepPause) |
85 _VAL2FLD(MCWDT_CTR_CONFIG_DEBUG_RUN, config->c1DebugRun);
86
87 MCWDT_CTR2_CONFIG(base) = _VAL2FLD(MCWDT_CTR2_CONFIG_BITS, config->c2ToggleBit) |
88 _VAL2FLD(MCWDT_CTR2_CONFIG_ACTION, config->c2Action) |
89 _VAL2FLD(MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE, config->c2SleepDeepPause) |
90 _VAL2FLD(MCWDT_CTR2_CONFIG_DEBUG_RUN, config->c2DebugRun);
91
92 Cy_MCWDT_Lock(base);
93
94 ret = CY_MCWDT_SUCCESS;
95 }
96
97 return (ret);
98 }
99
100
101 /*******************************************************************************
102 * Function Name: Cy_MCWDT_DeInit
103 ****************************************************************************//**
104 *
105 * De-initializes the MCWDT block, returns register values to their default state.
106 *
107 * \param base
108 * The base pointer to a structure that describes the registers.
109 *
110 * \note
111 * This API should not be called when the counters are running. Prior to calling
112 * this API the counter should be disabled.
113 *
114 *******************************************************************************/
Cy_MCWDT_DeInit(MCWDT_Type * base)115 void Cy_MCWDT_DeInit(MCWDT_Type *base)
116 {
117 Cy_MCWDT_Unlock(base);
118
119 // disable all counter
120 Cy_MCWDT_Disable(base, CY_MCWDT_CTR0, 0);
121 Cy_MCWDT_Disable(base, CY_MCWDT_CTR1, 0);
122 Cy_MCWDT_Disable(base, CY_MCWDT_CTR2, 0);
123
124 /* De-Init counter-0 */
125 while(Cy_MCWDT_GetEnabledStatus(base, CY_MCWDT_COUNTER0) != 0x0UL)
126 {
127 // wait until enabled bit become 1
128 }
129 Cy_MCWDT_SetLowerLimit(base, CY_MCWDT_COUNTER0, 0x0U, 0);
130 Cy_MCWDT_SetUpperLimit(base, CY_MCWDT_COUNTER0, 0x0U, 0);
131 Cy_MCWDT_SetWarnLimit(base, CY_MCWDT_COUNTER0, 0x0U, 0);
132 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0) = 0x0UL;
133 MCWDT_CTR_CNT(base, CY_MCWDT_COUNTER0) = 0x0UL;
134
135 /* De-Init counter-1 */
136 while(Cy_MCWDT_GetEnabledStatus(base, CY_MCWDT_COUNTER1) != 0x0UL)
137 {
138 // wait until enabled bit become 1
139 }
140 Cy_MCWDT_SetLowerLimit(base, CY_MCWDT_COUNTER1, 0x0U, 0);
141 Cy_MCWDT_SetUpperLimit(base, CY_MCWDT_COUNTER1, 0x0U, 0);
142 Cy_MCWDT_SetWarnLimit(base, CY_MCWDT_COUNTER1, 0x0U, 0);
143 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1) = 0x0UL;
144 MCWDT_CTR_CNT(base, CY_MCWDT_COUNTER1) = 0x0UL;
145
146 /* De-Init counter-2 */
147 while(Cy_MCWDT_GetEnabledStatus(base, CY_MCWDT_COUNTER2) != 0x0UL)
148 {
149 // wait until enabled bit become 1
150 }
151 Cy_MCWDT_CpuSelectForDpSlpPauseAction(base, CY_MCWDT_PAUSED_BY_DPSLP_CM0);
152 MCWDT_CTR2_CONFIG(base) = 0x0UL;
153 Cy_MCWDT_ResetCounters(base, CY_MCWDT_CTR0, 0);
154 Cy_MCWDT_ResetCounters(base, CY_MCWDT_CTR1, 0);
155 MCWDT_INTR(base) = 0xFFFFFFFFUL;
156 MCWDT_INTR_MASK(base) = 0x0UL;
157
158 Cy_MCWDT_Lock(base);
159
160 }
161
162 /*******************************************************************************
163 * Function Name: Cy_MCWDT_ClearWatchdog
164 ****************************************************************************//**
165 *
166 * Clears the MC watchdog counter, to prevent a XRES device reset or fault.
167 *
168 * \param base
169 * The base pointer to a structure that describes the registers.
170 *
171 * \param counters
172 * OR of all counters to clear watchdog. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
173 * CY_MCWDT_CTR2 macros.
174 *
175 *******************************************************************************/
Cy_MCWDT_ClearWatchdog(MCWDT_Type * base,uint32_t counters)176 void Cy_MCWDT_ClearWatchdog(MCWDT_Type *base, uint32_t counters)
177 {
178 Cy_MCWDT_Unlock(base);
179 Cy_MCWDT_ResetCounters(base, counters, 0u);
180 Cy_MCWDT_Lock(base);
181 }
182
183
184 /*******************************************************************************
185 * Function Name: Cy_MCWDT_CpuSelectForDpSlpPauseAction
186 ****************************************************************************//**
187 *
188 * Select deep sleep of which core for pausing this counter
189 *
190 * \param base
191 * The base pointer to a structure that describes registers.
192 *
193 * \param core
194 * The selected core. Deep sleep of the core pause this counter.
195 *
196 * \note
197 * This API is available for CAT1C devices.
198 *
199 *******************************************************************************/
Cy_MCWDT_CpuSelectForDpSlpPauseAction(MCWDT_Type * base,cy_en_mcwdt_select_core_t core)200 void Cy_MCWDT_CpuSelectForDpSlpPauseAction(MCWDT_Type *base, cy_en_mcwdt_select_core_t core)
201 {
202 MCWDT_CPU_SELECT(base) = _CLR_SET_FLD32U(MCWDT_CPU_SELECT(base), MCWDT_CPU_SELECT_CPU_SEL, core);
203 }
204
205 /*******************************************************************************
206 * Function Name: Cy_MCWDT_SetLowerAction
207 ****************************************************************************//**
208 *
209 * Sets the lower limit action of the specified counter.
210 *
211 * \param base
212 * The base pointer to a structure that describes registers.
213 *
214 * \param counter
215 * The number of the WDT counter. The valid range is [0-1].
216 *
217 * \param action
218 * The action of operation for the counter. See enum typedef cy_en_mcwdt_lower_upper_action_t.
219 *
220 * \note
221 * This API must not be called while the counters are running.
222 * Prior to calling this API, the counter must be disabled.
223 *
224 * \note
225 * This API is available for CAT1C devices.
226 *
227 *******************************************************************************/
Cy_MCWDT_SetLowerAction(MCWDT_Type * base,cy_en_mcwdtctr_t counter,cy_en_mcwdt_lower_upper_action_t action)228 void Cy_MCWDT_SetLowerAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdt_lower_upper_action_t action)
229 {
230 switch (counter)
231 {
232 case CY_MCWDT_COUNTER0:
233 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0), MCWDT_CTR_CONFIG_LOWER_ACTION, action);
234 break;
235 case CY_MCWDT_COUNTER1:
236 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1), MCWDT_CTR_CONFIG_LOWER_ACTION, action);
237 break;
238 default:
239 CY_ASSERT(0u != 0u);
240 break;
241 }
242 }
243
244 /*******************************************************************************
245 * Function Name: Cy_MCWDT_SetUpperAction
246 ****************************************************************************//**
247 *
248 * Sets the upper limit action of the specified counter.
249 *
250 * \param base
251 * The base pointer to a structure that describes registers.
252 *
253 * \param counter
254 * The number of the WDT counter. The valid range is [0-1].
255 *
256 * \param action
257 * The action of operation for the counter. See enum typedef cy_en_mcwdt_lower_upper_action_t.
258 *
259 * \note
260 * This API must not be called while the counters are running.
261 * Prior to calling this API, the counter must be disabled.
262 *
263 * \note
264 * This API is available for CAT1C devices.
265 *
266 *******************************************************************************/
Cy_MCWDT_SetUpperAction(MCWDT_Type * base,cy_en_mcwdtctr_t counter,cy_en_mcwdt_lower_upper_action_t action)267 void Cy_MCWDT_SetUpperAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdt_lower_upper_action_t action)
268 {
269 switch (counter)
270 {
271 case CY_MCWDT_COUNTER0:
272 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0), MCWDT_CTR_CONFIG_UPPER_ACTION, action);
273 break;
274 case CY_MCWDT_COUNTER1:
275 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1), MCWDT_CTR_CONFIG_UPPER_ACTION, action);
276 break;
277 default:
278 CY_ASSERT(0u != 0u);
279 break;
280 }
281 }
282
283 /*******************************************************************************
284 * Function Name: Cy_MCWDT_SetUpperAction
285 ****************************************************************************//**
286 *
287 * Sets the warn limit action of the specified counter.
288 *
289 * \param base
290 * The base pointer to a structure that describes registers.
291 *
292 * \param counter
293 * The number of the WDT counter. The valid range is [0-1].
294 *
295 * \param action
296 * The action of operation for the counter. See enum typedef cy_en_mcwdt_warn_action_t.
297 *
298 * \note
299 * This API must not be called while the counters are running.
300 * Prior to calling this API, the counter must be disabled.
301 *
302 * \note
303 * This API is available for CAT1C devices.
304 *
305 *******************************************************************************/
Cy_MCWDT_SetWarnAction(MCWDT_Type * base,cy_en_mcwdtctr_t counter,cy_en_mcwdt_warn_action_t action)306 void Cy_MCWDT_SetWarnAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdt_warn_action_t action)
307 {
308 switch (counter)
309 {
310 case CY_MCWDT_COUNTER0:
311 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0), MCWDT_CTR_CONFIG_WARN_ACTION, action);
312 break;
313 case CY_MCWDT_COUNTER1:
314 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1), MCWDT_CTR_CONFIG_WARN_ACTION, action);
315 break;
316 default:
317 CY_ASSERT(0u != 0u);
318 break;
319 }
320 }
321
322 /*******************************************************************************
323 * Function Name: Cy_MCWDT_SetSubCounter2Action
324 ****************************************************************************//**
325 *
326 * Sets the counter 2 action of the specified counter.
327 *
328 * \param base
329 * The base pointer to a structure that describes registers.
330 *
331 * \param action
332 * The action of operation for the counter. See enum typedef cy_en_mcwdt_cnt2_action_t.
333 *
334 * \note
335 * This API must not be called while the counters are running.
336 * Prior to calling this API, the counter must be disabled.
337 *
338 * \note
339 * This API is available for CAT1C devices.
340 *
341 *******************************************************************************/
Cy_MCWDT_SetSubCounter2Action(MCWDT_Type * base,cy_en_mcwdt_cnt2_action_t action)342 void Cy_MCWDT_SetSubCounter2Action(MCWDT_Type *base, cy_en_mcwdt_cnt2_action_t action)
343 {
344 MCWDT_CTR2_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CTR2_CONFIG(base), MCWDT_CTR2_CONFIG_ACTION, action);
345 }
346
347 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 10.8', 4, 'Intentional typecast to cy_en_mcwdt_lower_upper_action_t enum.')
348 /*******************************************************************************
349 * Function Name: Cy_MCWDT_GetLowerAction
350 ****************************************************************************//**
351 *
352 * Reports the lower limit action type of the specified counter.
353 *
354 * \param base
355 * The base pointer to a structure that describes registers.
356 *
357 * \param counter
358 * The number of the WDT counter. The valid range is [0-1].
359 *
360 * \return
361 * The current lower limit action type of the counter.
362 * See enum typedef cy_en_mcwdt_lower_upper_action_t.
363 *
364 * \note
365 * This API is available for CAT1C devices.
366 *
367 *******************************************************************************/
Cy_MCWDT_GetLowerAction(MCWDT_Type * base,cy_en_mcwdtctr_t counter)368 cy_en_mcwdt_lower_upper_action_t Cy_MCWDT_GetLowerAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter)
369 {
370 cy_en_mcwdt_lower_upper_action_t lowerLimitActionType = CY_MCWDT_ACTION_NONE;
371
372 switch (counter)
373 {
374 case CY_MCWDT_COUNTER0:
375 lowerLimitActionType = (cy_en_mcwdt_lower_upper_action_t)(_FLD2VAL(MCWDT_CTR_CONFIG_LOWER_ACTION, MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0)));
376 break;
377 case CY_MCWDT_COUNTER1:
378 lowerLimitActionType = (cy_en_mcwdt_lower_upper_action_t)(_FLD2VAL(MCWDT_CTR_CONFIG_LOWER_ACTION, MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1)));
379 break;
380 default:
381 CY_ASSERT(0u != 0u);
382 break;
383 }
384
385 return lowerLimitActionType; /* Control shouldn't reach here, fixes IAR compilation warning */
386 }
387
388 /*******************************************************************************
389 * Function Name: Cy_MCWDT_GetUpperAction
390 ****************************************************************************//**
391 *
392 * Reports the upper limit action type of the specified counter.
393 *
394 * \param base
395 * The base pointer to a structure that describes registers.
396 *
397 * \param counter
398 * The number of the WDT counter. The valid range is [0-1].
399 *
400 * \return
401 * The current upper limit action type of the counter.
402 * See enum typedef cy_en_mcwdt_lower_upper_action_t.
403 *
404 * \note
405 * This API is available for CAT1C devices.
406 *
407 *******************************************************************************/
Cy_MCWDT_GetUpperAction(MCWDT_Type * base,cy_en_mcwdtctr_t counter)408 cy_en_mcwdt_lower_upper_action_t Cy_MCWDT_GetUpperAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter)
409 {
410 cy_en_mcwdt_lower_upper_action_t upperLimitActionType = CY_MCWDT_ACTION_NONE;
411
412 switch (counter)
413 {
414 case CY_MCWDT_COUNTER0:
415 upperLimitActionType = (cy_en_mcwdt_lower_upper_action_t)(_FLD2VAL(MCWDT_CTR_CONFIG_UPPER_ACTION, MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0)));
416 break;
417 case CY_MCWDT_COUNTER1:
418 upperLimitActionType = (cy_en_mcwdt_lower_upper_action_t)(_FLD2VAL(MCWDT_CTR_CONFIG_UPPER_ACTION, MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1)));
419 break;
420 default:
421 CY_ASSERT(0u != 0u);
422 break;
423 }
424
425 return upperLimitActionType; /* Control shouldn't reach here, fixes IAR compilation warning */
426 }
427 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 10.8')
428
429 /*******************************************************************************
430 * Function Name: Cy_MCWDT_GetWarnAction
431 ****************************************************************************//**
432 *
433 * Reports the warn limit action type of the specified counter.
434 *
435 * \param base
436 * The base pointer to a structure that describes registers.
437 *
438 * \param counter
439 * The number of the WDT counter. The valid range is [0-1].
440 *
441 * \return
442 * The current warn limit action type of the counter.
443 * See enum typedef cy_en_mcwdt_warn_action_t.
444 *
445 * \note
446 * This API is available for CAT1C devices.
447 *
448 *******************************************************************************/
Cy_MCWDT_GetWarnAction(MCWDT_Type * base,cy_en_mcwdtctr_t counter)449 cy_en_mcwdt_warn_action_t Cy_MCWDT_GetWarnAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter)
450 {
451 cy_en_mcwdt_warn_action_t warnAction = CY_MCWDT_WARN_ACTION_NONE;
452
453 switch (counter)
454 {
455 case CY_MCWDT_COUNTER0:
456 {
457 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_mcwdt_warn_action_t enum.');
458 warnAction = (cy_en_mcwdt_warn_action_t)(_FLD2VAL(MCWDT_CTR_CONFIG_WARN_ACTION, MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0)));
459 break;
460 }
461 case CY_MCWDT_COUNTER1:
462 {
463 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_mcwdt_warn_action_t enum.');
464 warnAction = (cy_en_mcwdt_warn_action_t)(_FLD2VAL(MCWDT_CTR_CONFIG_WARN_ACTION, MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1)));
465 break;
466 }
467 default:
468 CY_ASSERT(0u != 0u);
469 break;
470 }
471
472 return warnAction; /* Control shouldn't reach here, fixes IAR compilation warning */
473 }
474
475 /*******************************************************************************
476 * Function Name: Cy_MCWDT_GetSubCounter2Action
477 ****************************************************************************//**
478 *
479 * Reports the counter 2 action type of the specified counter.
480 *
481 * \param base
482 * The base pointer to a structure that describes registers.
483 *
484 * \return
485 * The current counter 2 action type of the counter.
486 * See enum typedef cy_en_mcwdt_cnt2_action_t.
487 *
488 * \note
489 * This API is available for CAT1C devices.
490 *
491 *******************************************************************************/
Cy_MCWDT_GetSubCounter2Action(MCWDT_Type * base)492 cy_en_mcwdt_cnt2_action_t Cy_MCWDT_GetSubCounter2Action(MCWDT_Type *base)
493 {
494 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 10.8','Intentional typecast to cy_en_mcwdt_cnt2_action_t enum.');
495 return (cy_en_mcwdt_cnt2_action_t)(_FLD2VAL(MCWDT_CTR2_CONFIG_ACTION, MCWDT_CTR2_CONFIG(base)));
496 }
497
498 /*******************************************************************************
499 * Function Name: Cy_MCWDT_SetAutoService
500 ****************************************************************************//**
501 *
502 * Sets the Auto service option for the specified counter.
503 *
504 * \param base
505 * The base pointer to a structure that describes registers.
506 *
507 * \param counter
508 * The number of the WDT counter. The valid range is [0-1].
509 *
510 * \note
511 * The auto service option is not supported by Counter 2.
512 *
513 * \param enable
514 * Set 0 to disable; 1 to enable.
515 *
516 * \note
517 * This API must not be called while the counters are running.
518 * Prior to calling this API, the counter must be disabled.
519 *
520 * \note
521 * This API is available for CAT1C devices.
522 *
523 *******************************************************************************/
Cy_MCWDT_SetAutoService(MCWDT_Type * base,cy_en_mcwdtctr_t counter,uint32_t enable)524 void Cy_MCWDT_SetAutoService(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable)
525 {
526 switch (counter)
527 {
528 case CY_MCWDT_COUNTER0:
529 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0), MCWDT_CTR_CONFIG_AUTO_SERVICE, enable);
530 break;
531 case CY_MCWDT_COUNTER1:
532 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1), MCWDT_CTR_CONFIG_AUTO_SERVICE, enable);
533 break;
534 default:
535 CY_ASSERT(0u != 0u);
536 break;
537 }
538 }
539
540
541 /*******************************************************************************
542 * Function Name: Cy_MCWDT_GetAutoService
543 ****************************************************************************//**
544 *
545 * Reports the Auto service setting for the specified counter.
546 *
547 * \param base
548 * The base pointer to a structure that describes registers.
549 *
550 * \param counter
551 * The number of the WDT counter. The valid range is [0-1].
552 *
553 * \return
554 * The Auto service status: 1 = enabled, 0 = disabled.
555 *
556 * \note
557 * The Auto service option is not supported by Counter 2.
558 *
559 * \note
560 * This API is available for CAT1C devices.
561 *
562 *******************************************************************************/
Cy_MCWDT_GetAutoService(MCWDT_Type const * base,cy_en_mcwdtctr_t counter)563 uint32_t Cy_MCWDT_GetAutoService(MCWDT_Type const *base, cy_en_mcwdtctr_t counter)
564 {
565
566 uint32_t retVal = 0UL;
567
568 switch (counter)
569 {
570 case CY_MCWDT_COUNTER0:
571 retVal = (_FLD2VAL(MCWDT_CTR_CONFIG_AUTO_SERVICE, MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0)));
572 break;
573 case CY_MCWDT_COUNTER1:
574 retVal = (_FLD2VAL(MCWDT_CTR_CONFIG_AUTO_SERVICE, MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1)));
575 break;
576 default:
577 CY_ASSERT(0u != 0u);
578 break;
579 }
580
581 return retVal;/* Control shouldn't reach here, fixes IAR compilation warning */
582 }
583
584 /*******************************************************************************
585 * Function Name: Cy_MCWDT_SetSleepDeepPause
586 ****************************************************************************//**
587 *
588 * Sets the Sleep deep pause option for the specified counter.
589 *
590 * \param base
591 * The base pointer to a structure that describes registers.
592 *
593 * \param counter
594 * The number of the WDT counter. The valid range is [0-2].
595 *
596 * \param enable
597 * Set 0 to disable; 1 to enable.
598 *
599 * \note
600 * This API must not be called while the counters are running.
601 * Prior to calling this API, the counter must be disabled.
602 *
603 * \note
604 * This API is available for CAT1C devices.
605 *
606 *******************************************************************************/
Cy_MCWDT_SetSleepDeepPause(MCWDT_Type * base,cy_en_mcwdtctr_t counter,uint32_t enable)607 void Cy_MCWDT_SetSleepDeepPause(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable)
608 {
609 switch (counter)
610 {
611 case CY_MCWDT_COUNTER0:
612 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0), MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE, enable);
613 break;
614 case CY_MCWDT_COUNTER1:
615 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1), MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE, enable);
616 break;
617 case CY_MCWDT_COUNTER2:
618 MCWDT_CTR2_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CTR2_CONFIG(base), MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE, enable);
619 break;
620 default:
621 CY_ASSERT(0u != 0u);
622 break;
623 }
624 }
625
626
627 /*******************************************************************************
628 * Function Name: Cy_MCWDT_GetSleepDeepPause
629 ****************************************************************************//**
630 *
631 * Reports the Sleep deep pause setting for the specified counter.
632 *
633 * \param base
634 * The base pointer to a structure that describes registers.
635 *
636 * \param counter
637 * The number of the WDT counter. The valid range is [0-2].
638 *
639 * \return
640 * The Auto service status: 1 = enabled, 0 = disabled.
641 *
642 * \note
643 * This API is available for CAT1C devices.
644 *
645 *******************************************************************************/
Cy_MCWDT_GetSleepDeepPause(MCWDT_Type const * base,cy_en_mcwdtctr_t counter)646 uint32_t Cy_MCWDT_GetSleepDeepPause(MCWDT_Type const *base, cy_en_mcwdtctr_t counter)
647 {
648 uint32_t retVal = 0UL;
649
650 switch (counter)
651 {
652 case CY_MCWDT_COUNTER0:
653 retVal = (_FLD2VAL(MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE, MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0)));
654 break;
655 case CY_MCWDT_COUNTER1:
656 retVal = (_FLD2VAL(MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE, MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1)));
657 break;
658 case CY_MCWDT_COUNTER2:
659 retVal = (_FLD2VAL(MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE, MCWDT_CTR2_CONFIG(base)));
660 break;
661 default:
662 CY_ASSERT(0u != 0u);
663 break;
664 }
665
666 return retVal;/* Control shouldn't reach here, fixes IAR compilation warning */
667 }
668
669 /*******************************************************************************
670 * Function Name: Cy_MCWDT_SetDebugRun
671 ****************************************************************************//**
672 *
673 * Sets the Debug run option for the specified counter.
674 *
675 * \param base
676 * The base pointer to a structure that describes registers.
677 *
678 * \param counter
679 * The number of the WDT counter. The valid range is [0-2].
680 *
681 * \param enable
682 * Set 0 to disable; 1 to enable.
683 *
684 * \note
685 * This API must not be called while the counters are running.
686 * Prior to calling this API, the counter must be disabled.
687 *
688 * \note
689 * This API is available for CAT1C devices.
690 *
691 *******************************************************************************/
Cy_MCWDT_SetDebugRun(MCWDT_Type * base,cy_en_mcwdtctr_t counter,uint32_t enable)692 void Cy_MCWDT_SetDebugRun(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable)
693 {
694 switch (counter)
695 {
696 case CY_MCWDT_COUNTER0:
697 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0), MCWDT_CTR_CONFIG_DEBUG_RUN, enable);
698 break;
699 case CY_MCWDT_COUNTER1:
700 MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1), MCWDT_CTR_CONFIG_DEBUG_RUN, enable);
701 break;
702 case CY_MCWDT_COUNTER2:
703 MCWDT_CTR2_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CTR2_CONFIG(base), MCWDT_CTR2_CONFIG_DEBUG_RUN, enable);
704 break;
705 default:
706 CY_ASSERT(0u != 0u);
707 break;
708 }
709 }
710
711
712 /*******************************************************************************
713 * Function Name: Cy_MCWDT_GetDebugRun
714 ****************************************************************************//**
715 *
716 * Reports the Debug run setting for the specified counter.
717 *
718 * \param base
719 * The base pointer to a structure that describes registers.
720 *
721 * \param counter
722 * The number of the WDT counter. The valid range is [0-2].
723 *
724 * \return
725 * The Auto service status: 1 = enabled, 0 = disabled.
726 *
727 * \note
728 * This API is available for CAT1C devices.
729 *
730 *******************************************************************************/
Cy_MCWDT_GetDebugRun(MCWDT_Type const * base,cy_en_mcwdtctr_t counter)731 uint32_t Cy_MCWDT_GetDebugRun(MCWDT_Type const *base, cy_en_mcwdtctr_t counter)
732 {
733 uint32_t retVal = 0UL;
734
735 switch (counter)
736 {
737 case CY_MCWDT_COUNTER0:
738 retVal = (_FLD2VAL(MCWDT_CTR_CONFIG_DEBUG_RUN, MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0)));
739 break;
740 case CY_MCWDT_COUNTER1:
741 retVal = (_FLD2VAL(MCWDT_CTR_CONFIG_DEBUG_RUN, MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1)));
742 break;
743 case CY_MCWDT_COUNTER2:
744 retVal = (_FLD2VAL(MCWDT_CTR2_CONFIG_DEBUG_RUN, MCWDT_CTR2_CONFIG(base)));
745 break;
746 default:
747 CY_ASSERT(0u != 0u);
748 break;
749 }
750
751 return retVal;/* Control shouldn't reach here, fixes IAR compilation warning */
752 }
753
754
755 /*******************************************************************************
756 * Function Name: Cy_MCWDT_SetLowerLimit
757 ****************************************************************************//**
758 *
759 * Sets the lower limit value for the specified counter (0 or 1).
760 *
761 * \param base
762 * The base pointer to a structure that describes registers.
763 *
764 * \param counter
765 * The number of the WDT counter. The valid range is [0-1].
766 *
767 * \param limit
768 * The value to lower limit against the counter.
769 * The valid range is [0-65535] when Auto service is disabled and [1-65535] when
770 * Auto service enabled.
771 *
772 * \note
773 * The lower limit value is not supported by Counter 2.
774 *
775 * \note
776 * Action on lower limit is taken on the next increment after the counter value
777 * equal to lower limit value.
778 *
779 * \param waitUs
780 * The function waits for some delay in microseconds before returning,
781 * because the match affects after two lf_clk cycles pass. The recommended
782 * value is 93 us.
783 * \note
784 * Setting this parameter to a zero means No wait. This must be taken
785 * into account when changing the match values on the running counters.
786 *
787 * \note
788 * This API is available for CAT1C devices.
789 *
790 *******************************************************************************/
Cy_MCWDT_SetLowerLimit(MCWDT_Type * base,cy_en_mcwdtctr_t counter,uint16_t limit,uint16_t waitUs)791 void Cy_MCWDT_SetLowerLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint16_t limit, uint16_t waitUs)
792 {
793 switch (counter)
794 {
795 case CY_MCWDT_COUNTER0:
796 MCWDT_CTR_LOWER_LIMIT(base, CY_MCWDT_COUNTER0) = _CLR_SET_FLD32U(MCWDT_CTR_LOWER_LIMIT(base, CY_MCWDT_COUNTER0), MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT, limit);
797 break;
798 case CY_MCWDT_COUNTER1:
799 MCWDT_CTR_LOWER_LIMIT(base, CY_MCWDT_COUNTER1) = _CLR_SET_FLD32U(MCWDT_CTR_LOWER_LIMIT(base, CY_MCWDT_COUNTER1), MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT, limit);
800 break;
801 default:
802 CY_ASSERT(0u != 0u);
803 break;
804 }
805 Cy_SysLib_DelayUs(waitUs);
806 }
807
808 /*******************************************************************************
809 * Function Name: Cy_MCWDT_SetUpperLimit
810 ****************************************************************************//**
811 *
812 * Sets the upper limit value for the specified counter (0 or 1).
813 *
814 * \param base
815 * The base pointer to a structure that describes registers.
816 *
817 * \param counter
818 * The number of the WDT counter. The valid range is [0-1].
819 *
820 * \param limit
821 * The value to upper limit against the counter.
822 * The valid range is [0-65535] when Auto service is disabled and [1-65535] when
823 * Auto service enabled.
824 *
825 * \note
826 * The upper limit value is not supported by Counter 2.
827 *
828 * \note
829 * Action on upper limit is taken on the next increment after the counter value
830 * equal to upper limit value.
831 *
832 * \param waitUs
833 * The function waits for some delay in microseconds before returning,
834 * because the match affects after two lf_clk cycles pass. The recommended
835 * value is 93 us.
836 * \note
837 * Setting this parameter to a zero means No wait. This must be taken
838 * into account when changing the match values on the running counters.
839 *
840 * \note
841 * This API is available for CAT1C devices.
842 *
843 *******************************************************************************/
Cy_MCWDT_SetUpperLimit(MCWDT_Type * base,cy_en_mcwdtctr_t counter,uint16_t limit,uint16_t waitUs)844 void Cy_MCWDT_SetUpperLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint16_t limit, uint16_t waitUs)
845 {
846 switch (counter)
847 {
848 case CY_MCWDT_COUNTER0:
849 MCWDT_CTR_UPPER_LIMIT(base, CY_MCWDT_COUNTER0) = _CLR_SET_FLD32U(MCWDT_CTR_UPPER_LIMIT(base, CY_MCWDT_COUNTER0), MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT, limit);
850 break;
851 case CY_MCWDT_COUNTER1:
852 MCWDT_CTR_UPPER_LIMIT(base, CY_MCWDT_COUNTER1) = _CLR_SET_FLD32U(MCWDT_CTR_UPPER_LIMIT(base, CY_MCWDT_COUNTER1), MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT, limit);
853 break;
854 default:
855 CY_ASSERT(0u != 0u);
856 break;
857 }
858 Cy_SysLib_DelayUs(waitUs);
859 }
860
861 /*******************************************************************************
862 * Function Name: Cy_MCWDT_SetWarnLimit
863 ****************************************************************************//**
864 *
865 * Sets the warn limit value for the specified counter (0 or 1).
866 *
867 * \param base
868 * The base pointer to a structure that describes registers.
869 *
870 * \param counter
871 * The number of the WDT counter. The valid range is [0-1].
872 *
873 * \param limit
874 * The value to warn limit against the counter.
875 * The valid range is [0-65535] when Auto service is disabled and [1-65535] when
876 * Auto service enabled.
877 *
878 * \note
879 * The warn limit value is not supported by Counter 2.
880 *
881 * \note
882 * Action on warn limit is taken on the next increment after the counter value
883 * equal to warn limit value.
884 *
885 * \param waitUs
886 * The function waits for some delay in microseconds before returning,
887 * because the match affects after two lf_clk cycles pass. The recommended
888 * value is 93 us.
889 * \note
890 * Setting this parameter to a zero means No wait. This must be taken
891 * into account when changing the match values on the running counters.
892 *
893 * \note
894 * This API is available for CAT1C devices.
895 *
896 *******************************************************************************/
Cy_MCWDT_SetWarnLimit(MCWDT_Type * base,cy_en_mcwdtctr_t counter,uint16_t limit,uint16_t waitUs)897 void Cy_MCWDT_SetWarnLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint16_t limit, uint16_t waitUs)
898 {
899 switch (counter)
900 {
901 case CY_MCWDT_COUNTER0:
902 MCWDT_CTR_WARN_LIMIT(base, CY_MCWDT_COUNTER0) = _CLR_SET_FLD32U(MCWDT_CTR_WARN_LIMIT(base, CY_MCWDT_COUNTER0), MCWDT_CTR_WARN_LIMIT_WARN_LIMIT, limit);
903 break;
904 case CY_MCWDT_COUNTER1:
905 MCWDT_CTR_WARN_LIMIT(base, CY_MCWDT_COUNTER1) = _CLR_SET_FLD32U(MCWDT_CTR_WARN_LIMIT(base, CY_MCWDT_COUNTER1), MCWDT_CTR_WARN_LIMIT_WARN_LIMIT, limit);
906 break;
907 default:
908 CY_ASSERT(0u != 0u);
909 break;
910 }
911 Cy_SysLib_DelayUs(waitUs);
912 }
913
914 /*******************************************************************************
915 * Function Name: Cy_MCWDT_GetLowerLimit
916 ****************************************************************************//**
917 *
918 * Reports the lower limit comparison value for the specified counter (0 or 1).
919 *
920 * \param base
921 * The base pointer to a structure that describes registers.
922 *
923 * \param counter
924 * The number of the WDT counter. The valid range is [0-1].
925 *
926 * \note
927 * The lower limit value is not supported by Counter 2.
928 *
929 * \return
930 * A 16-bit lower limit value.
931 *
932 * \note
933 * This API is available for CAT1C devices.
934 *
935 *******************************************************************************/
Cy_MCWDT_GetLowerLimit(MCWDT_Type * base,cy_en_mcwdtctr_t counter)936 uint16_t Cy_MCWDT_GetLowerLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter)
937 {
938 uint16_t retVal = 0u;
939
940 switch (counter)
941 {
942 case CY_MCWDT_COUNTER0:
943 retVal = (uint16_t)(_FLD2VAL(MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT, MCWDT_CTR_LOWER_LIMIT(base, CY_MCWDT_COUNTER0)));
944 break;
945 case CY_MCWDT_COUNTER1:
946 retVal = (uint16_t)(_FLD2VAL(MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT, MCWDT_CTR_LOWER_LIMIT(base, CY_MCWDT_COUNTER1)));
947 break;
948 default:
949 CY_ASSERT(0u != 0u);
950 break;
951 }
952
953 return retVal;/* Control shouldn't reach here, fixes IAR compilation warning */
954 }
955
956 /*******************************************************************************
957 * Function Name: Cy_MCWDT_GetUpperLimit
958 ****************************************************************************//**
959 *
960 * Reports the upper limit comparison value for the specified counter (0 or 1).
961 *
962 * \param base
963 * The base pointer to a structure that describes registers.
964 *
965 * \param counter
966 * The number of the WDT counter. The valid range is [0-1].
967 *
968 * \note
969 * The upper limit value is not supported by Counter 2.
970 *
971 * \return
972 * A 16-bit upper limit value.
973 *
974 * \note
975 * This API is available for CAT1C devices.
976 *
977 *******************************************************************************/
Cy_MCWDT_GetUpperLimit(MCWDT_Type * base,cy_en_mcwdtctr_t counter)978 uint16_t Cy_MCWDT_GetUpperLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter)
979 {
980 uint16_t retVal = 0u;
981
982 switch (counter)
983 {
984 case CY_MCWDT_COUNTER0:
985 retVal = (uint16_t)(_FLD2VAL(MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT, MCWDT_CTR_UPPER_LIMIT(base, CY_MCWDT_COUNTER0)));
986 break;
987 case CY_MCWDT_COUNTER1:
988 retVal = (uint16_t)(_FLD2VAL(MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT, MCWDT_CTR_UPPER_LIMIT(base, CY_MCWDT_COUNTER1)));
989 break;
990 default:
991 CY_ASSERT(0u != 0u);
992 break;
993 }
994
995 return retVal;/* Control shouldn't reach here, fixes IAR compilation warning */
996 }
997
998 /*******************************************************************************
999 * Function Name: Cy_MCWDT_GetWarnLimit
1000 ****************************************************************************//**
1001 *
1002 * Reports the warn limit comparison value for the specified counter (0 or 1).
1003 *
1004 * \param base
1005 * The base pointer to a structure that describes registers.
1006 *
1007 * \param counter
1008 * The number of the WDT counter. The valid range is [0-1].
1009 *
1010 * \note
1011 * The warn limit value is not supported by Counter 2.
1012 *
1013 * \return
1014 * A 16-bit warn limit value.
1015 *
1016 * \note
1017 * This API is available for CAT1C devices.
1018 *
1019 *******************************************************************************/
Cy_MCWDT_GetWarnLimit(MCWDT_Type * base,cy_en_mcwdtctr_t counter)1020 uint16_t Cy_MCWDT_GetWarnLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter)
1021 {
1022 uint16_t retVal = 0u;
1023
1024 switch (counter)
1025 {
1026 case CY_MCWDT_COUNTER0:
1027 retVal = (uint16_t)(_FLD2VAL(MCWDT_CTR_WARN_LIMIT_WARN_LIMIT, MCWDT_CTR_WARN_LIMIT(base, CY_MCWDT_COUNTER0)));
1028 break;
1029 case CY_MCWDT_COUNTER1:
1030 retVal = (uint16_t)(_FLD2VAL(MCWDT_CTR_WARN_LIMIT_WARN_LIMIT, MCWDT_CTR_WARN_LIMIT(base, CY_MCWDT_COUNTER1)));
1031 break;
1032 default:
1033 CY_ASSERT(0u != 0u);
1034 break;
1035 }
1036
1037 return retVal;/* Control shouldn't reach here, fixes IAR compilation warning */
1038 }
1039
1040 /*******************************************************************************
1041 * Function Name: Cy_MCWDT_WaitForCounterReset
1042 ****************************************************************************//**
1043 *
1044 * wait completion of counter reset.
1045 *
1046 * \param base
1047 * The base pointer to a structure that describes registers.
1048 *
1049 * \param counter
1050 * The number of the MCWDT counter. The valid range is [0-1].
1051 *
1052 * \note
1053 * This API is available for CAT1C devices.
1054 *
1055 *******************************************************************************/
Cy_MCWDT_WaitForCounterReset(MCWDT_Type * base,cy_en_mcwdtctr_t counter)1056 void Cy_MCWDT_WaitForCounterReset(MCWDT_Type *base, cy_en_mcwdtctr_t counter)
1057 {
1058 switch (counter)
1059 {
1060 case CY_MCWDT_COUNTER0:
1061 {
1062 while((_FLD2VAL(MCWDT_SERVICE_CTR0_SERVICE, MCWDT_SERVICE(base))) != 0UL)
1063 {
1064 }
1065 break;
1066 }
1067 case CY_MCWDT_COUNTER1:
1068 {
1069 while((_FLD2VAL(MCWDT_SERVICE_CTR1_SERVICE, MCWDT_SERVICE(base))) != 0UL)
1070 {
1071 }
1072 break;
1073 }
1074 case CY_MCWDT_COUNTER2:
1075 default:
1076 CY_ASSERT(0u != 0u);
1077 break;
1078 }
1079 }
1080
1081
1082 #if defined(__cplusplus)
1083 }
1084 #endif
1085
1086 #endif /* (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3) */
1087
1088 /* [] END OF FILE */
1089
