1 /***************************************************************************//**
2 * \file cy_gpio.c
3 * \version 1.110
4 *
5 * Provides an API implementation of the GPIO driver
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_device.h"
27
28 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS40IOSS) || defined (CY_IP_MXS22IOSS)
29
30 #include "cy_gpio.h"
31 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
32 #include "cy_pra.h"
33 #endif
34
35 #if defined(__cplusplus)
36 extern "C" {
37 #endif
38
39
40 /* Define for AMUX A splitters */
41 #define GPIO_AMUXA_SPLITTER_MASK (uint32_t)(HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk \
42 | HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk \
43 | HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk)
44
45 /* Define for AMUX B splitters */
46 #define GPIO_AMUXB_SPLITTER_MASK (uint32_t)(HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk \
47 | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk \
48 | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk)
49
50 /*******************************************************************************
51 * Function Name: Cy_GPIO_Pin_Init
52 ****************************************************************************//**
53 *
54 * Initializes all pin configuration settings for the specified pin.
55 *
56 * \param base
57 * Pointer to the pin's port register base address
58 *
59 * \param pinNum
60 * Position of the pin bit-field within the port register
61 *
62 * \param config
63 * Pointer to the pin config structure base address
64 *
65 * \return
66 * Initialization status
67 *
68 * \note
69 * This function modifies port registers in read-modify-write operations. It is
70 * not thread safe as the resource is shared among multiple pins on a port.
71 *
72 * \note
73 * When EXT_CLK is source to HF0 and this API is called from application then
74 * make sure that the drivemode argument is CY_GPIO_DM_HIGHZ.
75 *
76 * \funcusage
77 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Pin_Init
78 *
79 *******************************************************************************/
Cy_GPIO_Pin_Init(GPIO_PRT_Type * base,uint32_t pinNum,const cy_stc_gpio_pin_config_t * config)80 cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const cy_stc_gpio_pin_config_t *config)
81 {
82 cy_en_gpio_status_t status = CY_GPIO_BAD_PARAM;
83
84 if ((NULL != base) && (NULL != config))
85 {
86 #if defined (CY_IP_MXS40IOSS)
87 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
88 cy_en_pra_pin_prot_type_t pinType;
89 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
90 uint32_t maskCfgOut;
91 #endif /* CY_IP_MXS40IOSS */
92 uint32_t tempReg, tempReg2;
93
94 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
95 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->outVal));
96 CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(config->driveMode));
97 CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(config->hsiom));
98 CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(config->intEdge));
99 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->intMask));
100 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtrip));
101
102 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vregEn));
103 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->ibufMode));
104 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtripSel));
105 CY_ASSERT_L2(CY_GPIO_IS_VREF_SEL_VALID(config->vrefSel));
106 CY_ASSERT_L2(CY_GPIO_IS_VOH_SEL_VALID(config->vohSel));
107 CY_ASSERT_L2(CY_GPIO_IS_DRIVE_SEL_VALID(config->driveSel));
108
109 #if defined (CY_IP_MXS22IOSS)
110 CY_ASSERT_L2(CY_GPIO_IS_PULLUP_RES_VALID(config->pullUpRes));
111 #endif /* CY_IP_MXS22IOSS */
112
113 /* Slew rate and Driver strength */
114 #if defined (CY_IP_MXS40IOSS)
115 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->slewRate));
116 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
117
118 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
119
120 if (pinType == CY_PRA_PIN_SECURE)
121 {
122 return(status); /* Protected pins are not allowed to configure */
123 }
124 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
125 maskCfgOut = (CY_GPIO_CFG_OUT_SLOW_MASK << pinNum)
126 | (CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << ((uint32_t)(pinNum << 1U) + CY_GPIO_CFG_OUT_DRIVE_OFFSET));
127
128 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
129 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
130 {
131 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT)) & ~(maskCfgOut);
132 }
133 else
134 {
135 tempReg = GPIO_PRT_CFG_OUT(base) & ~(maskCfgOut);
136 }
137 #else
138 tempReg = GPIO_PRT_CFG_OUT(base) & ~(maskCfgOut);
139 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
140
141 tempReg2 = tempReg | ((config->slewRate & CY_GPIO_CFG_OUT_SLOW_MASK) << pinNum)
142 | ((config->driveSel & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << ((uint32_t)(pinNum << 1U) + CY_GPIO_CFG_OUT_DRIVE_OFFSET));
143
144 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
145 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
146 {
147 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT), tempReg2);
148 }
149 else /* non-secure pin */
150 {
151 GPIO_PRT_CFG_OUT(base) = tempReg2;
152 }
153 #else
154 GPIO_PRT_CFG_OUT(base) = tempReg2;
155 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
156
157 #else
158 CY_ASSERT_L2(CY_GPIO_IS_SLEW_RATE_VALID(config->slewRate));
159 #if ((defined (IOSS_HSIOM_HSIOM_SEC_PORT_NR) && (IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0)) || (CPUSS_CM33_0_SECEXT_PRESENT != 0))
160 CY_ASSERT_L2(CY_GPIO_IS_HSIOM_SEC_VALID(config->nonSec));
161 Cy_GPIO_SetHSIOM_SecPin(base, pinNum, config->nonSec);
162 #endif /* IOSS_HSIOM_HSIOM_SEC_PORT_NR, CPUSS_CM33_0_SECEXT_PRESENT */
163 Cy_GPIO_SetSlewRate(base, pinNum, config->slewRate);
164 Cy_GPIO_SetDriveSel(base, pinNum, config->driveSel);
165 #endif /* CY_IP_MXS40IOSS */
166 Cy_GPIO_SetHSIOM(base, pinNum, config->hsiom);
167 Cy_GPIO_SetDrivemode(base, pinNum, config->driveMode);
168
169 Cy_GPIO_SetInterruptEdge(base, pinNum, config->intEdge);
170 Cy_GPIO_SetInterruptMask(base, pinNum, config->intMask);
171 Cy_GPIO_SetVtrip(base, pinNum, config->vtrip);
172
173 /* SIO specific configuration */
174 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
175 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
176 {
177 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO)) & ~(CY_GPIO_SIO_PIN_MASK);
178 }
179 else
180 {
181 tempReg = GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_SIO_PIN_MASK);
182 }
183 #else
184 tempReg = GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_SIO_PIN_MASK);
185 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
186
187 tempReg2 = tempReg | (((config->vregEn & CY_GPIO_VREG_EN_MASK)
188 | ((config->ibufMode & CY_GPIO_IBUF_MASK) << CY_GPIO_IBUF_SHIFT)
189 | ((config->vtripSel & CY_GPIO_VTRIP_SEL_MASK) << CY_GPIO_VTRIP_SEL_SHIFT)
190 | ((config->vrefSel & CY_GPIO_VREF_SEL_MASK) << CY_GPIO_VREF_SEL_SHIFT)
191 | ((config->vohSel & CY_GPIO_VOH_SEL_MASK) << CY_GPIO_VOH_SEL_SHIFT))
192 << ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET));
193
194 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
195 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
196 {
197 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), tempReg2);
198 }
199 else /* non-secure pin */
200 {
201 GPIO_PRT_CFG_SIO(base) = tempReg2;
202 }
203 #else
204 GPIO_PRT_CFG_SIO(base) = tempReg2;
205 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
206
207 #if defined (CY_IP_MXS22IOSS)
208 Cy_GPIO_SetPullupResistance(base, pinNum, config->pullUpRes);
209 #endif /* CY_IP_MXS22IOSS */
210
211 Cy_GPIO_Write(base, pinNum, config->outVal);
212
213 status = CY_GPIO_SUCCESS;
214 }
215
216 return(status);
217 }
218
219
220 /*******************************************************************************
221 * Function Name: Cy_GPIO_Port_Init
222 ****************************************************************************//**
223 *
224 * Initialize a complete port of pins from a single init structure.
225 *
226 * The configuration structure used in this function has a 1:1 mapping to the
227 * GPIO and HSIOM registers. Refer to the device Technical Reference Manual (TRM)
228 * for the register details on how to populate them.
229 *
230 * \param base
231 * Pointer to the pin's port register base address
232 *
233 * \param config
234 * Pointer to the pin config structure base address
235 *
236 * \return
237 * Initialization status
238 *
239 * \note
240 * If using the PSoC Creator IDE, there is no need to initialize the pins when
241 * using the GPIO component on the schematic. Ports are configured in
242 * Cy_SystemInit() before main() entry.
243 *
244 * \funcusage
245 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Port_Init
246 *
247 *******************************************************************************/
Cy_GPIO_Port_Init(GPIO_PRT_Type * base,const cy_stc_gpio_prt_config_t * config)248 cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt_config_t *config)
249 {
250 cy_en_gpio_status_t status = CY_GPIO_BAD_PARAM;
251
252 if ((NULL != base) && (NULL != config))
253 {
254 uint32_t portNum;
255 HSIOM_PRT_V1_Type* baseHSIOM;
256 #if (defined (CY_IP_MXS40SIOSS) && ((IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0) || (CPUSS_CM33_0_SECEXT_PRESENT != 0))) || defined (CY_IP_MXS22IOSS)
257 HSIOM_SECURE_PRT_Type *baseSecHSIOM;
258 #else
259 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
260 bool secPort;
261 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
262 #endif /* CY_IP_MXS40SIOSS, IOSS_HSIOM_HSIOM_SEC_PORT_NR, CPUSS_CM33_0_SECEXT_PRESENT, CY_IP_MXS22IOSS */
263 portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
264 baseHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
265
266 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
267 if (CY_GPIO_IS_SMIF_GPIO(base))
268 {
269 uint32_t smif_core_offset = ((void *)base >= (void *)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0) ? SMIF_CORE_SECTION_SIZE : 0U;
270 portNum = ((uint32_t)(base) - CY_SMIF_GPIO_BASE - smif_core_offset) / SMIF_CORE_SMIF_GPIO_SMIF_PRT_SECTION_SIZE;
271 baseHSIOM = (HSIOM_PRT_V1_Type*)(CY_SMIF_HSIOM_BASE + (SMIF_CORE_SMIF_HSIOM_SMIF_PRT_SECTION_SIZE * portNum) + smif_core_offset);
272 }
273 #endif
274
275 CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->out));
276 CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->cfgIn));
277 CY_ASSERT_L2(CY_GPIO_IS_INTR_CFG_VALID(config->intrCfg));
278 CY_ASSERT_L2(CY_GPIO_IS_INTR_MASK_VALID(config->intrMask));
279 CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel0Active));
280 CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel1Active));
281
282 #if defined (CY_IP_MXS22IOSS)
283 CY_ASSERT_L2(CY_GPIO_PRT_IS_PULLUP_RES_VALID(config->cfgRes));
284 #endif /* CY_IP_MXS22IOSS */
285
286 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS22IOSS)
287 #if ((defined (IOSS_HSIOM_HSIOM_SEC_PORT_NR) && (IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0)) || (CPUSS_CM33_0_SECEXT_PRESENT != 0))
288 CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->nonSecMask));
289
290 baseSecHSIOM = (HSIOM_SECURE_PRT_Type*)(CY_HSIOM_SECURE_BASE + (HSIOM_SECURE_PRT_SECTION_SIZE * portNum));
291
292 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
293 uint32_t smif_core_offset = ((void *)base >= (void *)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0) ? SMIF_CORE_SECTION_SIZE : 0U;
294 baseSecHSIOM = (HSIOM_SECURE_PRT_Type*)(CY_SMIF_SECURE_HSIOM_BASE + (SMIF_CORE_SMIF_HSIOM_SMIF_SECURE_PRT_SECTION_SIZE * portNum) + smif_core_offset);
295 #endif /* CY_IP_MXSMIF, CY_IP_MXSMIF_VERSION */
296 HSIOM_SEC_PRT_NONSEC_MASK(baseSecHSIOM) = config->nonSecMask;
297 #endif /* IOSS_HSIOM_HSIOM_SEC_PORT_NR, CPUSS_CM33_0_SECEXT_PRESENT */
298 GPIO_PRT_SLEW_EXT(base) = config->cfgSlew;
299 GPIO_PRT_DRIVE_EXT0(base) = config->cfgDriveSel0;
300 GPIO_PRT_DRIVE_EXT1(base) = config->cfgDriveSel1;
301 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
302
303 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
304 secPort = CY_PRA_IS_PORT_SECURE(base);
305 if (secPort)
306 {
307 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG), config->cfg);
308 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_IN), config->cfgIn);
309 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT), config->cfgOut);
310 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG), config->intrCfg);
311 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_MASK), config->intrMask);
312 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), config->cfgSIO);
313 CY_PRA_REG32_SET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0), config->sel0Active);
314 CY_PRA_REG32_SET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1), config->sel1Active);
315 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT), config->out);
316 }
317 else
318 {
319 GPIO_PRT_CFG(base) = config->cfg;
320 GPIO_PRT_CFG_IN(base) = config->cfgIn;
321 GPIO_PRT_CFG_OUT(base) = config->cfgOut;
322 GPIO_PRT_INTR_CFG(base) = config->intrCfg;
323 GPIO_PRT_INTR_MASK(base) = config->intrMask;
324 GPIO_PRT_CFG_SIO(base) = config->cfgSIO;
325 /* For 1M device check for secure HSIOM */
326 #if defined(CY_DEVICE_PSOC6ABLE2)
327 if (CY_PRA_IS_HSIOM_SECURE(base))
328 {
329 CY_PRA_REG32_SET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0), config->sel0Active);
330 CY_PRA_REG32_SET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1), config->sel1Active);
331 }
332 else
333 {
334 HSIOM_PRT_PORT_SEL0(baseHSIOM) = config->sel0Active;
335 HSIOM_PRT_PORT_SEL1(baseHSIOM) = config->sel1Active;
336 }
337 #else
338 HSIOM_PRT_PORT_SEL0(baseHSIOM) = config->sel0Active;
339 HSIOM_PRT_PORT_SEL1(baseHSIOM) = config->sel1Active;
340 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
341 GPIO_PRT_OUT(base) = config->out;
342 }
343 #else
344 GPIO_PRT_CFG(base) = config->cfg;
345 GPIO_PRT_CFG_IN(base) = config->cfgIn;
346 GPIO_PRT_CFG_OUT(base) = config->cfgOut;
347 GPIO_PRT_INTR_CFG(base) = config->intrCfg;
348 GPIO_PRT_INTR_MASK(base) = config->intrMask;
349 GPIO_PRT_CFG_SIO(base) = config->cfgSIO;
350 HSIOM_PRT_PORT_SEL0(baseHSIOM) = config->sel0Active;
351 HSIOM_PRT_PORT_SEL1(baseHSIOM) = config->sel1Active;
352 GPIO_PRT_OUT(base) = config->out;
353 #if defined (CY_IP_MXS22IOSS)
354 GPIO_PRT_CFG_OUT3(base) = config->cfgOut3;
355 GPIO_PRT_CFG_RES(base) = config->cfgRes;
356 #endif /* CY_IP_MXS22IOSS */
357 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
358
359 status = CY_GPIO_SUCCESS;
360 }
361
362 return (status);
363 }
364
365
366 /*******************************************************************************
367 * Function Name: Cy_GPIO_Pin_FastInit
368 ****************************************************************************//**
369 *
370 * Initialize the most common configuration settings for all pin types.
371 *
372 * These include, drive mode, initial output value, and HSIOM connection.
373 *
374 * \param base
375 * Pointer to the pin's port register base address
376 *
377 * \param pinNum
378 * Position of the pin bit-field within the port register
379 *
380 * \param driveMode
381 * Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros
382 *
383 * \param outVal
384 * Logic state of the output buffer driven to the pin (1 or 0)
385 *
386 * \param hsiom
387 * HSIOM input selection
388 *
389 * \note
390 * This function modifies port registers in read-modify-write operations. It is
391 * not thread safe as the resource is shared among multiple pins on a port.
392 * You can use the Cy_SysLib_EnterCriticalSection() and
393 * Cy_SysLib_ExitCriticalSection() functions to ensure that
394 * Cy_GPIO_Pin_FastInit() function execution is not interrupted.
395 *
396 * \note
397 * When EXT_CLK is source to HF0 and this API is called from application then
398 * make sure that the drivemode argument is CY_GPIO_DM_HIGHZ.
399 *
400 * \note
401 * This doesn't set pull-up resistance value. By default. the pull-up resistance
402 * is disabled. To select it, use Cy_GPIO_SetPullupResistance.
403 *
404 * \funcusage
405 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Pin_FastInit
406 *
407 *******************************************************************************/
Cy_GPIO_Pin_FastInit(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t driveMode,uint32_t outVal,en_hsiom_sel_t hsiom)408 void Cy_GPIO_Pin_FastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode,
409 uint32_t outVal, en_hsiom_sel_t hsiom)
410 {
411 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
412 cy_en_pra_pin_prot_type_t pinType;
413 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
414
415 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
416 CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(driveMode));
417 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(outVal));
418 CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(hsiom));
419
420 uint32_t tempReg;
421 #if defined (CY_IP_MXS22IOSS)
422 uint32_t tempRegCfg3;
423 #endif /* CY_IP_MXS22IOSS */
424
425 Cy_GPIO_SetHSIOM(base, pinNum, hsiom);
426
427 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
428 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
429
430 if (pinType != CY_PRA_PIN_SECURE)
431 {
432 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
433 {
434 #if defined(CY_DEVICE_PSOC6ABLE2)
435 tempReg = (CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT)) & ~(CY_GPIO_OUT_MASK << pinNum));
436 #else
437 tempReg = (GPIO_PRT_OUT(base) & ~(CY_GPIO_OUT_MASK << pinNum));
438 #endif
439 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT), (tempReg | ((outVal & CY_GPIO_OUT_MASK) << pinNum)));
440
441 #if defined(CY_DEVICE_PSOC6ABLE2)
442 tempReg = (CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG)) & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
443 #else
444 tempReg = (GPIO_PRT_CFG(base) & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
445 #endif
446 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG), (tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET))));
447 }
448 else /* non secure pin */
449 {
450 tempReg = (GPIO_PRT_OUT(base) & ~(CY_GPIO_OUT_MASK << pinNum));
451 GPIO_PRT_OUT(base) = tempReg | ((outVal & CY_GPIO_OUT_MASK) << pinNum);
452
453 tempReg = (GPIO_PRT_CFG(base) & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
454 GPIO_PRT_CFG(base) = tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
455 }
456 }
457 else
458 {
459 /* Secure PIN can't be modified using register policy */
460 }
461 #else
462 tempReg = (GPIO_PRT_OUT(base) & ~(CY_GPIO_OUT_MASK << pinNum));
463 GPIO_PRT_OUT(base) = tempReg | ((outVal & CY_GPIO_OUT_MASK) << pinNum);
464
465 tempReg = (GPIO_PRT_CFG(base) & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
466 #if defined (CY_IP_MXS22IOSS)
467 tempRegCfg3 = (GPIO_PRT_CFG_OUT3(base) & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
468
469 if(CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ == driveMode)
470 {
471 /* Enable CFG_OUT3 register and configure the extra drive mode with input buffer enabled. */
472 GPIO_PRT_CFG(base) = tempReg | (GPIO_PRT_CFG_IN_EN0_Msk << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
473 GPIO_PRT_CFG_OUT3(base) = tempRegCfg3 | (((driveMode >> CY_GPIO_EXT_DM_SHIFT) & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
474 }
475 else
476 {
477 /* If High-Z drive mode is selected, enable CFG_OUT3 register using CFG register and configure drive mode using CFG_OUT3 register. */
478 /* For other drive modes, disable CFG_OUT3 register and use CFG register to configure drive modes. */
479 GPIO_PRT_CFG(base) = tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
480 GPIO_PRT_CFG_OUT3(base) = tempRegCfg3 | ((0U & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
481 }
482 #else
483 GPIO_PRT_CFG(base) = tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
484 #endif /* CY_IP_MXS22IOSS */
485 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
486 }
487
488 #if (defined (CY_IP_MXS40SIOSS) && ((IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0) || (CPUSS_CM33_0_SECEXT_PRESENT != 0))) || defined (CY_IP_MXS22IOSS)
489 /*******************************************************************************
490 * Function Name: Cy_GPIO_Pin_SecFastInit
491 ****************************************************************************//**
492 *
493 * Initialize the most common configuration settings for all pin types.
494 *
495 * These include, drive mode, initial output value, and HSIOM connection. This
496 * function should be called from appropriate protection context where secure
497 * HSIOM port (HSIOM_SECURE_PRT_Type) is accessible.
498 *
499 * \param base
500 * Pointer to the pin's port register base address
501 *
502 * \param pinNum
503 * Position of the pin bit-field within the port register
504 *
505 * \param driveMode
506 * Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros
507 *
508 * \param outVal
509 * Logic state of the output buffer driven to the pin (1 or 0)
510 *
511 * \param hsiom
512 * HSIOM input selection
513 *
514 * \note
515 * This function modifies port registers in read-modify-write operations. It is
516 * not thread safe as the resource is shared among multiple pins on a port.
517 * You can use the Cy_SysLib_EnterCriticalSection() and
518 * Cy_SysLib_ExitCriticalSection() functions to ensure that
519 * Cy_GPIO_Pin_SecFastInit() function execution is not interrupted.
520 *
521 * \note
522 * This API is only available for the CAT1B and CAT1D devices. It should be
523 * accessed from secure domain only.
524 *
525 *******************************************************************************/
Cy_GPIO_Pin_SecFastInit(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t driveMode,uint32_t outVal,en_hsiom_sel_t hsiom)526 void Cy_GPIO_Pin_SecFastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode,
527 uint32_t outVal, en_hsiom_sel_t hsiom)
528 {
529 /* Restrict access to secure API. It should be accessed from secure domain only */
530 #if defined (CY_PDL_TZ_ENABLED)
531 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
532 CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(driveMode));
533 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(outVal));
534 CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(hsiom));
535
536 uint32_t tempReg;
537 #if defined (CY_IP_MXS22IOSS)
538 uint32_t tempRegCfg3;
539 #endif /* CY_IP_MXS22IOSS */
540
541 Cy_GPIO_SetHSIOM_SecPin(base, pinNum, 0UL); /* make the pin as secure */
542
543 Cy_GPIO_SetHSIOM(base, pinNum, hsiom);
544
545 tempReg = (GPIO_PRT_CFG(base) & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
546 #if defined (CY_IP_MXS22IOSS)
547 tempRegCfg3 = (GPIO_PRT_CFG_OUT3(base) & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
548
549 if(driveMode == CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ)
550 {
551 /* Enable CFG_OUT3 register and configure the extra drive mode. */
552 GPIO_PRT_CFG(base) = tempReg | ((0U & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
553 GPIO_PRT_CFG_OUT3(base) = tempRegCfg3 | (((driveMode >> CY_GPIO_EXT_DM_SHIFT) & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
554 }
555 else
556 {
557 /* If High-Z drive mode is selected, enable CFG_OUT3 register using CFG register and configure drive mode using CFG_OUT3 register. */
558 /* For other drive modes, disable CFG_OUT3 register and use CFG register to configure drive modes. */
559 GPIO_PRT_CFG(base) = tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
560 GPIO_PRT_CFG_OUT3(base) = tempRegCfg3 | ((0U & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
561 }
562 #else
563 GPIO_PRT_CFG(base) = tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
564 #endif /* CY_IP_MXS22IOSS */
565
566 tempReg = (GPIO_PRT_OUT(base) & ~(CY_GPIO_OUT_MASK << pinNum));
567 GPIO_PRT_OUT(base) = tempReg | ((outVal & CY_GPIO_OUT_MASK) << pinNum);
568 #else
569 /* Suppress a compiler warning about unused variables */
570 (void)base;
571 (void)pinNum;
572 (void)driveMode;
573 (void)outVal;
574 (void)hsiom;
575 #endif /* CY_PDL_TZ_ENABLED */
576 }
577 #endif /* CY_IP_MXS40SIOSS, IOSS_HSIOM_HSIOM_SEC_PORT_NR, CPUSS_CM33_0_SECEXT_PRESENT, CY_IP_MXS22IOSS */
578
579 /*******************************************************************************
580 * Function Name: Cy_GPIO_Port_Deinit
581 ****************************************************************************//**
582 *
583 * Reset a complete port of pins back to power on reset defaults.
584 *
585 * \param base
586 * Pointer to the pin's port register base address
587 *
588 * \funcusage
589 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Port_Deinit
590 *
591 *******************************************************************************/
Cy_GPIO_Port_Deinit(GPIO_PRT_Type * base)592 void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base)
593 {
594 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
595 bool secPort;
596 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
597 uint32_t portNum;
598 HSIOM_PRT_V1_Type* baseHSIOM;
599 portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
600 baseHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
601
602 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
603 if (CY_GPIO_IS_SMIF_GPIO(base))
604 {
605 uint32_t smif_core_offset = ((void *)base >= (void *)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0) ? SMIF_CORE_SECTION_SIZE : 0U;
606 portNum = ((uint32_t)(base) - CY_SMIF_GPIO_BASE - smif_core_offset) / SMIF_CORE_SMIF_GPIO_SMIF_PRT_SECTION_SIZE;
607 baseHSIOM = (HSIOM_PRT_V1_Type*)(CY_SMIF_HSIOM_BASE + (SMIF_CORE_SMIF_HSIOM_SMIF_PRT_SECTION_SIZE * portNum) + smif_core_offset);
608 }
609 #endif
610
611 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS22IOSS)
612 #if ((defined (IOSS_HSIOM_HSIOM_SEC_PORT_NR) && (IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0)) || (CPUSS_CM33_0_SECEXT_PRESENT != 0 ))
613 HSIOM_SECURE_PRT_Type *baseSecHSIOM;
614 baseSecHSIOM = (HSIOM_SECURE_PRT_Type*)(CY_HSIOM_SECURE_BASE + (HSIOM_SECURE_PRT_SECTION_SIZE * portNum));
615 HSIOM_SEC_PRT_NONSEC_MASK(baseSecHSIOM) = CY_HSIOM_NONSEC_DEINIT;
616 #endif /* IOSS_HSIOM_HSIOM_SEC_PORT_NR, CPUSS_CM33_0_SECEXT_PRESENT */
617 GPIO_PRT_SLEW_EXT(base) = CY_GPIO_PRT_DEINIT;
618 GPIO_PRT_DRIVE_EXT0(base) = CY_GPIO_PRT_DEINIT;
619 GPIO_PRT_DRIVE_EXT1(base) = CY_GPIO_PRT_DEINIT;
620 #endif /* CY_IP_MXS40SIOSS */
621
622 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
623 secPort = CY_PRA_IS_PORT_SECURE(base);
624 if (secPort)
625 {
626 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT), CY_GPIO_PRT_DEINIT);
627 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG), CY_GPIO_PRT_DEINIT);
628 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_IN), CY_GPIO_PRT_DEINIT);
629 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT), CY_GPIO_PRT_DEINIT);
630 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG), CY_GPIO_PRT_DEINIT);
631 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_MASK), CY_GPIO_PRT_DEINIT);
632 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), CY_GPIO_PRT_DEINIT);
633 CY_PRA_REG32_SET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0), CY_GPIO_PRT_DEINIT);
634 CY_PRA_REG32_SET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1), CY_GPIO_PRT_DEINIT);
635
636 }
637 else
638 {
639 GPIO_PRT_OUT(base) = CY_GPIO_PRT_DEINIT;
640 GPIO_PRT_CFG(base) = CY_GPIO_PRT_DEINIT;
641 GPIO_PRT_CFG_IN(base) = CY_GPIO_PRT_DEINIT;
642 GPIO_PRT_CFG_OUT(base) = CY_GPIO_PRT_DEINIT;
643 GPIO_PRT_INTR_CFG(base) = CY_GPIO_PRT_DEINIT;
644 GPIO_PRT_INTR_MASK(base) = CY_GPIO_PRT_DEINIT;
645 GPIO_PRT_CFG_SIO(base) = CY_GPIO_PRT_DEINIT;
646 /* For 1M device check for secure HSIOM */
647 #if defined(CY_DEVICE_PSOC6ABLE2)
648 if (CY_PRA_IS_HSIOM_SECURE(base))
649 {
650 CY_PRA_REG32_SET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0), CY_GPIO_PRT_DEINIT);
651 CY_PRA_REG32_SET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1), CY_GPIO_PRT_DEINIT);
652 }
653 else
654 {
655 HSIOM_PRT_PORT_SEL0(baseHSIOM) = CY_GPIO_PRT_DEINIT;
656 HSIOM_PRT_PORT_SEL1(baseHSIOM) = CY_GPIO_PRT_DEINIT;
657 }
658 #else
659 HSIOM_PRT_PORT_SEL0(baseHSIOM) = CY_GPIO_PRT_DEINIT;
660 HSIOM_PRT_PORT_SEL1(baseHSIOM) = CY_GPIO_PRT_DEINIT;
661 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
662 }
663 #else
664 GPIO_PRT_OUT(base) = CY_GPIO_PRT_DEINIT;
665 GPIO_PRT_CFG(base) = CY_GPIO_PRT_DEINIT;
666 GPIO_PRT_CFG_IN(base) = CY_GPIO_PRT_DEINIT;
667 GPIO_PRT_CFG_OUT(base) = CY_GPIO_PRT_DEINIT;
668 GPIO_PRT_INTR_CFG(base) = CY_GPIO_PRT_DEINIT;
669 GPIO_PRT_INTR_MASK(base) = CY_GPIO_PRT_DEINIT;
670 GPIO_PRT_CFG_SIO(base) = CY_GPIO_PRT_DEINIT;
671 HSIOM_PRT_PORT_SEL0(baseHSIOM) = CY_GPIO_PRT_DEINIT;
672 HSIOM_PRT_PORT_SEL1(baseHSIOM) = CY_GPIO_PRT_DEINIT;
673 #if defined (CY_IP_MXS22IOSS)
674 GPIO_PRT_CFG_OUT3(base) = CY_GPIO_PRT_DEINIT;
675 GPIO_PRT_CFG_RES(base) = CY_GPIO_PRT_DEINIT;
676 #endif /* CY_IP_MXS22IOSS */
677 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
678 }
679
680
681 /*******************************************************************************
682 * Function Name: Cy_GPIO_SetAmuxSplit
683 ****************************************************************************//**
684 *
685 * Configure a specific AMux bus splitter switch cell into a specific
686 * configuration.
687 *
688 * \param switchCtrl
689 * Selects specific AMux bus splitter cell between two segments.
690 * The cy_en_amux_split_t enumeration can be found in the GPIO header file
691 * for the device package.
692 *
693 * \param amuxConnect
694 * Selects configuration of the three switches within the splitter cell
695 *
696 * \param amuxBus
697 * Selects which AMux bus within the splitter is being configured
698 *
699 * \note
700 * This API is available for the CAT1A and CAT1D devices.
701 *
702 *******************************************************************************/
Cy_GPIO_SetAmuxSplit(cy_en_amux_split_t switchCtrl,cy_en_gpio_amuxconnect_t amuxConnect,cy_en_gpio_amuxselect_t amuxBus)703 void Cy_GPIO_SetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxconnect_t amuxConnect,
704 cy_en_gpio_amuxselect_t amuxBus)
705 {
706 #if defined (CY_IP_MXS40IOSS) || defined (CY_IP_MXS22IOSS)
707 CY_ASSERT_L2(CY_GPIO_IS_AMUX_SPLIT_VALID(switchCtrl));
708 CY_ASSERT_L3(CY_GPIO_IS_AMUX_CONNECT_VALID(amuxConnect));
709 CY_ASSERT_L3(CY_GPIO_IS_AMUX_SELECT_VALID(amuxBus));
710
711 uint32_t tmpReg;
712
713 if (amuxBus != CY_GPIO_AMUXBUSB)
714 {
715 tmpReg = HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXB_SPLITTER_MASK;
716 HSIOM_AMUX_SPLIT_CTL(switchCtrl) = tmpReg | ((uint32_t) amuxConnect & GPIO_AMUXA_SPLITTER_MASK);
717 }
718 else
719 {
720 tmpReg = HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXA_SPLITTER_MASK;
721 HSIOM_AMUX_SPLIT_CTL(switchCtrl) =
722 tmpReg | (((uint32_t) amuxConnect << HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos) & GPIO_AMUXB_SPLITTER_MASK);
723 }
724 #else
725 (void) switchCtrl;
726 (void) amuxConnect;
727 (void) amuxBus;
728
729 CY_ASSERT_L2(1);
730 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
731 }
732
733
734 /*******************************************************************************
735 * Function Name: Cy_GPIO_GetAmuxSplit
736 ****************************************************************************//**
737 *
738 * Returns the configuration of a specific AMux bus splitter switch cell.
739 *
740 * \param switchCtrl
741 * Selects specific AMux bus splitter cell between two segments.
742 * The cy_en_amux_split_t enumeration can be found in the GPIO header file
743 * for the device package.
744 *
745 * \param amuxBus
746 * Selects which AMux bus within the splitter is being configured
747 *
748 * \return
749 * Returns configuration of the three switches in the selected splitter cell
750 *
751 * \note
752 * This API is available for the CAT1A and CAT1D devices.
753 *
754 *******************************************************************************/
Cy_GPIO_GetAmuxSplit(cy_en_amux_split_t switchCtrl,cy_en_gpio_amuxselect_t amuxBus)755 cy_en_gpio_amuxconnect_t Cy_GPIO_GetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxselect_t amuxBus)
756 {
757 #if defined (CY_IP_MXS40IOSS) || defined (CY_IP_MXS22IOSS)
758 CY_ASSERT_L2(CY_GPIO_IS_AMUX_SPLIT_VALID(switchCtrl));
759 CY_ASSERT_L3(CY_GPIO_IS_AMUX_SELECT_VALID(amuxBus));
760
761 uint32_t retVal;
762
763 if (amuxBus != CY_GPIO_AMUXBUSB)
764 {
765 retVal = HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXA_SPLITTER_MASK;
766 }
767 else
768 {
769 retVal = ((uint32_t) ((HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXB_SPLITTER_MASK)
770 >> HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos));
771 }
772
773 return ((cy_en_gpio_amuxconnect_t) retVal);
774 #else
775 CY_ASSERT_L2(1);
776
777 (void) switchCtrl;
778 (void) amuxBus;
779
780 return ((cy_en_gpio_amuxconnect_t) CY_GPIO_AMUX_GLR);
781 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
782 }
783
784
785 /*******************************************************************************
786 * Function Name: Cy_GPIO_SetHSIOM
787 ****************************************************************************//**
788 *
789 * Configures the HSIOM connection to the pin.
790 *
791 * Connects the specified High-Speed Input Output Multiplexer (HSIOM) selection
792 * to the pin.
793 *
794 * \param base
795 * Pointer to the pin's port register base address
796 *
797 * \param pinNum
798 * Position of the pin bit-field within the port register
799 *
800 * \param value
801 * HSIOM input selection
802 *
803 * \note
804 * This function modifies a port register in a read-modify-write operation. It is
805 * not thread safe as the resource is shared among multiple pins on a port.
806 *
807 * \funcusage
808 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetHSIOM
809 *
810 *******************************************************************************/
Cy_GPIO_SetHSIOM(GPIO_PRT_Type * base,uint32_t pinNum,en_hsiom_sel_t value)811 void Cy_GPIO_SetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum, en_hsiom_sel_t value)
812 {
813 uint32_t portNum;
814 uint32_t tempReg;
815 uint32_t hsiomReg;
816 HSIOM_PRT_V1_Type* portAddrHSIOM;
817
818 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
819 cy_en_pra_pin_prot_type_t pinType;
820 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
821
822 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
823 CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(value));
824
825 portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
826 portAddrHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
827
828 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
829 if ((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) || (base == (GPIO_PRT_Type*)((void*)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0)))
830 {
831 portAddrHSIOM = (HSIOM_PRT_V1_Type*) ((void*)((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) ? ((void*)SMIF0_CORE0_SMIF_HSIOM_SMIF_PRT0) : ((void*)SMIF0_CORE1_SMIF_HSIOM_SMIF_PRT0)));
832 }
833 #endif
834
835 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
836 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
837 #endif
838
839 if(pinNum < CY_GPIO_PRT_HALF)
840 {
841 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
842 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
843 {
844 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0)) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
845 }
846 else if (pinType == CY_PRA_PIN_SECURE_NONE)
847 {
848 /* For 1M device check for secure HSIOM */
849 if (CY_PRA_IS_HSIOM_SECURE(base))
850 {
851 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0)) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
852 }
853 else
854 {
855 tempReg = HSIOM_PRT_PORT_SEL0(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
856 }
857 }
858 else
859 {
860 /* secure pin */
861 tempReg = 0UL;
862 }
863 #else
864 tempReg = HSIOM_PRT_PORT_SEL0(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
865 #endif
866 hsiomReg = tempReg | (((uint32_t)value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET));
867
868 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
869 if (pinType != CY_PRA_PIN_SECURE)
870 {
871 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
872 {
873 CY_PRA_REG32_SET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0), hsiomReg);
874 }
875 else
876 {
877 /* For 1M device check for secure HSIOM */
878 #if defined(CY_DEVICE_PSOC6ABLE2)
879 if (CY_PRA_IS_HSIOM_SECURE(base))
880 {
881 CY_PRA_REG32_SET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0), hsiomReg);
882 }
883 else
884 {
885 HSIOM_PRT_PORT_SEL0(portAddrHSIOM) = hsiomReg;
886 }
887 #else
888 HSIOM_PRT_PORT_SEL0(portAddrHSIOM) = hsiomReg;
889 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
890 }
891 }
892 else
893 {
894 /* Secure PIN can't be modified using register policy */
895 }
896 #else
897 HSIOM_PRT_PORT_SEL0(portAddrHSIOM) = hsiomReg;
898 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
899 }
900 else
901 {
902 pinNum -= CY_GPIO_PRT_HALF;
903
904 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
905 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
906 {
907 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1)) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
908 }
909 else if (pinType == CY_PRA_PIN_SECURE_NONE)
910 {
911 /* For 1M device check for secure HSIOM */
912 if (CY_PRA_IS_HSIOM_SECURE(base))
913 {
914 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1)) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
915 }
916 else
917 {
918 tempReg = HSIOM_PRT_PORT_SEL1(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
919 }
920
921 }
922 else
923 {
924 tempReg = 0UL;
925 }
926 #else
927 tempReg = HSIOM_PRT_PORT_SEL1(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
928 #endif
929
930 hsiomReg = tempReg | (((uint32_t)value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET));
931 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
932
933 if (pinType != CY_PRA_PIN_SECURE)
934 {
935 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
936 {
937 CY_PRA_REG32_SET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1), hsiomReg);
938 }
939 else
940 {
941 /* For 1M device check for secure HSIOM */
942 #if defined(CY_DEVICE_PSOC6ABLE2)
943 if (CY_PRA_IS_HSIOM_SECURE(base))
944 {
945 CY_PRA_REG32_SET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1), hsiomReg);
946 }
947 else
948 {
949 HSIOM_PRT_PORT_SEL1(portAddrHSIOM) = hsiomReg;
950 }
951 #else
952 HSIOM_PRT_PORT_SEL1(portAddrHSIOM) = hsiomReg;
953 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
954 }
955 }
956 else
957 {
958 /* Secure PIN can't be modified using register policy */
959 }
960 #else
961 HSIOM_PRT_PORT_SEL1(portAddrHSIOM) = hsiomReg;
962 #endif
963 }
964 }
965
966
967 /*******************************************************************************
968 * Function Name: Cy_GPIO_GetHSIOM
969 ****************************************************************************//**
970 *
971 * Returns the current HSIOM multiplexer connection to the pin.
972 *
973 * \param base
974 * Pointer to the pin's port register base address
975 *
976 * \param pinNum
977 * Position of the pin bit-field within the port register
978 *
979 * \return
980 * HSIOM input selection
981 *
982 * \funcusage
983 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetHSIOM
984 *
985 *******************************************************************************/
Cy_GPIO_GetHSIOM(GPIO_PRT_Type * base,uint32_t pinNum)986 en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum)
987 {
988 uint32_t returnValue;
989 uint32_t tempReg;
990 uint32_t portNum;
991 HSIOM_PRT_V1_Type* portAddrHSIOM;
992 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
993 cy_en_pra_pin_prot_type_t pinType;
994 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
995
996 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
997
998 portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
999 portAddrHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
1000
1001 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
1002 if ((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) || (base == (GPIO_PRT_Type*)((void*)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0)))
1003 {
1004 portAddrHSIOM = (HSIOM_PRT_V1_Type*) ((void*)((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) ? ((void*)SMIF0_CORE0_SMIF_HSIOM_SMIF_PRT0) : ((void*)SMIF0_CORE1_SMIF_HSIOM_SMIF_PRT0)));
1005 }
1006 #endif
1007
1008 if(pinNum < CY_GPIO_PRT_HALF)
1009 {
1010 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1011 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1012 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1013 {
1014 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0));
1015 }
1016 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1017 {
1018 /* For 1M device check for secure HSIOM */
1019 if (CY_PRA_IS_HSIOM_SECURE(base))
1020 {
1021 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0));
1022 }
1023 else
1024 {
1025 tempReg = HSIOM_PRT_PORT_SEL0(portAddrHSIOM);
1026 }
1027 }
1028 else
1029 {
1030 /* secure pin */
1031 tempReg = 0UL;
1032 }
1033 #else
1034 tempReg = HSIOM_PRT_PORT_SEL0(portAddrHSIOM);
1035 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1036
1037 returnValue = (tempReg >> (pinNum << CY_GPIO_HSIOM_OFFSET)) & CY_GPIO_HSIOM_MASK;
1038 }
1039 else
1040 {
1041 pinNum -= CY_GPIO_PRT_HALF;
1042
1043 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1044 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, (pinNum + CY_GPIO_PRT_HALF));
1045 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1046 {
1047 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1));
1048 }
1049 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1050 {
1051 /* For 1M device check for secure HSIOM */
1052 if (CY_PRA_IS_HSIOM_SECURE(base))
1053 {
1054 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1));
1055 }
1056 else
1057 {
1058 tempReg = HSIOM_PRT_PORT_SEL1(portAddrHSIOM);
1059 }
1060 }
1061 else
1062 {
1063 /* secure pin */
1064 tempReg = 0UL;
1065 }
1066 #else
1067 tempReg = HSIOM_PRT_PORT_SEL1(portAddrHSIOM);
1068 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1069
1070 returnValue = (tempReg >> (pinNum << CY_GPIO_HSIOM_OFFSET)) & CY_GPIO_HSIOM_MASK;
1071 }
1072
1073 return (en_hsiom_sel_t)returnValue;
1074 }
1075
1076
1077 /*******************************************************************************
1078 * Function Name: Cy_GPIO_Read
1079 ****************************************************************************//**
1080 *
1081 * Reads the current logic level on the input buffer of the pin.
1082 *
1083 * \param base
1084 * Pointer to the pin's port register base address
1085 *
1086 * \param pinNum
1087 * Position of the pin bit-field within the port register.
1088 * Bit position 8 is the routed pin through the port glitch filter.
1089 *
1090 * \return
1091 * Logic level present on the pin
1092 *
1093 * \funcusage
1094 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Read
1095 *
1096 *******************************************************************************/
Cy_GPIO_Read(GPIO_PRT_Type * base,uint32_t pinNum)1097 uint32_t Cy_GPIO_Read(GPIO_PRT_Type* base, uint32_t pinNum)
1098 {
1099 uint32_t tempReg;
1100 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1101 cy_en_pra_pin_prot_type_t pinType;
1102 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1103
1104 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
1105
1106 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1107 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1108 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1109 {
1110 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_IN));
1111 }
1112 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1113 {
1114 tempReg = GPIO_PRT_IN(base);
1115 }
1116 else
1117 {
1118 /* secure pin */
1119 tempReg = 0UL;
1120 }
1121 #else
1122 tempReg = GPIO_PRT_IN(base);
1123 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1124
1125 return (tempReg >> (pinNum)) & CY_GPIO_IN_MASK;
1126 }
1127
1128
1129 /*******************************************************************************
1130 * Function Name: Cy_GPIO_Write
1131 ****************************************************************************//**
1132 *
1133 * Write a logic 0 or logic 1 state to the output driver.
1134 *
1135 * This function should be used only for software driven pins. It does not have
1136 * any effect on peripheral driven pins.
1137 *
1138 * \param base
1139 * Pointer to the pin's port register base address
1140 *
1141 * \param pinNum
1142 * Position of the pin bit-field within the port register
1143 *
1144 * \param value
1145 * Logic level to drive out on the pin
1146 *
1147 * \funcusage
1148 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Write
1149 *
1150 *******************************************************************************/
Cy_GPIO_Write(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)1151 void Cy_GPIO_Write(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
1152 {
1153 uint32_t outMask;
1154
1155 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1156 cy_en_pra_pin_prot_type_t pinType;
1157 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1158
1159 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1160 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
1161
1162 outMask = CY_GPIO_OUT_MASK << pinNum;
1163
1164 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1165
1166 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1167
1168 if (pinType != CY_PRA_PIN_SECURE)
1169 {
1170 if(0UL == value)
1171 {
1172 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1173 {
1174 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT_CLR), outMask);
1175 }
1176 else /* non-secure pin */
1177 {
1178 GPIO_PRT_OUT_CLR(base) = outMask;
1179 }
1180 }
1181 else
1182 {
1183 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1184 {
1185 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT_SET), outMask);
1186 }
1187 else
1188 {
1189 GPIO_PRT_OUT_SET(base) = outMask;
1190 }
1191 }
1192 }
1193 else
1194 {
1195 /* Secure PIN can't be modified using register policy */
1196 }
1197 #else
1198 /* Thread-safe: Directly access the pin registers instead of base->OUT */
1199 if(0UL == value)
1200 {
1201 GPIO_PRT_OUT_CLR(base) = outMask;
1202 }
1203 else
1204 {
1205 GPIO_PRT_OUT_SET(base) = outMask;
1206 }
1207 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1208 }
1209
1210
1211 /*******************************************************************************
1212 * Function Name: Cy_GPIO_ReadOut
1213 ****************************************************************************//**
1214 *
1215 * Reads the current logic level on the pin output driver.
1216 *
1217 * \param base
1218 * Pointer to the pin's port register base address
1219 *
1220 * \param pinNum
1221 * Position of the pin bit-field within the port register
1222 *
1223 * \return
1224 * Logic level on the pin output driver
1225 *
1226 * \funcusage
1227 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_ReadOut
1228 *
1229 *******************************************************************************/
Cy_GPIO_ReadOut(GPIO_PRT_Type * base,uint32_t pinNum)1230 uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type* base, uint32_t pinNum)
1231 {
1232 uint32_t tempReg;
1233 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1234 cy_en_pra_pin_prot_type_t pinType;
1235 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1236
1237 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1238
1239 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1240 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1241 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1242 {
1243 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT));
1244 }
1245 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1246 {
1247 tempReg = GPIO_PRT_OUT(base);
1248 }
1249 else
1250 {
1251 /* secure pin */
1252 tempReg = 0UL;
1253 }
1254 #else
1255 tempReg = GPIO_PRT_OUT(base);
1256 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1257
1258 return (tempReg >> pinNum) & CY_GPIO_OUT_MASK;
1259 }
1260
1261
1262 /*******************************************************************************
1263 * Function Name: Cy_GPIO_Set
1264 ****************************************************************************//**
1265 *
1266 * Set a pin output to logic state high.
1267 *
1268 * This function should be used only for software driven pins. It does not have
1269 * any effect on peripheral driven pins.
1270 *
1271 * \param base
1272 * Pointer to the pin's port register base address
1273 *
1274 * \param pinNum
1275 * Position of the pin bit-field within the port register
1276 *
1277 * \funcusage
1278 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Set
1279 *
1280 *******************************************************************************/
Cy_GPIO_Set(GPIO_PRT_Type * base,uint32_t pinNum)1281 void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum)
1282 {
1283 uint32_t outMask;
1284
1285 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1286 cy_en_pra_pin_prot_type_t pinType;
1287 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1288
1289 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1290
1291 outMask = CY_GPIO_OUT_MASK << pinNum;
1292
1293 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1294 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1295
1296 if (pinType != CY_PRA_PIN_SECURE)
1297 {
1298 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1299 {
1300 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT_SET), outMask);
1301 }
1302 else
1303 {
1304 GPIO_PRT_OUT_SET(base) = outMask;
1305 }
1306 }
1307 else
1308 {
1309 /* Secure PIN can't be modified using register policy */
1310 }
1311 #else
1312 GPIO_PRT_OUT_SET(base) = outMask;
1313 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1314 }
1315
1316
1317 /*******************************************************************************
1318 * Function Name: Cy_GPIO_Clr
1319 ****************************************************************************//**
1320 *
1321 * Set a pin output to logic state Low.
1322 *
1323 * This function should be used only for software driven pins. It does not have
1324 * any effect on peripheral driven pins.
1325 *
1326 * \param base
1327 * Pointer to the pin's port register base address
1328 *
1329 * \param pinNum
1330 * Position of the pin bit-field within the port register
1331 *
1332 * \funcusage
1333 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Clr
1334 *
1335 *******************************************************************************/
Cy_GPIO_Clr(GPIO_PRT_Type * base,uint32_t pinNum)1336 void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum)
1337 {
1338 uint32_t outMask;
1339
1340 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1341 cy_en_pra_pin_prot_type_t pinType;
1342 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1343
1344 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1345
1346 outMask = CY_GPIO_OUT_MASK << pinNum;
1347
1348 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1349 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1350
1351 if (pinType != CY_PRA_PIN_SECURE)
1352 {
1353 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1354 {
1355 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT_CLR), outMask);
1356 }
1357 else
1358 {
1359 GPIO_PRT_OUT_CLR(base) = outMask;
1360 }
1361 }
1362 else
1363 {
1364 /* Secure PIN can't be modified using register policy */
1365 }
1366 #else
1367 GPIO_PRT_OUT_CLR(base) = outMask;
1368 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1369 }
1370
1371
1372 /*******************************************************************************
1373 * Function Name: Cy_GPIO_Inv
1374 ****************************************************************************//**
1375 *
1376 * Set a pin output logic state to the inverse of the current output
1377 * logic state.
1378 *
1379 * This function should be used only for software driven pins. It does not have
1380 * any effect on peripheral driven pins.
1381 *
1382 * \param base
1383 * Pointer to the pin's port register base address
1384 *
1385 * \param pinNum
1386 * Position of the pin bit-field within the port register
1387 *
1388 * \funcusage
1389 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Inv
1390 *
1391 *******************************************************************************/
Cy_GPIO_Inv(GPIO_PRT_Type * base,uint32_t pinNum)1392 void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum)
1393 {
1394 uint32_t outMask;
1395
1396 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1397 cy_en_pra_pin_prot_type_t pinType;
1398 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1399
1400 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1401
1402 outMask = CY_GPIO_OUT_MASK << pinNum;
1403
1404 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1405 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1406
1407 if (pinType != CY_PRA_PIN_SECURE)
1408 {
1409 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1410 {
1411 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT_INV), outMask);
1412 }
1413 else
1414 {
1415 GPIO_PRT_OUT_INV(base) = outMask;
1416 }
1417 }
1418 else
1419 {
1420 /* Secure PIN can't be modified using register policy */
1421 }
1422 #else
1423 GPIO_PRT_OUT_INV(base) = outMask;
1424 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1425 }
1426
1427
1428 /*******************************************************************************
1429 * Function Name: Cy_GPIO_SetDrivemode
1430 ****************************************************************************//**
1431 *
1432 * Configures the pin output buffer drive mode and input buffer enable.
1433 *
1434 * The output buffer drive mode and input buffer enable are combined into a single
1435 * parameter. The drive mode controls the behavior of the pin in general.
1436 * Enabling the input buffer allows the digital pin state to be read but also
1437 * contributes to extra current consumption.
1438 *
1439 * \param base
1440 * Pointer to the pin's port register base address
1441 *
1442 * \param pinNum
1443 * Position of the pin bit-field within the port register
1444 *
1445 * \param value
1446 * Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros
1447 *
1448 * \note
1449 * This function modifies a port register in a read-modify-write operation. It is
1450 * not thread safe as the resource is shared among multiple pins on a port.
1451 *
1452 * \funcusage
1453 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetDrivemode
1454 *
1455 *******************************************************************************/
Cy_GPIO_SetDrivemode(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)1456 void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
1457 {
1458 uint32_t tempReg;
1459 uint32_t pinLoc;
1460 uint32_t prtCfg;
1461 #if defined (CY_IP_MXS22IOSS)
1462 uint32_t prtCfg3;
1463 uint32_t tempRegCfg3;
1464 #endif /* CY_IP_MXS22IOSS */
1465 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1466 cy_en_pra_pin_prot_type_t pinType;
1467 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1468
1469 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1470 CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(value));
1471
1472 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1473 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1474 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1475
1476 pinLoc = pinNum << CY_GPIO_DRIVE_MODE_OFFSET;
1477
1478 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1479 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1480 {
1481 tempReg = (CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG)) & ~(CY_GPIO_CFG_DM_MASK << pinLoc));
1482 }
1483 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1484 {
1485 tempReg = (GPIO_PRT_CFG(base) & ~(CY_GPIO_CFG_DM_MASK << pinLoc));
1486 }
1487 else
1488 {
1489 /* secure pin */
1490 tempReg = 0;
1491 }
1492 #else
1493 tempReg = (GPIO_PRT_CFG(base) & ~(CY_GPIO_CFG_DM_MASK << pinLoc));
1494 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1495
1496 #if defined (CY_IP_MXS22IOSS)
1497 tempRegCfg3 = (GPIO_PRT_CFG_OUT3(base) & ~(CY_GPIO_CFG_DM_MASK << pinLoc));
1498 if(CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ == value)
1499 {
1500 prtCfg = tempReg & (~(CY_GPIO_CFG_DM_WIDTH_MASK << pinLoc));
1501 prtCfg |= (GPIO_PRT_CFG_IN_EN0_Msk << pinLoc);
1502 prtCfg3 = tempRegCfg3 | ((value >> CY_GPIO_EXT_DM_SHIFT) << pinLoc);
1503 }
1504 else
1505 {
1506 prtCfg = tempReg | ((value & CY_GPIO_CFG_DM_MASK) << pinLoc);
1507 prtCfg3 = tempRegCfg3 & (~(CY_GPIO_CFG_DM_WIDTH_MASK << pinLoc));
1508 }
1509 #else
1510 prtCfg = tempReg | ((value & CY_GPIO_CFG_DM_MASK) << pinLoc);
1511 #endif /* CY_IP_MXS22IOSS */
1512
1513 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1514 if (pinType != CY_PRA_PIN_SECURE)
1515 {
1516 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1517 {
1518 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG), prtCfg);
1519 }
1520 else
1521 {
1522 GPIO_PRT_CFG(base) = prtCfg;
1523 }
1524 }
1525 else
1526 {
1527 /* Secure PIN can't be modified using register policy */
1528 }
1529 #else
1530 GPIO_PRT_CFG(base) = prtCfg;
1531 #if defined (CY_IP_MXS22IOSS)
1532 GPIO_PRT_CFG_OUT3(base) = prtCfg3;
1533 #endif /* CY_IP_MXS22IOSS */
1534 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1535 }
1536
1537
1538 /*******************************************************************************
1539 * Function Name: Cy_GPIO_GetDrivemode
1540 ****************************************************************************//**
1541 *
1542 * Returns the pin output buffer drive mode and input buffer enable state.
1543 *
1544 * \param base
1545 * Pointer to the pin's port register base address
1546 *
1547 * \param pinNum
1548 * Position of the pin bit-field within the port register
1549 *
1550 * \return
1551 * Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros
1552 *
1553 * \funcusage
1554 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetDrivemode
1555 *
1556 *******************************************************************************/
Cy_GPIO_GetDrivemode(GPIO_PRT_Type * base,uint32_t pinNum)1557 uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum)
1558 {
1559 uint32_t tempReg, ret;
1560 #if defined (CY_IP_MXS22IOSS)
1561 uint32_t tempRegCfg3;
1562 #endif /* CY_IP_MXS22IOSS */
1563 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1564 cy_en_pra_pin_prot_type_t pinType;
1565 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1566
1567 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1568
1569 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1570 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1571 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1572 {
1573 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG));
1574 }
1575 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1576 {
1577 tempReg = GPIO_PRT_CFG(base);
1578 }
1579 else
1580 {
1581 /* secure pin */
1582 tempReg = 0UL;
1583 }
1584 #else
1585 tempReg = GPIO_PRT_CFG(base);
1586 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1587
1588 #if defined (CY_IP_MXS22IOSS)
1589 /* Check drive mode value in CFG_OUT register to check if CFG_OUT3 is enabled */
1590 if((((tempReg >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_CFG_DM_MASK) & CY_GPIO_CFG_DM_NO_INBUF_MASK) == 0U)
1591 {
1592 tempRegCfg3 = GPIO_PRT_CFG_OUT3(base);
1593 /* Check driver mode value in CFG_OUT3 register to check if it is set to CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ */
1594 if(((tempRegCfg3 >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_CFG_DM_WIDTH_MASK) == (CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ >> CY_GPIO_EXT_DM_SHIFT))
1595 {
1596 ret = CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ;
1597 }
1598 else
1599 {
1600 ret = (tempReg >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_CFG_DM_MASK;
1601 }
1602 }
1603 else
1604 {
1605 ret = (tempReg >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_CFG_DM_MASK;
1606 }
1607 #else
1608 ret = (tempReg >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_CFG_DM_MASK;
1609 #endif /* CY_IP_MXS22IOSS */
1610
1611 return ret;
1612 }
1613
1614
1615 /*******************************************************************************
1616 * Function Name: Cy_GPIO_SetVtrip
1617 ****************************************************************************//**
1618 *
1619 * Configures the GPIO pin input buffer voltage threshold mode.
1620 *
1621 * \param base
1622 * Pointer to the pin's port register base address
1623 *
1624 * \param pinNum
1625 * Position of the pin bit-field within the port register
1626 *
1627 * \param value
1628 * Pin voltage threshold mode. Options are detailed in \ref group_gpio_vtrip macros
1629 *
1630 * \note
1631 * This function modifies a port register in a read-modify-write operation. It is
1632 * not thread safe as the resource is shared among multiple pins on a port.
1633 *
1634 * \funcusage
1635 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVtrip
1636 *
1637 *******************************************************************************/
Cy_GPIO_SetVtrip(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)1638 void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
1639 {
1640 uint32_t tempReg;
1641 uint32_t cfgIn;
1642
1643 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1644 cy_en_pra_pin_prot_type_t pinType;
1645 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1646
1647 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1648 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
1649
1650 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1651 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1652
1653 #if defined(CY_DEVICE_PSOC6ABLE2)
1654 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1655 {
1656 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_IN)) & ~(CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK << pinNum);
1657 }
1658 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1659 {
1660 tempReg = GPIO_PRT_CFG_IN(base) & ~(CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK << pinNum);
1661 }
1662 else
1663 {
1664 /* secure pin */
1665 tempReg = 0UL;
1666 }
1667 #else
1668 tempReg = GPIO_PRT_CFG_IN(base) & ~(CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK << pinNum);
1669 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
1670 #else
1671 tempReg = GPIO_PRT_CFG_IN(base) & ~(CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK << pinNum);
1672 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1673
1674 cfgIn = tempReg | ((value & CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK) << pinNum);
1675
1676 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1677 if (pinType != CY_PRA_PIN_SECURE)
1678 {
1679 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1680 {
1681 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_IN), cfgIn);
1682 }
1683 else
1684 {
1685 GPIO_PRT_CFG_IN(base) = cfgIn;
1686 }
1687 }
1688 else
1689 {
1690 /* Secure PIN can't be modified using register policy */
1691 }
1692 #else
1693 GPIO_PRT_CFG_IN(base) = cfgIn;
1694 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1695 }
1696
1697
1698 /*******************************************************************************
1699 * Function Name: Cy_GPIO_GetVtrip
1700 ****************************************************************************//**
1701 *
1702 * Returns the pin input buffer voltage threshold mode.
1703 *
1704 * \param base
1705 * Pointer to the pin's port register base address
1706 *
1707 * \param pinNum
1708 * Position of the pin bit-field within the port register
1709 *
1710 * \return
1711 * Pin voltage threshold mode. Options are detailed in \ref group_gpio_vtrip macros
1712 *
1713 * \funcusage
1714 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVtrip
1715 *
1716 *******************************************************************************/
Cy_GPIO_GetVtrip(GPIO_PRT_Type * base,uint32_t pinNum)1717 uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum)
1718 {
1719 uint32_t tempReg;
1720 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1721 cy_en_pra_pin_prot_type_t pinType;
1722 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1723
1724 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1725
1726 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1727 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1728 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1729 {
1730 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_IN));
1731 }
1732 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1733 {
1734 tempReg = GPIO_PRT_CFG_IN(base);
1735 }
1736 else
1737 {
1738 /* secure pin */
1739 tempReg = 0UL;
1740 }
1741 #else
1742 tempReg = GPIO_PRT_CFG_IN(base);
1743 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1744
1745 return (tempReg >> pinNum) & CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK;
1746 }
1747
1748 #if defined(GPIO_AUTOLVL_AVAIL) || defined (CY_DOXYGEN)
1749 /*******************************************************************************
1750 * Function Name: Cy_GPIO_SetVtripAuto
1751 ****************************************************************************//**
1752 *
1753 * Configures the GPIO pin input buffer for automotive compatible or not.
1754 *
1755 * \param base
1756 * Pointer to the pin's port register base address
1757 *
1758 * \param pinNum
1759 * Position of the pin bit-field within the port register
1760 *
1761 * \param value
1762 * Pin voltage threshold mode. Options are detailed in
1763 * \ref group_gpio_vtrip_auto macros
1764 *
1765 * \note
1766 * This function modifies a port register in a read-modify-write operation. It is
1767 * not thread safe as the resource is shared among multiple pins on a port.
1768 *
1769 * \note
1770 * This API is available for CAT1B and CAT1C devices. TVIIBE also supports this functionality.
1771 *
1772 * \funcusage
1773 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVtripSel
1774 *******************************************************************************/
Cy_GPIO_SetVtripAuto(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)1775 void Cy_GPIO_SetVtripAuto(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
1776 {
1777 uint32_t tempReg;
1778 uint32_t vtripSel;
1779
1780 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1781 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
1782
1783 tempReg = GPIO_PRT_CFG_IN_AUTOLVL(base) & ~(CY_GPIO_CFG_IN_VTRIP_SEL_1_MASK << pinNum);
1784 vtripSel = tempReg | ((value & CY_GPIO_CFG_IN_VTRIP_SEL_1_MASK) << pinNum);
1785 GPIO_PRT_CFG_IN_AUTOLVL(base) = vtripSel;
1786 }
1787
1788
1789 /*******************************************************************************
1790 * Function Name: Cy_GPIO_GetVtripAuto
1791 ****************************************************************************//**
1792 *
1793 * Returns the pin input buffer voltage whether it is automotive compatible or not.
1794 *
1795 * \param base
1796 * Pointer to the pin's port register base address
1797 *
1798 * \param pinNum
1799 * Position of the pin bit-field within the port register
1800 *
1801 * \return
1802 * Pin voltage for automotive or not. Options are detailed in
1803 * \ref group_gpio_vtrip_auto macros
1804 *
1805 * \note
1806 * This API is available for CAT1B and CAT1C devices.
1807 *
1808 *******************************************************************************/
Cy_GPIO_GetVtripAuto(GPIO_PRT_Type * base,uint32_t pinNum)1809 uint32_t Cy_GPIO_GetVtripAuto(GPIO_PRT_Type* base, uint32_t pinNum)
1810 {
1811 uint32_t tempReg;
1812
1813 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1814
1815 tempReg = GPIO_PRT_CFG_IN_AUTOLVL(base);
1816
1817 return (tempReg >> pinNum) & CY_GPIO_CFG_IN_VTRIP_SEL_1_MASK;
1818 }
1819 #endif /* defined(GPIO_AUTOLVL_AVAIL) || defined (CY_DOXYGEN) */
1820 /*******************************************************************************
1821 * Function Name: Cy_GPIO_SetSlewRate
1822 ****************************************************************************//**
1823 *
1824 * Configures the pin output buffer slew rate.
1825 * GPIO pins have fast and slow output slew rate options for the strong drivers
1826 * configured using this API. By default the port works in fast slew mode.
1827 * Slower slew rate results in reduced EMI and crosstalk and are recommended for
1828 * low-frequency signals or signals without strict timing constraints.
1829 *
1830 * \note
1831 * This function has no effect for the GPIO ports, where the slew rate
1832 * configuration is not available. Refer to device datasheet for details.
1833 *
1834 * \param base
1835 * Pointer to the pin's port register base address
1836 *
1837 * \param pinNum
1838 * Position of the pin bit-field within the port register
1839 *
1840 * \param value
1841 * Pin slew rate. Options are detailed in \ref group_gpio_slewRate macros
1842 *
1843 * \note
1844 * This function modifies a port register in a read-modify-write operation. It is
1845 * not thread safe as the resource is shared among multiple pins on a port.
1846 *
1847 * \funcusage
1848 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetSlewRate
1849 *
1850 *******************************************************************************/
Cy_GPIO_SetSlewRate(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)1851 void Cy_GPIO_SetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
1852 {
1853 uint32_t tempReg;
1854 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS22IOSS)
1855 uint32_t pinLoc;
1856 #else
1857 uint32_t cfgOut;
1858 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
1859
1860 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1861 cy_en_pra_pin_prot_type_t pinType;
1862 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1863
1864 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1865 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
1866
1867 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS22IOSS)
1868 pinLoc = pinNum << CY_GPIO_CFG_SLEW_EXT_OFFSET;
1869 tempReg = (GPIO_PRT_SLEW_EXT(base) & ~(CY_GPIO_CFG_SLEW_EXT_MASK << pinLoc));
1870 GPIO_PRT_SLEW_EXT(base) = tempReg | ((value & CY_GPIO_CFG_SLEW_EXT_MASK) << pinLoc);
1871 #else
1872
1873 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1874 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1875 #if defined(CY_DEVICE_PSOC6ABLE2)
1876 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1877 {
1878 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT)) & ~(CY_GPIO_CFG_OUT_SLOW_MASK << pinNum);
1879 }
1880 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1881 {
1882 tempReg = GPIO_PRT_CFG_OUT(base) & ~(CY_GPIO_CFG_OUT_SLOW_MASK << pinNum);
1883 }
1884 else
1885 {
1886 /* secure pin */
1887 tempReg = 0UL;
1888 }
1889 #else
1890 tempReg = GPIO_PRT_CFG_OUT(base) & ~(CY_GPIO_CFG_OUT_SLOW_MASK << pinNum);
1891 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
1892 #else
1893 tempReg = GPIO_PRT_CFG_OUT(base) & ~(CY_GPIO_CFG_OUT_SLOW_MASK << pinNum);
1894 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1895 cfgOut = tempReg | ((value & CY_GPIO_CFG_OUT_SLOW_MASK) << pinNum);
1896
1897 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1898 if (pinType != CY_PRA_PIN_SECURE)
1899 {
1900 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1901 {
1902 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT), cfgOut);
1903 }
1904 else
1905 {
1906 GPIO_PRT_CFG_OUT(base) = cfgOut;
1907 }
1908 }
1909 else
1910 {
1911 /* Secure PIN can't be modified using register policy */
1912 }
1913 #else
1914 GPIO_PRT_CFG_OUT(base) = cfgOut;
1915 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1916 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
1917 }
1918
1919
1920 /*******************************************************************************
1921 * Function Name: Cy_GPIO_GetSlewRate
1922 ****************************************************************************//**
1923 *
1924 * Returns the pin output buffer slew rate.
1925 *
1926 * \param base
1927 * Pointer to the pin's port register base address
1928 *
1929 * \param pinNum
1930 * Position of the pin bit-field within the port register
1931 *
1932 * \return
1933 * Pin slew rate. Options are detailed in \ref group_gpio_slewRate macros
1934 *
1935 * \funcusage
1936 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetSlewRate
1937 *
1938 *******************************************************************************/
Cy_GPIO_GetSlewRate(GPIO_PRT_Type * base,uint32_t pinNum)1939 uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum)
1940 {
1941 #if defined (CY_IP_MXS40IOSS)
1942 uint32_t tempReg;
1943 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1944 cy_en_pra_pin_prot_type_t pinType;
1945 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1946 #endif /* defined (CY_IP_MXS40IOSS) */
1947
1948 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1949
1950 #if defined (CY_IP_MXS40IOSS)
1951
1952 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1953 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1954 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1955 {
1956 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT));
1957 }
1958 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1959 {
1960 tempReg = GPIO_PRT_CFG_OUT(base);
1961 }
1962 else
1963 {
1964 /* secure pin */
1965 tempReg = 0UL;
1966 }
1967 #else
1968 tempReg = GPIO_PRT_CFG_OUT(base);
1969 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1970
1971 return (tempReg >> pinNum) & CY_GPIO_CFG_OUT_SLOW_MASK;
1972 #else
1973 return (GPIO_PRT_SLEW_EXT(base) >> (pinNum << CY_GPIO_CFG_SLEW_EXT_OFFSET)) & CY_GPIO_CFG_SLEW_EXT_MASK;
1974 #endif /* CY_IP_MXS40IOSS */
1975 }
1976
1977
1978 /*******************************************************************************
1979 * Function Name: Cy_GPIO_SetDriveSel
1980 ****************************************************************************//**
1981 *
1982 * Configures the pin output buffer drive strength.
1983 * The drive strength field determines the active portion of the output drivers
1984 * used and can affect the slew rate of output signals. Drive strength options
1985 * are full drive strength (default), one-half strength, one-quarter strength,
1986 * and oneeighth strength. Drive strength must be set to full drive strength when
1987 * the slow slew rate bit (SLOW) is set.
1988 *
1989 * \param base
1990 * Pointer to the pin's port register base address
1991 *
1992 * \param pinNum
1993 * Position of the pin bit-field within the port register.
1994 *
1995 * \param value
1996 * Pin drive strength. Options are detailed in \ref group_gpio_driveStrength macros
1997 *
1998 * \note
1999 * This function modifies a port register in a read-modify-write operation. It is
2000 * not thread safe as the resource is shared among multiple pins on a port.
2001 *
2002 * \funcusage
2003 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetDriveSel
2004 *
2005 *******************************************************************************/
Cy_GPIO_SetDriveSel(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)2006 void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
2007 {
2008 uint32_t tempReg;
2009 #if defined (CY_IP_MXS40IOSS)
2010 uint32_t pinLoc;
2011 uint32_t cfgOut;
2012 #endif /* CY_IP_MXS40IOSS */
2013
2014 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2015 cy_en_pra_pin_prot_type_t pinType;
2016 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2017
2018 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2019 CY_ASSERT_L2(CY_GPIO_IS_DRIVE_SEL_VALID(value));
2020
2021 #if defined (CY_IP_MXS40IOSS)
2022 pinLoc = (uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET;
2023 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2024 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2025 #if defined(CY_DEVICE_PSOC6ABLE2)
2026 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2027 {
2028 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT)) & ~(CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << pinLoc);
2029 }
2030 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2031 {
2032 tempReg = GPIO_PRT_CFG_OUT(base) & ~(CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << pinLoc);
2033 }
2034 else
2035 {
2036 /* secure pin */
2037 tempReg = 0UL;
2038 }
2039 #else
2040 tempReg = GPIO_PRT_CFG_OUT(base) & ~(CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << pinLoc);
2041 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
2042 #else
2043 tempReg = GPIO_PRT_CFG_OUT(base) & ~(CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << pinLoc);
2044 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2045 cfgOut = tempReg | ((value & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << pinLoc);
2046
2047 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2048 if (pinType != CY_PRA_PIN_SECURE)
2049 {
2050 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2051 {
2052 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT), cfgOut);
2053 }
2054 else
2055 {
2056 GPIO_PRT_CFG_OUT(base) = cfgOut;
2057 }
2058 }
2059 else
2060 {
2061 /* Secure PIN can't be modified using register policy */
2062 }
2063 #else
2064 GPIO_PRT_CFG_OUT(base) = cfgOut;
2065 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2066 #else
2067 if(pinNum < CY_GPIO_PRT_HALF)
2068 {
2069 tempReg = GPIO_PRT_DRIVE_EXT0(base) & ~(CY_GPIO_CFG_DRIVE_SEL_EXT_MASK << (pinNum << CY_GPIO_CFG_DRIVE_SEL_EXT_OFFSET));
2070 GPIO_PRT_DRIVE_EXT0(base) = tempReg | ((value & CY_GPIO_CFG_DRIVE_SEL_EXT_MASK) << (pinNum << CY_GPIO_CFG_DRIVE_SEL_EXT_OFFSET));
2071 }
2072 else
2073 {
2074 pinNum -= CY_GPIO_PRT_HALF;
2075 tempReg = GPIO_PRT_DRIVE_EXT1(base) & ~(CY_GPIO_CFG_DRIVE_SEL_EXT_MASK << (pinNum << CY_GPIO_CFG_DRIVE_SEL_EXT_OFFSET));
2076 GPIO_PRT_DRIVE_EXT1(base) = tempReg | ((value & CY_GPIO_CFG_DRIVE_SEL_EXT_MASK) << (pinNum << CY_GPIO_CFG_DRIVE_SEL_EXT_OFFSET));
2077 }
2078 #endif /* CY_IP_MXS40SIOSS */
2079 }
2080
2081
2082 /*******************************************************************************
2083 * Function Name: Cy_GPIO_GetDriveSel
2084 ****************************************************************************//**
2085 *
2086 * Returns the pin output buffer drive strength.
2087 *
2088 * \param base
2089 * Pointer to the pin's port register base address
2090 *
2091 * \param pinNum
2092 * Position of the pin bit-field within the port register
2093 *
2094 * \return
2095 * Pin drive strength. Options are detailed in \ref group_gpio_driveStrength macros
2096 *
2097 * \funcusage
2098 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetDriveSel
2099 *
2100 *******************************************************************************/
Cy_GPIO_GetDriveSel(GPIO_PRT_Type * base,uint32_t pinNum)2101 uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum)
2102 {
2103 #if defined (CY_IP_MXS40IOSS)
2104 uint32_t tempReg;
2105 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2106 cy_en_pra_pin_prot_type_t pinType;
2107 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2108 #endif /* defined (CY_IP_MXS40IOSS) */
2109
2110 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2111
2112 #if defined (CY_IP_MXS40IOSS)
2113 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2114 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2115 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2116 {
2117 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT));
2118 }
2119 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2120 {
2121 tempReg = GPIO_PRT_CFG_OUT(base);
2122 }
2123 else
2124 {
2125 /* secure pin */
2126 tempReg = 0UL;
2127 }
2128 #else
2129 tempReg = GPIO_PRT_CFG_OUT(base);
2130 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2131
2132 return ((tempReg >> ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET))
2133 & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK);
2134 #else
2135 uint32_t returnValue;
2136 if(pinNum < CY_GPIO_PRT_HALF)
2137 {
2138 returnValue = (GPIO_PRT_DRIVE_EXT0(base) >> (pinNum << CY_GPIO_CFG_DRIVE_SEL_EXT_OFFSET)) & CY_GPIO_CFG_DRIVE_SEL_EXT_MASK;
2139 }
2140 else
2141 {
2142 pinNum -= CY_GPIO_PRT_HALF;
2143 returnValue = (GPIO_PRT_DRIVE_EXT1(base) >> (pinNum << CY_GPIO_CFG_DRIVE_SEL_EXT_OFFSET)) & CY_GPIO_CFG_DRIVE_SEL_EXT_MASK;
2144 }
2145 return returnValue;
2146 #endif /* CY_IP_MXS40IOSS */
2147 }
2148
2149
2150 /*******************************************************************************
2151 * Function Name: Cy_GPIO_SetVregEn
2152 ****************************************************************************//**
2153 *
2154 * Configures the SIO pin pair output buffer regulation mode.
2155 *
2156 * Note that this function has no effect on non-SIO pins.
2157 *
2158 * \param base
2159 * Pointer to the pin's port register base address
2160 *
2161 * \param pinNum
2162 * Position of the pin bit-field within the port register
2163 *
2164 * \param value
2165 * SIO pair output buffer regulator mode. Options are detailed in \ref group_gpio_sioVreg macros
2166 *
2167 * \note
2168 * This function modifies a port register in a read-modify-write operation. It is
2169 * not thread safe as the resource is shared among multiple pins on a port.
2170 *
2171 * \funcusage
2172 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVregEn
2173 *
2174 *******************************************************************************/
Cy_GPIO_SetVregEn(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)2175 void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
2176 {
2177 #if defined (CY_IP_MXS40IOSS)
2178 uint32_t tempReg;
2179 uint32_t pinLoc;
2180 uint32_t cfgSio;
2181
2182 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2183 cy_en_pra_pin_prot_type_t pinType;
2184 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2185
2186 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2187 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
2188
2189 pinLoc = (pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET;
2190 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2191 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2192 #if defined(CY_DEVICE_PSOC6ABLE2)
2193 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2194 {
2195 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO)) & ~(CY_GPIO_VREG_EN_MASK << pinLoc);
2196 }
2197 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2198 {
2199 tempReg = GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VREG_EN_MASK << pinLoc);
2200 }
2201 else
2202 {
2203 /* secure pin */
2204 tempReg = 0UL;
2205 }
2206 #else
2207 tempReg = GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VREG_EN_MASK << pinLoc);
2208 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
2209 #else
2210 tempReg = GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VREG_EN_MASK << pinLoc);
2211 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2212 cfgSio = tempReg | ((value & CY_GPIO_VREG_EN_MASK) << pinLoc);
2213
2214 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2215 if (pinType != CY_PRA_PIN_SECURE)
2216 {
2217 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2218 {
2219 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), cfgSio);
2220 }
2221 else
2222 {
2223 GPIO_PRT_CFG_SIO(base) = cfgSio;
2224 }
2225 }
2226 else
2227 {
2228 /* Secure PIN can't be modified using register policy */
2229 }
2230 #else
2231 GPIO_PRT_CFG_SIO(base) = cfgSio;
2232 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2233 #else
2234 CY_ASSERT_L2(1);
2235 (void) base;
2236 (void) pinNum;
2237 (void) value;
2238
2239 #endif /* CY_IP_MXS40IOSS */
2240 }
2241
2242
2243 /*******************************************************************************
2244 * Function Name: Cy_GPIO_GetVregEn
2245 ****************************************************************************//**
2246 *
2247 * Returns the SIO pin pair output buffer regulation mode.
2248 *
2249 * Note that this function has no effect on non-SIO pins.
2250 *
2251 * \param base
2252 * Pointer to the pin's port register base address
2253 *
2254 * \param pinNum
2255 * Position of the pin bit-field within the port register
2256 *
2257 * \return
2258 * SIO pair output buffer regulator mode. Options are detailed in \ref group_gpio_sioVreg macros
2259 *
2260 * \funcusage
2261 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVregEn
2262 *
2263 *******************************************************************************/
Cy_GPIO_GetVregEn(GPIO_PRT_Type * base,uint32_t pinNum)2264 uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum)
2265 {
2266 #if defined (CY_IP_MXS40IOSS)
2267 uint32_t tempReg;
2268 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2269 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2270 cy_en_pra_pin_prot_type_t pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2271 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2272 {
2273 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO));
2274 }
2275 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2276 {
2277 tempReg = GPIO_PRT_CFG_SIO(base);
2278 }
2279 else
2280 {
2281 /* secure pin */
2282 tempReg = 0UL;
2283 }
2284 #else
2285 tempReg = GPIO_PRT_CFG_SIO(base);
2286 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2287
2288
2289 return (tempReg >> ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET)) & CY_GPIO_VREG_EN_MASK;
2290 #else
2291 CY_ASSERT_L2(1);
2292
2293 (void) base;
2294 (void) pinNum;
2295
2296 return CYRET_INVALID_STATE;
2297 #endif /* CY_IP_MXS40IOSS */
2298 }
2299
2300
2301 /*******************************************************************************
2302 * Function Name: Cy_GPIO_SetIbufMode
2303 ****************************************************************************//**
2304 *
2305 * Configures the SIO pin pair input buffer mode.
2306 *
2307 * Note that this function has no effect on non-SIO pins.
2308 *
2309 * \param base
2310 * Pointer to the pin's port register base address
2311 *
2312 * \param pinNum
2313 * Position of the pin bit-field within the port register
2314 *
2315 * \param value
2316 * SIO pair input buffer mode. Options are detailed in \ref group_gpio_sioIbuf macros
2317 *
2318 * \note
2319 * This function modifies a port register in a read-modify-write operation. It is
2320 * not thread safe as the resource is shared among multiple pins on a port.
2321 *
2322 * \funcusage
2323 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetIbufMode
2324 *
2325 *******************************************************************************/
Cy_GPIO_SetIbufMode(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)2326 void Cy_GPIO_SetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
2327 {
2328 #if defined (CY_IP_MXS40IOSS)
2329 uint32_t tempReg;
2330 uint32_t pinLoc;
2331 uint32_t cfgSio;
2332
2333 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2334 cy_en_pra_pin_prot_type_t pinType;
2335 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2336
2337 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2338 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
2339
2340 pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_IBUF_SHIFT;
2341 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2342 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2343 #if defined(CY_DEVICE_PSOC6ABLE2)
2344 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2345 {
2346 tempReg = (CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO)) & ~(CY_GPIO_IBUF_MASK << pinLoc));
2347 }
2348 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2349 {
2350 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_IBUF_MASK << pinLoc));
2351 }
2352 else
2353 {
2354 /* secure pin */
2355 tempReg = 0UL;
2356 }
2357 #else
2358 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_IBUF_MASK << pinLoc));
2359 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
2360 #else
2361 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_IBUF_MASK << pinLoc));
2362 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2363
2364 cfgSio = tempReg | ((value & CY_GPIO_IBUF_MASK) << pinLoc);
2365
2366 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2367 if (pinType != CY_PRA_PIN_SECURE)
2368 {
2369 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2370 {
2371 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), cfgSio);
2372 }
2373 else
2374 {
2375 GPIO_PRT_CFG_SIO(base) = cfgSio;
2376 }
2377 }
2378 else
2379 {
2380 /* Secure PIN can't be modified using register policy */
2381 }
2382 #else
2383 GPIO_PRT_CFG_SIO(base) = cfgSio;
2384 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2385 #else
2386 CY_ASSERT_L2(1);
2387 (void) base;
2388 (void) pinNum;
2389 (void) value;
2390
2391 #endif /* CY_IP_MXS40IOSS */
2392 }
2393
2394
2395 /*******************************************************************************
2396 * Function Name: Cy_GPIO_GetIbufMode
2397 ****************************************************************************//**
2398 *
2399 * Returns the SIO pin pair input buffer mode.
2400 *
2401 * Note that this function has no effect on non-SIO pins.
2402 *
2403 * \param base
2404 * Pointer to the pin's port register base address
2405 *
2406 * \param pinNum
2407 * Position of the pin bit-field within the port register
2408 *
2409 * \return
2410 * SIO pair input buffer mode. Options are detailed in \ref group_gpio_sioIbuf macros
2411 *
2412 * \funcusage
2413 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetIbufMode
2414 *
2415 *******************************************************************************/
Cy_GPIO_GetIbufMode(GPIO_PRT_Type * base,uint32_t pinNum)2416 uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum)
2417 {
2418 #if defined (CY_IP_MXS40IOSS)
2419 uint32_t tempReg;
2420
2421 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2422
2423 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2424 cy_en_pra_pin_prot_type_t pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2425 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2426 {
2427 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO));
2428 }
2429 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2430 {
2431 tempReg = GPIO_PRT_CFG_SIO(base);
2432 }
2433 else
2434 {
2435 /* secure pin */
2436 tempReg = 0UL;
2437 }
2438 #else
2439 tempReg = GPIO_PRT_CFG_SIO(base);
2440 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2441
2442 return (tempReg >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_IBUF_SHIFT)) & CY_GPIO_IBUF_MASK;
2443 #else
2444 CY_ASSERT_L2(1);
2445
2446 (void) base;
2447 (void) pinNum;
2448
2449 return CYRET_INVALID_STATE;
2450 #endif /* CY_IP_MXS40IOSS */
2451 }
2452
2453
2454 /*******************************************************************************
2455 * Function Name: Cy_GPIO_SetVtripSel
2456 ****************************************************************************//**
2457 *
2458 * Configures the SIO pin pair input buffer trip point.
2459 *
2460 * Note that this function has no effect on non-SIO pins.
2461 *
2462 * \param base
2463 * Pointer to the pin's port register base address
2464 *
2465 * \param pinNum
2466 * Position of the pin bit-field within the port register
2467 *
2468 * \param value
2469 * SIO pair input buffer trip point. Options are detailed in \ref group_gpio_sioVtrip macros
2470 *
2471 * \note
2472 * This function modifies a port register in a read-modify-write operation. It is
2473 * not thread safe as the resource is shared among multiple pins on a port.
2474 *
2475 * \funcusage
2476 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVtripSel
2477 *
2478 *******************************************************************************/
Cy_GPIO_SetVtripSel(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)2479 void Cy_GPIO_SetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
2480 {
2481 #if defined (CY_IP_MXS40IOSS)
2482 uint32_t tempReg;
2483 uint32_t pinLoc;
2484 uint32_t cfgSio;
2485
2486 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2487 cy_en_pra_pin_prot_type_t pinType;
2488 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2489
2490 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2491 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
2492
2493 pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VTRIP_SEL_SHIFT;
2494 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2495 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2496 #if defined(CY_DEVICE_PSOC6ABLE2)
2497 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2498 {
2499 tempReg = (CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO)) & ~(CY_GPIO_VTRIP_SEL_MASK << pinLoc));
2500 }
2501 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2502 {
2503 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VTRIP_SEL_MASK << pinLoc));
2504 }
2505 else
2506 {
2507 /* secure pin */
2508 tempReg = 0UL;
2509 }
2510 #else
2511 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VTRIP_SEL_MASK << pinLoc));
2512 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
2513 #else
2514 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VTRIP_SEL_MASK << pinLoc));
2515 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2516
2517 cfgSio = tempReg | ((value & CY_GPIO_VTRIP_SEL_MASK) << pinLoc);
2518
2519 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2520 if (pinType != CY_PRA_PIN_SECURE)
2521 {
2522 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2523 {
2524 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), cfgSio);
2525 }
2526 else
2527 {
2528 GPIO_PRT_CFG_SIO(base) = cfgSio;
2529 }
2530 }
2531 else
2532 {
2533 /* Secure PIN can't be modified using register policy */
2534 }
2535 #else
2536 GPIO_PRT_CFG_SIO(base) = cfgSio;
2537 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2538 #else
2539 (void) base;
2540 (void) pinNum;
2541 (void) value;
2542
2543 CY_ASSERT_L2(1);
2544 #endif /* CY_IP_MXS40IOSS */
2545 }
2546
2547
2548 /*******************************************************************************
2549 * Function Name: Cy_GPIO_GetVtripSel
2550 ****************************************************************************//**
2551 *
2552 * Returns the SIO pin pair input buffer trip point.
2553 *
2554 * Note that this function has no effect on non-SIO pins.
2555 *
2556 * \param base
2557 * Pointer to the pin's port register base address
2558 *
2559 * \param pinNum
2560 * Position of the pin bit-field within the port register
2561 *
2562 * \return
2563 * SIO pair input buffer trip point. Options are detailed in \ref group_gpio_sioVtrip macros
2564 *
2565 * \funcusage
2566 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVtripSel
2567 *
2568 *******************************************************************************/
Cy_GPIO_GetVtripSel(GPIO_PRT_Type * base,uint32_t pinNum)2569 uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum)
2570 {
2571 #if defined (CY_IP_MXS40IOSS)
2572 uint32_t tempReg;
2573
2574 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2575
2576 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2577 cy_en_pra_pin_prot_type_t pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2578 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2579 {
2580 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO));
2581 }
2582 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2583 {
2584 tempReg = GPIO_PRT_CFG_SIO(base);
2585 }
2586 else
2587 {
2588 /* secure pin */
2589 tempReg = 0UL;
2590 }
2591 #else
2592 tempReg = GPIO_PRT_CFG_SIO(base);
2593 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2594
2595 return (tempReg >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VTRIP_SEL_SHIFT)) & CY_GPIO_VTRIP_SEL_MASK;
2596 #else
2597 CY_ASSERT_L2(1);
2598
2599 (void) base;
2600 (void) pinNum;
2601
2602 return CYRET_INVALID_STATE;
2603 #endif /* CY_IP_MXS40IOSS */
2604 }
2605
2606
2607
2608 /*******************************************************************************
2609 * Function Name: Cy_GPIO_SetVrefSel
2610 ****************************************************************************//**
2611 *
2612 * Configures the SIO reference voltage for the input buffer trip point.
2613 *
2614 * Note that this function has no effect on non-SIO pins.
2615 *
2616 * \param base
2617 * Pointer to the pin's port register base address
2618 *
2619 * \param pinNum
2620 * Position of the pin bit-field within the port register
2621 *
2622 * \param value
2623 * SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVref macros
2624 *
2625 * \note
2626 * This function modifies a port register in a read-modify-write operation. It is
2627 * not thread safe as the resource is shared among multiple pins on a port.
2628 *
2629 * \funcusage
2630 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVrefSel
2631 *
2632 *******************************************************************************/
Cy_GPIO_SetVrefSel(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)2633 void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
2634 {
2635 #if defined (CY_IP_MXS40IOSS)
2636 uint32_t tempReg;
2637 uint32_t pinLoc;
2638 uint32_t cfgSio;
2639
2640 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2641 cy_en_pra_pin_prot_type_t pinType;
2642 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2643
2644 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2645 CY_ASSERT_L2(CY_GPIO_IS_VREF_SEL_VALID(value));
2646
2647 pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT;
2648 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2649 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2650 #if defined(CY_DEVICE_PSOC6ABLE2)
2651 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2652 {
2653 tempReg = (CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO)) & ~(CY_GPIO_VREF_SEL_MASK << pinLoc));
2654 }
2655 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2656 {
2657 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VREF_SEL_MASK << pinLoc));
2658 }
2659 else
2660 {
2661 /* secure pin */
2662 tempReg = 0UL;
2663 }
2664 #else
2665 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VREF_SEL_MASK << pinLoc));
2666 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
2667 #else
2668 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VREF_SEL_MASK << pinLoc));
2669 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2670
2671 cfgSio = tempReg | ((value & CY_GPIO_VREF_SEL_MASK) << pinLoc);
2672
2673 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2674 if (pinType != CY_PRA_PIN_SECURE)
2675 {
2676 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2677 {
2678 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), cfgSio);
2679 }
2680 else
2681 {
2682 GPIO_PRT_CFG_SIO(base) = cfgSio;
2683 }
2684 }
2685 else
2686 {
2687 /* Secure PIN can't be modified using register policy */
2688 }
2689 #else
2690 GPIO_PRT_CFG_SIO(base) = cfgSio;
2691 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2692 #else
2693 (void) base;
2694 (void) pinNum;
2695 (void) value;
2696
2697 CY_ASSERT_L2(1);
2698 #endif /* CY_IP_MXS40IOSS */
2699 }
2700
2701
2702 /*******************************************************************************
2703 * Function Name: Cy_GPIO_GetVrefSel
2704 ****************************************************************************//**
2705 *
2706 * Returns the SIO reference voltage for the input buffer trip point.
2707 *
2708 * Note that this function has no effect on non-SIO pins.
2709 *
2710 * \param base
2711 * Pointer to the pin's port register base address
2712 *
2713 * \param pinNum
2714 * Position of the pin bit-field within the port register
2715 *
2716 * \return
2717 * SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVref macros
2718 *
2719 * \funcusage
2720 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVrefSel
2721 *
2722 *******************************************************************************/
Cy_GPIO_GetVrefSel(GPIO_PRT_Type * base,uint32_t pinNum)2723 uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum)
2724 {
2725 #if defined (CY_IP_MXS40IOSS)
2726 uint32_t tempReg;
2727 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2728
2729 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2730 cy_en_pra_pin_prot_type_t pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2731 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2732 {
2733 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO));
2734 }
2735 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2736 {
2737 tempReg = GPIO_PRT_CFG_SIO(base);
2738 }
2739 else
2740 {
2741 /* secure pin */
2742 tempReg = 0UL;
2743 }
2744 #else
2745 tempReg = GPIO_PRT_CFG_SIO(base);
2746 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2747
2748 return (tempReg >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT)) & CY_GPIO_VREF_SEL_MASK;
2749 #else
2750 CY_ASSERT_L2(1);
2751
2752 (void) base;
2753 (void) pinNum;
2754
2755 return CYRET_INVALID_STATE;
2756 #endif /* CY_IP_MXS40IOSS */
2757 }
2758
2759
2760
2761 /*******************************************************************************
2762 * Function Name: Cy_GPIO_SetVohSel
2763 ****************************************************************************//**
2764 *
2765 * Configures the regulated output reference multiplier for the SIO pin pair.
2766 *
2767 * The regulated output reference controls both the output level of digital output
2768 * pin and the input trip point of digital input pin in the SIO pair.
2769 *
2770 * Note that this function has no effect on non-SIO pins.
2771 *
2772 * \param base
2773 * Pointer to the pin's port register base address
2774 *
2775 * \param pinNum
2776 * Position of the pin bit-field within the port register
2777 *
2778 * \param value
2779 * SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVoh macros
2780 *
2781 * \note
2782 * This function modifies a port register in a read-modify-write operation. It is
2783 * not thread safe as the resource is shared among multiple pins on a port.
2784 *
2785 * \funcusage
2786 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVohSel
2787 *
2788 *******************************************************************************/
Cy_GPIO_SetVohSel(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)2789 void Cy_GPIO_SetVohSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
2790 {
2791 #if defined (CY_IP_MXS40IOSS)
2792 uint32_t tempReg;
2793 uint32_t pinLoc;
2794 uint32_t cfgSio;
2795
2796 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2797 cy_en_pra_pin_prot_type_t pinType;
2798 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2799
2800 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2801 CY_ASSERT_L2(CY_GPIO_IS_VOH_SEL_VALID(value));
2802
2803 pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VOH_SEL_SHIFT;
2804 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2805 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2806 #if defined(CY_DEVICE_PSOC6ABLE2)
2807 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2808 {
2809 tempReg = (CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO)) & ~(CY_GPIO_VOH_SEL_MASK << pinLoc));
2810 }
2811 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2812 {
2813 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VOH_SEL_MASK << pinLoc));
2814 }
2815 else
2816 {
2817 /* secure pin */
2818 tempReg = 0UL;
2819 }
2820 #else
2821 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VOH_SEL_MASK << pinLoc));
2822 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
2823 #else
2824 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VOH_SEL_MASK << pinLoc));
2825 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2826 cfgSio = tempReg | ((value & CY_GPIO_VOH_SEL_MASK) << pinLoc);
2827
2828 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2829 if (pinType != CY_PRA_PIN_SECURE)
2830 {
2831 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2832 {
2833 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), cfgSio);
2834 }
2835 else
2836 {
2837 GPIO_PRT_CFG_SIO(base) = cfgSio;
2838 }
2839 }
2840 else
2841 {
2842 /* Secure PIN can't be modified using register policy */
2843 }
2844 #else
2845 GPIO_PRT_CFG_SIO(base) = cfgSio;
2846 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2847 #else
2848 CY_ASSERT_L2(1);
2849 (void) base;
2850 (void) pinNum;
2851 (void) value;
2852
2853 #endif /* CY_IP_MXS40IOSS */
2854 }
2855
2856
2857 /*******************************************************************************
2858 * Function Name: Cy_GPIO_GetVohSel
2859 ****************************************************************************//**
2860 *
2861 * Returns the regulated output reference multiplier for the SIO pin pair.
2862 *
2863 * Note that this function has no effect on non-SIO pins.
2864 *
2865 * \param base
2866 * Pointer to the pin's port register base address
2867 *
2868 * \param pinNum
2869 * Position of the pin bit-field within the port register
2870 *
2871 * \return
2872 * SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVoh macros
2873 *
2874 * \funcusage
2875 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVohSel
2876 *
2877 *******************************************************************************/
Cy_GPIO_GetVohSel(GPIO_PRT_Type * base,uint32_t pinNum)2878 uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum)
2879 {
2880 #if defined (CY_IP_MXS40IOSS)
2881 uint32_t tempReg;
2882 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2883
2884 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2885 cy_en_pra_pin_prot_type_t pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2886 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2887 {
2888 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO));
2889 }
2890 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2891 {
2892 tempReg = GPIO_PRT_CFG_SIO(base);
2893 }
2894 else
2895 {
2896 /* secure pin */
2897 tempReg = 0UL;
2898 }
2899 #else
2900 tempReg = GPIO_PRT_CFG_SIO(base);
2901 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2902
2903 return (tempReg >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VOH_SEL_SHIFT)) & CY_GPIO_VOH_SEL_MASK;
2904 #else
2905 CY_ASSERT_L2(1);
2906 (void) base;
2907 (void) pinNum;
2908
2909 return CYRET_INVALID_STATE;
2910 #endif /* CY_IP_MXS40IOSS */
2911 }
2912
2913
2914 /*******************************************************************************
2915 * Function Name: Cy_GPIO_GetInterruptStatus
2916 ****************************************************************************//**
2917 *
2918 * Returns the current unmasked interrupt state of the pin.
2919 *
2920 * The core processor's NVIC is triggered by the masked interrupt bits. This
2921 * function allows reading the unmasked interrupt state. Whether the bit
2922 * positions actually trigger the interrupt are defined by the interrupt mask bits.
2923 *
2924 * \param base
2925 * Pointer to the pin's port register base address
2926 *
2927 * \param pinNum
2928 * Position of the pin bit-field within the port register
2929 * Bit position 8 is the routed pin through the port glitch filter.
2930 *
2931 * \return
2932 * 0 = Pin interrupt condition not detected
2933 * 1 = Pin interrupt condition detected
2934 *
2935 * \funcusage
2936 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_GetInterruptStatus
2937 *
2938 *******************************************************************************/
Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type * base,uint32_t pinNum)2939 uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_t pinNum)
2940 {
2941 uint32_t tempReg;
2942 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2943 cy_en_pra_pin_prot_type_t pinType;
2944 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2945
2946 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
2947
2948 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2949 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2950 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2951 {
2952 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR));
2953 }
2954 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2955 {
2956 tempReg = GPIO_PRT_INTR(base);
2957 }
2958 else
2959 {
2960 /* secure pin */
2961 tempReg = 0UL;
2962 }
2963 #else
2964 tempReg = GPIO_PRT_INTR(base);
2965 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2966
2967 return (tempReg >> pinNum) & CY_GPIO_INTR_STATUS_MASK;
2968 }
2969
2970
2971
2972 /*******************************************************************************
2973 * Function Name: Cy_GPIO_ClearInterrupt
2974 ****************************************************************************//**
2975 *
2976 * Clears the triggered pin interrupt.
2977 *
2978 * \param base
2979 * Pointer to the pin's port register base address
2980 *
2981 * \param pinNum
2982 * Position of the pin bit-field within the port register
2983 * Bit position 8 is the routed pin through the port glitch filter.
2984 *
2985 * \funcusage
2986 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_ClearInterrupt
2987 *
2988 *******************************************************************************/
Cy_GPIO_ClearInterrupt(GPIO_PRT_Type * base,uint32_t pinNum)2989 void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum)
2990 {
2991 uint32_t prtIntr;
2992 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2993 cy_en_pra_pin_prot_type_t pinType;
2994 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2995
2996 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
2997
2998 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2999 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
3000 #if defined(CY_DEVICE_PSOC6ABLE2)
3001 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3002 {
3003 (void)CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR));
3004 }
3005 else if (pinType == CY_PRA_PIN_SECURE_NONE)
3006 {
3007 /* Any INTR MMIO registers AHB clearing must be preceded with an AHB read access */
3008 (void)GPIO_PRT_INTR(base);
3009 }
3010 else
3011 {
3012 /* secure pin */
3013 }
3014 #else
3015 /* Any INTR MMIO registers AHB clearing must be preceded with an AHB read access */
3016 (void)GPIO_PRT_INTR(base);
3017 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
3018 #else
3019 /* Any INTR MMIO registers AHB clearing must be preceded with an AHB read access */
3020 (void)GPIO_PRT_INTR(base);
3021 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3022
3023 prtIntr = CY_GPIO_INTR_STATUS_MASK << pinNum;
3024
3025 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3026 if (pinType != CY_PRA_PIN_SECURE)
3027 {
3028 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3029 {
3030 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR), prtIntr);
3031 }
3032 else
3033 {
3034 GPIO_PRT_INTR(base) = prtIntr;
3035 }
3036 }
3037 else
3038 {
3039 /* Secure PIN can't be modified using register policy */
3040 }
3041 #else
3042 GPIO_PRT_INTR(base) = prtIntr;
3043 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3044
3045 /* This read ensures that the initial write has been flushed out to the hardware */
3046 (void)GPIO_PRT_INTR(base);
3047 }
3048
3049
3050 /*******************************************************************************
3051 * Function Name: Cy_GPIO_SetInterruptMask
3052 ****************************************************************************//**
3053 *
3054 * Configures the pin interrupt to be forwarded to the CPU NVIC.
3055 *
3056 * \param base
3057 * Pointer to the pin's port register base address
3058 *
3059 * \param pinNum
3060 * Position of the pin bit-field within the port register.
3061 * Bit position 8 is the routed pin through the port glitch filter.
3062 *
3063 * \param value
3064 * 0 = Pin interrupt not forwarded to CPU interrupt controller
3065 * 1 = Pin interrupt masked and forwarded to CPU interrupt controller
3066 *
3067 * \note
3068 * This function modifies a port register in a read-modify-write operation. It is
3069 * not thread safe as the resource is shared among multiple pins on a port.
3070 *
3071 * \funcusage
3072 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetInterruptMask
3073 *
3074 *******************************************************************************/
Cy_GPIO_SetInterruptMask(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)3075 void Cy_GPIO_SetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
3076 {
3077 uint32_t tempReg;
3078 uint32_t intrMask;
3079
3080 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3081 cy_en_pra_pin_prot_type_t pinType;
3082 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3083
3084 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
3085 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
3086
3087 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3088 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
3089 #if defined(CY_DEVICE_PSOC6ABLE2)
3090 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3091 {
3092 tempReg= CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_MASK)) & ~(CY_GPIO_INTR_EN_MASK << pinNum);
3093 }
3094 else if (pinType == CY_PRA_PIN_SECURE_NONE)
3095 {
3096 tempReg= GPIO_PRT_INTR_MASK(base) & ~(CY_GPIO_INTR_EN_MASK << pinNum);
3097 }
3098 else
3099 {
3100 /* secure pin */
3101 tempReg = 0UL;
3102 }
3103 #else
3104 tempReg= GPIO_PRT_INTR_MASK(base) & ~(CY_GPIO_INTR_EN_MASK << pinNum);
3105 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
3106 #else
3107 tempReg= GPIO_PRT_INTR_MASK(base) & ~(CY_GPIO_INTR_EN_MASK << pinNum);
3108 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3109
3110 intrMask = tempReg | ((value & CY_GPIO_INTR_EN_MASK) << pinNum);
3111
3112 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3113 if (pinType != CY_PRA_PIN_SECURE)
3114 {
3115 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3116 {
3117 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_MASK), intrMask);
3118 }
3119 else
3120 {
3121 GPIO_PRT_INTR_MASK(base) = intrMask;
3122 }
3123 }
3124 else
3125 {
3126 /* Secure PIN can't be modified using register policy */
3127 }
3128 #else
3129 GPIO_PRT_INTR_MASK(base) = intrMask;
3130 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3131 }
3132
3133
3134 /*******************************************************************************
3135 * Function Name: Cy_GPIO_GetInterruptMask
3136 ****************************************************************************//**
3137 *
3138 * Returns the state of the pin interrupt mask.
3139 *
3140 * This mask is used to determine whether the pin is configured to be forwarded
3141 * to the CPU NVIC.
3142 *
3143 * \param base
3144 * Pointer to the pin's port register base address
3145 *
3146 * \param pinNum
3147 * Position of the pin bit-field within the port register.
3148 * Bit position 8 is the routed pin through the port glitch filter.
3149 *
3150 * \return
3151 * 0 = Pin interrupt not forwarded to CPU interrupt controller
3152 * 1 = Pin interrupt masked and forwarded to CPU interrupt controller
3153 *
3154 * \funcusage
3155 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetInterruptMask
3156 *
3157 *******************************************************************************/
Cy_GPIO_GetInterruptMask(GPIO_PRT_Type * base,uint32_t pinNum)3158 uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum)
3159 {
3160 uint32_t tempReg;
3161 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
3162 cy_en_pra_pin_prot_type_t pinType;
3163 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
3164
3165 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
3166
3167 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
3168 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
3169 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3170 {
3171 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_MASK));
3172 }
3173 else if (pinType == CY_PRA_PIN_SECURE_NONE)
3174 {
3175 tempReg = GPIO_PRT_INTR_MASK(base);
3176 }
3177 else
3178 {
3179 /* secure pin */
3180 tempReg = 0UL;
3181 }
3182 #else
3183 tempReg = GPIO_PRT_INTR_MASK(base);
3184 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
3185
3186 return (tempReg >> pinNum) & CY_GPIO_INTR_EN_MASK;
3187 }
3188
3189
3190 /*******************************************************************************
3191 * Function Name: Cy_GPIO_GetInterruptStatusMasked
3192 ****************************************************************************//**
3193 *
3194 * Return the pin's current interrupt state after being masked.
3195 *
3196 * The core processor's NVIC is triggered by the masked interrupt bits. This
3197 * function allows reading this masked interrupt state. Note that the bits that
3198 * are not masked will not be forwarded to the NVIC.
3199 *
3200 * \param base
3201 * Pointer to the pin's port register base address
3202 *
3203 * \param pinNum
3204 * Position of the pin bit-field within the port register.
3205 * Bit position 8 is the routed pin through the port glitch filter.
3206 *
3207 * \return
3208 * 0 = Pin interrupt not detected or not forwarded to CPU interrupt controller
3209 * 1 = Pin interrupt detected and forwarded to CPU interrupt controller
3210 *
3211 * \funcusage
3212 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_GetInterruptStatusMasked
3213 *
3214 *******************************************************************************/
Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type * base,uint32_t pinNum)3215 uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, uint32_t pinNum)
3216 {
3217 uint32_t tempReg;
3218 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
3219 cy_en_pra_pin_prot_type_t pinType;
3220 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
3221
3222 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
3223
3224 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
3225 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
3226 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3227 {
3228 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_MASKED));
3229 }
3230 else if (pinType == CY_PRA_PIN_SECURE_NONE)
3231 {
3232 tempReg = GPIO_PRT_INTR_MASKED(base);
3233 }
3234 else
3235 {
3236 /* secure pin */
3237 tempReg = 0UL;
3238 }
3239 #else
3240 tempReg = GPIO_PRT_INTR_MASKED(base);
3241 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
3242
3243 return (tempReg >> pinNum) & CY_GPIO_INTR_MASKED_MASK;
3244 }
3245
3246
3247 /*******************************************************************************
3248 * Function Name: Cy_GPIO_SetSwInterrupt
3249 ****************************************************************************//**
3250 *
3251 * Force a pin interrupt to trigger.
3252 *
3253 * \param base
3254 * Pointer to the pin's port register base address
3255 *
3256 * \param pinNum
3257 * Position of the pin bit-field within the port register.
3258 * Bit position 8 is the routed pin through the port glitch filter.
3259 *
3260 * \funcusage
3261 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetSwInterrupt
3262 *
3263 *******************************************************************************/
Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type * base,uint32_t pinNum)3264 void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum)
3265 {
3266 uint32_t intrSet;
3267 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3268 cy_en_pra_pin_prot_type_t pinType;
3269 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3270
3271 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
3272
3273 intrSet = CY_GPIO_INTR_SET_MASK << pinNum;
3274
3275 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3276 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
3277
3278 if (pinType != CY_PRA_PIN_SECURE)
3279 {
3280 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3281 {
3282 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_SET), intrSet);
3283 }
3284 else
3285 {
3286 GPIO_PRT_INTR_SET(base) = intrSet;
3287 }
3288 }
3289 else
3290 {
3291 /* Secure PIN can't be modified using register policy */
3292 }
3293 #else
3294 GPIO_PRT_INTR_SET(base) = intrSet;
3295 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3296 }
3297
3298
3299 /*******************************************************************************
3300 * Function Name: Cy_GPIO_SetInterruptEdge
3301 ****************************************************************************//**
3302 *
3303 * Configures the type of edge that will trigger a pin interrupt.
3304 *
3305 * \param base
3306 * Pointer to the pin's port register base address
3307 *
3308 * \param pinNum
3309 * Position of the pin bit-field within the port register.
3310 * Bit position 8 is the routed pin through the port glitch filter.
3311 *
3312 * \param value
3313 * Pin interrupt mode. Options are detailed in \ref group_gpio_interruptTrigger macros
3314 *
3315 * \note
3316 * This function modifies a port register in a read-modify-write operation. It is
3317 * not thread safe as the resource is shared among multiple pins on a port.
3318 *
3319 * \funcusage
3320 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetInterruptEdge
3321 *
3322 *******************************************************************************/
Cy_GPIO_SetInterruptEdge(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)3323 void Cy_GPIO_SetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
3324 {
3325 uint32_t tempReg;
3326 uint32_t pinLoc;
3327 uint32_t intrCfg;
3328
3329 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3330 cy_en_pra_pin_prot_type_t pinType;
3331 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3332
3333 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
3334 CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(value));
3335
3336 pinLoc = pinNum << CY_GPIO_INTR_CFG_OFFSET;
3337 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3338 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
3339 #if defined(CY_DEVICE_PSOC6ABLE2)
3340 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3341 {
3342 tempReg= CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG)) & ~(CY_GPIO_INTR_EDGE_MASK << pinLoc);
3343 }
3344 else if (pinType == CY_PRA_PIN_SECURE_NONE)
3345 {
3346 tempReg = GPIO_PRT_INTR_CFG(base) & ~(CY_GPIO_INTR_EDGE_MASK << pinLoc);
3347 }
3348 else
3349 {
3350 /* secure pin */
3351 tempReg = 0UL;
3352 }
3353 #else
3354 tempReg = GPIO_PRT_INTR_CFG(base) & ~(CY_GPIO_INTR_EDGE_MASK << pinLoc);
3355 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
3356 #else
3357 tempReg = GPIO_PRT_INTR_CFG(base) & ~(CY_GPIO_INTR_EDGE_MASK << pinLoc);
3358 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3359
3360 intrCfg = tempReg | ((value & CY_GPIO_INTR_EDGE_MASK) << pinLoc);
3361
3362 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3363 if (pinType != CY_PRA_PIN_SECURE)
3364 {
3365 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3366 {
3367 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG), intrCfg);
3368 }
3369 else
3370 {
3371 GPIO_PRT_INTR_CFG(base) = intrCfg;
3372 }
3373 }
3374 else
3375 {
3376 /* Secure PIN can't be modified using register policy */
3377 }
3378 #else
3379 GPIO_PRT_INTR_CFG(base) = intrCfg;
3380 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3381 }
3382
3383
3384 /*******************************************************************************
3385 * Function Name: Cy_GPIO_GetInterruptEdge
3386 ****************************************************************************//**
3387 *
3388 * Returns the current pin interrupt edge type.
3389 *
3390 * \param base
3391 * Pointer to the pin's port register base address
3392 *
3393 * \param pinNum
3394 * Position of the pin bit-field within the port register.
3395 * Bit position 8 is the routed pin through the port glitch filter.
3396 *
3397 * \return
3398 * Pin interrupt mode. Options are detailed in \ref group_gpio_interruptTrigger macros
3399 *
3400 * \funcusage
3401 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetInterruptEdge
3402 *
3403 *******************************************************************************/
Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type * base,uint32_t pinNum)3404 uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum)
3405 {
3406 uint32_t tempReg;
3407 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
3408 cy_en_pra_pin_prot_type_t pinType;
3409 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
3410
3411 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
3412
3413 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
3414 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
3415 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3416 {
3417 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG));
3418 }
3419 else if (pinType == CY_PRA_PIN_SECURE_NONE)
3420 {
3421 tempReg = GPIO_PRT_INTR_CFG(base);
3422 }
3423 else
3424 {
3425 /* secure pin */
3426 tempReg = 0UL;
3427 }
3428 #else
3429 tempReg = GPIO_PRT_INTR_CFG(base);
3430 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
3431
3432 return (tempReg >> (pinNum << CY_GPIO_INTR_CFG_OFFSET)) & CY_GPIO_INTR_EDGE_MASK;
3433 }
3434
3435
3436 /*******************************************************************************
3437 * Function Name: Cy_GPIO_SetFilter
3438 ****************************************************************************//**
3439 *
3440 * Configures which pin on the port connects to the port-specific glitch filter.
3441 *
3442 * Each port contains a single 50ns glitch filter. Any of the pins on the port
3443 * can be routed to this filter such that the input signal is filtered before
3444 * reaching the edge-detect interrupt circuitry. The state of the filtered pin
3445 * can also be read by calling the Cy_GPIO_Read() function.
3446 *
3447 * \param base
3448 * Pointer to the pin's port register base address
3449 *
3450 * \param value
3451 * The number of the port pin to route to the port filter (0...7)
3452 *
3453 * \note
3454 * This function modifies a port register in a read-modify-write operation. It is
3455 * not thread safe as the resource is shared among multiple pins on a port.
3456 *
3457 * \note
3458 * The filtered pin does not have an associated HSIOM connection. Therefore
3459 * it cannot be routed directly to other peripherals in hardware.
3460 *
3461 * \funcusage
3462 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetFilter
3463 *
3464 *******************************************************************************/
Cy_GPIO_SetFilter(GPIO_PRT_Type * base,uint32_t value)3465 void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value)
3466 {
3467 uint32_t tempReg;
3468 uint32_t intrCfg;
3469
3470 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3471 cy_en_pra_pin_prot_type_t pinType;
3472 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3473
3474 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(value));
3475
3476 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3477 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, value);
3478 #if defined(CY_DEVICE_PSOC6ABLE2)
3479 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3480 {
3481 tempReg= CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG)) & ~(CY_GPIO_INTR_FLT_EDGE_MASK << CY_GPIO_INTR_FILT_OFFSET);
3482 }
3483 else if (pinType == CY_PRA_PIN_SECURE_NONE)
3484 {
3485 tempReg = GPIO_PRT_INTR_CFG(base) & ~(CY_GPIO_INTR_FLT_EDGE_MASK << CY_GPIO_INTR_FILT_OFFSET);
3486 }
3487 else
3488 {
3489 /* secure pin */
3490 tempReg = 0UL;
3491 }
3492 #else
3493 tempReg = GPIO_PRT_INTR_CFG(base) & ~(CY_GPIO_INTR_FLT_EDGE_MASK << CY_GPIO_INTR_FILT_OFFSET);
3494 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
3495 #else
3496 tempReg = GPIO_PRT_INTR_CFG(base) & ~(CY_GPIO_INTR_FLT_EDGE_MASK << CY_GPIO_INTR_FILT_OFFSET);
3497 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3498
3499 intrCfg = tempReg | ((value & CY_GPIO_INTR_FLT_EDGE_MASK) << CY_GPIO_INTR_FILT_OFFSET);
3500
3501 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3502 if (pinType != CY_PRA_PIN_SECURE)
3503 {
3504 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3505 {
3506 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG), intrCfg);
3507 }
3508 else
3509 {
3510 GPIO_PRT_INTR_CFG(base) = intrCfg;
3511 }
3512 }
3513 else
3514 {
3515 /* Secure PIN can't be modified using register policy */
3516 }
3517 #else
3518 GPIO_PRT_INTR_CFG(base) = intrCfg;
3519 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3520 }
3521
3522
3523 /*******************************************************************************
3524 * Function Name: Cy_GPIO_GetFilter
3525 ****************************************************************************//**
3526 *
3527 * Returns which pin is currently configured to connect to the port-specific
3528 * glitch filter.
3529 *
3530 * Each port contains a single 50ns glitch filter. Any of the pins on the port
3531 * can be routed to this filter such that the input signal is filtered before
3532 * reaching the edge-detect interrupt circuitry. The state of the filtered pin
3533 * can also be read by calling the Cy_GPIO_Read() function.
3534 *
3535 * \param base
3536 * Pointer to the pin's port register base address
3537 *
3538 * \return
3539 * The number of the port pin routed to the port filter (0...7)
3540 *
3541 * \funcusage
3542 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetFilter
3543 *
3544 *******************************************************************************/
Cy_GPIO_GetFilter(GPIO_PRT_Type * base)3545 uint32_t Cy_GPIO_GetFilter(GPIO_PRT_Type* base)
3546 {
3547 uint32_t tempReg;
3548 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
3549 if (CY_PRA_IS_PORT_SECURE(base))
3550 {
3551 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG));
3552 }
3553 else
3554 {
3555 tempReg = GPIO_PRT_INTR_CFG(base);
3556 }
3557 #else
3558 tempReg = GPIO_PRT_INTR_CFG(base);
3559 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
3560
3561 return ((tempReg >> CY_GPIO_INTR_FILT_OFFSET) & CY_GPIO_INTR_FLT_EDGE_MASK);
3562 }
3563
3564 #if defined (CY_IP_MXS22IOSS)
3565 /*******************************************************************************
3566 * Function Name: Cy_GPIO_SetPullupResistance
3567 ****************************************************************************//**
3568 *
3569 * Configures the GPIO pin Pull-up mode.
3570 *
3571 * \param base
3572 * Pointer to the pin's port register base address
3573 *
3574 * \param pinNum
3575 * Position of the pin bit-field within the port register
3576 *
3577 * \param value
3578 * Pull-up mode for a pin. Options are detailed in
3579 * \ref group_gpio_PullUpMode macros
3580 *
3581 * \note
3582 * This API configures pull-up resistors only when
3583 * \ref CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ is selected. For all other pin drive
3584 * modes, it disables additional pull-up resistors.
3585 *
3586 * \note
3587 * This API modifies a port register in a read-modify-write operation. It is
3588 * not thread safe as the resource is shared among multiple pins on a port.
3589 *
3590 * \note
3591 * This API is available for the CAT1D devices.
3592 *
3593 * \funcusage
3594 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetPullupResistance
3595 *
3596 *******************************************************************************/
Cy_GPIO_SetPullupResistance(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)3597 void Cy_GPIO_SetPullupResistance(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
3598 {
3599 uint32_t tempReg, pinLoc, prtCfg;
3600
3601 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
3602 CY_ASSERT_L2(CY_GPIO_IS_PULLUP_RES_VALID(value));
3603
3604 if(Cy_GPIO_GetDrivemode(base, pinNum) != CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ)
3605 {
3606 value = CY_GPIO_PULLUP_RES_DISABLE;
3607 }
3608
3609 pinLoc = pinNum << CY_GPIO_CFG_RES_PULLUP_MODE_OFFSET;
3610 tempReg = (GPIO_PRT_CFG_RES(base) & ~(CY_GPIO_CFG_RES_PULLUP_MODE_MASK << pinLoc));
3611 prtCfg = tempReg | ((value & CY_GPIO_CFG_RES_PULLUP_MODE_MASK) << pinLoc);
3612
3613 GPIO_PRT_CFG_RES(base) = prtCfg;
3614 }
3615
3616 /*******************************************************************************
3617 * Function Name: Cy_GPIO_GetPullupResistance
3618 ****************************************************************************//**
3619 *
3620 * Returns the Pull-up mode of GPIO Pin.
3621 *
3622 * \param base
3623 * Pointer to the pin's port register base address
3624 *
3625 * \param pinNum
3626 * Position of the pin bit-field within the port register
3627 *
3628 * \return
3629 * Pull-up mode. Options are detailed in \ref group_gpio_PullUpMode macros
3630 *
3631 * \note
3632 * This API is available for the CAT1D devices.
3633 *
3634 * \funcusage
3635 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetPullupResistance
3636 *
3637 *******************************************************************************/
Cy_GPIO_GetPullupResistance(GPIO_PRT_Type * base,uint32_t pinNum)3638 uint32_t Cy_GPIO_GetPullupResistance(GPIO_PRT_Type* base, uint32_t pinNum)
3639 {
3640 uint32_t tempReg;
3641
3642 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
3643
3644 tempReg = GPIO_PRT_CFG_RES(base);
3645
3646 return ((tempReg >> (pinNum << CY_GPIO_CFG_RES_PULLUP_MODE_OFFSET)) & CY_GPIO_CFG_RES_PULLUP_MODE_MASK);
3647 }
3648 #endif /* CY_IP_MXS22IOSS */
3649
3650 #if defined(__cplusplus)
3651 }
3652 #endif
3653
3654 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS40IOSS, CY_IP_MXS22IOSS */
3655 /* [] END OF FILE */
3656
