1 /***************************************************************************//**
2 * \file cy_gpio.c
3 * \version 1.90
4 *
5 * Provides an API implementation of the GPIO driver
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_device.h"
27
28 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS40IOSS) || defined (CY_IP_MXS22IOSS)
29
30 #include "cy_gpio.h"
31 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
32 #include "cy_pra.h"
33 #endif
34
35 #if defined(__cplusplus)
36 extern "C" {
37 #endif
38
39
40 /* Define for AMUX A splitters */
41 #define GPIO_AMUXA_SPLITTER_MASK (uint32_t)(HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk \
42 | HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk \
43 | HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk)
44
45 /* Define for AMUX B splitters */
46 #define GPIO_AMUXB_SPLITTER_MASK (uint32_t)(HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk \
47 | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk \
48 | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk)
49
50 /*******************************************************************************
51 * Function Name: Cy_GPIO_Pin_Init
52 ****************************************************************************//**
53 *
54 * Initializes all pin configuration settings for the specified pin.
55 *
56 * \param base
57 * Pointer to the pin's port register base address
58 *
59 * \param pinNum
60 * Position of the pin bit-field within the port register
61 *
62 * \param config
63 * Pointer to the pin config structure base address
64 *
65 * \return
66 * Initialization status
67 *
68 * \note
69 * This function modifies port registers in read-modify-write operations. It is
70 * not thread safe as the resource is shared among multiple pins on a port.
71 *
72 * \note
73 * When EXT_CLK is source to HF0 and this API is called from application then
74 * make sure that the drivemode argument is CY_GPIO_DM_HIGHZ.
75 *
76 * \funcusage
77 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Pin_Init
78 *
79 *******************************************************************************/
Cy_GPIO_Pin_Init(GPIO_PRT_Type * base,uint32_t pinNum,const cy_stc_gpio_pin_config_t * config)80 cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const cy_stc_gpio_pin_config_t *config)
81 {
82 cy_en_gpio_status_t status = CY_GPIO_BAD_PARAM;
83
84 if ((NULL != base) && (NULL != config))
85 {
86 #if defined (CY_IP_MXS40IOSS)
87 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
88 cy_en_pra_pin_prot_type_t pinType;
89 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
90 uint32_t maskCfgOut;
91 #endif /* CY_IP_MXS40IOSS */
92 uint32_t tempReg, tempReg2;
93
94 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
95 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->outVal));
96 CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(config->driveMode));
97 CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(config->hsiom));
98 CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(config->intEdge));
99 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->intMask));
100 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtrip));
101
102 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vregEn));
103 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->ibufMode));
104 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtripSel));
105 CY_ASSERT_L2(CY_GPIO_IS_VREF_SEL_VALID(config->vrefSel));
106 CY_ASSERT_L2(CY_GPIO_IS_VOH_SEL_VALID(config->vohSel));
107 CY_ASSERT_L2(CY_GPIO_IS_DRIVE_SEL_VALID(config->driveSel));
108
109 #if defined (CY_IP_MXS22IOSS)
110 CY_ASSERT_L2(CY_GPIO_IS_PULLUP_RES_VALID(config->pullUpRes));
111 #endif /* CY_IP_MXS22IOSS */
112
113 /* Slew rate and Driver strength */
114 #if defined (CY_IP_MXS40IOSS)
115 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->slewRate));
116 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
117
118 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
119
120 if (pinType == CY_PRA_PIN_SECURE)
121 {
122 return(status); /* Protected pins are not allowed to configure */
123 }
124 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
125 maskCfgOut = (CY_GPIO_CFG_OUT_SLOW_MASK << pinNum)
126 | (CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << ((uint32_t)(pinNum << 1U) + CY_GPIO_CFG_OUT_DRIVE_OFFSET));
127
128 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
129 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
130 {
131 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT)) & ~(maskCfgOut);
132 }
133 else
134 {
135 tempReg = GPIO_PRT_CFG_OUT(base) & ~(maskCfgOut);
136 }
137 #else
138 tempReg = GPIO_PRT_CFG_OUT(base) & ~(maskCfgOut);
139 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
140
141 tempReg2 = tempReg | ((config->slewRate & CY_GPIO_CFG_OUT_SLOW_MASK) << pinNum)
142 | ((config->driveSel & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << ((uint32_t)(pinNum << 1U) + CY_GPIO_CFG_OUT_DRIVE_OFFSET));
143
144 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
145 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
146 {
147 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT), tempReg2);
148 }
149 else /* non-secure pin */
150 {
151 GPIO_PRT_CFG_OUT(base) = tempReg2;
152 }
153 #else
154 GPIO_PRT_CFG_OUT(base) = tempReg2;
155 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
156
157 #else
158 CY_ASSERT_L2(CY_GPIO_IS_SLEW_RATE_VALID(config->slewRate));
159 #if ((defined (IOSS_HSIOM_HSIOM_SEC_PORT_NR) && (IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0)) || (CPUSS_CM33_0_SECEXT_PRESENT != 0))
160 CY_ASSERT_L2(CY_GPIO_IS_HSIOM_SEC_VALID(config->nonSec));
161 Cy_GPIO_SetHSIOM_SecPin(base, pinNum, config->nonSec);
162 #endif /* IOSS_HSIOM_HSIOM_SEC_PORT_NR, CPUSS_CM33_0_SECEXT_PRESENT */
163 Cy_GPIO_SetSlewRate(base, pinNum, config->slewRate);
164 Cy_GPIO_SetDriveSel(base, pinNum, config->driveSel);
165 #endif /* CY_IP_MXS40IOSS */
166 Cy_GPIO_SetHSIOM(base, pinNum, config->hsiom);
167 Cy_GPIO_SetDrivemode(base, pinNum, config->driveMode);
168
169 Cy_GPIO_SetInterruptEdge(base, pinNum, config->intEdge);
170 Cy_GPIO_SetInterruptMask(base, pinNum, config->intMask);
171 Cy_GPIO_SetVtrip(base, pinNum, config->vtrip);
172
173 /* SIO specific configuration */
174 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
175 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
176 {
177 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO)) & ~(CY_GPIO_SIO_PIN_MASK);
178 }
179 else
180 {
181 tempReg = GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_SIO_PIN_MASK);
182 }
183 #else
184 tempReg = GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_SIO_PIN_MASK);
185 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
186
187 tempReg2 = tempReg | (((config->vregEn & CY_GPIO_VREG_EN_MASK)
188 | ((config->ibufMode & CY_GPIO_IBUF_MASK) << CY_GPIO_IBUF_SHIFT)
189 | ((config->vtripSel & CY_GPIO_VTRIP_SEL_MASK) << CY_GPIO_VTRIP_SEL_SHIFT)
190 | ((config->vrefSel & CY_GPIO_VREF_SEL_MASK) << CY_GPIO_VREF_SEL_SHIFT)
191 | ((config->vohSel & CY_GPIO_VOH_SEL_MASK) << CY_GPIO_VOH_SEL_SHIFT))
192 << ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET));
193
194 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
195 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
196 {
197 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), tempReg2);
198 }
199 else /* non-secure pin */
200 {
201 GPIO_PRT_CFG_SIO(base) = tempReg2;
202 }
203 #else
204 GPIO_PRT_CFG_SIO(base) = tempReg2;
205 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
206
207 #if defined (CY_IP_MXS22IOSS)
208 Cy_GPIO_SetPullupResistance(base, pinNum, config->pullUpRes);
209 #endif /* CY_IP_MXS22IOSS */
210
211 Cy_GPIO_Write(base, pinNum, config->outVal);
212
213 status = CY_GPIO_SUCCESS;
214 }
215
216 return(status);
217 }
218
219
220 /*******************************************************************************
221 * Function Name: Cy_GPIO_Port_Init
222 ****************************************************************************//**
223 *
224 * Initialize a complete port of pins from a single init structure.
225 *
226 * The configuration structure used in this function has a 1:1 mapping to the
227 * GPIO and HSIOM registers. Refer to the device Technical Reference Manual (TRM)
228 * for the register details on how to populate them.
229 *
230 * \param base
231 * Pointer to the pin's port register base address
232 *
233 * \param config
234 * Pointer to the pin config structure base address
235 *
236 * \return
237 * Initialization status
238 *
239 * \note
240 * If using the PSoC Creator IDE, there is no need to initialize the pins when
241 * using the GPIO component on the schematic. Ports are configured in
242 * Cy_SystemInit() before main() entry.
243 *
244 * \funcusage
245 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Port_Init
246 *
247 *******************************************************************************/
Cy_GPIO_Port_Init(GPIO_PRT_Type * base,const cy_stc_gpio_prt_config_t * config)248 cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt_config_t *config)
249 {
250 cy_en_gpio_status_t status = CY_GPIO_BAD_PARAM;
251
252 if ((NULL != base) && (NULL != config))
253 {
254 uint32_t portNum;
255 HSIOM_PRT_V1_Type* baseHSIOM;
256 #if (defined (CY_IP_MXS40SIOSS) && ((IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0) || (CPUSS_CM33_0_SECEXT_PRESENT != 0))) || defined (CY_IP_MXS22IOSS)
257 HSIOM_SECURE_PRT_Type *baseSecHSIOM;
258 #else
259 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
260 bool secPort;
261 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
262 #endif /* CY_IP_MXS40SIOSS, IOSS_HSIOM_HSIOM_SEC_PORT_NR, CPUSS_CM33_0_SECEXT_PRESENT, CY_IP_MXS22IOSS */
263 portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
264 baseHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
265
266 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
267 if ((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) || (base == (GPIO_PRT_Type*)((void*)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0)))
268 {
269 portNum = 0;
270 baseHSIOM = (HSIOM_PRT_V1_Type*) ((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) ? ((void*)SMIF0_CORE0_SMIF_HSIOM_SMIF_PRT0) : ((void*)SMIF0_CORE1_SMIF_HSIOM_SMIF_PRT0));
271 }
272 #endif
273
274 CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->out));
275 CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->cfgIn));
276 CY_ASSERT_L2(CY_GPIO_IS_INTR_CFG_VALID(config->intrCfg));
277 CY_ASSERT_L2(CY_GPIO_IS_INTR_MASK_VALID(config->intrMask));
278 CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel0Active));
279 CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel1Active));
280
281 #if defined (CY_IP_MXS22IOSS)
282 CY_ASSERT_L2(CY_GPIO_PRT_IS_PULLUP_RES_VALID(config->cfgRes));
283 #endif /* CY_IP_MXS22IOSS */
284
285 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS22IOSS)
286 #if ((defined (IOSS_HSIOM_HSIOM_SEC_PORT_NR) && (IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0)) || (CPUSS_CM33_0_SECEXT_PRESENT != 0))
287 CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->nonSecMask));
288 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
289 if ((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) || (base == (GPIO_PRT_Type*)((void*)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0)))
290 {
291 baseSecHSIOM = (HSIOM_SECURE_PRT_Type*) ((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) ? ((void*)SMIF0_CORE0_SMIF_HSIOM_SMIF_SECURE_PRT0) : ((void*)SMIF0_CORE1_SMIF_HSIOM_SMIF_SECURE_PRT0));
292 }
293 else
294 {
295 baseSecHSIOM = (HSIOM_SECURE_PRT_Type*)(CY_HSIOM_SECURE_BASE + (HSIOM_SECURE_PRT_SECTION_SIZE * portNum));
296 }
297 #else
298 baseSecHSIOM = (HSIOM_SECURE_PRT_Type*)(CY_HSIOM_SECURE_BASE + (HSIOM_SECURE_PRT_SECTION_SIZE * portNum));
299 #endif /* CY_IP_MXSMIF, CY_IP_MXSMIF_VERSION */
300 HSIOM_SEC_PRT_NONSEC_MASK(baseSecHSIOM) = config->nonSecMask;
301 #endif /* IOSS_HSIOM_HSIOM_SEC_PORT_NR, CPUSS_CM33_0_SECEXT_PRESENT */
302 GPIO_PRT_SLEW_EXT(base) = config->cfgSlew;
303 GPIO_PRT_DRIVE_EXT0(base) = config->cfgDriveSel0;
304 GPIO_PRT_DRIVE_EXT1(base) = config->cfgDriveSel1;
305 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
306
307 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
308 secPort = CY_PRA_IS_PORT_SECURE(base);
309 if (secPort)
310 {
311 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG), config->cfg);
312 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_IN), config->cfgIn);
313 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT), config->cfgOut);
314 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG), config->intrCfg);
315 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_MASK), config->intrMask);
316 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), config->cfgSIO);
317 CY_PRA_REG32_SET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0), config->sel0Active);
318 CY_PRA_REG32_SET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1), config->sel1Active);
319 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT), config->out);
320 }
321 else
322 {
323 GPIO_PRT_CFG(base) = config->cfg;
324 GPIO_PRT_CFG_IN(base) = config->cfgIn;
325 GPIO_PRT_CFG_OUT(base) = config->cfgOut;
326 GPIO_PRT_INTR_CFG(base) = config->intrCfg;
327 GPIO_PRT_INTR_MASK(base) = config->intrMask;
328 GPIO_PRT_CFG_SIO(base) = config->cfgSIO;
329 /* For 1M device check for secure HSIOM */
330 #if defined(CY_DEVICE_PSOC6ABLE2)
331 if (CY_PRA_IS_HSIOM_SECURE(base))
332 {
333 CY_PRA_REG32_SET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0), config->sel0Active);
334 CY_PRA_REG32_SET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1), config->sel1Active);
335 }
336 else
337 {
338 HSIOM_PRT_PORT_SEL0(baseHSIOM) = config->sel0Active;
339 HSIOM_PRT_PORT_SEL1(baseHSIOM) = config->sel1Active;
340 }
341 #else
342 HSIOM_PRT_PORT_SEL0(baseHSIOM) = config->sel0Active;
343 HSIOM_PRT_PORT_SEL1(baseHSIOM) = config->sel1Active;
344 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
345 GPIO_PRT_OUT(base) = config->out;
346 }
347 #else
348 GPIO_PRT_CFG(base) = config->cfg;
349 GPIO_PRT_CFG_IN(base) = config->cfgIn;
350 GPIO_PRT_CFG_OUT(base) = config->cfgOut;
351 GPIO_PRT_INTR_CFG(base) = config->intrCfg;
352 GPIO_PRT_INTR_MASK(base) = config->intrMask;
353 GPIO_PRT_CFG_SIO(base) = config->cfgSIO;
354 HSIOM_PRT_PORT_SEL0(baseHSIOM) = config->sel0Active;
355 HSIOM_PRT_PORT_SEL1(baseHSIOM) = config->sel1Active;
356 GPIO_PRT_OUT(base) = config->out;
357 #if defined (CY_IP_MXS22IOSS)
358 GPIO_PRT_CFG_OUT3(base) = config->cfgOut3;
359 GPIO_PRT_CFG_RES(base) = config->cfgRes;
360 #endif /* CY_IP_MXS22IOSS */
361 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
362
363 status = CY_GPIO_SUCCESS;
364 }
365
366 return (status);
367 }
368
369
370 /*******************************************************************************
371 * Function Name: Cy_GPIO_Pin_FastInit
372 ****************************************************************************//**
373 *
374 * Initialize the most common configuration settings for all pin types.
375 *
376 * These include, drive mode, initial output value, and HSIOM connection.
377 *
378 * \param base
379 * Pointer to the pin's port register base address
380 *
381 * \param pinNum
382 * Position of the pin bit-field within the port register
383 *
384 * \param driveMode
385 * Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros
386 *
387 * \param outVal
388 * Logic state of the output buffer driven to the pin (1 or 0)
389 *
390 * \param hsiom
391 * HSIOM input selection
392 *
393 * \note
394 * This function modifies port registers in read-modify-write operations. It is
395 * not thread safe as the resource is shared among multiple pins on a port.
396 * You can use the Cy_SysLib_EnterCriticalSection() and
397 * Cy_SysLib_ExitCriticalSection() functions to ensure that
398 * Cy_GPIO_Pin_FastInit() function execution is not interrupted.
399 *
400 * \note
401 * When EXT_CLK is source to HF0 and this API is called from application then
402 * make sure that the drivemode argument is CY_GPIO_DM_HIGHZ.
403 *
404 * \note
405 * This doesn't set pull-up resistance value. By default. the pull-up resistance
406 * is disabled. To select it, use Cy_GPIO_SetPullupResistance.
407 *
408 * \funcusage
409 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Pin_FastInit
410 *
411 *******************************************************************************/
Cy_GPIO_Pin_FastInit(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t driveMode,uint32_t outVal,en_hsiom_sel_t hsiom)412 void Cy_GPIO_Pin_FastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode,
413 uint32_t outVal, en_hsiom_sel_t hsiom)
414 {
415 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
416 cy_en_pra_pin_prot_type_t pinType;
417 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
418
419 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
420 CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(driveMode));
421 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(outVal));
422 CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(hsiom));
423
424 uint32_t tempReg;
425 #if defined (CY_IP_MXS22IOSS)
426 uint32_t tempRegCfg3;
427 #endif /* CY_IP_MXS22IOSS */
428
429 Cy_GPIO_SetHSIOM(base, pinNum, hsiom);
430
431 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
432 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
433
434 if (pinType != CY_PRA_PIN_SECURE)
435 {
436 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
437 {
438 #if defined(CY_DEVICE_PSOC6ABLE2)
439 tempReg = (CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT)) & ~(CY_GPIO_OUT_MASK << pinNum));
440 #else
441 tempReg = (GPIO_PRT_OUT(base) & ~(CY_GPIO_OUT_MASK << pinNum));
442 #endif
443 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT), (tempReg | ((outVal & CY_GPIO_OUT_MASK) << pinNum)));
444
445 #if defined(CY_DEVICE_PSOC6ABLE2)
446 tempReg = (CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG)) & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
447 #else
448 tempReg = (GPIO_PRT_CFG(base) & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
449 #endif
450 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG), (tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET))));
451 }
452 else /* non secure pin */
453 {
454 tempReg = (GPIO_PRT_OUT(base) & ~(CY_GPIO_OUT_MASK << pinNum));
455 GPIO_PRT_OUT(base) = tempReg | ((outVal & CY_GPIO_OUT_MASK) << pinNum);
456
457 tempReg = (GPIO_PRT_CFG(base) & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
458 GPIO_PRT_CFG(base) = tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
459 }
460 }
461 else
462 {
463 /* Secure PIN can't be modified using register policy */
464 }
465 #else
466 tempReg = (GPIO_PRT_OUT(base) & ~(CY_GPIO_OUT_MASK << pinNum));
467 GPIO_PRT_OUT(base) = tempReg | ((outVal & CY_GPIO_OUT_MASK) << pinNum);
468
469 tempReg = (GPIO_PRT_CFG(base) & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
470 #if defined (CY_IP_MXS22IOSS)
471 tempRegCfg3 = (GPIO_PRT_CFG_OUT3(base) & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
472
473 if(CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ == driveMode)
474 {
475 /* Enable CFG_OUT3 register and configure the extra drive mode. */
476 GPIO_PRT_CFG(base) = tempReg | ((0U & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
477 GPIO_PRT_CFG_OUT3(base) = tempRegCfg3 | (((driveMode >> CY_GPIO_EXT_DM_SHIFT) & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
478 }
479 else
480 {
481 /* If High-Z drive mode is selected, enable CFG_OUT3 register using CFG register and configure drive mode using CFG_OUT3 register. */
482 /* For other drive modes, disable CFG_OUT3 register and use CFG register to configure drive modes. */
483 GPIO_PRT_CFG(base) = tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
484 GPIO_PRT_CFG_OUT3(base) = tempRegCfg3 | ((0U & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
485 }
486 #else
487 GPIO_PRT_CFG(base) = tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
488 #endif /* CY_IP_MXS22IOSS */
489 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
490 }
491
492 #if (defined (CY_IP_MXS40SIOSS) && ((IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0) || (CPUSS_CM33_0_SECEXT_PRESENT != 0))) || defined (CY_IP_MXS22IOSS)
493 /*******************************************************************************
494 * Function Name: Cy_GPIO_Pin_SecFastInit
495 ****************************************************************************//**
496 *
497 * Initialize the most common configuration settings for all pin types.
498 *
499 * These include, drive mode, initial output value, and HSIOM connection. This
500 * function should be called from appropriate protection context where secure
501 * HSIOM port (HSIOM_SECURE_PRT_Type) is accessible.
502 *
503 * \param base
504 * Pointer to the pin's port register base address
505 *
506 * \param pinNum
507 * Position of the pin bit-field within the port register
508 *
509 * \param driveMode
510 * Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros
511 *
512 * \param outVal
513 * Logic state of the output buffer driven to the pin (1 or 0)
514 *
515 * \param hsiom
516 * HSIOM input selection
517 *
518 * \note
519 * This function modifies port registers in read-modify-write operations. It is
520 * not thread safe as the resource is shared among multiple pins on a port.
521 * You can use the Cy_SysLib_EnterCriticalSection() and
522 * Cy_SysLib_ExitCriticalSection() functions to ensure that
523 * Cy_GPIO_Pin_SecFastInit() function execution is not interrupted.
524 *
525 * \note
526 * This API is only available for the CAT1B and CAT1D devices.
527 *
528 *******************************************************************************/
Cy_GPIO_Pin_SecFastInit(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t driveMode,uint32_t outVal,en_hsiom_sel_t hsiom)529 void Cy_GPIO_Pin_SecFastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode,
530 uint32_t outVal, en_hsiom_sel_t hsiom)
531 {
532 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
533 CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(driveMode));
534 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(outVal));
535 CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(hsiom));
536
537 uint32_t tempReg;
538 #if defined (CY_IP_MXS22IOSS)
539 uint32_t tempRegCfg3;
540 #endif /* CY_IP_MXS22IOSS */
541
542 Cy_GPIO_SetHSIOM_SecPin(base, pinNum, 0UL); /* make the pin as secure */
543
544 tempReg = (GPIO_PRT_CFG(base) & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
545 #if defined (CY_IP_MXS22IOSS)
546 tempRegCfg3 = (GPIO_PRT_CFG_OUT3(base) & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
547
548 if(driveMode == CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ)
549 {
550 /* Enable CFG_OUT3 register and configure the extra drive mode. */
551 GPIO_PRT_CFG(base) = tempReg | ((0U & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
552 GPIO_PRT_CFG_OUT3(base) = tempRegCfg3 | (((driveMode >> CY_GPIO_EXT_DM_SHIFT) & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
553 }
554 else
555 {
556 /* If High-Z drive mode is selected, enable CFG_OUT3 register using CFG register and configure drive mode using CFG_OUT3 register. */
557 /* For other drive modes, disable CFG_OUT3 register and use CFG register to configure drive modes. */
558 GPIO_PRT_CFG(base) = tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
559 GPIO_PRT_CFG_OUT3(base) = tempRegCfg3 | ((0U & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
560 }
561 #else
562 GPIO_PRT_CFG(base) = tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
563 #endif /* CY_IP_MXS22IOSS */
564
565 Cy_GPIO_SetHSIOM(base, pinNum, hsiom);
566
567 tempReg = (GPIO_PRT_OUT(base) & ~(CY_GPIO_OUT_MASK << pinNum));
568 GPIO_PRT_OUT(base) = tempReg | ((outVal & CY_GPIO_OUT_MASK) << pinNum);
569
570 }
571 #endif /* CY_IP_MXS40SIOSS, IOSS_HSIOM_HSIOM_SEC_PORT_NR, CPUSS_CM33_0_SECEXT_PRESENT, CY_IP_MXS22IOSS */
572
573 /*******************************************************************************
574 * Function Name: Cy_GPIO_Port_Deinit
575 ****************************************************************************//**
576 *
577 * Reset a complete port of pins back to power on reset defaults.
578 *
579 * \param base
580 * Pointer to the pin's port register base address
581 *
582 * \funcusage
583 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Port_Deinit
584 *
585 *******************************************************************************/
Cy_GPIO_Port_Deinit(GPIO_PRT_Type * base)586 void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base)
587 {
588 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
589 bool secPort;
590 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
591 uint32_t portNum;
592 HSIOM_PRT_V1_Type* baseHSIOM;
593 portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
594 baseHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
595
596 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
597 if ((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) || (base == (GPIO_PRT_Type*)((void*)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0)))
598 {
599 portNum = 0;
600 baseHSIOM = (HSIOM_PRT_V1_Type*) ((void*)((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) ? ((void*)SMIF0_CORE0_SMIF_HSIOM_SMIF_PRT0) : ((void*)SMIF0_CORE1_SMIF_HSIOM_SMIF_PRT0)));
601 }
602 #endif
603
604 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS22IOSS)
605 #if ((defined (IOSS_HSIOM_HSIOM_SEC_PORT_NR) && (IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0)) || (CPUSS_CM33_0_SECEXT_PRESENT != 0 ))
606 HSIOM_SECURE_PRT_Type *baseSecHSIOM;
607 baseSecHSIOM = (HSIOM_SECURE_PRT_Type*)(CY_HSIOM_SECURE_BASE + (HSIOM_SECURE_PRT_SECTION_SIZE * portNum));
608 HSIOM_SEC_PRT_NONSEC_MASK(baseSecHSIOM) = CY_HSIOM_NONSEC_DEINIT;
609 #endif /* IOSS_HSIOM_HSIOM_SEC_PORT_NR, CPUSS_CM33_0_SECEXT_PRESENT */
610 GPIO_PRT_SLEW_EXT(base) = CY_GPIO_PRT_DEINIT;
611 GPIO_PRT_DRIVE_EXT0(base) = CY_GPIO_PRT_DEINIT;
612 GPIO_PRT_DRIVE_EXT1(base) = CY_GPIO_PRT_DEINIT;
613 #endif /* CY_IP_MXS40SIOSS */
614
615 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
616 secPort = CY_PRA_IS_PORT_SECURE(base);
617 if (secPort)
618 {
619 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT), CY_GPIO_PRT_DEINIT);
620 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG), CY_GPIO_PRT_DEINIT);
621 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_IN), CY_GPIO_PRT_DEINIT);
622 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT), CY_GPIO_PRT_DEINIT);
623 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG), CY_GPIO_PRT_DEINIT);
624 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_MASK), CY_GPIO_PRT_DEINIT);
625 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), CY_GPIO_PRT_DEINIT);
626 CY_PRA_REG32_SET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0), CY_GPIO_PRT_DEINIT);
627 CY_PRA_REG32_SET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1), CY_GPIO_PRT_DEINIT);
628
629 }
630 else
631 {
632 GPIO_PRT_OUT(base) = CY_GPIO_PRT_DEINIT;
633 GPIO_PRT_CFG(base) = CY_GPIO_PRT_DEINIT;
634 GPIO_PRT_CFG_IN(base) = CY_GPIO_PRT_DEINIT;
635 GPIO_PRT_CFG_OUT(base) = CY_GPIO_PRT_DEINIT;
636 GPIO_PRT_INTR_CFG(base) = CY_GPIO_PRT_DEINIT;
637 GPIO_PRT_INTR_MASK(base) = CY_GPIO_PRT_DEINIT;
638 GPIO_PRT_CFG_SIO(base) = CY_GPIO_PRT_DEINIT;
639 /* For 1M device check for secure HSIOM */
640 #if defined(CY_DEVICE_PSOC6ABLE2)
641 if (CY_PRA_IS_HSIOM_SECURE(base))
642 {
643 CY_PRA_REG32_SET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0), CY_GPIO_PRT_DEINIT);
644 CY_PRA_REG32_SET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1), CY_GPIO_PRT_DEINIT);
645 }
646 else
647 {
648 HSIOM_PRT_PORT_SEL0(baseHSIOM) = CY_GPIO_PRT_DEINIT;
649 HSIOM_PRT_PORT_SEL1(baseHSIOM) = CY_GPIO_PRT_DEINIT;
650 }
651 #else
652 HSIOM_PRT_PORT_SEL0(baseHSIOM) = CY_GPIO_PRT_DEINIT;
653 HSIOM_PRT_PORT_SEL1(baseHSIOM) = CY_GPIO_PRT_DEINIT;
654 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
655 }
656 #else
657 GPIO_PRT_OUT(base) = CY_GPIO_PRT_DEINIT;
658 GPIO_PRT_CFG(base) = CY_GPIO_PRT_DEINIT;
659 GPIO_PRT_CFG_IN(base) = CY_GPIO_PRT_DEINIT;
660 GPIO_PRT_CFG_OUT(base) = CY_GPIO_PRT_DEINIT;
661 GPIO_PRT_INTR_CFG(base) = CY_GPIO_PRT_DEINIT;
662 GPIO_PRT_INTR_MASK(base) = CY_GPIO_PRT_DEINIT;
663 GPIO_PRT_CFG_SIO(base) = CY_GPIO_PRT_DEINIT;
664 HSIOM_PRT_PORT_SEL0(baseHSIOM) = CY_GPIO_PRT_DEINIT;
665 HSIOM_PRT_PORT_SEL1(baseHSIOM) = CY_GPIO_PRT_DEINIT;
666 #if defined (CY_IP_MXS22IOSS)
667 GPIO_PRT_CFG_OUT3(base) = CY_GPIO_PRT_DEINIT;
668 GPIO_PRT_CFG_RES(base) = CY_GPIO_PRT_DEINIT;
669 #endif /* CY_IP_MXS22IOSS */
670 #if (defined(CY_IP_MXS40IOSS) && (CY_IP_MXS40IOSS_VERSION == 3U))
671 GPIO_PRT_CFG_IN_AUTOLVL(base) = CY_GPIO_VTRIP_DIS_AUTO;
672 #endif /* CY_IP_MXS40IOSS_VERSION */
673 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
674 }
675
676
677 /*******************************************************************************
678 * Function Name: Cy_GPIO_SetAmuxSplit
679 ****************************************************************************//**
680 *
681 * Configure a specific AMux bus splitter switch cell into a specific
682 * configuration.
683 *
684 * \param switchCtrl
685 * Selects specific AMux bus splitter cell between two segments.
686 * The cy_en_amux_split_t enumeration can be found in the GPIO header file
687 * for the device package.
688 *
689 * \param amuxConnect
690 * Selects configuration of the three switches within the splitter cell
691 *
692 * \param amuxBus
693 * Selects which AMux bus within the splitter is being configured
694 *
695 * \note
696 * This API is available for the CAT1A and CAT1D devices.
697 *
698 *******************************************************************************/
Cy_GPIO_SetAmuxSplit(cy_en_amux_split_t switchCtrl,cy_en_gpio_amuxconnect_t amuxConnect,cy_en_gpio_amuxselect_t amuxBus)699 void Cy_GPIO_SetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxconnect_t amuxConnect,
700 cy_en_gpio_amuxselect_t amuxBus)
701 {
702 #if defined (CY_IP_MXS40IOSS) || defined (CY_IP_MXS22IOSS)
703 CY_ASSERT_L2(CY_GPIO_IS_AMUX_SPLIT_VALID(switchCtrl));
704 CY_ASSERT_L3(CY_GPIO_IS_AMUX_CONNECT_VALID(amuxConnect));
705 CY_ASSERT_L3(CY_GPIO_IS_AMUX_SELECT_VALID(amuxBus));
706
707 uint32_t tmpReg;
708
709 if (amuxBus != CY_GPIO_AMUXBUSB)
710 {
711 tmpReg = HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXB_SPLITTER_MASK;
712 HSIOM_AMUX_SPLIT_CTL(switchCtrl) = tmpReg | ((uint32_t) amuxConnect & GPIO_AMUXA_SPLITTER_MASK);
713 }
714 else
715 {
716 tmpReg = HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXA_SPLITTER_MASK;
717 HSIOM_AMUX_SPLIT_CTL(switchCtrl) =
718 tmpReg | (((uint32_t) amuxConnect << HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos) & GPIO_AMUXB_SPLITTER_MASK);
719 }
720 #else
721 (void) switchCtrl;
722 (void) amuxConnect;
723 (void) amuxBus;
724
725 CY_ASSERT_L2(1);
726 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
727 }
728
729
730 /*******************************************************************************
731 * Function Name: Cy_GPIO_GetAmuxSplit
732 ****************************************************************************//**
733 *
734 * Returns the configuration of a specific AMux bus splitter switch cell.
735 *
736 * \param switchCtrl
737 * Selects specific AMux bus splitter cell between two segments.
738 * The cy_en_amux_split_t enumeration can be found in the GPIO header file
739 * for the device package.
740 *
741 * \param amuxBus
742 * Selects which AMux bus within the splitter is being configured
743 *
744 * \return
745 * Returns configuration of the three switches in the selected splitter cell
746 *
747 * \note
748 * This API is available for the CAT1A and CAT1D devices.
749 *
750 *******************************************************************************/
Cy_GPIO_GetAmuxSplit(cy_en_amux_split_t switchCtrl,cy_en_gpio_amuxselect_t amuxBus)751 cy_en_gpio_amuxconnect_t Cy_GPIO_GetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxselect_t amuxBus)
752 {
753 #if defined (CY_IP_MXS40IOSS) || defined (CY_IP_MXS22IOSS)
754 CY_ASSERT_L2(CY_GPIO_IS_AMUX_SPLIT_VALID(switchCtrl));
755 CY_ASSERT_L3(CY_GPIO_IS_AMUX_SELECT_VALID(amuxBus));
756
757 uint32_t retVal;
758
759 if (amuxBus != CY_GPIO_AMUXBUSB)
760 {
761 retVal = HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXA_SPLITTER_MASK;
762 }
763 else
764 {
765 retVal = ((uint32_t) ((HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXB_SPLITTER_MASK)
766 >> HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos));
767 }
768
769 return ((cy_en_gpio_amuxconnect_t) retVal);
770 #else
771 CY_ASSERT_L2(1);
772
773 (void) switchCtrl;
774 (void) amuxBus;
775
776 return ((cy_en_gpio_amuxconnect_t) CY_GPIO_AMUX_GLR);
777 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
778 }
779
780
781 /*******************************************************************************
782 * Function Name: Cy_GPIO_SetHSIOM
783 ****************************************************************************//**
784 *
785 * Configures the HSIOM connection to the pin.
786 *
787 * Connects the specified High-Speed Input Output Multiplexer (HSIOM) selection
788 * to the pin.
789 *
790 * \param base
791 * Pointer to the pin's port register base address
792 *
793 * \param pinNum
794 * Position of the pin bit-field within the port register
795 *
796 * \param value
797 * HSIOM input selection
798 *
799 * \note
800 * This function modifies a port register in a read-modify-write operation. It is
801 * not thread safe as the resource is shared among multiple pins on a port.
802 *
803 * \funcusage
804 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetHSIOM
805 *
806 *******************************************************************************/
Cy_GPIO_SetHSIOM(GPIO_PRT_Type * base,uint32_t pinNum,en_hsiom_sel_t value)807 void Cy_GPIO_SetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum, en_hsiom_sel_t value)
808 {
809 uint32_t portNum;
810 uint32_t tempReg;
811 uint32_t hsiomReg;
812 HSIOM_PRT_V1_Type* portAddrHSIOM;
813
814 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
815 cy_en_pra_pin_prot_type_t pinType;
816 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
817
818 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
819 CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(value));
820
821 portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
822 portAddrHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
823
824 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
825 if ((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) || (base == (GPIO_PRT_Type*)((void*)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0)))
826 {
827 portAddrHSIOM = (HSIOM_PRT_V1_Type*) ((void*)((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) ? ((void*)SMIF0_CORE0_SMIF_HSIOM_SMIF_PRT0) : ((void*)SMIF0_CORE1_SMIF_HSIOM_SMIF_PRT0)));
828 }
829 #endif
830
831 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
832 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
833 #endif
834
835 if(pinNum < CY_GPIO_PRT_HALF)
836 {
837 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
838 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
839 {
840 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0)) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
841 }
842 else if (pinType == CY_PRA_PIN_SECURE_NONE)
843 {
844 /* For 1M device check for secure HSIOM */
845 if (CY_PRA_IS_HSIOM_SECURE(base))
846 {
847 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0)) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
848 }
849 else
850 {
851 tempReg = HSIOM_PRT_PORT_SEL0(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
852 }
853 }
854 else
855 {
856 /* secure pin */
857 tempReg = 0UL;
858 }
859 #else
860 tempReg = HSIOM_PRT_PORT_SEL0(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
861 #endif
862 hsiomReg = tempReg | (((uint32_t)value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET));
863
864 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
865 if (pinType != CY_PRA_PIN_SECURE)
866 {
867 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
868 {
869 CY_PRA_REG32_SET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0), hsiomReg);
870 }
871 else
872 {
873 /* For 1M device check for secure HSIOM */
874 #if defined(CY_DEVICE_PSOC6ABLE2)
875 if (CY_PRA_IS_HSIOM_SECURE(base))
876 {
877 CY_PRA_REG32_SET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0), hsiomReg);
878 }
879 else
880 {
881 HSIOM_PRT_PORT_SEL0(portAddrHSIOM) = hsiomReg;
882 }
883 #else
884 HSIOM_PRT_PORT_SEL0(portAddrHSIOM) = hsiomReg;
885 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
886 }
887 }
888 else
889 {
890 /* Secure PIN can't be modified using register policy */
891 }
892 #else
893 HSIOM_PRT_PORT_SEL0(portAddrHSIOM) = hsiomReg;
894 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
895 }
896 else
897 {
898 pinNum -= CY_GPIO_PRT_HALF;
899
900 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
901 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
902 {
903 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1)) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
904 }
905 else if (pinType == CY_PRA_PIN_SECURE_NONE)
906 {
907 /* For 1M device check for secure HSIOM */
908 if (CY_PRA_IS_HSIOM_SECURE(base))
909 {
910 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1)) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
911 }
912 else
913 {
914 tempReg = HSIOM_PRT_PORT_SEL1(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
915 }
916
917 }
918 else
919 {
920 tempReg = 0UL;
921 }
922 #else
923 tempReg = HSIOM_PRT_PORT_SEL1(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
924 #endif
925
926 hsiomReg = tempReg | (((uint32_t)value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET));
927 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
928
929 if (pinType != CY_PRA_PIN_SECURE)
930 {
931 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
932 {
933 CY_PRA_REG32_SET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1), hsiomReg);
934 }
935 else
936 {
937 /* For 1M device check for secure HSIOM */
938 #if defined(CY_DEVICE_PSOC6ABLE2)
939 if (CY_PRA_IS_HSIOM_SECURE(base))
940 {
941 CY_PRA_REG32_SET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1), hsiomReg);
942 }
943 else
944 {
945 HSIOM_PRT_PORT_SEL1(portAddrHSIOM) = hsiomReg;
946 }
947 #else
948 HSIOM_PRT_PORT_SEL1(portAddrHSIOM) = hsiomReg;
949 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
950 }
951 }
952 else
953 {
954 /* Secure PIN can't be modified using register policy */
955 }
956 #else
957 HSIOM_PRT_PORT_SEL1(portAddrHSIOM) = hsiomReg;
958 #endif
959 }
960 }
961
962
963 /*******************************************************************************
964 * Function Name: Cy_GPIO_GetHSIOM
965 ****************************************************************************//**
966 *
967 * Returns the current HSIOM multiplexer connection to the pin.
968 *
969 * \param base
970 * Pointer to the pin's port register base address
971 *
972 * \param pinNum
973 * Position of the pin bit-field within the port register
974 *
975 * \return
976 * HSIOM input selection
977 *
978 * \funcusage
979 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetHSIOM
980 *
981 *******************************************************************************/
Cy_GPIO_GetHSIOM(GPIO_PRT_Type * base,uint32_t pinNum)982 en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum)
983 {
984 uint32_t returnValue;
985 uint32_t tempReg;
986 uint32_t portNum;
987 HSIOM_PRT_V1_Type* portAddrHSIOM;
988 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
989 cy_en_pra_pin_prot_type_t pinType;
990 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
991
992 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
993
994 portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
995 portAddrHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
996
997 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
998 if ((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) || (base == (GPIO_PRT_Type*)((void*)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0)))
999 {
1000 portAddrHSIOM = (HSIOM_PRT_V1_Type*) ((void*)((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) ? ((void*)SMIF0_CORE0_SMIF_HSIOM_SMIF_PRT0) : ((void*)SMIF0_CORE1_SMIF_HSIOM_SMIF_PRT0)));
1001 }
1002 #endif
1003
1004 if(pinNum < CY_GPIO_PRT_HALF)
1005 {
1006 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1007 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1008 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1009 {
1010 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0));
1011 }
1012 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1013 {
1014 /* For 1M device check for secure HSIOM */
1015 if (CY_PRA_IS_HSIOM_SECURE(base))
1016 {
1017 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0));
1018 }
1019 else
1020 {
1021 tempReg = HSIOM_PRT_PORT_SEL0(portAddrHSIOM);
1022 }
1023 }
1024 else
1025 {
1026 /* secure pin */
1027 tempReg = 0UL;
1028 }
1029 #else
1030 tempReg = HSIOM_PRT_PORT_SEL0(portAddrHSIOM);
1031 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1032
1033 returnValue = (tempReg >> (pinNum << CY_GPIO_HSIOM_OFFSET)) & CY_GPIO_HSIOM_MASK;
1034 }
1035 else
1036 {
1037 pinNum -= CY_GPIO_PRT_HALF;
1038
1039 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1040 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, (pinNum + CY_GPIO_PRT_HALF));
1041 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1042 {
1043 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1));
1044 }
1045 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1046 {
1047 /* For 1M device check for secure HSIOM */
1048 if (CY_PRA_IS_HSIOM_SECURE(base))
1049 {
1050 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1));
1051 }
1052 else
1053 {
1054 tempReg = HSIOM_PRT_PORT_SEL1(portAddrHSIOM);
1055 }
1056 }
1057 else
1058 {
1059 /* secure pin */
1060 tempReg = 0UL;
1061 }
1062 #else
1063 tempReg = HSIOM_PRT_PORT_SEL1(portAddrHSIOM);
1064 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1065
1066 returnValue = (tempReg >> (pinNum << CY_GPIO_HSIOM_OFFSET)) & CY_GPIO_HSIOM_MASK;
1067 }
1068
1069 return (en_hsiom_sel_t)returnValue;
1070 }
1071
1072
1073 /*******************************************************************************
1074 * Function Name: Cy_GPIO_Read
1075 ****************************************************************************//**
1076 *
1077 * Reads the current logic level on the input buffer of the pin.
1078 *
1079 * \param base
1080 * Pointer to the pin's port register base address
1081 *
1082 * \param pinNum
1083 * Position of the pin bit-field within the port register.
1084 * Bit position 8 is the routed pin through the port glitch filter.
1085 *
1086 * \return
1087 * Logic level present on the pin
1088 *
1089 * \funcusage
1090 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Read
1091 *
1092 *******************************************************************************/
Cy_GPIO_Read(GPIO_PRT_Type * base,uint32_t pinNum)1093 uint32_t Cy_GPIO_Read(GPIO_PRT_Type* base, uint32_t pinNum)
1094 {
1095 uint32_t tempReg;
1096 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1097 cy_en_pra_pin_prot_type_t pinType;
1098 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1099
1100 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
1101
1102 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1103 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1104 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1105 {
1106 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_IN));
1107 }
1108 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1109 {
1110 tempReg = GPIO_PRT_IN(base);
1111 }
1112 else
1113 {
1114 /* secure pin */
1115 tempReg = 0UL;
1116 }
1117 #else
1118 tempReg = GPIO_PRT_IN(base);
1119 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1120
1121 return (tempReg >> (pinNum)) & CY_GPIO_IN_MASK;
1122 }
1123
1124
1125 /*******************************************************************************
1126 * Function Name: Cy_GPIO_Write
1127 ****************************************************************************//**
1128 *
1129 * Write a logic 0 or logic 1 state to the output driver.
1130 *
1131 * This function should be used only for software driven pins. It does not have
1132 * any effect on peripheral driven pins.
1133 *
1134 * \param base
1135 * Pointer to the pin's port register base address
1136 *
1137 * \param pinNum
1138 * Position of the pin bit-field within the port register
1139 *
1140 * \param value
1141 * Logic level to drive out on the pin
1142 *
1143 * \funcusage
1144 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Write
1145 *
1146 *******************************************************************************/
Cy_GPIO_Write(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)1147 void Cy_GPIO_Write(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
1148 {
1149 uint32_t outMask;
1150
1151 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1152 cy_en_pra_pin_prot_type_t pinType;
1153 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1154
1155 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1156 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
1157
1158 outMask = CY_GPIO_OUT_MASK << pinNum;
1159
1160 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1161
1162 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1163
1164 if (pinType != CY_PRA_PIN_SECURE)
1165 {
1166 if(0UL == value)
1167 {
1168 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1169 {
1170 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT_CLR), outMask);
1171 }
1172 else /* non-secure pin */
1173 {
1174 GPIO_PRT_OUT_CLR(base) = outMask;
1175 }
1176 }
1177 else
1178 {
1179 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1180 {
1181 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT_SET), outMask);
1182 }
1183 else
1184 {
1185 GPIO_PRT_OUT_SET(base) = outMask;
1186 }
1187 }
1188 }
1189 else
1190 {
1191 /* Secure PIN can't be modified using register policy */
1192 }
1193 #else
1194 /* Thread-safe: Directly access the pin registers instead of base->OUT */
1195 if(0UL == value)
1196 {
1197 GPIO_PRT_OUT_CLR(base) = outMask;
1198 }
1199 else
1200 {
1201 GPIO_PRT_OUT_SET(base) = outMask;
1202 }
1203 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1204 }
1205
1206
1207 /*******************************************************************************
1208 * Function Name: Cy_GPIO_ReadOut
1209 ****************************************************************************//**
1210 *
1211 * Reads the current logic level on the pin output driver.
1212 *
1213 * \param base
1214 * Pointer to the pin's port register base address
1215 *
1216 * \param pinNum
1217 * Position of the pin bit-field within the port register
1218 *
1219 * \return
1220 * Logic level on the pin output driver
1221 *
1222 * \funcusage
1223 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_ReadOut
1224 *
1225 *******************************************************************************/
Cy_GPIO_ReadOut(GPIO_PRT_Type * base,uint32_t pinNum)1226 uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type* base, uint32_t pinNum)
1227 {
1228 uint32_t tempReg;
1229 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1230 cy_en_pra_pin_prot_type_t pinType;
1231 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1232
1233 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1234
1235 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1236 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1237 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1238 {
1239 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT));
1240 }
1241 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1242 {
1243 tempReg = GPIO_PRT_OUT(base);
1244 }
1245 else
1246 {
1247 /* secure pin */
1248 tempReg = 0UL;
1249 }
1250 #else
1251 tempReg = GPIO_PRT_OUT(base);
1252 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1253
1254 return (tempReg >> pinNum) & CY_GPIO_OUT_MASK;
1255 }
1256
1257
1258 /*******************************************************************************
1259 * Function Name: Cy_GPIO_Set
1260 ****************************************************************************//**
1261 *
1262 * Set a pin output to logic state high.
1263 *
1264 * This function should be used only for software driven pins. It does not have
1265 * any effect on peripheral driven pins.
1266 *
1267 * \param base
1268 * Pointer to the pin's port register base address
1269 *
1270 * \param pinNum
1271 * Position of the pin bit-field within the port register
1272 *
1273 * \funcusage
1274 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Set
1275 *
1276 *******************************************************************************/
Cy_GPIO_Set(GPIO_PRT_Type * base,uint32_t pinNum)1277 void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum)
1278 {
1279 uint32_t outMask;
1280
1281 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1282 cy_en_pra_pin_prot_type_t pinType;
1283 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1284
1285 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1286
1287 outMask = CY_GPIO_OUT_MASK << pinNum;
1288
1289 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1290 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1291
1292 if (pinType != CY_PRA_PIN_SECURE)
1293 {
1294 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1295 {
1296 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT_SET), outMask);
1297 }
1298 else
1299 {
1300 GPIO_PRT_OUT_SET(base) = outMask;
1301 }
1302 }
1303 else
1304 {
1305 /* Secure PIN can't be modified using register policy */
1306 }
1307 #else
1308 GPIO_PRT_OUT_SET(base) = outMask;
1309 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1310 }
1311
1312
1313 /*******************************************************************************
1314 * Function Name: Cy_GPIO_Clr
1315 ****************************************************************************//**
1316 *
1317 * Set a pin output to logic state Low.
1318 *
1319 * This function should be used only for software driven pins. It does not have
1320 * any effect on peripheral driven pins.
1321 *
1322 * \param base
1323 * Pointer to the pin's port register base address
1324 *
1325 * \param pinNum
1326 * Position of the pin bit-field within the port register
1327 *
1328 * \funcusage
1329 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Clr
1330 *
1331 *******************************************************************************/
Cy_GPIO_Clr(GPIO_PRT_Type * base,uint32_t pinNum)1332 void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum)
1333 {
1334 uint32_t outMask;
1335
1336 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1337 cy_en_pra_pin_prot_type_t pinType;
1338 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1339
1340 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1341
1342 outMask = CY_GPIO_OUT_MASK << pinNum;
1343
1344 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1345 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1346
1347 if (pinType != CY_PRA_PIN_SECURE)
1348 {
1349 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1350 {
1351 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT_CLR), outMask);
1352 }
1353 else
1354 {
1355 GPIO_PRT_OUT_CLR(base) = outMask;
1356 }
1357 }
1358 else
1359 {
1360 /* Secure PIN can't be modified using register policy */
1361 }
1362 #else
1363 GPIO_PRT_OUT_CLR(base) = outMask;
1364 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1365 }
1366
1367
1368 /*******************************************************************************
1369 * Function Name: Cy_GPIO_Inv
1370 ****************************************************************************//**
1371 *
1372 * Set a pin output logic state to the inverse of the current output
1373 * logic state.
1374 *
1375 * This function should be used only for software driven pins. It does not have
1376 * any effect on peripheral driven pins.
1377 *
1378 * \param base
1379 * Pointer to the pin's port register base address
1380 *
1381 * \param pinNum
1382 * Position of the pin bit-field within the port register
1383 *
1384 * \funcusage
1385 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Inv
1386 *
1387 *******************************************************************************/
Cy_GPIO_Inv(GPIO_PRT_Type * base,uint32_t pinNum)1388 void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum)
1389 {
1390 uint32_t outMask;
1391
1392 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1393 cy_en_pra_pin_prot_type_t pinType;
1394 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1395
1396 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1397
1398 outMask = CY_GPIO_OUT_MASK << pinNum;
1399
1400 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1401 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1402
1403 if (pinType != CY_PRA_PIN_SECURE)
1404 {
1405 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1406 {
1407 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_OUT_INV), outMask);
1408 }
1409 else
1410 {
1411 GPIO_PRT_OUT_INV(base) = outMask;
1412 }
1413 }
1414 else
1415 {
1416 /* Secure PIN can't be modified using register policy */
1417 }
1418 #else
1419 GPIO_PRT_OUT_INV(base) = outMask;
1420 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1421 }
1422
1423
1424 /*******************************************************************************
1425 * Function Name: Cy_GPIO_SetDrivemode
1426 ****************************************************************************//**
1427 *
1428 * Configures the pin output buffer drive mode and input buffer enable.
1429 *
1430 * The output buffer drive mode and input buffer enable are combined into a single
1431 * parameter. The drive mode controls the behavior of the pin in general.
1432 * Enabling the input buffer allows the digital pin state to be read but also
1433 * contributes to extra current consumption.
1434 *
1435 * \param base
1436 * Pointer to the pin's port register base address
1437 *
1438 * \param pinNum
1439 * Position of the pin bit-field within the port register
1440 *
1441 * \param value
1442 * Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros
1443 *
1444 * \note
1445 * This function modifies a port register in a read-modify-write operation. It is
1446 * not thread safe as the resource is shared among multiple pins on a port.
1447 *
1448 * \funcusage
1449 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetDrivemode
1450 *
1451 *******************************************************************************/
Cy_GPIO_SetDrivemode(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)1452 void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
1453 {
1454 uint32_t tempReg;
1455 uint32_t pinLoc;
1456 uint32_t prtCfg;
1457 #if defined (CY_IP_MXS22IOSS)
1458 uint32_t prtCfg3;
1459 uint32_t tempRegCfg3;
1460 #endif /* CY_IP_MXS22IOSS */
1461 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1462 cy_en_pra_pin_prot_type_t pinType;
1463 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1464
1465 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1466 CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(value));
1467
1468 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1469 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1470 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1471
1472 pinLoc = pinNum << CY_GPIO_DRIVE_MODE_OFFSET;
1473
1474 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1475 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1476 {
1477 tempReg = (CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG)) & ~(CY_GPIO_CFG_DM_MASK << pinLoc));
1478 }
1479 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1480 {
1481 tempReg = (GPIO_PRT_CFG(base) & ~(CY_GPIO_CFG_DM_MASK << pinLoc));
1482 }
1483 else
1484 {
1485 /* secure pin */
1486 tempReg = 0;
1487 }
1488 #else
1489 tempReg = (GPIO_PRT_CFG(base) & ~(CY_GPIO_CFG_DM_MASK << pinLoc));
1490 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1491
1492 #if defined (CY_IP_MXS22IOSS)
1493 tempRegCfg3 = (GPIO_PRT_CFG_OUT3(base) & ~(CY_GPIO_CFG_DM_MASK << pinLoc));
1494 if(CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ == value)
1495 {
1496 prtCfg = tempReg & (~(CY_GPIO_CFG_DM_WIDTH_MASK << pinLoc));
1497 prtCfg3 = tempRegCfg3 | ((value >> CY_GPIO_EXT_DM_SHIFT) << pinLoc);
1498 }
1499 else
1500 {
1501 prtCfg = tempReg | ((value & CY_GPIO_CFG_DM_MASK) << pinLoc);
1502 prtCfg3 = tempRegCfg3 & (~(CY_GPIO_CFG_DM_WIDTH_MASK << pinLoc));
1503 }
1504 #else
1505 prtCfg = tempReg | ((value & CY_GPIO_CFG_DM_MASK) << pinLoc);
1506 #endif /* CY_IP_MXS22IOSS */
1507
1508 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1509 if (pinType != CY_PRA_PIN_SECURE)
1510 {
1511 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1512 {
1513 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG), prtCfg);
1514 }
1515 else
1516 {
1517 GPIO_PRT_CFG(base) = prtCfg;
1518 }
1519 }
1520 else
1521 {
1522 /* Secure PIN can't be modified using register policy */
1523 }
1524 #else
1525 GPIO_PRT_CFG(base) = prtCfg;
1526 #if defined (CY_IP_MXS22IOSS)
1527 GPIO_PRT_CFG_OUT3(base) = prtCfg3;
1528 #endif /* CY_IP_MXS22IOSS */
1529 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1530 }
1531
1532
1533 /*******************************************************************************
1534 * Function Name: Cy_GPIO_GetDrivemode
1535 ****************************************************************************//**
1536 *
1537 * Returns the pin output buffer drive mode and input buffer enable state.
1538 *
1539 * \param base
1540 * Pointer to the pin's port register base address
1541 *
1542 * \param pinNum
1543 * Position of the pin bit-field within the port register
1544 *
1545 * \return
1546 * Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros
1547 *
1548 * \funcusage
1549 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetDrivemode
1550 *
1551 *******************************************************************************/
Cy_GPIO_GetDrivemode(GPIO_PRT_Type * base,uint32_t pinNum)1552 uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum)
1553 {
1554 uint32_t tempReg, ret;
1555 #if defined (CY_IP_MXS22IOSS)
1556 uint32_t tempRegCfg3;
1557 #endif /* CY_IP_MXS22IOSS */
1558 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1559 cy_en_pra_pin_prot_type_t pinType;
1560 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1561
1562 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1563
1564 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1565 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1566 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1567 {
1568 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG));
1569 }
1570 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1571 {
1572 tempReg = GPIO_PRT_CFG(base);
1573 }
1574 else
1575 {
1576 /* secure pin */
1577 tempReg = 0UL;
1578 }
1579 #else
1580 tempReg = GPIO_PRT_CFG(base);
1581 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1582
1583 #if defined (CY_IP_MXS22IOSS)
1584 /* Check drive mode value in CFG_OUT register to check if CFG_OUT3 is enabled */
1585 if((((tempReg >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_CFG_DM_MASK) & CY_GPIO_CFG_DM_NO_INBUF_MASK) == 0U)
1586 {
1587 tempRegCfg3 = GPIO_PRT_CFG_OUT3(base);
1588 /* Check driver mode value in CFG_OUT3 register to check if it is set to CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ */
1589 if(((tempRegCfg3 >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_PRT_PINS_MASK) == (CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ >> CY_GPIO_EXT_DM_SHIFT))
1590 {
1591 ret = CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ;
1592 }
1593 else
1594 {
1595 ret = (tempReg >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_CFG_DM_MASK;
1596 }
1597 }
1598 else
1599 {
1600 ret = (tempReg >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_CFG_DM_MASK;
1601 }
1602 #else
1603 ret = (tempReg >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_CFG_DM_MASK;
1604 #endif /* CY_IP_MXS22IOSS */
1605
1606 return ret;
1607 }
1608
1609
1610 /*******************************************************************************
1611 * Function Name: Cy_GPIO_SetVtrip
1612 ****************************************************************************//**
1613 *
1614 * Configures the GPIO pin input buffer voltage threshold mode.
1615 *
1616 * \param base
1617 * Pointer to the pin's port register base address
1618 *
1619 * \param pinNum
1620 * Position of the pin bit-field within the port register
1621 *
1622 * \param value
1623 * Pin voltage threshold mode. Options are detailed in \ref group_gpio_vtrip macros
1624 *
1625 * \note
1626 * This function modifies a port register in a read-modify-write operation. It is
1627 * not thread safe as the resource is shared among multiple pins on a port.
1628 *
1629 * \funcusage
1630 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVtrip
1631 *
1632 *******************************************************************************/
Cy_GPIO_SetVtrip(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)1633 void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
1634 {
1635 uint32_t tempReg;
1636 uint32_t cfgIn;
1637
1638 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1639 cy_en_pra_pin_prot_type_t pinType;
1640 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1641
1642 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1643 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
1644
1645 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1646 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1647
1648 #if defined(CY_DEVICE_PSOC6ABLE2)
1649 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1650 {
1651 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_IN)) & ~(CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK << pinNum);
1652 }
1653 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1654 {
1655 tempReg = GPIO_PRT_CFG_IN(base) & ~(CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK << pinNum);
1656 }
1657 else
1658 {
1659 /* secure pin */
1660 tempReg = 0UL;
1661 }
1662 #else
1663 tempReg = GPIO_PRT_CFG_IN(base) & ~(CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK << pinNum);
1664 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
1665 #else
1666 tempReg = GPIO_PRT_CFG_IN(base) & ~(CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK << pinNum);
1667 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1668
1669 cfgIn = tempReg | ((value & CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK) << pinNum);
1670
1671 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1672 if (pinType != CY_PRA_PIN_SECURE)
1673 {
1674 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1675 {
1676 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_IN), cfgIn);
1677 }
1678 else
1679 {
1680 GPIO_PRT_CFG_IN(base) = cfgIn;
1681 }
1682 }
1683 else
1684 {
1685 /* Secure PIN can't be modified using register policy */
1686 }
1687 #else
1688 GPIO_PRT_CFG_IN(base) = cfgIn;
1689 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1690 }
1691
1692
1693 /*******************************************************************************
1694 * Function Name: Cy_GPIO_GetVtrip
1695 ****************************************************************************//**
1696 *
1697 * Returns the pin input buffer voltage threshold mode.
1698 *
1699 * \param base
1700 * Pointer to the pin's port register base address
1701 *
1702 * \param pinNum
1703 * Position of the pin bit-field within the port register
1704 *
1705 * \return
1706 * Pin voltage threshold mode. Options are detailed in \ref group_gpio_vtrip macros
1707 *
1708 * \funcusage
1709 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVtrip
1710 *
1711 *******************************************************************************/
Cy_GPIO_GetVtrip(GPIO_PRT_Type * base,uint32_t pinNum)1712 uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum)
1713 {
1714 uint32_t tempReg;
1715 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1716 cy_en_pra_pin_prot_type_t pinType;
1717 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1718
1719 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1720
1721 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1722 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1723 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1724 {
1725 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_IN));
1726 }
1727 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1728 {
1729 tempReg = GPIO_PRT_CFG_IN(base);
1730 }
1731 else
1732 {
1733 /* secure pin */
1734 tempReg = 0UL;
1735 }
1736 #else
1737 tempReg = GPIO_PRT_CFG_IN(base);
1738 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1739
1740 return (tempReg >> pinNum) & CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK;
1741 }
1742
1743 #if (defined(CY_IP_MXS40IOSS) && (CY_IP_MXS40IOSS_VERSION == 3U)) || defined(CY_IP_MXS40SIOSS_VERSION) || defined (CY_DOXYGEN)
1744 /*******************************************************************************
1745 * Function Name: Cy_GPIO_SetVtripAuto
1746 ****************************************************************************//**
1747 *
1748 * Configures the GPIO pin input buffer for automotive compatible or not.
1749 *
1750 * \param base
1751 * Pointer to the pin's port register base address
1752 *
1753 * \param pinNum
1754 * Position of the pin bit-field within the port register
1755 *
1756 * \param value
1757 * Pin voltage threshold mode. Options are detailed in
1758 * \ref group_gpio_vtrip_auto macros
1759 *
1760 * \note
1761 * This function modifies a port register in a read-modify-write operation. It is
1762 * not thread safe as the resource is shared among multiple pins on a port.
1763 *
1764 * \note
1765 * This API is available for CAT1B and CAT1C devices.
1766 *
1767 *******************************************************************************/
Cy_GPIO_SetVtripAuto(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)1768 void Cy_GPIO_SetVtripAuto(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
1769 {
1770 uint32_t tempReg;
1771 uint32_t vtripSel;
1772
1773 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1774 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
1775
1776 tempReg = GPIO_PRT_CFG_IN_AUTOLVL(base) & ~(CY_GPIO_CFG_IN_VTRIP_SEL_1_MASK << pinNum);
1777 vtripSel = tempReg | ((value & CY_GPIO_CFG_IN_VTRIP_SEL_1_MASK) << pinNum);
1778 GPIO_PRT_CFG_IN_AUTOLVL(base) = vtripSel;
1779 }
1780
1781
1782 /*******************************************************************************
1783 * Function Name: Cy_GPIO_GetVtripAuto
1784 ****************************************************************************//**
1785 *
1786 * Returns the pin input buffer voltage whether it is automotive compatible or not.
1787 *
1788 * \param base
1789 * Pointer to the pin's port register base address
1790 *
1791 * \param pinNum
1792 * Position of the pin bit-field within the port register
1793 *
1794 * \return
1795 * Pin voltage for automotive or not. Options are detailed in
1796 * \ref group_gpio_vtrip_auto macros
1797 *
1798 * \note
1799 * This API is available for CAT1B and CAT1C devices.
1800 *
1801 *******************************************************************************/
Cy_GPIO_GetVtripAuto(GPIO_PRT_Type * base,uint32_t pinNum)1802 uint32_t Cy_GPIO_GetVtripAuto(GPIO_PRT_Type* base, uint32_t pinNum)
1803 {
1804 uint32_t tempReg;
1805
1806 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1807
1808 tempReg = GPIO_PRT_CFG_IN_AUTOLVL(base);
1809
1810 return (tempReg >> pinNum) & CY_GPIO_CFG_IN_VTRIP_SEL_1_MASK;
1811 }
1812 #endif /* CY_IP_MXS40IOSS_VERSION */
1813 /*******************************************************************************
1814 * Function Name: Cy_GPIO_SetSlewRate
1815 ****************************************************************************//**
1816 *
1817 * Configures the pin output buffer slew rate.
1818 * GPIO pins have fast and slow output slew rate options for the strong drivers
1819 * configured using this API. By default the port works in fast slew mode.
1820 * Slower slew rate results in reduced EMI and crosstalk and are recommended for
1821 * low-frequency signals or signals without strict timing constraints.
1822 *
1823 * \note
1824 * This function has no effect for the GPIO ports, where the slew rate
1825 * configuration is not available. Refer to device datasheet for details.
1826 *
1827 * \param base
1828 * Pointer to the pin's port register base address
1829 *
1830 * \param pinNum
1831 * Position of the pin bit-field within the port register
1832 *
1833 * \param value
1834 * Pin slew rate. Options are detailed in \ref group_gpio_slewRate macros
1835 *
1836 * \note
1837 * This function modifies a port register in a read-modify-write operation. It is
1838 * not thread safe as the resource is shared among multiple pins on a port.
1839 *
1840 * \funcusage
1841 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetSlewRate
1842 *
1843 *******************************************************************************/
Cy_GPIO_SetSlewRate(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)1844 void Cy_GPIO_SetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
1845 {
1846 uint32_t tempReg;
1847 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS22IOSS)
1848 uint32_t pinLoc;
1849 #else
1850 uint32_t cfgOut;
1851 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
1852
1853 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1854 cy_en_pra_pin_prot_type_t pinType;
1855 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1856
1857 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1858 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
1859
1860 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS22IOSS)
1861 pinLoc = pinNum << CY_GPIO_CFG_SLEW_EXT_OFFSET;
1862 tempReg = (GPIO_PRT_SLEW_EXT(base) & ~(CY_GPIO_CFG_SLEW_EXT_MASK << pinLoc));
1863 GPIO_PRT_SLEW_EXT(base) = tempReg | ((value & CY_GPIO_CFG_SLEW_EXT_MASK) << pinLoc);
1864 #else
1865
1866 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1867 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1868 #if defined(CY_DEVICE_PSOC6ABLE2)
1869 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1870 {
1871 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT)) & ~(CY_GPIO_CFG_OUT_SLOW_MASK << pinNum);
1872 }
1873 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1874 {
1875 tempReg = GPIO_PRT_CFG_OUT(base) & ~(CY_GPIO_CFG_OUT_SLOW_MASK << pinNum);
1876 }
1877 else
1878 {
1879 /* secure pin */
1880 tempReg = 0UL;
1881 }
1882 #else
1883 tempReg = GPIO_PRT_CFG_OUT(base) & ~(CY_GPIO_CFG_OUT_SLOW_MASK << pinNum);
1884 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
1885 #else
1886 tempReg = GPIO_PRT_CFG_OUT(base) & ~(CY_GPIO_CFG_OUT_SLOW_MASK << pinNum);
1887 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1888 cfgOut = tempReg | ((value & CY_GPIO_CFG_OUT_SLOW_MASK) << pinNum);
1889
1890 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
1891 if (pinType != CY_PRA_PIN_SECURE)
1892 {
1893 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1894 {
1895 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT), cfgOut);
1896 }
1897 else
1898 {
1899 GPIO_PRT_CFG_OUT(base) = cfgOut;
1900 }
1901 }
1902 else
1903 {
1904 /* Secure PIN can't be modified using register policy */
1905 }
1906 #else
1907 GPIO_PRT_CFG_OUT(base) = cfgOut;
1908 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
1909 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
1910 }
1911
1912
1913 /*******************************************************************************
1914 * Function Name: Cy_GPIO_GetSlewRate
1915 ****************************************************************************//**
1916 *
1917 * Returns the pin output buffer slew rate.
1918 *
1919 * \param base
1920 * Pointer to the pin's port register base address
1921 *
1922 * \param pinNum
1923 * Position of the pin bit-field within the port register
1924 *
1925 * \return
1926 * Pin slew rate. Options are detailed in \ref group_gpio_slewRate macros
1927 *
1928 * \funcusage
1929 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetSlewRate
1930 *
1931 *******************************************************************************/
Cy_GPIO_GetSlewRate(GPIO_PRT_Type * base,uint32_t pinNum)1932 uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum)
1933 {
1934 #if defined (CY_IP_MXS40IOSS)
1935 uint32_t tempReg;
1936 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1937 cy_en_pra_pin_prot_type_t pinType;
1938 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1939 #endif /* defined (CY_IP_MXS40IOSS) */
1940
1941 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1942
1943 #if defined (CY_IP_MXS40IOSS)
1944
1945 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
1946 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
1947 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
1948 {
1949 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT));
1950 }
1951 else if (pinType == CY_PRA_PIN_SECURE_NONE)
1952 {
1953 tempReg = GPIO_PRT_CFG_OUT(base);
1954 }
1955 else
1956 {
1957 /* secure pin */
1958 tempReg = 0UL;
1959 }
1960 #else
1961 tempReg = GPIO_PRT_CFG_OUT(base);
1962 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
1963
1964 return (tempReg >> pinNum) & CY_GPIO_CFG_OUT_SLOW_MASK;
1965 #else
1966 return (GPIO_PRT_SLEW_EXT(base) >> (pinNum << CY_GPIO_CFG_SLEW_EXT_OFFSET)) & CY_GPIO_CFG_SLEW_EXT_MASK;
1967 #endif /* CY_IP_MXS40IOSS */
1968 }
1969
1970
1971 /*******************************************************************************
1972 * Function Name: Cy_GPIO_SetDriveSel
1973 ****************************************************************************//**
1974 *
1975 * Configures the pin output buffer drive strength.
1976 * The drive strength field determines the active portion of the output drivers
1977 * used and can affect the slew rate of output signals. Drive strength options
1978 * are full drive strength (default), one-half strength, one-quarter strength,
1979 * and oneeighth strength. Drive strength must be set to full drive strength when
1980 * the slow slew rate bit (SLOW) is set.
1981 *
1982 * \param base
1983 * Pointer to the pin's port register base address
1984 *
1985 * \param pinNum
1986 * Position of the pin bit-field within the port register.
1987 *
1988 * \param value
1989 * Pin drive strength. Options are detailed in \ref group_gpio_driveStrength macros
1990 *
1991 * \note
1992 * This function modifies a port register in a read-modify-write operation. It is
1993 * not thread safe as the resource is shared among multiple pins on a port.
1994 *
1995 * \funcusage
1996 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetDriveSel
1997 *
1998 *******************************************************************************/
Cy_GPIO_SetDriveSel(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)1999 void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
2000 {
2001 uint32_t tempReg;
2002 #if defined (CY_IP_MXS40IOSS)
2003 uint32_t pinLoc;
2004 uint32_t cfgOut;
2005 #endif /* CY_IP_MXS40IOSS */
2006
2007 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2008 cy_en_pra_pin_prot_type_t pinType;
2009 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2010
2011 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2012 CY_ASSERT_L2(CY_GPIO_IS_DRIVE_SEL_VALID(value));
2013
2014 #if defined (CY_IP_MXS40IOSS)
2015 pinLoc = (uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET;
2016 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2017 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2018 #if defined(CY_DEVICE_PSOC6ABLE2)
2019 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2020 {
2021 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT)) & ~(CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << pinLoc);
2022 }
2023 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2024 {
2025 tempReg = GPIO_PRT_CFG_OUT(base) & ~(CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << pinLoc);
2026 }
2027 else
2028 {
2029 /* secure pin */
2030 tempReg = 0UL;
2031 }
2032 #else
2033 tempReg = GPIO_PRT_CFG_OUT(base) & ~(CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << pinLoc);
2034 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
2035 #else
2036 tempReg = GPIO_PRT_CFG_OUT(base) & ~(CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << pinLoc);
2037 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2038 cfgOut = tempReg | ((value & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << pinLoc);
2039
2040 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2041 if (pinType != CY_PRA_PIN_SECURE)
2042 {
2043 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2044 {
2045 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT), cfgOut);
2046 }
2047 else
2048 {
2049 GPIO_PRT_CFG_OUT(base) = cfgOut;
2050 }
2051 }
2052 else
2053 {
2054 /* Secure PIN can't be modified using register policy */
2055 }
2056 #else
2057 GPIO_PRT_CFG_OUT(base) = cfgOut;
2058 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2059 #else
2060 if(pinNum < CY_GPIO_PRT_HALF)
2061 {
2062 tempReg = GPIO_PRT_DRIVE_EXT0(base) & ~(CY_GPIO_CFG_DRIVE_SEL_EXT_MASK << (pinNum << CY_GPIO_CFG_DRIVE_SEL_EXT_OFFSET));
2063 GPIO_PRT_DRIVE_EXT0(base) = tempReg | ((value & CY_GPIO_CFG_DRIVE_SEL_EXT_MASK) << (pinNum << CY_GPIO_CFG_DRIVE_SEL_EXT_OFFSET));
2064 }
2065 else
2066 {
2067 pinNum -= CY_GPIO_PRT_HALF;
2068 tempReg = GPIO_PRT_DRIVE_EXT1(base) & ~(CY_GPIO_CFG_DRIVE_SEL_EXT_MASK << (pinNum << CY_GPIO_CFG_DRIVE_SEL_EXT_OFFSET));
2069 GPIO_PRT_DRIVE_EXT1(base) = tempReg | ((value & CY_GPIO_CFG_DRIVE_SEL_EXT_MASK) << (pinNum << CY_GPIO_CFG_DRIVE_SEL_EXT_OFFSET));
2070 }
2071 #endif /* CY_IP_MXS40SIOSS */
2072 }
2073
2074
2075 /*******************************************************************************
2076 * Function Name: Cy_GPIO_GetDriveSel
2077 ****************************************************************************//**
2078 *
2079 * Returns the pin output buffer drive strength.
2080 *
2081 * \param base
2082 * Pointer to the pin's port register base address
2083 *
2084 * \param pinNum
2085 * Position of the pin bit-field within the port register
2086 *
2087 * \return
2088 * Pin drive strength. Options are detailed in \ref group_gpio_driveStrength macros
2089 *
2090 * \funcusage
2091 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetDriveSel
2092 *
2093 *******************************************************************************/
Cy_GPIO_GetDriveSel(GPIO_PRT_Type * base,uint32_t pinNum)2094 uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum)
2095 {
2096 #if defined (CY_IP_MXS40IOSS)
2097 uint32_t tempReg;
2098 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2099 cy_en_pra_pin_prot_type_t pinType;
2100 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2101 #endif /* defined (CY_IP_MXS40IOSS) */
2102
2103 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2104
2105 #if defined (CY_IP_MXS40IOSS)
2106 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2107 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2108 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2109 {
2110 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT));
2111 }
2112 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2113 {
2114 tempReg = GPIO_PRT_CFG_OUT(base);
2115 }
2116 else
2117 {
2118 /* secure pin */
2119 tempReg = 0UL;
2120 }
2121 #else
2122 tempReg = GPIO_PRT_CFG_OUT(base);
2123 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2124
2125 return ((tempReg >> ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET))
2126 & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK);
2127 #else
2128 uint32_t returnValue;
2129 if(pinNum < CY_GPIO_PRT_HALF)
2130 {
2131 returnValue = (GPIO_PRT_DRIVE_EXT0(base) >> (pinNum << CY_GPIO_CFG_DRIVE_SEL_EXT_OFFSET)) & CY_GPIO_CFG_DRIVE_SEL_EXT_MASK;
2132 }
2133 else
2134 {
2135 pinNum -= CY_GPIO_PRT_HALF;
2136 returnValue = (GPIO_PRT_DRIVE_EXT1(base) >> (pinNum << CY_GPIO_CFG_DRIVE_SEL_EXT_OFFSET)) & CY_GPIO_CFG_DRIVE_SEL_EXT_MASK;
2137 }
2138 return returnValue;
2139 #endif /* CY_IP_MXS40IOSS */
2140 }
2141
2142
2143 /*******************************************************************************
2144 * Function Name: Cy_GPIO_SetVregEn
2145 ****************************************************************************//**
2146 *
2147 * Configures the SIO pin pair output buffer regulation mode.
2148 *
2149 * Note that this function has no effect on non-SIO pins.
2150 *
2151 * \param base
2152 * Pointer to the pin's port register base address
2153 *
2154 * \param pinNum
2155 * Position of the pin bit-field within the port register
2156 *
2157 * \param value
2158 * SIO pair output buffer regulator mode. Options are detailed in \ref group_gpio_sioVreg macros
2159 *
2160 * \note
2161 * This function modifies a port register in a read-modify-write operation. It is
2162 * not thread safe as the resource is shared among multiple pins on a port.
2163 *
2164 * \funcusage
2165 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVregEn
2166 *
2167 *******************************************************************************/
Cy_GPIO_SetVregEn(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)2168 void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
2169 {
2170 #if defined (CY_IP_MXS40IOSS)
2171 uint32_t tempReg;
2172 uint32_t pinLoc;
2173 uint32_t cfgSio;
2174
2175 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2176 cy_en_pra_pin_prot_type_t pinType;
2177 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2178
2179 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2180 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
2181
2182 pinLoc = (pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET;
2183 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2184 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2185 #if defined(CY_DEVICE_PSOC6ABLE2)
2186 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2187 {
2188 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO)) & ~(CY_GPIO_VREG_EN_MASK << pinLoc);
2189 }
2190 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2191 {
2192 tempReg = GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VREG_EN_MASK << pinLoc);
2193 }
2194 else
2195 {
2196 /* secure pin */
2197 tempReg = 0UL;
2198 }
2199 #else
2200 tempReg = GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VREG_EN_MASK << pinLoc);
2201 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
2202 #else
2203 tempReg = GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VREG_EN_MASK << pinLoc);
2204 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2205 cfgSio = tempReg | ((value & CY_GPIO_VREG_EN_MASK) << pinLoc);
2206
2207 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2208 if (pinType != CY_PRA_PIN_SECURE)
2209 {
2210 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2211 {
2212 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), cfgSio);
2213 }
2214 else
2215 {
2216 GPIO_PRT_CFG_SIO(base) = cfgSio;
2217 }
2218 }
2219 else
2220 {
2221 /* Secure PIN can't be modified using register policy */
2222 }
2223 #else
2224 GPIO_PRT_CFG_SIO(base) = cfgSio;
2225 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2226 #else
2227 CY_ASSERT_L2(1);
2228 (void) base;
2229 (void) pinNum;
2230 (void) value;
2231
2232 #endif /* CY_IP_MXS40IOSS */
2233 }
2234
2235
2236 /*******************************************************************************
2237 * Function Name: Cy_GPIO_GetVregEn
2238 ****************************************************************************//**
2239 *
2240 * Returns the SIO pin pair output buffer regulation mode.
2241 *
2242 * Note that this function has no effect on non-SIO pins.
2243 *
2244 * \param base
2245 * Pointer to the pin's port register base address
2246 *
2247 * \param pinNum
2248 * Position of the pin bit-field within the port register
2249 *
2250 * \return
2251 * SIO pair output buffer regulator mode. Options are detailed in \ref group_gpio_sioVreg macros
2252 *
2253 * \funcusage
2254 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVregEn
2255 *
2256 *******************************************************************************/
Cy_GPIO_GetVregEn(GPIO_PRT_Type * base,uint32_t pinNum)2257 uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum)
2258 {
2259 #if defined (CY_IP_MXS40IOSS)
2260 uint32_t tempReg;
2261 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2262 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2263 cy_en_pra_pin_prot_type_t pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2264 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2265 {
2266 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO));
2267 }
2268 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2269 {
2270 tempReg = GPIO_PRT_CFG_SIO(base);
2271 }
2272 else
2273 {
2274 /* secure pin */
2275 tempReg = 0UL;
2276 }
2277 #else
2278 tempReg = GPIO_PRT_CFG_SIO(base);
2279 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2280
2281
2282 return (tempReg >> ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET)) & CY_GPIO_VREG_EN_MASK;
2283 #else
2284 CY_ASSERT_L2(1);
2285
2286 (void) base;
2287 (void) pinNum;
2288
2289 return CYRET_INVALID_STATE;
2290 #endif /* CY_IP_MXS40IOSS */
2291 }
2292
2293
2294 /*******************************************************************************
2295 * Function Name: Cy_GPIO_SetIbufMode
2296 ****************************************************************************//**
2297 *
2298 * Configures the SIO pin pair input buffer mode.
2299 *
2300 * Note that this function has no effect on non-SIO pins.
2301 *
2302 * \param base
2303 * Pointer to the pin's port register base address
2304 *
2305 * \param pinNum
2306 * Position of the pin bit-field within the port register
2307 *
2308 * \param value
2309 * SIO pair input buffer mode. Options are detailed in \ref group_gpio_sioIbuf macros
2310 *
2311 * \note
2312 * This function modifies a port register in a read-modify-write operation. It is
2313 * not thread safe as the resource is shared among multiple pins on a port.
2314 *
2315 * \funcusage
2316 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetIbufMode
2317 *
2318 *******************************************************************************/
Cy_GPIO_SetIbufMode(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)2319 void Cy_GPIO_SetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
2320 {
2321 #if defined (CY_IP_MXS40IOSS)
2322 uint32_t tempReg;
2323 uint32_t pinLoc;
2324 uint32_t cfgSio;
2325
2326 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2327 cy_en_pra_pin_prot_type_t pinType;
2328 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2329
2330 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2331 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
2332
2333 pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_IBUF_SHIFT;
2334 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2335 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2336 #if defined(CY_DEVICE_PSOC6ABLE2)
2337 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2338 {
2339 tempReg = (CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO)) & ~(CY_GPIO_IBUF_MASK << pinLoc));
2340 }
2341 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2342 {
2343 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_IBUF_MASK << pinLoc));
2344 }
2345 else
2346 {
2347 /* secure pin */
2348 tempReg = 0UL;
2349 }
2350 #else
2351 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_IBUF_MASK << pinLoc));
2352 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
2353 #else
2354 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_IBUF_MASK << pinLoc));
2355 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2356
2357 cfgSio = tempReg | ((value & CY_GPIO_IBUF_MASK) << pinLoc);
2358
2359 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2360 if (pinType != CY_PRA_PIN_SECURE)
2361 {
2362 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2363 {
2364 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), cfgSio);
2365 }
2366 else
2367 {
2368 GPIO_PRT_CFG_SIO(base) = cfgSio;
2369 }
2370 }
2371 else
2372 {
2373 /* Secure PIN can't be modified using register policy */
2374 }
2375 #else
2376 GPIO_PRT_CFG_SIO(base) = cfgSio;
2377 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2378 #else
2379 CY_ASSERT_L2(1);
2380 (void) base;
2381 (void) pinNum;
2382 (void) value;
2383
2384 #endif /* CY_IP_MXS40IOSS */
2385 }
2386
2387
2388 /*******************************************************************************
2389 * Function Name: Cy_GPIO_GetIbufMode
2390 ****************************************************************************//**
2391 *
2392 * Returns the SIO pin pair input buffer mode.
2393 *
2394 * Note that this function has no effect on non-SIO pins.
2395 *
2396 * \param base
2397 * Pointer to the pin's port register base address
2398 *
2399 * \param pinNum
2400 * Position of the pin bit-field within the port register
2401 *
2402 * \return
2403 * SIO pair input buffer mode. Options are detailed in \ref group_gpio_sioIbuf macros
2404 *
2405 * \funcusage
2406 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetIbufMode
2407 *
2408 *******************************************************************************/
Cy_GPIO_GetIbufMode(GPIO_PRT_Type * base,uint32_t pinNum)2409 uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum)
2410 {
2411 #if defined (CY_IP_MXS40IOSS)
2412 uint32_t tempReg;
2413
2414 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2415
2416 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2417 cy_en_pra_pin_prot_type_t pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2418 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2419 {
2420 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO));
2421 }
2422 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2423 {
2424 tempReg = GPIO_PRT_CFG_SIO(base);
2425 }
2426 else
2427 {
2428 /* secure pin */
2429 tempReg = 0UL;
2430 }
2431 #else
2432 tempReg = GPIO_PRT_CFG_SIO(base);
2433 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2434
2435 return (tempReg >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_IBUF_SHIFT)) & CY_GPIO_IBUF_MASK;
2436 #else
2437 CY_ASSERT_L2(1);
2438
2439 (void) base;
2440 (void) pinNum;
2441
2442 return CYRET_INVALID_STATE;
2443 #endif /* CY_IP_MXS40IOSS */
2444 }
2445
2446
2447 /*******************************************************************************
2448 * Function Name: Cy_GPIO_SetVtripSel
2449 ****************************************************************************//**
2450 *
2451 * Configures the SIO pin pair input buffer trip point.
2452 *
2453 * Note that this function has no effect on non-SIO pins.
2454 *
2455 * \param base
2456 * Pointer to the pin's port register base address
2457 *
2458 * \param pinNum
2459 * Position of the pin bit-field within the port register
2460 *
2461 * \param value
2462 * SIO pair input buffer trip point. Options are detailed in \ref group_gpio_sioVtrip macros
2463 *
2464 * \note
2465 * This function modifies a port register in a read-modify-write operation. It is
2466 * not thread safe as the resource is shared among multiple pins on a port.
2467 *
2468 * \funcusage
2469 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVtripSel
2470 *
2471 *******************************************************************************/
Cy_GPIO_SetVtripSel(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)2472 void Cy_GPIO_SetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
2473 {
2474 #if defined (CY_IP_MXS40IOSS)
2475 uint32_t tempReg;
2476 uint32_t pinLoc;
2477 uint32_t cfgSio;
2478
2479 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2480 cy_en_pra_pin_prot_type_t pinType;
2481 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2482
2483 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2484 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
2485
2486 pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VTRIP_SEL_SHIFT;
2487 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2488 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2489 #if defined(CY_DEVICE_PSOC6ABLE2)
2490 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2491 {
2492 tempReg = (CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO)) & ~(CY_GPIO_VTRIP_SEL_MASK << pinLoc));
2493 }
2494 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2495 {
2496 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VTRIP_SEL_MASK << pinLoc));
2497 }
2498 else
2499 {
2500 /* secure pin */
2501 tempReg = 0UL;
2502 }
2503 #else
2504 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VTRIP_SEL_MASK << pinLoc));
2505 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
2506 #else
2507 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VTRIP_SEL_MASK << pinLoc));
2508 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2509
2510 cfgSio = tempReg | ((value & CY_GPIO_VTRIP_SEL_MASK) << pinLoc);
2511
2512 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2513 if (pinType != CY_PRA_PIN_SECURE)
2514 {
2515 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2516 {
2517 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), cfgSio);
2518 }
2519 else
2520 {
2521 GPIO_PRT_CFG_SIO(base) = cfgSio;
2522 }
2523 }
2524 else
2525 {
2526 /* Secure PIN can't be modified using register policy */
2527 }
2528 #else
2529 GPIO_PRT_CFG_SIO(base) = cfgSio;
2530 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2531 #else
2532 (void) base;
2533 (void) pinNum;
2534 (void) value;
2535
2536 CY_ASSERT_L2(1);
2537 #endif /* CY_IP_MXS40IOSS */
2538 }
2539
2540
2541 /*******************************************************************************
2542 * Function Name: Cy_GPIO_GetVtripSel
2543 ****************************************************************************//**
2544 *
2545 * Returns the SIO pin pair input buffer trip point.
2546 *
2547 * Note that this function has no effect on non-SIO pins.
2548 *
2549 * \param base
2550 * Pointer to the pin's port register base address
2551 *
2552 * \param pinNum
2553 * Position of the pin bit-field within the port register
2554 *
2555 * \return
2556 * SIO pair input buffer trip point. Options are detailed in \ref group_gpio_sioVtrip macros
2557 *
2558 * \funcusage
2559 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVtripSel
2560 *
2561 *******************************************************************************/
Cy_GPIO_GetVtripSel(GPIO_PRT_Type * base,uint32_t pinNum)2562 uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum)
2563 {
2564 #if defined (CY_IP_MXS40IOSS)
2565 uint32_t tempReg;
2566
2567 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2568
2569 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2570 cy_en_pra_pin_prot_type_t pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2571 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2572 {
2573 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO));
2574 }
2575 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2576 {
2577 tempReg = GPIO_PRT_CFG_SIO(base);
2578 }
2579 else
2580 {
2581 /* secure pin */
2582 tempReg = 0UL;
2583 }
2584 #else
2585 tempReg = GPIO_PRT_CFG_SIO(base);
2586 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2587
2588 return (tempReg >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VTRIP_SEL_SHIFT)) & CY_GPIO_VTRIP_SEL_MASK;
2589 #else
2590 CY_ASSERT_L2(1);
2591
2592 (void) base;
2593 (void) pinNum;
2594
2595 return CYRET_INVALID_STATE;
2596 #endif /* CY_IP_MXS40IOSS */
2597 }
2598
2599
2600 /*******************************************************************************
2601 * Function Name: Cy_GPIO_SetVrefSel
2602 ****************************************************************************//**
2603 *
2604 * Configures the SIO reference voltage for the input buffer trip point.
2605 *
2606 * Note that this function has no effect on non-SIO pins.
2607 *
2608 * \param base
2609 * Pointer to the pin's port register base address
2610 *
2611 * \param pinNum
2612 * Position of the pin bit-field within the port register
2613 *
2614 * \param value
2615 * SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVref macros
2616 *
2617 * \note
2618 * This function modifies a port register in a read-modify-write operation. It is
2619 * not thread safe as the resource is shared among multiple pins on a port.
2620 *
2621 * \funcusage
2622 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVrefSel
2623 *
2624 *******************************************************************************/
Cy_GPIO_SetVrefSel(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)2625 void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
2626 {
2627 #if defined (CY_IP_MXS40IOSS)
2628 uint32_t tempReg;
2629 uint32_t pinLoc;
2630 uint32_t cfgSio;
2631
2632 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2633 cy_en_pra_pin_prot_type_t pinType;
2634 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2635
2636 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2637 CY_ASSERT_L2(CY_GPIO_IS_VREF_SEL_VALID(value));
2638
2639 pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT;
2640 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2641 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2642 #if defined(CY_DEVICE_PSOC6ABLE2)
2643 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2644 {
2645 tempReg = (CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO)) & ~(CY_GPIO_VREF_SEL_MASK << pinLoc));
2646 }
2647 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2648 {
2649 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VREF_SEL_MASK << pinLoc));
2650 }
2651 else
2652 {
2653 /* secure pin */
2654 tempReg = 0UL;
2655 }
2656 #else
2657 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VREF_SEL_MASK << pinLoc));
2658 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
2659 #else
2660 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VREF_SEL_MASK << pinLoc));
2661 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2662
2663 cfgSio = tempReg | ((value & CY_GPIO_VREF_SEL_MASK) << pinLoc);
2664
2665 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2666 if (pinType != CY_PRA_PIN_SECURE)
2667 {
2668 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2669 {
2670 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), cfgSio);
2671 }
2672 else
2673 {
2674 GPIO_PRT_CFG_SIO(base) = cfgSio;
2675 }
2676 }
2677 else
2678 {
2679 /* Secure PIN can't be modified using register policy */
2680 }
2681 #else
2682 GPIO_PRT_CFG_SIO(base) = cfgSio;
2683 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2684 #else
2685 (void) base;
2686 (void) pinNum;
2687 (void) value;
2688
2689 CY_ASSERT_L2(1);
2690 #endif /* CY_IP_MXS40IOSS */
2691 }
2692
2693
2694 /*******************************************************************************
2695 * Function Name: Cy_GPIO_GetVrefSel
2696 ****************************************************************************//**
2697 *
2698 * Returns the SIO reference voltage for the input buffer trip point.
2699 *
2700 * Note that this function has no effect on non-SIO pins.
2701 *
2702 * \param base
2703 * Pointer to the pin's port register base address
2704 *
2705 * \param pinNum
2706 * Position of the pin bit-field within the port register
2707 *
2708 * \return
2709 * SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVref macros
2710 *
2711 * \funcusage
2712 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVrefSel
2713 *
2714 *******************************************************************************/
Cy_GPIO_GetVrefSel(GPIO_PRT_Type * base,uint32_t pinNum)2715 uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum)
2716 {
2717 #if defined (CY_IP_MXS40IOSS)
2718 uint32_t tempReg;
2719 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2720
2721 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2722 cy_en_pra_pin_prot_type_t pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2723 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2724 {
2725 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO));
2726 }
2727 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2728 {
2729 tempReg = GPIO_PRT_CFG_SIO(base);
2730 }
2731 else
2732 {
2733 /* secure pin */
2734 tempReg = 0UL;
2735 }
2736 #else
2737 tempReg = GPIO_PRT_CFG_SIO(base);
2738 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2739
2740 return (tempReg >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT)) & CY_GPIO_VREF_SEL_MASK;
2741 #else
2742 CY_ASSERT_L2(1);
2743
2744 (void) base;
2745 (void) pinNum;
2746
2747 return CYRET_INVALID_STATE;
2748 #endif /* CY_IP_MXS40IOSS */
2749 }
2750
2751
2752 /*******************************************************************************
2753 * Function Name: Cy_GPIO_SetVohSel
2754 ****************************************************************************//**
2755 *
2756 * Configures the regulated output reference multiplier for the SIO pin pair.
2757 *
2758 * The regulated output reference controls both the output level of digital output
2759 * pin and the input trip point of digital input pin in the SIO pair.
2760 *
2761 * Note that this function has no effect on non-SIO pins.
2762 *
2763 * \param base
2764 * Pointer to the pin's port register base address
2765 *
2766 * \param pinNum
2767 * Position of the pin bit-field within the port register
2768 *
2769 * \param value
2770 * SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVoh macros
2771 *
2772 * \note
2773 * This function modifies a port register in a read-modify-write operation. It is
2774 * not thread safe as the resource is shared among multiple pins on a port.
2775 *
2776 * \funcusage
2777 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVohSel
2778 *
2779 *******************************************************************************/
Cy_GPIO_SetVohSel(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)2780 void Cy_GPIO_SetVohSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
2781 {
2782 #if defined (CY_IP_MXS40IOSS)
2783 uint32_t tempReg;
2784 uint32_t pinLoc;
2785 uint32_t cfgSio;
2786
2787 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2788 cy_en_pra_pin_prot_type_t pinType;
2789 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2790
2791 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2792 CY_ASSERT_L2(CY_GPIO_IS_VOH_SEL_VALID(value));
2793
2794 pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VOH_SEL_SHIFT;
2795 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2796 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2797 #if defined(CY_DEVICE_PSOC6ABLE2)
2798 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2799 {
2800 tempReg = (CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO)) & ~(CY_GPIO_VOH_SEL_MASK << pinLoc));
2801 }
2802 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2803 {
2804 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VOH_SEL_MASK << pinLoc));
2805 }
2806 else
2807 {
2808 /* secure pin */
2809 tempReg = 0UL;
2810 }
2811 #else
2812 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VOH_SEL_MASK << pinLoc));
2813 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
2814 #else
2815 tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VOH_SEL_MASK << pinLoc));
2816 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2817 cfgSio = tempReg | ((value & CY_GPIO_VOH_SEL_MASK) << pinLoc);
2818
2819 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2820 if (pinType != CY_PRA_PIN_SECURE)
2821 {
2822 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2823 {
2824 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), cfgSio);
2825 }
2826 else
2827 {
2828 GPIO_PRT_CFG_SIO(base) = cfgSio;
2829 }
2830 }
2831 else
2832 {
2833 /* Secure PIN can't be modified using register policy */
2834 }
2835 #else
2836 GPIO_PRT_CFG_SIO(base) = cfgSio;
2837 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2838 #else
2839 CY_ASSERT_L2(1);
2840 (void) base;
2841 (void) pinNum;
2842 (void) value;
2843
2844 #endif /* CY_IP_MXS40IOSS */
2845 }
2846
2847
2848 /*******************************************************************************
2849 * Function Name: Cy_GPIO_GetVohSel
2850 ****************************************************************************//**
2851 *
2852 * Returns the regulated output reference multiplier for the SIO pin pair.
2853 *
2854 * Note that this function has no effect on non-SIO pins.
2855 *
2856 * \param base
2857 * Pointer to the pin's port register base address
2858 *
2859 * \param pinNum
2860 * Position of the pin bit-field within the port register
2861 *
2862 * \return
2863 * SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVoh macros
2864 *
2865 * \funcusage
2866 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetVohSel
2867 *
2868 *******************************************************************************/
Cy_GPIO_GetVohSel(GPIO_PRT_Type * base,uint32_t pinNum)2869 uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum)
2870 {
2871 #if defined (CY_IP_MXS40IOSS)
2872 uint32_t tempReg;
2873 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
2874
2875 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2876 cy_en_pra_pin_prot_type_t pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2877 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2878 {
2879 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO));
2880 }
2881 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2882 {
2883 tempReg = GPIO_PRT_CFG_SIO(base);
2884 }
2885 else
2886 {
2887 /* secure pin */
2888 tempReg = 0UL;
2889 }
2890 #else
2891 tempReg = GPIO_PRT_CFG_SIO(base);
2892 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2893
2894 return (tempReg >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VOH_SEL_SHIFT)) & CY_GPIO_VOH_SEL_MASK;
2895 #else
2896 CY_ASSERT_L2(1);
2897 (void) base;
2898 (void) pinNum;
2899
2900 return CYRET_INVALID_STATE;
2901 #endif /* CY_IP_MXS40IOSS */
2902 }
2903
2904
2905 /*******************************************************************************
2906 * Function Name: Cy_GPIO_GetInterruptStatus
2907 ****************************************************************************//**
2908 *
2909 * Returns the current unmasked interrupt state of the pin.
2910 *
2911 * The core processor's NVIC is triggered by the masked interrupt bits. This
2912 * function allows reading the unmasked interrupt state. Whether the bit
2913 * positions actually trigger the interrupt are defined by the interrupt mask bits.
2914 *
2915 * \param base
2916 * Pointer to the pin's port register base address
2917 *
2918 * \param pinNum
2919 * Position of the pin bit-field within the port register
2920 * Bit position 8 is the routed pin through the port glitch filter.
2921 *
2922 * \return
2923 * 0 = Pin interrupt condition not detected
2924 * 1 = Pin interrupt condition detected
2925 *
2926 * \funcusage
2927 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_GetInterruptStatus
2928 *
2929 *******************************************************************************/
Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type * base,uint32_t pinNum)2930 uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_t pinNum)
2931 {
2932 uint32_t tempReg;
2933 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2934 cy_en_pra_pin_prot_type_t pinType;
2935 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2936
2937 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
2938
2939 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
2940 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2941 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2942 {
2943 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR));
2944 }
2945 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2946 {
2947 tempReg = GPIO_PRT_INTR(base);
2948 }
2949 else
2950 {
2951 /* secure pin */
2952 tempReg = 0UL;
2953 }
2954 #else
2955 tempReg = GPIO_PRT_INTR(base);
2956 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
2957
2958 return (tempReg >> pinNum) & CY_GPIO_INTR_STATUS_MASK;
2959 }
2960
2961
2962 /*******************************************************************************
2963 * Function Name: Cy_GPIO_ClearInterrupt
2964 ****************************************************************************//**
2965 *
2966 * Clears the triggered pin interrupt.
2967 *
2968 * \param base
2969 * Pointer to the pin's port register base address
2970 *
2971 * \param pinNum
2972 * Position of the pin bit-field within the port register
2973 * Bit position 8 is the routed pin through the port glitch filter.
2974 *
2975 * \funcusage
2976 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_ClearInterrupt
2977 *
2978 *******************************************************************************/
Cy_GPIO_ClearInterrupt(GPIO_PRT_Type * base,uint32_t pinNum)2979 void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum)
2980 {
2981 uint32_t prtIntr;
2982 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2983 cy_en_pra_pin_prot_type_t pinType;
2984 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
2985
2986 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
2987
2988 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
2989 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
2990 #if defined(CY_DEVICE_PSOC6ABLE2)
2991 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
2992 {
2993 (void)CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR));
2994 }
2995 else if (pinType == CY_PRA_PIN_SECURE_NONE)
2996 {
2997 /* Any INTR MMIO registers AHB clearing must be preceded with an AHB read access */
2998 (void)GPIO_PRT_INTR(base);
2999 }
3000 else
3001 {
3002 /* secure pin */
3003 }
3004 #else
3005 /* Any INTR MMIO registers AHB clearing must be preceded with an AHB read access */
3006 (void)GPIO_PRT_INTR(base);
3007 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
3008 #else
3009 /* Any INTR MMIO registers AHB clearing must be preceded with an AHB read access */
3010 (void)GPIO_PRT_INTR(base);
3011 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3012
3013 prtIntr = CY_GPIO_INTR_STATUS_MASK << pinNum;
3014
3015 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3016 if (pinType != CY_PRA_PIN_SECURE)
3017 {
3018 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3019 {
3020 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR), prtIntr);
3021 }
3022 else
3023 {
3024 GPIO_PRT_INTR(base) = prtIntr;
3025 }
3026 }
3027 else
3028 {
3029 /* Secure PIN can't be modified using register policy */
3030 }
3031 #else
3032 GPIO_PRT_INTR(base) = prtIntr;
3033 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3034
3035 /* This read ensures that the initial write has been flushed out to the hardware */
3036 (void)GPIO_PRT_INTR(base);
3037 }
3038
3039
3040 /*******************************************************************************
3041 * Function Name: Cy_GPIO_SetInterruptMask
3042 ****************************************************************************//**
3043 *
3044 * Configures the pin interrupt to be forwarded to the CPU NVIC.
3045 *
3046 * \param base
3047 * Pointer to the pin's port register base address
3048 *
3049 * \param pinNum
3050 * Position of the pin bit-field within the port register.
3051 * Bit position 8 is the routed pin through the port glitch filter.
3052 *
3053 * \param value
3054 * 0 = Pin interrupt not forwarded to CPU interrupt controller
3055 * 1 = Pin interrupt masked and forwarded to CPU interrupt controller
3056 *
3057 * \note
3058 * This function modifies a port register in a read-modify-write operation. It is
3059 * not thread safe as the resource is shared among multiple pins on a port.
3060 *
3061 * \funcusage
3062 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetInterruptMask
3063 *
3064 *******************************************************************************/
Cy_GPIO_SetInterruptMask(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)3065 void Cy_GPIO_SetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
3066 {
3067 uint32_t tempReg;
3068 uint32_t intrMask;
3069
3070 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3071 cy_en_pra_pin_prot_type_t pinType;
3072 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3073
3074 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
3075 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
3076
3077 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3078 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
3079 #if defined(CY_DEVICE_PSOC6ABLE2)
3080 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3081 {
3082 tempReg= CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_MASK)) & ~(CY_GPIO_INTR_EN_MASK << pinNum);
3083 }
3084 else if (pinType == CY_PRA_PIN_SECURE_NONE)
3085 {
3086 tempReg= GPIO_PRT_INTR_MASK(base) & ~(CY_GPIO_INTR_EN_MASK << pinNum);
3087 }
3088 else
3089 {
3090 /* secure pin */
3091 tempReg = 0UL;
3092 }
3093 #else
3094 tempReg= GPIO_PRT_INTR_MASK(base) & ~(CY_GPIO_INTR_EN_MASK << pinNum);
3095 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
3096 #else
3097 tempReg= GPIO_PRT_INTR_MASK(base) & ~(CY_GPIO_INTR_EN_MASK << pinNum);
3098 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3099
3100 intrMask = tempReg | ((value & CY_GPIO_INTR_EN_MASK) << pinNum);
3101
3102 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3103 if (pinType != CY_PRA_PIN_SECURE)
3104 {
3105 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3106 {
3107 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_MASK), intrMask);
3108 }
3109 else
3110 {
3111 GPIO_PRT_INTR_MASK(base) = intrMask;
3112 }
3113 }
3114 else
3115 {
3116 /* Secure PIN can't be modified using register policy */
3117 }
3118 #else
3119 GPIO_PRT_INTR_MASK(base) = intrMask;
3120 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3121 }
3122
3123
3124 /*******************************************************************************
3125 * Function Name: Cy_GPIO_GetInterruptMask
3126 ****************************************************************************//**
3127 *
3128 * Returns the state of the pin interrupt mask.
3129 *
3130 * This mask is used to determine whether the pin is configured to be forwarded
3131 * to the CPU NVIC.
3132 *
3133 * \param base
3134 * Pointer to the pin's port register base address
3135 *
3136 * \param pinNum
3137 * Position of the pin bit-field within the port register.
3138 * Bit position 8 is the routed pin through the port glitch filter.
3139 *
3140 * \return
3141 * 0 = Pin interrupt not forwarded to CPU interrupt controller
3142 * 1 = Pin interrupt masked and forwarded to CPU interrupt controller
3143 *
3144 * \funcusage
3145 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetInterruptMask
3146 *
3147 *******************************************************************************/
Cy_GPIO_GetInterruptMask(GPIO_PRT_Type * base,uint32_t pinNum)3148 uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum)
3149 {
3150 uint32_t tempReg;
3151 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
3152 cy_en_pra_pin_prot_type_t pinType;
3153 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
3154
3155 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
3156
3157 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
3158 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
3159 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3160 {
3161 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_MASK));
3162 }
3163 else if (pinType == CY_PRA_PIN_SECURE_NONE)
3164 {
3165 tempReg = GPIO_PRT_INTR_MASK(base);
3166 }
3167 else
3168 {
3169 /* secure pin */
3170 tempReg = 0UL;
3171 }
3172 #else
3173 tempReg = GPIO_PRT_INTR_MASK(base);
3174 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
3175
3176 return (tempReg >> pinNum) & CY_GPIO_INTR_EN_MASK;
3177 }
3178
3179
3180 /*******************************************************************************
3181 * Function Name: Cy_GPIO_GetInterruptStatusMasked
3182 ****************************************************************************//**
3183 *
3184 * Return the pin's current interrupt state after being masked.
3185 *
3186 * The core processor's NVIC is triggered by the masked interrupt bits. This
3187 * function allows reading this masked interrupt state. Note that the bits that
3188 * are not masked will not be forwarded to the NVIC.
3189 *
3190 * \param base
3191 * Pointer to the pin's port register base address
3192 *
3193 * \param pinNum
3194 * Position of the pin bit-field within the port register.
3195 * Bit position 8 is the routed pin through the port glitch filter.
3196 *
3197 * \return
3198 * 0 = Pin interrupt not detected or not forwarded to CPU interrupt controller
3199 * 1 = Pin interrupt detected and forwarded to CPU interrupt controller
3200 *
3201 * \funcusage
3202 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_GetInterruptStatusMasked
3203 *
3204 *******************************************************************************/
Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type * base,uint32_t pinNum)3205 uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, uint32_t pinNum)
3206 {
3207 uint32_t tempReg;
3208 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
3209 cy_en_pra_pin_prot_type_t pinType;
3210 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
3211
3212 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
3213
3214 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
3215 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
3216 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3217 {
3218 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_MASKED));
3219 }
3220 else if (pinType == CY_PRA_PIN_SECURE_NONE)
3221 {
3222 tempReg = GPIO_PRT_INTR_MASKED(base);
3223 }
3224 else
3225 {
3226 /* secure pin */
3227 tempReg = 0UL;
3228 }
3229 #else
3230 tempReg = GPIO_PRT_INTR_MASKED(base);
3231 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
3232
3233 return (tempReg >> pinNum) & CY_GPIO_INTR_MASKED_MASK;
3234 }
3235
3236
3237 /*******************************************************************************
3238 * Function Name: Cy_GPIO_SetSwInterrupt
3239 ****************************************************************************//**
3240 *
3241 * Force a pin interrupt to trigger.
3242 *
3243 * \param base
3244 * Pointer to the pin's port register base address
3245 *
3246 * \param pinNum
3247 * Position of the pin bit-field within the port register.
3248 * Bit position 8 is the routed pin through the port glitch filter.
3249 *
3250 * \funcusage
3251 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetSwInterrupt
3252 *
3253 *******************************************************************************/
Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type * base,uint32_t pinNum)3254 void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum)
3255 {
3256 uint32_t intrSet;
3257 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3258 cy_en_pra_pin_prot_type_t pinType;
3259 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3260
3261 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
3262
3263 intrSet = CY_GPIO_INTR_SET_MASK << pinNum;
3264
3265 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3266 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
3267
3268 if (pinType != CY_PRA_PIN_SECURE)
3269 {
3270 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3271 {
3272 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_SET), intrSet);
3273 }
3274 else
3275 {
3276 GPIO_PRT_INTR_SET(base) = intrSet;
3277 }
3278 }
3279 else
3280 {
3281 /* Secure PIN can't be modified using register policy */
3282 }
3283 #else
3284 GPIO_PRT_INTR_SET(base) = intrSet;
3285 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3286 }
3287
3288
3289 /*******************************************************************************
3290 * Function Name: Cy_GPIO_SetInterruptEdge
3291 ****************************************************************************//**
3292 *
3293 * Configures the type of edge that will trigger a pin interrupt.
3294 *
3295 * \param base
3296 * Pointer to the pin's port register base address
3297 *
3298 * \param pinNum
3299 * Position of the pin bit-field within the port register.
3300 * Bit position 8 is the routed pin through the port glitch filter.
3301 *
3302 * \param value
3303 * Pin interrupt mode. Options are detailed in \ref group_gpio_interruptTrigger macros
3304 *
3305 * \note
3306 * This function modifies a port register in a read-modify-write operation. It is
3307 * not thread safe as the resource is shared among multiple pins on a port.
3308 *
3309 * \funcusage
3310 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetInterruptEdge
3311 *
3312 *******************************************************************************/
Cy_GPIO_SetInterruptEdge(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)3313 void Cy_GPIO_SetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
3314 {
3315 uint32_t tempReg;
3316 uint32_t pinLoc;
3317 uint32_t intrCfg;
3318
3319 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3320 cy_en_pra_pin_prot_type_t pinType;
3321 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3322
3323 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
3324 CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(value));
3325
3326 pinLoc = pinNum << CY_GPIO_INTR_CFG_OFFSET;
3327 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3328 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
3329 #if defined(CY_DEVICE_PSOC6ABLE2)
3330 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3331 {
3332 tempReg= CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG)) & ~(CY_GPIO_INTR_EDGE_MASK << pinLoc);
3333 }
3334 else if (pinType == CY_PRA_PIN_SECURE_NONE)
3335 {
3336 tempReg = GPIO_PRT_INTR_CFG(base) & ~(CY_GPIO_INTR_EDGE_MASK << pinLoc);
3337 }
3338 else
3339 {
3340 /* secure pin */
3341 tempReg = 0UL;
3342 }
3343 #else
3344 tempReg = GPIO_PRT_INTR_CFG(base) & ~(CY_GPIO_INTR_EDGE_MASK << pinLoc);
3345 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
3346 #else
3347 tempReg = GPIO_PRT_INTR_CFG(base) & ~(CY_GPIO_INTR_EDGE_MASK << pinLoc);
3348 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3349
3350 intrCfg = tempReg | ((value & CY_GPIO_INTR_EDGE_MASK) << pinLoc);
3351
3352 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3353 if (pinType != CY_PRA_PIN_SECURE)
3354 {
3355 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3356 {
3357 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG), intrCfg);
3358 }
3359 else
3360 {
3361 GPIO_PRT_INTR_CFG(base) = intrCfg;
3362 }
3363 }
3364 else
3365 {
3366 /* Secure PIN can't be modified using register policy */
3367 }
3368 #else
3369 GPIO_PRT_INTR_CFG(base) = intrCfg;
3370 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3371 }
3372
3373
3374 /*******************************************************************************
3375 * Function Name: Cy_GPIO_GetInterruptEdge
3376 ****************************************************************************//**
3377 *
3378 * Returns the current pin interrupt edge type.
3379 *
3380 * \param base
3381 * Pointer to the pin's port register base address
3382 *
3383 * \param pinNum
3384 * Position of the pin bit-field within the port register.
3385 * Bit position 8 is the routed pin through the port glitch filter.
3386 *
3387 * \return
3388 * Pin interrupt mode. Options are detailed in \ref group_gpio_interruptTrigger macros
3389 *
3390 * \funcusage
3391 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetInterruptEdge
3392 *
3393 *******************************************************************************/
Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type * base,uint32_t pinNum)3394 uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum)
3395 {
3396 uint32_t tempReg;
3397 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
3398 cy_en_pra_pin_prot_type_t pinType;
3399 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
3400
3401 CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
3402
3403 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
3404 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum);
3405 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3406 {
3407 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG));
3408 }
3409 else if (pinType == CY_PRA_PIN_SECURE_NONE)
3410 {
3411 tempReg = GPIO_PRT_INTR_CFG(base);
3412 }
3413 else
3414 {
3415 /* secure pin */
3416 tempReg = 0UL;
3417 }
3418 #else
3419 tempReg = GPIO_PRT_INTR_CFG(base);
3420 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
3421
3422 return (tempReg >> (pinNum << CY_GPIO_INTR_CFG_OFFSET)) & CY_GPIO_INTR_EDGE_MASK;
3423 }
3424
3425
3426 /*******************************************************************************
3427 * Function Name: Cy_GPIO_SetFilter
3428 ****************************************************************************//**
3429 *
3430 * Configures which pin on the port connects to the port-specific glitch filter.
3431 *
3432 * Each port contains a single 50ns glitch filter. Any of the pins on the port
3433 * can be routed to this filter such that the input signal is filtered before
3434 * reaching the edge-detect interrupt circuitry. The state of the filtered pin
3435 * can also be read by calling the Cy_GPIO_Read() function.
3436 *
3437 * \param base
3438 * Pointer to the pin's port register base address
3439 *
3440 * \param value
3441 * The number of the port pin to route to the port filter (0...7)
3442 *
3443 * \note
3444 * This function modifies a port register in a read-modify-write operation. It is
3445 * not thread safe as the resource is shared among multiple pins on a port.
3446 *
3447 * \note
3448 * The filtered pin does not have an associated HSIOM connection. Therefore
3449 * it cannot be routed directly to other peripherals in hardware.
3450 *
3451 * \funcusage
3452 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetFilter
3453 *
3454 *******************************************************************************/
Cy_GPIO_SetFilter(GPIO_PRT_Type * base,uint32_t value)3455 void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value)
3456 {
3457 uint32_t tempReg;
3458 uint32_t intrCfg;
3459
3460 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3461 cy_en_pra_pin_prot_type_t pinType;
3462 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3463
3464 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(value));
3465
3466 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3467 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, value);
3468 #if defined(CY_DEVICE_PSOC6ABLE2)
3469 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3470 {
3471 tempReg= CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG)) & ~(CY_GPIO_INTR_FLT_EDGE_MASK << CY_GPIO_INTR_FILT_OFFSET);
3472 }
3473 else if (pinType == CY_PRA_PIN_SECURE_NONE)
3474 {
3475 tempReg = GPIO_PRT_INTR_CFG(base) & ~(CY_GPIO_INTR_FLT_EDGE_MASK << CY_GPIO_INTR_FILT_OFFSET);
3476 }
3477 else
3478 {
3479 /* secure pin */
3480 tempReg = 0UL;
3481 }
3482 #else
3483 tempReg = GPIO_PRT_INTR_CFG(base) & ~(CY_GPIO_INTR_FLT_EDGE_MASK << CY_GPIO_INTR_FILT_OFFSET);
3484 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
3485 #else
3486 tempReg = GPIO_PRT_INTR_CFG(base) & ~(CY_GPIO_INTR_FLT_EDGE_MASK << CY_GPIO_INTR_FILT_OFFSET);
3487 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3488
3489 intrCfg = tempReg | ((value & CY_GPIO_INTR_FLT_EDGE_MASK) << CY_GPIO_INTR_FILT_OFFSET);
3490
3491 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE)
3492 if (pinType != CY_PRA_PIN_SECURE)
3493 {
3494 if (pinType == CY_PRA_PIN_SECURE_UNCONSTRAINED)
3495 {
3496 CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG), intrCfg);
3497 }
3498 else
3499 {
3500 GPIO_PRT_INTR_CFG(base) = intrCfg;
3501 }
3502 }
3503 else
3504 {
3505 /* Secure PIN can't be modified using register policy */
3506 }
3507 #else
3508 GPIO_PRT_INTR_CFG(base) = intrCfg;
3509 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) */
3510 }
3511
3512
3513 /*******************************************************************************
3514 * Function Name: Cy_GPIO_GetFilter
3515 ****************************************************************************//**
3516 *
3517 * Returns which pin is currently configured to connect to the port-specific
3518 * glitch filter.
3519 *
3520 * Each port contains a single 50ns glitch filter. Any of the pins on the port
3521 * can be routed to this filter such that the input signal is filtered before
3522 * reaching the edge-detect interrupt circuitry. The state of the filtered pin
3523 * can also be read by calling the Cy_GPIO_Read() function.
3524 *
3525 * \param base
3526 * Pointer to the pin's port register base address
3527 *
3528 * \return
3529 * The number of the port pin routed to the port filter (0...7)
3530 *
3531 * \funcusage
3532 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetFilter
3533 *
3534 *******************************************************************************/
Cy_GPIO_GetFilter(GPIO_PRT_Type * base)3535 uint32_t Cy_GPIO_GetFilter(GPIO_PRT_Type* base)
3536 {
3537 uint32_t tempReg;
3538 #if (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2)
3539 if (CY_PRA_IS_PORT_SECURE(base))
3540 {
3541 tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG));
3542 }
3543 else
3544 {
3545 tempReg = GPIO_PRT_INTR_CFG(base);
3546 }
3547 #else
3548 tempReg = GPIO_PRT_INTR_CFG(base);
3549 #endif /* (CY_CPU_CORTEX_M4) && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */
3550
3551 return ((tempReg >> CY_GPIO_INTR_FILT_OFFSET) & CY_GPIO_INTR_FLT_EDGE_MASK);
3552 }
3553
3554 #if defined (CY_IP_MXS22IOSS)
3555 /*******************************************************************************
3556 * Function Name: Cy_GPIO_SetPullupResistance
3557 ****************************************************************************//**
3558 *
3559 * Configures the GPIO pin Pull-up mode.
3560 *
3561 * \param base
3562 * Pointer to the pin's port register base address
3563 *
3564 * \param pinNum
3565 * Position of the pin bit-field within the port register
3566 *
3567 * \param value
3568 * Pull-up mode for a pin. Options are detailed in
3569 * \ref group_gpio_PullUpMode macros
3570 *
3571 * \note
3572 * This API configures pull-up resistors only when
3573 * \ref CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ is selected. For all other pin drive
3574 * modes, it disables additional pull-up resistors.
3575 *
3576 * \note
3577 * This API modifies a port register in a read-modify-write operation. It is
3578 * not thread safe as the resource is shared among multiple pins on a port.
3579 *
3580 * \note
3581 * This API is available for the CAT1D devices.
3582 *
3583 * \funcusage
3584 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetPullupResistance
3585 *
3586 *******************************************************************************/
Cy_GPIO_SetPullupResistance(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)3587 void Cy_GPIO_SetPullupResistance(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
3588 {
3589 uint32_t tempReg, pinLoc, prtCfg;
3590
3591 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
3592 CY_ASSERT_L2(CY_GPIO_IS_PULLUP_RES_VALID(value));
3593
3594 if(Cy_GPIO_GetDrivemode(base, pinNum) != CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ)
3595 {
3596 value = CY_GPIO_PULLUP_RES_DISABLE;
3597 }
3598
3599 pinLoc = pinNum << CY_GPIO_CFG_RES_PULLUP_MODE_OFFSET;
3600 tempReg = (GPIO_PRT_CFG_RES(base) & ~(CY_GPIO_CFG_RES_PULLUP_MODE_MASK << pinLoc));
3601 prtCfg = tempReg | ((value & CY_GPIO_CFG_RES_PULLUP_MODE_MASK) << pinLoc);
3602
3603 GPIO_PRT_CFG_RES(base) = prtCfg;
3604 }
3605
3606 /*******************************************************************************
3607 * Function Name: Cy_GPIO_GetPullupResistance
3608 ****************************************************************************//**
3609 *
3610 * Returns the Pull-up mode of GPIO Pin.
3611 *
3612 * \param base
3613 * Pointer to the pin's port register base address
3614 *
3615 * \param pinNum
3616 * Position of the pin bit-field within the port register
3617 *
3618 * \return
3619 * Pull-up mode. Options are detailed in \ref group_gpio_PullUpMode macros
3620 *
3621 * \note
3622 * This API is available for the CAT1D devices.
3623 *
3624 * \funcusage
3625 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_SetPullupResistance
3626 *
3627 *******************************************************************************/
Cy_GPIO_GetPullupResistance(GPIO_PRT_Type * base,uint32_t pinNum)3628 uint32_t Cy_GPIO_GetPullupResistance(GPIO_PRT_Type* base, uint32_t pinNum)
3629 {
3630 uint32_t tempReg;
3631
3632 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
3633
3634 tempReg = GPIO_PRT_CFG_RES(base);
3635
3636 return ((tempReg >> (pinNum << CY_GPIO_CFG_RES_PULLUP_MODE_OFFSET)) & CY_GPIO_CFG_RES_PULLUP_MODE_MASK);
3637 }
3638 #endif /* CY_IP_MXS22IOSS */
3639
3640 #if defined(__cplusplus)
3641 }
3642 #endif
3643
3644 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS40IOSS, CY_IP_MXS22IOSS */
3645 /* [] END OF FILE */
3646
