1 /***************************************************************************//**
2 * \file cy_dma.h
3 * \version 2.90
4 *
5 * \brief
6 * The header file of the DMA driver.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2016-2023 Cypress Semiconductor Corporation
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 /**
27 * \addtogroup group_dma
28 * \{
29 * Configures a DMA channel and its descriptor(s).
30 *
31 * The functions and other declarations used in this driver are in cy_dma.h.
32 * You can include cy_pdl.h to get access to all functions
33 * and declarations in the PDL.
34 *
35 * The DMA channel can be used in any project to transfer data
36 * without CPU intervention basing on a hardware trigger signal from another component.
37 *
38 * A device may support more than one DMA hardware block. Each block has a set of
39 * registers, a base hardware address, and supports multiple channels.
40 * Many API functions for the DMA driver require a base hardware address and
41 * channel number. Ensure that you use the correct hardware address for the DMA block in use.
42 *
43 * Features:
44 * * Multiple DW blocks (device specific)
45 * * Multiple channels per each DW block (device specific)
46 * * Four priority levels for each channel
47 * * Byte, half-word (2-byte), and word (4-byte) transfers
48 * * Configurable source and destination addresses
49 * * CRC calculation support (only for CPUSS_ver2)
50 *
51 * \section group_dma_configuration Configuration Considerations
52 *
53 * To set up a DMA driver, initialize a descriptor,
54 * initialize and enable a channel, and enable the DMA block.
55 *
56 * To set up a descriptor, provide the configuration parameters for the
57 * descriptor in the \ref cy_stc_dma_descriptor_config_t structure. Then call the
58 * \ref Cy_DMA_Descriptor_Init function to initialize the descriptor in SRAM. You can
59 * modify the source and destination addresses dynamically by calling
60 * \ref Cy_DMA_Descriptor_SetSrcAddress and \ref Cy_DMA_Descriptor_SetDstAddress.
61 *
62 * To set up a DMA channel, provide a filled \ref cy_stc_dma_channel_config_t
63 * structure. Call the \ref Cy_DMA_Channel_Init function, specifying the channel
64 * number. Use \ref Cy_DMA_Channel_Enable to enable the configured DMA channel.
65 *
66 * Call \ref Cy_DMA_Channel_Enable for each DMA channel in use.
67 *
68 * When configured, another peripheral typically triggers the DMA. The trigger is
69 * connected to the DMA using the trigger multiplexer. The trigger multiplexer
70 * driver has a software trigger you can use in firmware to trigger the DMA. See the
71 * <a href="group__group__trigmux.html">Trigger Multiplexer</a> documentation.
72 *
73 * The following is a simplified structure of the DMA driver API interdependencies
74 * in a typical user application:
75 * \image html dma.png
76 *
77 * <B>NOTE:</B> DMA Trigger can also be provided through \ref Cy_DMA_Channel_SetSWTrigger API on supported targets. \n
78 * <B>NOTE:</B> DMA will read descriptors from SRAM memory. To run DMA on devices with Core CM7,
79 * D cache needs to be cleaned before DMA transfer and should be invalidated after DMA transfer. \n
80 * <B>NOTE:</B> Even if a DMA channel is enabled, it is not operational until
81 * the DMA block is enabled using function \ref Cy_DMA_Enable.\n
82 * <B>NOTE:</B> If the DMA descriptor is configured to generate an interrupt,
83 * the interrupt must be enabled using the \ref Cy_DMA_Channel_SetInterruptMask
84 * function for each DMA channel.
85 *
86 * For example:
87 * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
88 *
89 * CM7 cores in CAT1C devices support Data Cache. Data Cache line is 32 bytes.
90 * User needs to make sure that the source and destination buffer pointers and the config structure pointers passed
91 * to the following functions points to 32 bit aligned data.
92 * Cy_DMA_Channel_SetDescriptor, Cy_DMA_Descriptor_SetNextDescriptor, Cy_DMA_Descriptor_SetSrcAddress, Cy_DMA_Descriptor_SetDstAddress.
93 * User can use CY_ALIGN(32) macro for 32 bit alignment.
94 * User needs to clean the following data elements from the cache and invalidate before accessing them.
95 * source and destination buffers and descriptor structure.
96 * \snippet dma/snippet/main.c snippet_Cy_DMA_Cache_usage
97 *
98 * \section group_dma_more_information More Information.
99 * See: the DMA chapter of the device technical reference manual (TRM);
100 * the DMA Component datasheet;
101 * CE219940 - PSoC 6 MCU Multiple DMA Concatenation.
102 *
103 * \section group_dma_changelog Changelog
104 *
105 * <table class="doxtable">
106 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
107 * <tr>
108 * <td>2.90</td>
109 * <td>Added new APIs \ref Cy_DMA_Channel_IsEnabled and \ref Cy_DMA_Channel_GetCurrentYIndex.</td>
110 * <td>New devices support.</td>
111 * </tr>
112 * <tr>
113 * <td>2.80</td>
114 * <td>Updated \ref Cy_DMA_GetActiveChannel. Added new API \ref Cy_DMA_GetActiveChannelIndex.</td>
115 * <td>Bug fix.</td>
116 * </tr>
117 * <tr>
118 * <td>2.70</td>
119 * <td>Updated \ref Cy_DMA_Descriptor_SetNextDescriptor and \ref Cy_DMA_Descriptor_GetNextDescriptor.</td>
120 * <td>Coverity bug fixes.</td>
121 * </tr>
122 * <tr>
123 * <td>2.60</td>
124 * <td>Fixed MISRA 2012 violations and minor documentation update.</td>
125 * <td>MISRA 2012 compliance.</td>
126 * </tr>
127 * <tr>
128 * <td>2.50</td>
129 * <td>Fixed MISRA 2012 violations.</td>
130 * <td>MISRA 2012 compliance.</td>
131 * </tr>
132 * <tr>
133 * <td>2.40.1</td>
134 * <td>Minor documentation updates.</td>
135 * <td>Update to configure DMA on core CM7.</td>
136 * </tr>
137 * <tr>
138 * <td>2.40</td>
139 * <td>Minor Bug fixes.</td>
140 * <td>Check for valid parameters.</td>
141 * </tr>
142 * <tr>
143 * <td>2.30</td>
144 * <td>Fixed MISRA 2012 violations.</td>
145 * <td>MISRA 2012 compliance.</td>
146 * </tr>
147 * <tr>
148 * <td>2.20.1</td>
149 * <td>Minor documentation updates.</td>
150 * <td>Documentation enhancement.</td>
151 * </tr>
152 * <tr>
153 * <td>2.20</td>
154 * <td>The channel number validation method is updated.</td>
155 * <td>New devices support.</td>
156 * </tr>
157 * <tr>
158 * <td rowspan="3">2.10</td>
159 * <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
160 * <td>Driver library directory-structure simplification.</td>
161 * </tr>
162 * <tr>
163 * <td>Added CRC mode and the CRC descriptor support. \n Added the \ref Cy_DMA_Crc_Init function.</td>
164 * <td>New devices support.</td>
165 * </tr>
166 * <tr>
167 * <td>Added register access layer. Use register access macros instead
168 * of direct register access using dereferenced pointers.</td>
169 * <td>Makes register access device-independent, so that the PDL does
170 * not need to be recompiled for each supported part number.</td>
171 * </tr>
172 * <tr>
173 * <td>2.0.1</td>
174 * <td>Changed CY_DMA_BWC macro values from Boolean to numeric</td>
175 * <td>Improvements made based on usability feedback</td>
176 * </tr>
177 * <tr>
178 * <td>2.0</td>
179 * <td> * All the API is refactored to be consistent within itself and with the
180 * rest of the PDL content.
181 * * The descriptor API is updated as follows:
182 * The \ref Cy_DMA_Descriptor_Init function sets a full bunch of descriptor
183 * settings, and the rest of the descriptor API is a get/set interface
184 * to each of the descriptor settings.
185 * * There is a group of macros to support the backward compatibility with most
186 * of the driver version 1.0 API. But, you should use
187 * the new v2.0 interface in new designs (do not just copy-paste from old
188 * projects). To enable the backward compatibility support, the CY_DMA_BWC
189 * definition should be changed to "1".</td>
190 * <td></td>
191 * </tr>
192 * <tr>
193 * <td>1.0</td>
194 * <td>Initial version</td>
195 * <td></td>
196 * </tr>
197 * </table>
198 *
199
200 * \defgroup group_dma_macros Macros
201 * \defgroup group_dma_functions Functions
202 * \{
203 * \defgroup group_dma_block_functions Block Functions
204 * \defgroup group_dma_channel_functions Channel Functions
205 * \defgroup group_dma_descriptor_functions Descriptor Functions
206 * \}
207 * \defgroup group_dma_data_structures Data Structures
208 * \defgroup group_dma_enums Enumerated Types
209 */
210
211 #if !defined (CY_DMA_H)
212 #define CY_DMA_H
213
214 #include "cy_device.h"
215
216 #if defined (CY_IP_M4CPUSS_DMA) || defined (CY_IP_MXDW) || defined (CY_IP_M7CPUSS_DMA)
217
218 #include "cy_syslib.h"
219 #include <stdint.h>
220 #include <stdbool.h>
221 #include <stddef.h>
222
223 #if defined(__cplusplus)
224 extern "C" {
225 #endif
226
227 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 10.8', 15, \
228 'Value extracted from _VAL2FLD macro will not exceed enum range.')
229
230 /******************************************************************************
231 * Macro definitions *
232 ******************************************************************************/
233
234 /**
235 * \addtogroup group_dma_macros
236 * \{
237 */
238
239 /** The driver major version */
240 #define CY_DMA_DRV_VERSION_MAJOR 2
241
242 /** The driver minor version */
243 #define CY_DMA_DRV_VERSION_MINOR 90
244
245 /** The DMA driver identifier */
246 #define CY_DMA_ID (CY_PDL_DRV_ID(0x13U))
247
248 /** The DMA channel interrupt mask */
249 #define CY_DMA_INTR_MASK (0x01UL)
250
251 /** The minimum X/Y Count API parameters */
252 #define CY_DMA_LOOP_COUNT_MIN (1UL)
253 /** The maximum X/Y Count API parameters */
254 #define CY_DMA_LOOP_COUNT_MAX (256UL)
255
256 /** The minimum X/Y Increment API parameters */
257 #define CY_DMA_LOOP_INCREMENT_MIN (-2048L)
258 /** The maximum X/Y Increment API parameters */
259 #define CY_DMA_LOOP_INCREMENT_MAX (2047L)
260
261 /** No active channels */
262 #define CY_DMA_NO_ACTIVE_CHANNELS (0xFFFFFFFFU)
263
264 /** The backward compatibility flag. Enables a group of macros which provide
265 * the backward compatibility with most of the DMA driver version 1.0 interface. */
266 #ifndef CY_DMA_BWC
267 #define CY_DMA_BWC (0U) /* Disabled by default */
268 #endif
269
270 /** \} group_dma_macros */
271
272 /**
273 * \addtogroup group_dma_enums
274 * \{
275 */
276
277 /** Contains the possible interrupt cause values */
278 typedef enum
279 {
280 CY_DMA_INTR_CAUSE_NO_INTR = 0U, /**< No interrupt. */
281 CY_DMA_INTR_CAUSE_COMPLETION = 1U, /**< Completion. */
282 CY_DMA_INTR_CAUSE_SRC_BUS_ERROR = 2U, /**< Source bus error. */
283 CY_DMA_INTR_CAUSE_DST_BUS_ERROR = 3U, /**< Destination bus error. */
284 CY_DMA_INTR_CAUSE_SRC_MISAL = 4U, /**< Source address is not aligned. */
285 CY_DMA_INTR_CAUSE_DST_MISAL = 5U, /**< Destination address is not aligned. */
286 CY_DMA_INTR_CAUSE_CURR_PTR_NULL = 6U, /**< Current descriptor pointer is NULL. */
287 CY_DMA_INTR_CAUSE_ACTIVE_CH_DISABLED = 7U, /**< Active channel is disabled. */
288 CY_DMA_INTR_CAUSE_DESCR_BUS_ERROR = 8U /**< Descriptor bus error. */
289 } cy_en_dma_intr_cause_t;
290
291 /** Contains the options for the descriptor type */
292 typedef enum
293 {
294 CY_DMA_SINGLE_TRANSFER = 0UL, /**< Single transfer. */
295 CY_DMA_1D_TRANSFER = 1UL, /**< 1D transfer. */
296 CY_DMA_2D_TRANSFER = 2UL, /**< 2D transfer. */
297 CY_DMA_CRC_TRANSFER = 3UL, /**< CRC transfer. Supported by the CPUSS_ver2 only. */
298 } cy_en_dma_descriptor_type_t;
299
300 /** Contains the options for the interrupt, trig-in and trig-out type parameters of the descriptor */
301 typedef enum
302 {
303 CY_DMA_1ELEMENT = 0UL, /**< One element transfer. */
304 CY_DMA_X_LOOP = 1UL, /**< One X loop transfer. */
305 CY_DMA_DESCR = 2UL, /**< One descriptor transfer. */
306 CY_DMA_DESCR_CHAIN = 3UL /**< Entire descriptor chain transfer. */
307 } cy_en_dma_trigger_type_t;
308
309 /** Contains the options for the data size */
310 typedef enum
311 {
312 CY_DMA_BYTE = 0UL, /**< One byte. */
313 CY_DMA_HALFWORD = 1UL, /**< Half word (two bytes). */
314 CY_DMA_WORD = 2UL /**< Full word (four bytes). */
315 } cy_en_dma_data_size_t;
316
317 /** Contains the options for descriptor retriggering */
318 typedef enum
319 {
320 CY_DMA_RETRIG_IM = 0UL, /**< Retrigger immediately. */
321 CY_DMA_RETRIG_4CYC = 1UL, /**< Retrigger after 4 Clk_Slow cycles. */
322 CY_DMA_RETRIG_16CYC = 2UL, /**< Retrigger after 16 Clk_Slow cycles. */
323 CY_DMA_WAIT_FOR_REACT = 3UL /**< Wait for trigger reactivation. */
324 } cy_en_dma_retrigger_t;
325
326 /** Contains the options for the transfer size */
327 typedef enum
328 {
329 CY_DMA_TRANSFER_SIZE_DATA = 0UL, /**< As specified by dataSize. */
330 CY_DMA_TRANSFER_SIZE_WORD = 1UL, /**< A full word (four bytes). */
331 } cy_en_dma_transfer_size_t;
332
333 /** Contains the options for the state of the channel when the descriptor is completed */
334 typedef enum
335 {
336 CY_DMA_CHANNEL_ENABLED = 0UL, /**< Channel stays enabled. */
337 CY_DMA_CHANNEL_DISABLED = 1UL /**< Channel is disabled. */
338 } cy_en_dma_channel_state_t;
339
340 /** Contains the return values of the DMA driver */
341 typedef enum
342 {
343 CY_DMA_SUCCESS = 0x00UL, /**< Success. */
344 CY_DMA_BAD_PARAM = CY_DMA_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< The input parameters passed to the DMA API are not valid. */
345 } cy_en_dma_status_t;
346
347 /** \} group_dma_enums */
348
349
350 /** \cond Internal */
351
352 /* Macros for the conditions used by CY_ASSERT calls */
353 #define CY_DMA_IS_LOOP_COUNT_VALID(count) (((count) >= CY_DMA_LOOP_COUNT_MIN) && ((count) <= CY_DMA_LOOP_COUNT_MAX))
354 #define CY_DMA_IS_LOOP_INCR_VALID(incr) (((incr) >= CY_DMA_LOOP_INCREMENT_MIN) && ((incr) <= CY_DMA_LOOP_INCREMENT_MAX))
355 #define CY_DMA_IS_PRIORITY_VALID(prio) ((prio) <= 3UL)
356 #define CY_DMA_IS_INTR_MASK_VALID(intr) (0UL == ((intr) & ((uint32_t) ~CY_DMA_INTR_MASK)))
357
358 #define CY_DMA_IS_RETRIG_VALID(retrig) ((CY_DMA_RETRIG_IM == (retrig)) || \
359 (CY_DMA_RETRIG_4CYC == (retrig)) || \
360 (CY_DMA_RETRIG_16CYC == (retrig)) || \
361 (CY_DMA_WAIT_FOR_REACT == (retrig)))
362
363 #define CY_DMA_IS_TRIG_TYPE_VALID(trigType) ((CY_DMA_1ELEMENT == (trigType)) || \
364 (CY_DMA_X_LOOP == (trigType)) || \
365 (CY_DMA_DESCR == (trigType)) || \
366 (CY_DMA_DESCR_CHAIN == (trigType)))
367
368 #define CY_DMA_IS_XFER_SIZE_VALID(xferSize) ((CY_DMA_TRANSFER_SIZE_DATA == (xferSize)) || \
369 (CY_DMA_TRANSFER_SIZE_WORD == (xferSize)))
370
371 #define CY_DMA_IS_CHANNEL_STATE_VALID(state) ((CY_DMA_CHANNEL_ENABLED == (state)) || \
372 (CY_DMA_CHANNEL_DISABLED == (state)))
373
374 #define CY_DMA_IS_DATA_SIZE_VALID(dataSize) ((CY_DMA_BYTE == (dataSize)) || \
375 (CY_DMA_HALFWORD == (dataSize)) || \
376 (CY_DMA_WORD == (dataSize)))
377
378 #define CY_DMA_IS_TYPE_VALID(descrType) ((CY_DMA_SINGLE_TRANSFER == (descrType)) || \
379 (CY_DMA_1D_TRANSFER == (descrType)) || \
380 (CY_DMA_2D_TRANSFER == (descrType)) || \
381 (CY_DMA_CRC_TRANSFER == (descrType)))
382
383 #define CY_DMA_IS_CH_NR_VALID(base, chNr) ((CY_DW0_BASE == (base)) ? ((chNr) < CY_DW0_CH_NR) : \
384 ((chNr) < CY_DW1_CH_NR))
385
386 #define CY_DMA_CH_NR_AVAILABLE(base) ((CY_DW0_BASE == (base)) ? CY_DW0_CH_NR : CY_DW1_CH_NR)
387
388 /* The descriptor structure bit field definitions */
389 #define CY_DMA_CTL_RETRIG_Pos (0UL)
390 #define CY_DMA_CTL_RETRIG_Msk ((uint32_t)0x3UL << CY_DMA_CTL_RETRIG_Pos)
391 #define CY_DMA_CTL_INTR_TYPE_Pos (2UL)
392 #define CY_DMA_CTL_INTR_TYPE_Msk ((uint32_t)0x3UL << CY_DMA_CTL_INTR_TYPE_Pos)
393 #define CY_DMA_CTL_TR_OUT_TYPE_Pos (4UL)
394 #define CY_DMA_CTL_TR_OUT_TYPE_Msk ((uint32_t)0x3UL << CY_DMA_CTL_TR_OUT_TYPE_Pos)
395 #define CY_DMA_CTL_TR_IN_TYPE_Pos (6UL)
396 #define CY_DMA_CTL_TR_IN_TYPE_Msk ((uint32_t)0x3UL << CY_DMA_CTL_TR_IN_TYPE_Pos)
397 #define CY_DMA_CTL_CH_DISABLE_Pos (24UL)
398 #define CY_DMA_CTL_CH_DISABLE_Msk ((uint32_t)0x1UL << CY_DMA_CTL_CH_DISABLE_Pos)
399 #define CY_DMA_CTL_SRC_SIZE_Pos (26UL)
400 #define CY_DMA_CTL_SRC_SIZE_Msk ((uint32_t)0x1UL << CY_DMA_CTL_SRC_SIZE_Pos)
401 #define CY_DMA_CTL_DST_SIZE_Pos (27UL)
402 #define CY_DMA_CTL_DST_SIZE_Msk ((uint32_t)0x1UL << CY_DMA_CTL_DST_SIZE_Pos)
403 #define CY_DMA_CTL_DATA_SIZE_Pos (28UL)
404 #define CY_DMA_CTL_DATA_SIZE_Msk ((uint32_t)0x3UL << CY_DMA_CTL_DATA_SIZE_Pos)
405 #define CY_DMA_CTL_TYPE_Pos (30UL)
406 #define CY_DMA_CTL_TYPE_Msk ((uint32_t)0x3UL << CY_DMA_CTL_TYPE_Pos)
407
408 #define CY_DMA_CTL_SRC_INCR_Pos (0UL)
409 #define CY_DMA_CTL_SRC_INCR_Msk ((uint32_t)0xFFFUL << CY_DMA_CTL_SRC_INCR_Pos)
410 #define CY_DMA_CTL_DST_INCR_Pos (12UL)
411 #define CY_DMA_CTL_DST_INCR_Msk ((uint32_t)0xFFFUL << CY_DMA_CTL_DST_INCR_Pos)
412 #define CY_DMA_CTL_COUNT_Pos (24UL)
413 #define CY_DMA_CTL_COUNT_Msk ((uint32_t)0xFFUL << CY_DMA_CTL_COUNT_Pos)
414
415 /** \endcond */
416
417
418 /**
419 * \addtogroup group_dma_data_structures
420 * \{
421 */
422
423 /**
424 * DMA descriptor structure type. It is a user/component-declared structure
425 * allocated in RAM. The DMA HW requires a pointer to this structure to work with it.
426 *
427 * For advanced users: the descriptor can be allocated even in flash, then the user
428 * manually predefines all the structure items with constants. This is
429 * because most of the driver's API (especially functions modifying
430 * descriptors, including \ref Cy_DMA_Descriptor_Init()) can't work with
431 * read-only descriptors.
432 */
433 typedef struct
434 {
435 uint32_t ctl; /*!< 0x00000000 Descriptor control */
436 uint32_t src; /*!< 0x00000004 Descriptor source */
437 uint32_t dst; /*!< 0x00000008 Descriptor destination */
438 uint32_t xCtl; /*!< 0x0000000C Descriptor X loop control */
439 uint32_t yCtl; /*!< 0x00000010 Descriptor Y loop control */
440 uint32_t nextPtr; /*!< 0x00000014 Descriptor next pointer */
441 } cy_stc_dma_descriptor_t;
442
443 /**
444 * This structure is a configuration structure pre-initialized by the user and
445 * passed as a parameter to the \ref Cy_DMA_Descriptor_Init().
446 * It can be allocated in RAM/flash (the user's choice).
447 * In case of flash allocation, there is a possibility to reinitialize the descriptor in runtime.
448 * This structure has all the parameters of the descriptor as separate parameters.
449 * Most of these parameters are represented in the \ref cy_stc_dma_descriptor_t structure as bitfields.
450 */
451 typedef struct
452 {
453 cy_en_dma_retrigger_t retrigger; /**< Specifies whether the DW controller should wait for the input trigger to be deactivated. */
454 cy_en_dma_trigger_type_t interruptType; /**< Sets the event that triggers an interrupt. See \ref cy_en_dma_trigger_type_t. */
455 cy_en_dma_trigger_type_t triggerOutType; /**< Sets the event that triggers an output. See \ref cy_en_dma_trigger_type_t. */
456 cy_en_dma_channel_state_t channelState; /**< Specifies whether the channel is enabled or disabled on completion of descriptor. See \ref cy_en_dma_channel_state_t. */
457 cy_en_dma_trigger_type_t triggerInType; /**< Sets what type of transfer is triggered. See \ref cy_en_dma_trigger_type_t. */
458 cy_en_dma_data_size_t dataSize; /**< The size of the data bus for transfer. See \ref cy_en_dma_data_size_t. */
459 cy_en_dma_transfer_size_t srcTransferSize; /**< The source transfer size. */
460 cy_en_dma_transfer_size_t dstTransferSize; /**< The destination transfer size. */
461 cy_en_dma_descriptor_type_t descriptorType; /**< The type of the descriptor. See \ref cy_en_dma_descriptor_type_t. */
462 void * srcAddress; /**< The source address of the transfer. */
463 void * dstAddress; /**< The destination address of the transfer.
464 * For CPUSS_ver2 only: for CRC transfer, the CRC result without post-processing
465 * (reversing and/or XORing, if used) is placed into the dstAddress.
466 */
467 int32_t srcXincrement; /**< The address increment of the source after each X-loop transfer. Valid range is -2048 ... 2047. */
468 int32_t dstXincrement; /**< The address increment of the destination after each X-loop transfer. Valid range is -2048 ... 2047. */
469 uint32_t xCount; /**< The number of transfers in an X-loop. Valid range is 1 ... 256. */
470 int32_t srcYincrement; /**< The address increment of the source after each Y-loop transfer. Valid range is -2048 ... 2047. */
471 int32_t dstYincrement; /**< The address increment of the destination after each Y-loop transfer. Valid range is -2048 ... 2047. */
472 uint32_t yCount; /**< The number of X-loops in the Y-loop. Valid range is 1 ... 256. */
473 cy_stc_dma_descriptor_t * nextDescriptor; /**< The next descriptor to chain after completion. A NULL value will signify no chaining. */
474 } cy_stc_dma_descriptor_config_t;
475
476 /** This structure holds the initialization values for the DMA channel */
477 typedef struct
478 {
479 cy_stc_dma_descriptor_t * descriptor; /**< The DMA descriptor associated with the channel being initialized. */
480 bool preemptable; /**< Specifies whether the channel is preemptable by another higher-priority channel. */
481 uint32_t priority; /**< This parameter specifies the channel's priority. */
482 bool enable; /**< This parameter specifies whether the channel is enabled after initializing. */
483 bool bufferable; /**< This parameter specifies whether a write transaction can complete.
484 without waiting for the destination to accept the write transaction data. */
485 } cy_stc_dma_channel_config_t;
486
487
488 /** This structure holds the initialization values for the CRC feature, only for CPUSS_ver2 */
489 typedef struct
490 {
491 bool dataReverse; /**< Specifies the bit order in which a data byte is processed (reversal is performed after XORing):
492 * 'false': Most significant bit (bit 1) first.
493 * 'true': Least significant bit (bit 0) first.
494 */
495 uint32_t dataXor; /**< Specifies a byte mask with which each data byte is XORed. The XOR is performed before data reversal. */
496 bool reminderReverse; /**< Specifies whether the remainder is bit reversed (reversal is performed after XORing).
497 * Note: this parameter doesn't affect the CRC value stored into the dstAddress.
498 * The reversed value remains in the CRC_REM_RESULT register.
499 */
500 uint32_t reminderXor; /**< Specifies a mask with which the remainder is XORed. The XOR is performed before remainder reversal.
501 * Note: this parameter doesn't affect the CRC value stored into the dstAddress.
502 * The XORed value remains in the CRC_REM_RESULT register.
503 */
504 uint32_t polynomial; /**< CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1').
505 * The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial
506 * and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials:
507 * - CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1).
508 * - CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions).
509 * - CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions).
510 */
511 uint32_t lfsrInitVal; /**< The initial value of the Linear Feedback Shift Register */
512 } cy_stc_dma_crc_config_t;
513
514 /** \} group_dma_data_structures */
515
516
517 /**
518 * \addtogroup group_dma_functions
519 * \{
520 */
521
522
523 /**
524 * \addtogroup group_dma_block_functions
525 * \{
526 */
527
528
529 __STATIC_INLINE void Cy_DMA_Enable (DW_Type * base);
530 __STATIC_INLINE void Cy_DMA_Disable (DW_Type * base);
531 __STATIC_INLINE uint32_t Cy_DMA_GetActiveChannel (DW_Type const * base);
532 __STATIC_INLINE void * Cy_DMA_GetActiveSrcAddress(DW_Type const * base);
533 __STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type const * base);
534 cy_en_dma_status_t Cy_DMA_Crc_Init (DW_Type * base, cy_stc_dma_crc_config_t const * crcConfig);
535
536 /** \} group_dma_block_functions */
537
538
539 /**
540 * \addtogroup group_dma_channel_functions
541 * \{
542 */
543 cy_en_dma_status_t Cy_DMA_Channel_Init (DW_Type * base, uint32_t channel, cy_stc_dma_channel_config_t const * channelConfig);
544 void Cy_DMA_Channel_DeInit (DW_Type * base, uint32_t channel);
545 __STATIC_INLINE void Cy_DMA_Channel_SetDescriptor (DW_Type * base, uint32_t channel, cy_stc_dma_descriptor_t const * descriptor);
546 __STATIC_INLINE void Cy_DMA_Channel_Enable (DW_Type * base, uint32_t channel);
547 __STATIC_INLINE bool Cy_DMA_Channel_IsEnabled (DW_Type * base, uint32_t channel);
548 __STATIC_INLINE void Cy_DMA_Channel_Disable (DW_Type * base, uint32_t channel);
549 __STATIC_INLINE void Cy_DMA_Channel_SetPriority (DW_Type * base, uint32_t channel, uint32_t priority);
550 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority (DW_Type const * base, uint32_t channel);
551 __STATIC_INLINE
552 cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus (DW_Type const * base, uint32_t channel);
553 __STATIC_INLINE
554 cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor (DW_Type const * base, uint32_t channel);
555 __STATIC_INLINE uint8_t Cy_DMA_Channel_GetCurrentYIndex (DW_Type const * base, uint32_t channel);
556
557 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus (DW_Type const * base, uint32_t channel);
558 __STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt (DW_Type * base, uint32_t channel);
559 __STATIC_INLINE void Cy_DMA_Channel_SetInterrupt (DW_Type * base, uint32_t channel);
560 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask (DW_Type const * base, uint32_t channel);
561 __STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask (DW_Type * base, uint32_t channel, uint32_t interrupt);
562 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base, uint32_t channel);
563 #if !(defined (CY_IP_M4CPUSS_DMA) && (CY_IP_M4CPUSS_DMA_VERSION == 1u)) || defined (CY_DOXYGEN)
564 __STATIC_FORCEINLINE void Cy_DMA_Channel_SetSWTrigger(DW_Type const * base, uint32_t channel);
565 #endif /* (defined (CY_IP_M4CPUSS_DMA) && (CY_IP_M4CPUSS_DMA_VERSION >= 1u)) || defined (CY_IP_MXDW) || defined (CY_IP_M7CPUSS_DMA) */
566 /** \} group_dma_channel_functions */
567
568
569 /**
570 * \addtogroup group_dma_descriptor_functions
571 * \{
572 */
573
574 cy_en_dma_status_t Cy_DMA_Descriptor_Init (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_config_t const * config);
575 void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor);
576
577 void Cy_DMA_Descriptor_SetNextDescriptor (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_t const * nextDescriptor);
578 void Cy_DMA_Descriptor_SetDescriptorType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_descriptor_type_t descriptorType);
579 __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress (cy_stc_dma_descriptor_t * descriptor, void const * srcAddress);
580 __STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress (cy_stc_dma_descriptor_t * descriptor, void const * dstAddress);
581 __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount (cy_stc_dma_descriptor_t * descriptor, uint32_t xCount);
582 __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount (cy_stc_dma_descriptor_t * descriptor, uint32_t yCount);
583 __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcXincrement);
584 __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstXincrement);
585 __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcYincrement);
586 __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstYincrement);
587 __STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t interruptType);
588 __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerInType);
589 __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerOutType);
590 __STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_data_size_t dataSize);
591 __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t srcTransferSize);
592 __STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t dstTransferSize);
593 __STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_retrigger_t retrigger);
594 __STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_channel_state_t channelState);
595
596 cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor (cy_stc_dma_descriptor_t const * descriptor);
597 __STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType (cy_stc_dma_descriptor_t const * descriptor);
598 __STATIC_INLINE void * Cy_DMA_Descriptor_GetSrcAddress (cy_stc_dma_descriptor_t const * descriptor);
599 __STATIC_INLINE void * Cy_DMA_Descriptor_GetDstAddress (cy_stc_dma_descriptor_t const * descriptor);
600 __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount (cy_stc_dma_descriptor_t const * descriptor);
601 __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount (cy_stc_dma_descriptor_t const * descriptor);
602 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor);
603 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor);
604 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor);
605 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor);
606 __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType (cy_stc_dma_descriptor_t const * descriptor);
607 __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType (cy_stc_dma_descriptor_t const * descriptor);
608 __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType (cy_stc_dma_descriptor_t const * descriptor);
609 __STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize (cy_stc_dma_descriptor_t const * descriptor);
610 __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize (cy_stc_dma_descriptor_t const * descriptor);
611 __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize (cy_stc_dma_descriptor_t const * descriptor);
612 __STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger (cy_stc_dma_descriptor_t const * descriptor);
613 __STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState (cy_stc_dma_descriptor_t const * descriptor);
614
615 /** \} group_dma_descriptor_functions */
616
617
618
619 /***************************************
620 * In-line Function Implementation
621 ***************************************/
622
623
624 /**
625 * \addtogroup group_dma_block_functions
626 * \{
627 */
628
629
630 /*******************************************************************************
631 * Function Name: Cy_DMA_Enable
632 ****************************************************************************//**
633 *
634 * Enables the DMA block.
635 *
636 * \param base
637 * The pointer to the hardware DMA block.
638 *
639 * \funcusage
640 * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
641 *
642 *******************************************************************************/
Cy_DMA_Enable(DW_Type * base)643 __STATIC_INLINE void Cy_DMA_Enable(DW_Type * base)
644 {
645 DW_CTL(base) |= DW_CTL_ENABLED_Msk;
646 }
647
648
649 /*******************************************************************************
650 * Function Name: Cy_DMA_Disable
651 ****************************************************************************//**
652 *
653 * Disables the DMA block.
654 *
655 * \param base
656 * The pointer to the hardware DMA block.
657 *
658 * \funcusage
659 * \snippet dma/snippet/main.c snippet_Cy_DMA_Disable
660 *
661 *******************************************************************************/
Cy_DMA_Disable(DW_Type * base)662 __STATIC_INLINE void Cy_DMA_Disable(DW_Type * base)
663 {
664 DW_CTL(base) &= (uint32_t) ~DW_CTL_ENABLED_Msk;
665 }
666
667
668 /*******************************************************************************
669 * Function Name: Cy_DMA_GetActiveChannel
670 ****************************************************************************//**
671 *
672 * Returns the status of the active/pending channels in
673 * the DMA block.
674 *
675 * \param base
676 * The pointer to the hardware DMA block.
677 *
678 * \return
679 * For DW Version 1 based devices,
680 * returns a bit-field with all of the currently active/pending channels in the
681 * DMA block.
682 *
683 * \note For DW Version 2 based devices,
684 * returns a bit-field with first 32 channels currently active/pending in the DMA block.
685 * In addition to this, user can get the active channel index using \ref Cy_DMA_GetActiveChannelIndex.
686 *
687 * \funcusage
688 * \snippet dma/snippet/main.c snippet_Cy_DMA_Disable
689 *
690 *******************************************************************************/
Cy_DMA_GetActiveChannel(DW_Type const * base)691 __STATIC_INLINE uint32_t Cy_DMA_GetActiveChannel(DW_Type const * base)
692 {
693
694 #if defined (CY_IP_M4CPUSS_DMA) && (CY_IP_M4CPUSS_DMA_VERSION == 1u)
695 /* DW version 1 provides consolidated status of pending and active channels in PENDING register */
696 return (DW_PENDING(base));
697 #else
698 /* DW version 2 supports upto 512 channels and cannot fit the status in a 32-bit integer */
699 /* Returns bit-field for 32 channels in case more channels are available user to use new API */
700 {
701 uint32_t channels_pending = 0UL;
702 uint32_t max_channels = CY_DMA_CH_NR_AVAILABLE(base);
703
704 /* Get Channel Pending status from individual channel status information */
705 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 14.3','channel_nr may be higher or lower than 32 depending on target device.');
706 for(uint8_t channel_nr = 0U; (channel_nr < 32U && channel_nr < max_channels); channel_nr++)
707 {
708 channels_pending |= (_FLD2VAL(DW_CH_STRUCT_CH_STATUS_PENDING, DW_CH_STATUS(base, channel_nr)) << channel_nr);
709 }
710
711 return channels_pending;
712 }
713 #endif
714
715 }
716 /*******************************************************************************
717 * Function Name: Cy_DMA_GetActiveChannelIndex
718 ****************************************************************************//**
719 *
720 * Returns the index of the active channel within the DMA block.
721 *
722 * \param base
723 * The pointer to the hardware DMA block.
724 *
725 * \return
726 * active channel index if present otherwise \ref CY_DMA_NO_ACTIVE_CHANNELS
727 *
728 *******************************************************************************/
Cy_DMA_GetActiveChannelIndex(DW_Type const * base)729 __STATIC_INLINE uint32_t Cy_DMA_GetActiveChannelIndex(DW_Type const * base)
730 {
731 if (_FLD2VAL(DW_STATUS_ACTIVE, DW_STATUS(base)) == 1U)
732 {
733 return(_FLD2VAL(CY_DW_STATUS_CH_IDX, DW_STATUS(base)));
734 }
735 else
736 {
737 return CY_DMA_NO_ACTIVE_CHANNELS;
738 }
739 }
740
741
742 /*******************************************************************************
743 * Function Name: Cy_DMA_GetActiveSrcAddress
744 ****************************************************************************//**
745 *
746 * Returns the source address being used for the current transfer.
747 *
748 * \param base
749 * The pointer to the hardware DMA block.
750 *
751 * \return
752 * Returns the pointer to the source of transfer.
753 *
754 * \funcusage
755 * \snippet dma/snippet/main.c snippet_Cy_DMA_GetActiveSrcAddress
756 *
757 *******************************************************************************/
Cy_DMA_GetActiveSrcAddress(DW_Type const * base)758 __STATIC_INLINE void * Cy_DMA_GetActiveSrcAddress(DW_Type const * base)
759 {
760 return ((void *) DW_DESCR_SRC(base));
761 }
762
763
764 /*******************************************************************************
765 * Function Name: Cy_DMA_GetActiveDstAddress
766 ****************************************************************************//**
767 *
768 * Returns the destination address being used for the current transfer.
769 *
770 * \param base
771 * The pointer to the hardware DMA block.
772 *
773 * \return
774 * Returns the pointer to the destination of transfer.
775 *
776 * \funcusage
777 * \snippet dma/snippet/main.c snippet_Cy_DMA_GetActiveSrcAddress
778 *
779 *******************************************************************************/
Cy_DMA_GetActiveDstAddress(DW_Type const * base)780 __STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type const * base)
781 {
782 return ((void *) DW_DESCR_DST(base));
783 }
784
785 /** \} group_dma_block_functions */
786
787 /**
788 * \addtogroup group_dma_descriptor_functions
789 * \{
790 */
791
792
793 /*******************************************************************************
794 * Function Name: Cy_DMA_Descriptor_SetSrcAddress
795 ****************************************************************************//**
796 *
797 * Sets the source address for the specified descriptor.
798 *
799 * \param descriptor
800 * The descriptor structure instance declared by the user/component.
801 *
802 * \param srcAddress
803 * The source address value for the descriptor.
804 * For CAT1C devices this data pointer needs to point to 32 bit aligned data.
805 *
806 * \funcusage
807 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
808 *
809 *******************************************************************************/
Cy_DMA_Descriptor_SetSrcAddress(cy_stc_dma_descriptor_t * descriptor,void const * srcAddress)810 __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress(cy_stc_dma_descriptor_t * descriptor, void const * srcAddress)
811 {
812 descriptor->src = (uint32_t) srcAddress;
813 }
814
815
816 /*******************************************************************************
817 * Function Name: Cy_DMA_Descriptor_GetSrcAddress
818 ****************************************************************************//**
819 *
820 * Returns the source address parameter of the specified descriptor.
821 *
822 * \param descriptor
823 * The descriptor structure instance declared by the user/component.
824 *
825 * \return
826 * The source address value of the descriptor.
827 *
828 * \funcusage
829 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
830 *
831 *******************************************************************************/
Cy_DMA_Descriptor_GetSrcAddress(cy_stc_dma_descriptor_t const * descriptor)832 __STATIC_INLINE void * Cy_DMA_Descriptor_GetSrcAddress(cy_stc_dma_descriptor_t const * descriptor)
833 {
834 return ((void *) descriptor->src);
835 }
836
837
838 /*******************************************************************************
839 * Function Name: Cy_DMA_Descriptor_SetDstAddress
840 ****************************************************************************//**
841 *
842 * Sets the destination address for the specified descriptor.
843 *
844 * \param descriptor
845 * The descriptor structure instance declared by the user/component.
846 *
847 * \param dstAddress
848 * The destination address value for the descriptor.
849 * For CAT1C devices this data pointer needs to point to 32 byte aligned data.
850 *
851 * \funcusage
852 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
853 *
854 *******************************************************************************/
Cy_DMA_Descriptor_SetDstAddress(cy_stc_dma_descriptor_t * descriptor,void const * dstAddress)855 __STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress(cy_stc_dma_descriptor_t * descriptor, void const * dstAddress)
856 {
857 descriptor->dst = (uint32_t) dstAddress;
858 }
859
860
861 /*******************************************************************************
862 * Function Name: Cy_DMA_Descriptor_GetDstAddress
863 ****************************************************************************//**
864 *
865 * Returns the destination address parameter of the specified descriptor.
866 *
867 * \param descriptor
868 * The descriptor structure instance declared by the user/component.
869 *
870 * \return
871 * The destination address value of the descriptor.
872 *
873 * \funcusage
874 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
875 *
876 *******************************************************************************/
Cy_DMA_Descriptor_GetDstAddress(cy_stc_dma_descriptor_t const * descriptor)877 __STATIC_INLINE void * Cy_DMA_Descriptor_GetDstAddress(cy_stc_dma_descriptor_t const * descriptor)
878 {
879 return ((void *) descriptor->dst);
880 }
881
882
883 /*******************************************************************************
884 * Function Name: Cy_DMA_Descriptor_SetInterruptType
885 ****************************************************************************//**
886 *
887 * Sets the interrupt type for the specified descriptor.
888 *
889 * \param descriptor
890 * The descriptor structure instance declared by the user/component.
891 *
892 * \param interruptType
893 * The interrupt type set for the descriptor. \ref cy_en_dma_trigger_type_t
894 *
895 * \funcusage
896 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
897 *
898 *******************************************************************************/
Cy_DMA_Descriptor_SetInterruptType(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_trigger_type_t interruptType)899 __STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t interruptType)
900 {
901 CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(interruptType));
902
903 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_INTR_TYPE, interruptType);
904 }
905
906
907 /*******************************************************************************
908 * Function Name: Cy_DMA_Descriptor_GetInterruptType
909 ****************************************************************************//**
910 *
911 * Returns the Interrupt-Type of the specified descriptor.
912 *
913 * \param descriptor
914 * The descriptor structure instance declared by the user/component.
915 *
916 * \return
917 * The Interrupt-Type \ref cy_en_dma_trigger_type_t.
918 *
919 * \funcusage
920 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
921 *
922 *******************************************************************************/
Cy_DMA_Descriptor_GetInterruptType(cy_stc_dma_descriptor_t const * descriptor)923 __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType(cy_stc_dma_descriptor_t const * descriptor)
924 {
925 return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_INTR_TYPE, descriptor->ctl));
926 }
927
928
929 /*******************************************************************************
930 * Function Name: Cy_DMA_Descriptor_SetTriggerInType
931 ****************************************************************************//**
932 *
933 * Sets the Trigger-In-Type for the specified descriptor.
934 *
935 * \param descriptor
936 * The descriptor structure instance declared by the user/component.
937 *
938 * \param triggerInType
939 * The Trigger In Type parameter \ref cy_en_dma_trigger_type_t
940 *
941 * \funcusage
942 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
943 *
944 *******************************************************************************/
Cy_DMA_Descriptor_SetTriggerInType(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_trigger_type_t triggerInType)945 __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerInType)
946 {
947 CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerInType));
948
949 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_TR_IN_TYPE, triggerInType);
950 }
951
952
953 /*******************************************************************************
954 * Function Name: Cy_DMA_Descriptor_GetTriggerInType
955 ****************************************************************************//**
956 *
957 * Returns the Trigger-In-Type parameter of the specified descriptor.
958 *
959 * \param descriptor
960 * The descriptor structure instance declared by the user/component.
961 *
962 * \return
963 * The Trigger-In-Type \ref cy_en_dma_trigger_type_t
964 *
965 * \funcusage
966 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
967 *
968 *******************************************************************************/
Cy_DMA_Descriptor_GetTriggerInType(cy_stc_dma_descriptor_t const * descriptor)969 __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType(cy_stc_dma_descriptor_t const * descriptor)
970 {
971 return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_IN_TYPE, descriptor->ctl));
972 }
973
974
975 /*******************************************************************************
976 * Function Name: Cy_DMA_Descriptor_SetTriggerOutType
977 ****************************************************************************//**
978 *
979 * Sets the Trigger-Out-Type for the specified descriptor.
980 *
981 * \param descriptor
982 * The descriptor structure instance declared by the user/component.
983 *
984 * \param triggerOutType
985 * The Trigger-Out-Type set for the descriptor. \ref cy_en_dma_trigger_type_t
986 *
987 * \funcusage
988 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
989 *
990 *******************************************************************************/
Cy_DMA_Descriptor_SetTriggerOutType(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_trigger_type_t triggerOutType)991 __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerOutType)
992 {
993 CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerOutType));
994
995 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_TR_OUT_TYPE, triggerOutType);
996 }
997
998
999 /*******************************************************************************
1000 * Function Name: Cy_DMA_Descriptor_GetTriggerOutType
1001 ****************************************************************************//**
1002 *
1003 * Returns the Trigger-Out-Type parameter of the specified descriptor.
1004 *
1005 * \param descriptor
1006 * The descriptor structure instance declared by the user/component.
1007 *
1008 * \return
1009 * The Trigger-Out-Type parameter \ref cy_en_dma_trigger_type_t.
1010 *
1011 * \funcusage
1012 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1013 *
1014 *******************************************************************************/
Cy_DMA_Descriptor_GetTriggerOutType(cy_stc_dma_descriptor_t const * descriptor)1015 __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType(cy_stc_dma_descriptor_t const * descriptor)
1016 {
1017 return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_OUT_TYPE, descriptor->ctl));
1018 }
1019
1020
1021 /*******************************************************************************
1022 * Function Name: Cy_DMA_Descriptor_SetDataSize
1023 ****************************************************************************//**
1024 *
1025 * Sets the Data Element Size for the specified descriptor.
1026 *
1027 * \param descriptor
1028 * The descriptor structure instance declared by the user/component.
1029 *
1030 * \param dataSize
1031 * The Data Element Size \ref cy_en_dma_data_size_t
1032 *
1033 * \funcusage
1034 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1035 *
1036 *******************************************************************************/
Cy_DMA_Descriptor_SetDataSize(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_data_size_t dataSize)1037 __STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_data_size_t dataSize)
1038 {
1039 CY_ASSERT_L3(CY_DMA_IS_DATA_SIZE_VALID(dataSize));
1040
1041 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_DATA_SIZE, dataSize);
1042 }
1043
1044
1045 /*******************************************************************************
1046 * Function Name: Cy_DMA_Descriptor_GetDataSize
1047 ****************************************************************************//**
1048 *
1049 * Returns the Data Element Size parameter of the specified descriptor.
1050 *
1051 * \param descriptor
1052 * The descriptor structure instance declared by the user/component.
1053 *
1054 * \return
1055 * The Data Element Size \ref cy_en_dma_data_size_t.
1056 *
1057 * \funcusage
1058 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1059 *
1060 *******************************************************************************/
Cy_DMA_Descriptor_GetDataSize(cy_stc_dma_descriptor_t const * descriptor)1061 __STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize(cy_stc_dma_descriptor_t const * descriptor)
1062 {
1063 return((cy_en_dma_data_size_t) _FLD2VAL(CY_DMA_CTL_DATA_SIZE, descriptor->ctl));
1064 }
1065
1066
1067 /*******************************************************************************
1068 * Function Name: Cy_DMA_Descriptor_SetSrcTransferSize
1069 ****************************************************************************//**
1070 *
1071 * Sets the Source Transfer Size for the specified descriptor.
1072 *
1073 * \param descriptor
1074 * The descriptor structure instance declared by the user/component.
1075 *
1076 * \param srcTransferSize
1077 * The Source Transfer Size \ref cy_en_dma_transfer_size_t.
1078 *
1079 * \funcusage
1080 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1081 *
1082 *******************************************************************************/
Cy_DMA_Descriptor_SetSrcTransferSize(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_transfer_size_t srcTransferSize)1083 __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t srcTransferSize)
1084 {
1085 CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(srcTransferSize));
1086
1087 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_SRC_SIZE, srcTransferSize);
1088 }
1089
1090
1091 /*******************************************************************************
1092 * Function Name: Cy_DMA_Descriptor_GetSrcTransferSize
1093 ****************************************************************************//**
1094 *
1095 * Returns the Source Transfer Size parameter of the specified descriptor.
1096 *
1097 * \param descriptor
1098 * The descriptor structure instance declared by the user/component.
1099 *
1100 * \return
1101 * The Source Transfer Size \ref cy_en_dma_transfer_size_t.
1102 *
1103 * \funcusage
1104 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1105 *
1106 *******************************************************************************/
Cy_DMA_Descriptor_GetSrcTransferSize(cy_stc_dma_descriptor_t const * descriptor)1107 __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize(cy_stc_dma_descriptor_t const * descriptor)
1108 {
1109 return((cy_en_dma_transfer_size_t) _FLD2VAL(CY_DMA_CTL_SRC_SIZE, descriptor->ctl));
1110 }
1111
1112
1113 /*******************************************************************************
1114 * Function Name: Cy_DMA_Descriptor_SetDstTransferSize
1115 ****************************************************************************//**
1116 *
1117 * Sets the Destination Transfer Size for the specified descriptor.
1118 *
1119 * \param descriptor
1120 * The descriptor structure instance declared by the user/component.
1121 *
1122 * \param dstTransferSize
1123 * The Destination Transfer Size \ref cy_en_dma_transfer_size_t.
1124 *
1125 * \funcusage
1126 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1127 *
1128 *******************************************************************************/
Cy_DMA_Descriptor_SetDstTransferSize(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_transfer_size_t dstTransferSize)1129 __STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t dstTransferSize)
1130 {
1131 CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(dstTransferSize));
1132
1133 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_DST_SIZE, dstTransferSize);
1134 }
1135
1136
1137 /*******************************************************************************
1138 * Function Name: Cy_DMA_Descriptor_GetDstTransferSize
1139 ****************************************************************************//**
1140 *
1141 * Returns the Destination Transfer Size parameter of the specified descriptor.
1142 *
1143 * \param descriptor
1144 * The descriptor structure instance declared by the user/component.
1145 *
1146 * \return
1147 * The Destination Transfer Size \ref cy_en_dma_transfer_size_t.
1148 *
1149 * \funcusage
1150 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1151 *
1152 *******************************************************************************/
Cy_DMA_Descriptor_GetDstTransferSize(cy_stc_dma_descriptor_t const * descriptor)1153 __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize(cy_stc_dma_descriptor_t const * descriptor)
1154 {
1155 return((cy_en_dma_transfer_size_t) _FLD2VAL(CY_DMA_CTL_DST_SIZE, descriptor->ctl));
1156 }
1157
1158
1159 /*******************************************************************************
1160 * Function Name: Cy_DMA_Descriptor_SetRetrigger
1161 ****************************************************************************//**
1162 *
1163 * Sets the retrigger value that specifies whether the controller should
1164 * wait for the input trigger to be deactivated.
1165 *
1166 * \param descriptor
1167 * The descriptor structure instance declared by the user/component.
1168 *
1169 * \param retrigger
1170 * The \ref cy_en_dma_retrigger_t parameter specifies whether the controller
1171 * should wait for the input trigger to be deactivated.
1172 *
1173 * \funcusage
1174 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1175 *
1176 *******************************************************************************/
Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_retrigger_t retrigger)1177 __STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_retrigger_t retrigger)
1178 {
1179 CY_ASSERT_L3(CY_DMA_IS_RETRIG_VALID(retrigger));
1180
1181 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_RETRIG, retrigger);
1182 }
1183
1184
1185 /*******************************************************************************
1186 * Function Name: Cy_DMA_Descriptor_GetRetrigger
1187 ****************************************************************************//**
1188 *
1189 * Returns a value that specifies whether the controller should
1190 * wait for the input trigger to be deactivated.
1191 *
1192 * \param descriptor
1193 * The descriptor structure instance declared by the user/component.
1194 *
1195 * \return
1196 * The Retrigger setting \ref cy_en_dma_retrigger_t.
1197 *
1198 * \funcusage
1199 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1200 *
1201 *******************************************************************************/
Cy_DMA_Descriptor_GetRetrigger(cy_stc_dma_descriptor_t const * descriptor)1202 __STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger(cy_stc_dma_descriptor_t const * descriptor)
1203 {
1204 return((cy_en_dma_retrigger_t) _FLD2VAL(CY_DMA_CTL_RETRIG, descriptor->ctl));
1205 }
1206
1207
1208 /*******************************************************************************
1209 * Function Name: Cy_DMA_Descriptor_GetDescriptorType
1210 ****************************************************************************//**
1211 *
1212 * Returns the descriptor's type of the specified descriptor.
1213 *
1214 * \param descriptor
1215 * The descriptor structure instance declared by the user/component.
1216 *
1217 * \return
1218 * The descriptor type \ref cy_en_dma_descriptor_type_t.
1219 *
1220 * \funcusage
1221 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1222 *
1223 *******************************************************************************/
Cy_DMA_Descriptor_GetDescriptorType(cy_stc_dma_descriptor_t const * descriptor)1224 __STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType(cy_stc_dma_descriptor_t const * descriptor)
1225 {
1226 return((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl));
1227 }
1228
1229
1230 /*******************************************************************************
1231 * Function Name: Cy_DMA_Descriptor_SetChannelState
1232 ****************************************************************************//**
1233 *
1234 * Sets the channel state on completion of the specified descriptor.
1235 *
1236 * \param descriptor
1237 * The descriptor structure instance declared by the user/component.
1238 *
1239 * \param channelState
1240 * The channel state \ref cy_en_dma_channel_state_t.
1241 *
1242 * \funcusage
1243 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1244 *
1245 *******************************************************************************/
Cy_DMA_Descriptor_SetChannelState(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_channel_state_t channelState)1246 __STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_channel_state_t channelState)
1247 {
1248 CY_ASSERT_L3(CY_DMA_IS_CHANNEL_STATE_VALID(channelState));
1249
1250 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_CH_DISABLE, channelState);
1251 }
1252
1253
1254 /*******************************************************************************
1255 * Function Name: Cy_DMA_Descriptor_GetChannelState
1256 ****************************************************************************//**
1257 *
1258 * Returns the channel state on completion of the specified descriptor.
1259 *
1260 * \param descriptor
1261 * The descriptor structure instance declared by the user/component.
1262 *
1263 * \return
1264 * The Channel State setting \ref cy_en_dma_channel_state_t.
1265 *
1266 * \funcusage
1267 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1268 *
1269 *******************************************************************************/
Cy_DMA_Descriptor_GetChannelState(cy_stc_dma_descriptor_t const * descriptor)1270 __STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState(cy_stc_dma_descriptor_t const * descriptor)
1271 {
1272 return((cy_en_dma_channel_state_t) _FLD2VAL(CY_DMA_CTL_CH_DISABLE, descriptor->ctl));
1273 }
1274
1275
1276 /*******************************************************************************
1277 * Function Name: Cy_DMA_Descriptor_SetXloopDataCount
1278 ****************************************************************************//**
1279 *
1280 * Sets the number of data elements to transfer in the X loop
1281 * for the specified descriptor (for 1D or 2D descriptors only).
1282 *
1283 * \param descriptor
1284 * The descriptor structure instance declared by the user/component.
1285 *
1286 * \param xCount
1287 * The number of data elements to transfer in the X loop. Valid range is 1 ... 256.
1288 *
1289 * \funcusage
1290 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1291 *
1292 *******************************************************************************/
Cy_DMA_Descriptor_SetXloopDataCount(cy_stc_dma_descriptor_t * descriptor,uint32_t xCount)1293 __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t xCount)
1294 {
1295 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1296 CY_ASSERT_L2(CY_DMA_IS_LOOP_COUNT_VALID(xCount));
1297 /* Convert the data count from the user's range (1-256) into the machine range (0-255). */
1298 CY_REG32_CLR_SET(descriptor->xCtl, CY_DMA_CTL_COUNT, xCount - 1UL);
1299 }
1300
1301
1302 /*******************************************************************************
1303 * Function Name: Cy_DMA_Descriptor_GetXloopDataCount
1304 ****************************************************************************//**
1305 *
1306 * Returns the number of data elements for the X loop of the specified
1307 * descriptor (for 1D or 2D descriptors only).
1308 *
1309 * \param descriptor
1310 * The descriptor structure instance declared by the user/component.
1311 *
1312 * \return
1313 * The number of data elements to transfer in the X loop. The range is 1 ... 256.
1314 *
1315 * \funcusage
1316 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1317 *
1318 *******************************************************************************/
Cy_DMA_Descriptor_GetXloopDataCount(cy_stc_dma_descriptor_t const * descriptor)1319 __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount(cy_stc_dma_descriptor_t const * descriptor)
1320 {
1321 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1322 /* Convert the data count from the machine range (0-255) into the user's range (1-256). */
1323 return (_FLD2VAL(CY_DMA_CTL_COUNT, descriptor->xCtl) + 1UL);
1324 }
1325
1326
1327 /*******************************************************************************
1328 * Function Name: Cy_DMA_Descriptor_SetXloopSrcIncrement
1329 ****************************************************************************//**
1330 *
1331 * Sets the source increment parameter for the X loop of the specified
1332 * descriptor (for 1D or 2D descriptors only).
1333 *
1334 * \param descriptor
1335 * The descriptor structure instance declared by the user/component.
1336 *
1337 * \param srcXincrement
1338 * The value of the source increment. The valid range is -2048 ... 2047.
1339 *
1340 * \funcusage
1341 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1342 *
1343 *******************************************************************************/
Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor,int32_t srcXincrement)1344 __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcXincrement)
1345 {
1346 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1347 CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(srcXincrement));
1348
1349 CY_REG32_CLR_SET(descriptor->xCtl, CY_DMA_CTL_SRC_INCR, srcXincrement);
1350 }
1351
1352
1353 /*******************************************************************************
1354 * Function Name: Cy_DMA_Descriptor_GetXloopSrcIncrement
1355 ****************************************************************************//**
1356 *
1357 * Returns the source increment parameter for the X loop of the specified
1358 * descriptor (for 1D or 2D descriptors only).
1359 *
1360 * \param descriptor
1361 * The descriptor structure instance declared by the user/component.
1362 *
1363 * \return
1364 * The value of the source increment. The range is -2048 ... 2047.
1365 *
1366 * \funcusage
1367 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1368 *
1369 *******************************************************************************/
Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor)1370 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor)
1371 {
1372 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1373
1374 return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->xCtl));
1375 }
1376
1377
1378 /*******************************************************************************
1379 * Function Name: Cy_DMA_Descriptor_SetXloopDstIncrement
1380 ****************************************************************************//**
1381 *
1382 * Sets the destination increment parameter for the X loop for the specified
1383 * descriptor (for 1D or 2D descriptors only).
1384 *
1385 * \param descriptor
1386 * The descriptor structure instance declared by the user/component.
1387 *
1388 * \param dstXincrement
1389 * The value of the destination increment. The valid range is -2048 ... 2047.
1390 *
1391 * \funcusage
1392 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1393 *
1394 *******************************************************************************/
Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor,int32_t dstXincrement)1395 __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstXincrement)
1396 {
1397 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1398 CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(dstXincrement));
1399
1400 CY_REG32_CLR_SET(descriptor->xCtl, CY_DMA_CTL_DST_INCR, dstXincrement);
1401 }
1402
1403
1404 /*******************************************************************************
1405 * Function Name: Cy_DMA_Descriptor_GetXloopDstIncrement
1406 ****************************************************************************//**
1407 *
1408 * Returns the destination increment parameter for the X loop of the specified
1409 * descriptor (for 1D or 2D descriptors only).
1410 *
1411 * \param descriptor
1412 * The descriptor structure instance declared by the user/component.
1413 *
1414 * \return
1415 * The value of the destination increment. The range is -2048 ... 2047.
1416 *
1417 * \funcusage
1418 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1419 *
1420 *******************************************************************************/
Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor)1421 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor)
1422 {
1423 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1424
1425 return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->xCtl));
1426 }
1427
1428
1429 /*******************************************************************************
1430 * Function Name: Cy_DMA_Descriptor_SetYloopDataCount
1431 ****************************************************************************//**
1432 *
1433 * Sets the number of data elements for the Y loop of the specified descriptor
1434 * (for 2D descriptors only).
1435 *
1436 * \param descriptor
1437 * The descriptor structure instance declared by the user/component.
1438 *
1439 * \param yCount
1440 * The number of X loops to execute in the Y loop. The valid range is 1 ... 256.
1441 *
1442 * \funcusage
1443 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1444 *
1445 *******************************************************************************/
Cy_DMA_Descriptor_SetYloopDataCount(cy_stc_dma_descriptor_t * descriptor,uint32_t yCount)1446 __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t yCount)
1447 {
1448 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1449 CY_ASSERT_L2(CY_DMA_IS_LOOP_COUNT_VALID(yCount));
1450 /* Convert the data count from the user's range (1-256) into the machine range (0-255). */
1451 CY_REG32_CLR_SET(descriptor->yCtl, CY_DMA_CTL_COUNT, yCount - 1UL);
1452 }
1453
1454
1455 /*******************************************************************************
1456 * Function Name: Cy_DMA_Descriptor_GetYloopDataCount
1457 ****************************************************************************//**
1458 *
1459 * Returns the number of X loops to execute in the Y loop of the specified
1460 * descriptor (for 2D descriptors only).
1461 *
1462 * \param descriptor
1463 * The descriptor structure instance declared by the user/component.
1464 *
1465 * \return
1466 * The number of X loops to execute in the Y loop. The range is 1 ... 256.
1467 *
1468 * \funcusage
1469 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1470 *
1471 *******************************************************************************/
Cy_DMA_Descriptor_GetYloopDataCount(cy_stc_dma_descriptor_t const * descriptor)1472 __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount(cy_stc_dma_descriptor_t const * descriptor)
1473 {
1474 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1475 /* Convert the data count from the machine range (0-255) into the user's range (1-256). */
1476 return (_FLD2VAL(CY_DMA_CTL_COUNT, descriptor->yCtl) + 1UL);
1477 }
1478
1479
1480 /*******************************************************************************
1481 * Function Name: Cy_DMA_Descriptor_SetYloopSrcIncrement
1482 ****************************************************************************//**
1483 *
1484 * Sets the source increment parameter for the Y loop for the specified
1485 * descriptor (for 2D descriptors only).
1486 *
1487 * \param descriptor
1488 * The descriptor structure instance declared by the user/component.
1489 *
1490 * \param srcYincrement
1491 * The value of the source increment. The valid range is -2048 ... 2047.
1492 *
1493 * \funcusage
1494 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1495 *
1496 *******************************************************************************/
Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor,int32_t srcYincrement)1497 __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcYincrement)
1498 {
1499 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1500 CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(srcYincrement));
1501
1502 CY_REG32_CLR_SET(descriptor->yCtl, CY_DMA_CTL_SRC_INCR, srcYincrement);
1503 }
1504
1505
1506 /*******************************************************************************
1507 * Function Name: Cy_DMA_Descriptor_GetYloopSrcIncrement
1508 ****************************************************************************//**
1509 *
1510 * Returns the source increment parameter for the outer Y of the specified
1511 * descriptor (for 2D descriptors only).
1512 *
1513 * \param descriptor
1514 * The descriptor structure instance declared by the user/component.
1515 *
1516 * \return
1517 * The value of the source increment. The range is -2048 ... 2047.
1518 *
1519 * \funcusage
1520 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1521 *
1522 *******************************************************************************/
Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor)1523 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor)
1524 {
1525 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1526
1527 return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->yCtl));
1528 }
1529
1530
1531 /*******************************************************************************
1532 * Function Name: Cy_DMA_Descriptor_SetYloopDstIncrement
1533 ****************************************************************************//**
1534 *
1535 * Sets the destination increment parameter for the Y loop of the specified
1536 * descriptor (for 2D descriptors only).
1537 *
1538 * \param descriptor
1539 * The descriptor structure instance declared by the user/component.
1540 *
1541 * \param dstYincrement
1542 * The value of the destination increment. The valid range is -2048 ... 2047.
1543 *
1544 * \funcusage
1545 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1546 *
1547 *******************************************************************************/
Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descriptor_t * descriptor,int32_t dstYincrement)1548 __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstYincrement)
1549 {
1550 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1551 CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(dstYincrement));
1552
1553 CY_REG32_CLR_SET(descriptor->yCtl, CY_DMA_CTL_DST_INCR, dstYincrement);
1554 }
1555
1556
1557 /*******************************************************************************
1558 * Function Name: Cy_DMA_Descriptor_GetYloopDstIncrement
1559 ****************************************************************************//**
1560 *
1561 * Returns the destination increment parameter for the Y loop of the specified
1562 * descriptor (for 2D descriptors only).
1563 *
1564 * \param descriptor
1565 * The descriptor structure instance declared by the user/component.
1566 *
1567 * \return
1568 * The value of the destination increment. The range is -2048 ... 2047.
1569 *
1570 * \funcusage
1571 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1572 *
1573 *******************************************************************************/
Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor)1574 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor)
1575 {
1576 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1577
1578 return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->yCtl));
1579 }
1580
1581
1582 /** \} group_dma_descriptor_functions */
1583
1584
1585 /**
1586 * \addtogroup group_dma_channel_functions
1587 * \{
1588 */
1589
1590
1591 /*******************************************************************************
1592 * Function Name: Cy_DMA_Channel_SetDescriptor
1593 ****************************************************************************//**
1594 *
1595 * Sets a descriptor as current for the specified DMA channel.
1596 *
1597 * \param base
1598 * The pointer to the hardware DMA block.
1599 *
1600 * \param channel
1601 * The channel number.
1602 *
1603 * \param descriptor
1604 * This is the descriptor to be associated with the channel.
1605 * For CAT1C devices this pointer needs to point to 32 byte aligned structure.
1606 *
1607 * \funcusage
1608 * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
1609 *
1610 *******************************************************************************/
Cy_DMA_Channel_SetDescriptor(DW_Type * base,uint32_t channel,cy_stc_dma_descriptor_t const * descriptor)1611 __STATIC_INLINE void Cy_DMA_Channel_SetDescriptor(DW_Type * base, uint32_t channel, cy_stc_dma_descriptor_t const * descriptor)
1612 {
1613 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1614
1615 DW_CH_CURR_PTR(base, channel) = (uint32_t)descriptor;
1616 DW_CH_IDX(base, channel) &= (uint32_t) ~(DW_CH_STRUCT_CH_IDX_X_IDX_Msk | DW_CH_STRUCT_CH_IDX_Y_IDX_Msk);
1617 }
1618
1619
1620 /*******************************************************************************
1621 * Function Name: Cy_DMA_Channel_Enable
1622 ****************************************************************************//**
1623 *
1624 * The function is used to enable a DMA channel.
1625 *
1626 * \param base
1627 * The pointer to the hardware DMA block.
1628 *
1629 * \param channel
1630 * The channel number.
1631 *
1632 * \funcusage
1633 * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
1634 *
1635 *******************************************************************************/
Cy_DMA_Channel_Enable(DW_Type * base,uint32_t channel)1636 __STATIC_INLINE void Cy_DMA_Channel_Enable(DW_Type * base, uint32_t channel)
1637 {
1638 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1639
1640 DW_CH_CTL(base, channel) |= DW_CH_STRUCT_CH_CTL_ENABLED_Msk;
1641 }
1642
1643
1644 /*******************************************************************************
1645 * Function Name: Cy_DMA_Channel_Disable
1646 ****************************************************************************//**
1647 *
1648 * The function is used to disable a DMA channel.
1649 *
1650 * \param base
1651 * The pointer to the hardware DMA block.
1652 *
1653 * \param channel
1654 * The channel number.
1655 *
1656 * \funcusage
1657 * \snippet dma/snippet/main.c snippet_Cy_DMA_Disable
1658 *
1659 *******************************************************************************/
Cy_DMA_Channel_Disable(DW_Type * base,uint32_t channel)1660 __STATIC_INLINE void Cy_DMA_Channel_Disable(DW_Type * base, uint32_t channel)
1661 {
1662 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1663
1664 DW_CH_CTL(base, channel) &= (uint32_t) ~DW_CH_STRUCT_CH_CTL_ENABLED_Msk;
1665 }
1666
1667
1668 /*******************************************************************************
1669 * Function Name: Cy_DMA_Channel_IsEnabled
1670 ****************************************************************************//**
1671 *
1672 * The function checks whether a channel is in the enabled state.
1673 *
1674 * \param base
1675 * The pointer to the hardware DMA block.
1676 *
1677 * \param channel
1678 * The channel number.
1679 *
1680 * \funcusage
1681 * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
1682 *
1683 *******************************************************************************/
Cy_DMA_Channel_IsEnabled(DW_Type * base,uint32_t channel)1684 __STATIC_INLINE bool Cy_DMA_Channel_IsEnabled(DW_Type * base, uint32_t channel)
1685 {
1686 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1687
1688 return ((bool)((DW_CH_CTL(base, channel) & DW_CH_STRUCT_CH_CTL_ENABLED_Msk) != 0u));
1689 }
1690
1691
1692 /*******************************************************************************
1693 * Function Name: Cy_DMA_Channel_SetPriority
1694 ****************************************************************************//**
1695 *
1696 * The function is used to set a priority for the DMA channel.
1697 *
1698 * \param base
1699 * The pointer to the hardware DMA block.
1700 *
1701 * \param channel
1702 * The channel number.
1703 *
1704 * \param priority
1705 * The priority to be set for the DMA channel. The allowed values are 0,1,2,3.
1706 *
1707 * \funcusage
1708 * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
1709 *
1710 *******************************************************************************/
Cy_DMA_Channel_SetPriority(DW_Type * base,uint32_t channel,uint32_t priority)1711 __STATIC_INLINE void Cy_DMA_Channel_SetPriority(DW_Type * base, uint32_t channel, uint32_t priority)
1712 {
1713 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1714 CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(priority));
1715
1716 CY_REG32_CLR_SET(DW_CH_CTL(base, channel), CY_DW_CH_CTL_PRIO, priority);
1717 }
1718
1719
1720 /*******************************************************************************
1721 * Function Name: Cy_DMA_Channel_GetPriority
1722 ****************************************************************************//**
1723 *
1724 * Returns the priority of the DMA channel.
1725 *
1726 * \param base
1727 * The pointer to the hardware DMA block.
1728 *
1729 * \param channel
1730 * The channel number.
1731 *
1732 * \return
1733 * The priority of the channel.
1734 *
1735 * \funcusage
1736 * \snippet dma/snippet/main.c snippet_Cy_DMA_Disable
1737 *
1738 *******************************************************************************/
Cy_DMA_Channel_GetPriority(DW_Type const * base,uint32_t channel)1739 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority(DW_Type const * base, uint32_t channel)
1740 {
1741 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1742
1743 return ((uint32_t) _FLD2VAL(CY_DW_CH_CTL_PRIO, DW_CH_CTL(base, channel)));
1744 }
1745
1746
1747 /*******************************************************************************
1748 * Function Name: Cy_DMA_Channel_GetCurrentDescriptor
1749 ****************************************************************************//**
1750 *
1751 * Returns the descriptor that is active in the channel.
1752 *
1753 * \param base
1754 * The pointer to the hardware DMA block.
1755 *
1756 * \param channel
1757 * The channel number.
1758 *
1759 * \return
1760 * The pointer to the descriptor associated with the channel.
1761 *
1762 * \funcusage
1763 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_Deinit
1764 *
1765 *******************************************************************************/
Cy_DMA_Channel_GetCurrentDescriptor(DW_Type const * base,uint32_t channel)1766 __STATIC_INLINE cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor(DW_Type const * base, uint32_t channel)
1767 {
1768 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1769
1770 return ((cy_stc_dma_descriptor_t*)(DW_CH_CURR_PTR(base, channel)));
1771 }
1772
1773 /*******************************************************************************
1774 * Function Name: Cy_DMA_Channel_GetCurrentYIndex
1775 ****************************************************************************//**
1776 *
1777 * Returns the current Y loop index for the channel.
1778 *
1779 * \param base
1780 * The pointer to the hardware DMA block.
1781 *
1782 * \param channel
1783 * The channel number.
1784 *
1785 * \return
1786 * Y loop index value.
1787 *
1788 * \funcusage
1789 * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
1790 *
1791 *******************************************************************************/
Cy_DMA_Channel_GetCurrentYIndex(DW_Type const * base,uint32_t channel)1792 __STATIC_INLINE uint8_t Cy_DMA_Channel_GetCurrentYIndex(DW_Type const * base, uint32_t channel)
1793 {
1794 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1795
1796 return (uint8_t)((DW_CH_IDX(base, channel) & DW_CH_STRUCT_CH_IDX_Y_IDX_Msk) >> DW_CH_STRUCT_CH_IDX_Y_IDX_Pos);
1797 }
1798
1799 /*******************************************************************************
1800 * Function Name: Cy_DMA_Channel_GetInterruptStatus
1801 ****************************************************************************//**
1802 *
1803 * Returns the interrupt status of the specified channel.
1804 *
1805 * \param base
1806 * The pointer to the hardware DMA block.
1807 *
1808 * \param channel
1809 * The channel number.
1810 *
1811 * \return
1812 * The status of an interrupt for the specified channel.
1813 *
1814 * \funcusage
1815 * \snippet dma/snippet/main.c snippet_Cy_DMA_GetInterruptStatus
1816 *
1817 *******************************************************************************/
Cy_DMA_Channel_GetInterruptStatus(DW_Type const * base,uint32_t channel)1818 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus(DW_Type const * base, uint32_t channel)
1819 {
1820 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1821
1822 return (DW_CH_INTR(base, channel));
1823 }
1824
1825
1826 /*******************************************************************************
1827 * Function Name: Cy_DMA_Channel_GetStatus
1828 ****************************************************************************//**
1829 *
1830 * Returns the interrupt reason of the specified channel.
1831 *
1832 * \param base
1833 * The pointer to the hardware DMA block.
1834 *
1835 * \param channel
1836 * The channel number.
1837 *
1838 * \return
1839 * The cause \ref cy_en_dma_intr_cause_t of the interrupt.
1840 *
1841 * \funcusage
1842 * \snippet dma/snippet/main.c snippet_Cy_DMA_ClearInterrupt
1843 *
1844 *******************************************************************************/
Cy_DMA_Channel_GetStatus(DW_Type const * base,uint32_t channel)1845 __STATIC_INLINE cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus(DW_Type const * base, uint32_t channel)
1846 {
1847 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1848
1849 return ((cy_en_dma_intr_cause_t) _FLD2VAL(DW_CH_STRUCT_CH_STATUS_INTR_CAUSE, DW_CH_STATUS(base, channel)));
1850 }
1851
1852
1853 /*******************************************************************************
1854 * Function Name: Cy_DMA_Channel_ClearInterrupt
1855 ****************************************************************************//**
1856 *
1857 * Clears the interrupt status of the specified channel.
1858 *
1859 * \param base
1860 * The pointer to the hardware DMA block.
1861 *
1862 * \param channel
1863 * The channel number.
1864 *
1865 * \funcusage
1866 * \snippet dma/snippet/main.c snippet_Cy_DMA_ClearInterrupt
1867 *
1868 *******************************************************************************/
Cy_DMA_Channel_ClearInterrupt(DW_Type * base,uint32_t channel)1869 __STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt(DW_Type * base, uint32_t channel)
1870 {
1871 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1872
1873 DW_CH_INTR(base, channel) = CY_DMA_INTR_MASK;
1874 /* This dummy reading is necessary here. It provides a guarantee that interrupt is cleared at returning from this function. */
1875 (void) DW_CH_INTR(base, channel);
1876 }
1877
1878
1879 /*******************************************************************************
1880 * Function Name: Cy_DMA_Channel_SetInterrupt
1881 ****************************************************************************//**
1882 *
1883 * Sets the interrupt for the specified channel.
1884 *
1885 * \param base
1886 * The pointer to the hardware DMA block.
1887 *
1888 * \param channel
1889 * The channel number.
1890 *
1891 * \funcusage
1892 * \snippet dma/snippet/main.c snippet_Cy_DMA_SetInterruptMask
1893 *
1894 *******************************************************************************/
Cy_DMA_Channel_SetInterrupt(DW_Type * base,uint32_t channel)1895 __STATIC_INLINE void Cy_DMA_Channel_SetInterrupt(DW_Type * base, uint32_t channel)
1896 {
1897 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1898
1899 DW_CH_INTR_SET(base, channel) = CY_DMA_INTR_MASK;
1900 }
1901
1902
1903 /*******************************************************************************
1904 * Function Name: Cy_DMA_Channel_GetInterruptMask
1905 ****************************************************************************//**
1906 *
1907 * Returns the interrupt mask value of the specified channel.
1908 *
1909 * \param base
1910 * The pointer to the hardware DMA block.
1911 *
1912 * \param channel
1913 * The channel number.
1914 *
1915 * \return
1916 * The interrupt mask value.
1917 *
1918 * \funcusage
1919 * \snippet dma/snippet/main.c snippet_Cy_DMA_SetInterruptMask
1920 *
1921 *******************************************************************************/
Cy_DMA_Channel_GetInterruptMask(DW_Type const * base,uint32_t channel)1922 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask(DW_Type const * base, uint32_t channel)
1923 {
1924 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1925
1926 return (DW_CH_INTR_MASK(base, channel));
1927 }
1928
1929
1930 /*******************************************************************************
1931 * Function Name: Cy_DMA_Channel_SetInterruptMask
1932 ****************************************************************************//**
1933 *
1934 * Sets an interrupt mask value for the specified channel.
1935 *
1936 * \param base
1937 * The pointer to the hardware DMA block.
1938 *
1939 * \param channel
1940 * The channel number.
1941 *
1942 * \param interrupt
1943 * The interrupt mask:
1944 * CY_DMA_INTR_MASK to enable the interrupt or 0UL to disable the interrupt.
1945 *
1946 * \funcusage
1947 * \snippet dma/snippet/main.c snippet_Cy_DMA_SetInterruptMask
1948 *
1949 *******************************************************************************/
Cy_DMA_Channel_SetInterruptMask(DW_Type * base,uint32_t channel,uint32_t interrupt)1950 __STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask(DW_Type * base, uint32_t channel, uint32_t interrupt)
1951 {
1952 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1953 CY_ASSERT_L2(CY_DMA_IS_INTR_MASK_VALID(interrupt));
1954 DW_CH_INTR_MASK(base, channel) = interrupt;
1955 }
1956
1957
1958 /*******************************************************************************
1959 * Function Name: Cy_DMA_Channel_GetInterruptStatusMasked
1960 ****************************************************************************//**
1961 *
1962 * Returns the logical AND of the corresponding INTR and INTR_MASK fields
1963 * in a single-load operation.
1964 *
1965 * \param base
1966 * The pointer to the hardware DMA block.
1967 *
1968 * \param channel
1969 * The channel number.
1970 *
1971 * \funcusage
1972 * \snippet dma/snippet/main.c snippet_Cy_DMA_ClearInterrupt
1973 *
1974 *******************************************************************************/
Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base,uint32_t channel)1975 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base, uint32_t channel)
1976 {
1977 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1978
1979 return (DW_CH_INTR_MASKED(base, channel));
1980 }
1981
1982 #if !(defined (CY_IP_M4CPUSS_DMA) && (CY_IP_M4CPUSS_DMA_VERSION == 1u)) || defined (CY_DOXYGEN)
1983 /*******************************************************************************
1984 * Function Name: Cy_DMA_Channel_SetSWTrigger
1985 ****************************************************************************//**
1986 *
1987 * The function is used to set a SW trigger for a channel.
1988 *
1989 * \param base
1990 * The pointer to the hardware DMA block.
1991 *
1992 * \param channel
1993 * The channel number.
1994 *
1995 *
1996 *******************************************************************************/
Cy_DMA_Channel_SetSWTrigger(DW_Type const * base,uint32_t channel)1997 __STATIC_FORCEINLINE void Cy_DMA_Channel_SetSWTrigger(DW_Type const * base, uint32_t channel)
1998 {
1999 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
2000 CY_REG32_CLR_SET(DW_CH_TR_CMD(base, channel), DW_CH_STRUCT_TR_CMD_ACTIVATE, 1U);
2001 }
2002 #endif /* !(defined (CY_IP_M4CPUSS_DMA) && (CY_IP_M4CPUSS_DMA_VERSION == 1u)) || defined (CY_DOXYGEN) */
2003 /** \} group_dma_channel_functions */
2004
2005 /** \} group_dma_functions */
2006
2007
2008 /** \cond The definitions to support the backward compatibility, do not use them in new designs */
2009
2010 #if(0U != CY_DMA_BWC)
2011
2012 /* Type definitions */
2013 #define cy_stc_dma_chnl_config_t cy_stc_dma_channel_config_t
2014 #define cy_stc_dma_descr_t cy_stc_dma_descriptor_t
2015 #define cy_stc_dma_descr_config_t cy_stc_dma_descriptor_config_t
2016 #define cy_en_dma_trig_type_t cy_en_dma_trigger_type_t
2017
2018 /* Structure items */
2019 #define DMA_Descriptor descriptor
2020 #define deact retrigger
2021 #define intrType interruptType
2022 #define chStateAtCmplt channelState
2023 #define srcTxfrSize srcTransferSize
2024 #define destTxfrSize dstTransferSize
2025 #define trigoutType triggerOutType
2026 #define triginType triggerInType
2027 #define descrType descriptorType
2028 #define srcAddr srcAddress
2029 #define destAddr dstAddress
2030 #define srcXincr srcXincrement
2031 #define srcYincr srcYincrement
2032 #define destXincr dstXincrement
2033 #define destYincr dstYincrement
2034 #define descrNext nextDescriptor
2035
2036 /* Constants */
2037 #define CY_DMA_CH_DISABLED (CY_DMA_CHANNEL_DISABLED)
2038 #define CY_DMA_CH_ENABLED (CY_DMA_CHANNEL_ENABLED)
2039
2040 #define CY_DMA_TXFR_SIZE_DATA_SIZE (CY_DMA_TRANSFER_SIZE_DATA)
2041 #define CY_DMA_TXFR_SIZE_WORD (CY_DMA_TRANSFER_SIZE_WORD)
2042
2043 #define CY_DMA_INTR_1ELEMENT_CMPLT (CY_DMA_1ELEMENT)
2044 #define CY_DMA_INTR_X_LOOP_CMPLT (CY_DMA_X_LOOP)
2045 #define CY_DMA_INTR_DESCR_CMPLT (CY_DMA_DESCR)
2046 #define CY_DMA_INTR_DESCRCHAIN_CMPLT (CY_DMA_DESCR_CHAIN)
2047
2048 #define CY_DMA_TRIGOUT_1ELEMENT_CMPLT (CY_DMA_1ELEMENT)
2049 #define CY_DMA_TRIGOUT_X_LOOP_CMPLT (CY_DMA_X_LOOP)
2050 #define CY_DMA_TRIGOUT_DESCR_CMPLT (CY_DMA_DESCR)
2051 #define CY_DMA_TRIGOUT_DESCRCHAIN_CMPLT (CY_DMA_DESCR_CHAIN)
2052
2053 #define CY_DMA_TRIGIN_1ELEMENT (CY_DMA_1ELEMENT)
2054 #define CY_DMA_TRIGIN_XLOOP (CY_DMA_X_LOOP)
2055 #define CY_DMA_TRIGIN_DESCR (CY_DMA_DESCR)
2056 #define CY_DMA_TRIGIN_DESCRCHAIN (CY_DMA_DESCR_CHAIN)
2057
2058 #define CY_DMA_INVALID_INPUT_PARAMETERS (CY_DMA_BAD_PARAM)
2059
2060 #define CY_DMA_RETDIG_IM (CY_DMA_RETRIG_IM)
2061 #define CY_DMA_RETDIG_4CYC (CY_DMA_RETRIG_4CYC)
2062 #define CY_DMA_RETDIG_16CYC (CY_DMA_RETRIG_16CYC)
2063
2064 /* Descriptor structure items */
2065 #define DESCR_CTL ctl
2066 #define DESCR_SRC src
2067 #define DESCR_DST dst
2068 #define DESCR_X_CTL xCtl
2069 #define DESCR_Y_CTL yCtl
2070 #define DESCR_NEXT_PTR nextPtr
2071
2072 /* Descriptor structure bitfields */
2073 #define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Pos 0UL
2074 #define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Msk 0x3UL
2075 #define DW_DESCR_STRUCT_DESCR_CTL_INTR_TYPE_Pos 2UL
2076 #define DW_DESCR_STRUCT_DESCR_CTL_INTR_TYPE_Msk 0xCUL
2077 #define DW_DESCR_STRUCT_DESCR_CTL_TR_OUT_TYPE_Pos 4UL
2078 #define DW_DESCR_STRUCT_DESCR_CTL_TR_OUT_TYPE_Msk 0x30UL
2079 #define DW_DESCR_STRUCT_DESCR_CTL_TR_IN_TYPE_Pos 6UL
2080 #define DW_DESCR_STRUCT_DESCR_CTL_TR_IN_TYPE_Msk 0xC0UL
2081 #define DW_DESCR_STRUCT_DESCR_CTL_CH_DISABLE_Pos 24UL
2082 #define DW_DESCR_STRUCT_DESCR_CTL_CH_DISABLE_Msk 0x1000000UL
2083 #define DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Pos 26UL
2084 #define DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Msk 0x4000000UL
2085 #define DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Pos 27UL
2086 #define DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Msk 0x8000000UL
2087 #define DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Pos 28UL
2088 #define DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Msk 0x30000000UL
2089 #define DW_DESCR_STRUCT_DESCR_CTL_DESCR_TYPE_Pos 30UL
2090 #define DW_DESCR_STRUCT_DESCR_CTL_DESCR_TYPE_Msk 0xC0000000UL
2091 #define DW_DESCR_STRUCT_DESCR_SRC_SRC_ADDR_Pos 0UL
2092 #define DW_DESCR_STRUCT_DESCR_SRC_SRC_ADDR_Msk 0xFFFFFFFFUL
2093 #define DW_DESCR_STRUCT_DESCR_DST_DST_ADDR_Pos 0UL
2094 #define DW_DESCR_STRUCT_DESCR_DST_DST_ADDR_Msk 0xFFFFFFFFUL
2095 #define DW_DESCR_STRUCT_DESCR_X_CTL_SRC_X_INCR_Pos 0UL
2096 #define DW_DESCR_STRUCT_DESCR_X_CTL_SRC_X_INCR_Msk 0xFFFUL
2097 #define DW_DESCR_STRUCT_DESCR_X_CTL_DST_X_INCR_Pos 12UL
2098 #define DW_DESCR_STRUCT_DESCR_X_CTL_DST_X_INCR_Msk 0xFFF000UL
2099 #define DW_DESCR_STRUCT_DESCR_X_CTL_X_COUNT_Pos 24UL
2100 #define DW_DESCR_STRUCT_DESCR_X_CTL_X_COUNT_Msk 0xFF000000UL
2101 #define DW_DESCR_STRUCT_DESCR_Y_CTL_SRC_Y_INCR_Pos 0UL
2102 #define DW_DESCR_STRUCT_DESCR_Y_CTL_SRC_Y_INCR_Msk 0xFFFUL
2103 #define DW_DESCR_STRUCT_DESCR_Y_CTL_DST_Y_INCR_Pos 12UL
2104 #define DW_DESCR_STRUCT_DESCR_Y_CTL_DST_Y_INCR_Msk 0xFFF000UL
2105 #define DW_DESCR_STRUCT_DESCR_Y_CTL_Y_COUNT_Pos 24UL
2106 #define DW_DESCR_STRUCT_DESCR_Y_CTL_Y_COUNT_Msk 0xFF000000UL
2107 #define DW_DESCR_STRUCT_DESCR_NEXT_PTR_ADDR_Pos 2UL
2108 #define DW_DESCR_STRUCT_DESCR_NEXT_PTR_ADDR_Msk 0xFFFFFFFCUL
2109
2110 /* Functions */
2111 #define Cy_DMA_GetActiveChnl Cy_DMA_GetActiveChannel
2112 #define Cy_DMA_GetActiveSrcAddr Cy_DMA_GetActiveSrcAddress
2113 #define Cy_DMA_GetActiveDstAddr Cy_DMA_GetActiveDstAddress
2114 #define Cy_DMA_Descr_Init Cy_DMA_Descriptor_Init
2115 #define Cy_DMA_Descr_DeInit Cy_DMA_Descriptor_DeInit
2116 #define Cy_DMA_Descr_SetSrcAddr Cy_DMA_Descriptor_SetSrcAddress
2117 #define Cy_DMA_Descr_SetDestAddr Cy_DMA_Descriptor_SetDstAddress
2118 #define Cy_DMA_Descr_SetNxtDescr Cy_DMA_Descriptor_SetNextDescriptor
2119 #define Cy_DMA_Descr_SetIntrType Cy_DMA_Descriptor_SetInterruptType
2120 #define Cy_DMA_Descr_SetTrigInType Cy_DMA_Descriptor_SetTriggerInType
2121 #define Cy_DMA_Descr_SetTrigOutType Cy_DMA_Descriptor_SetTriggerOutType
2122 #define Cy_DMA_Chnl_Init Cy_DMA_Channel_Init
2123 #define Cy_DMA_Chnl_DeInit Cy_DMA_Channel_DeInit
2124 #define Cy_DMA_Chnl_SetDescr Cy_DMA_Channel_SetDescriptor
2125 #define Cy_DMA_Chnl_Enable Cy_DMA_Channel_Enable
2126 #define Cy_DMA_Chnl_Disable Cy_DMA_Channel_Disable
2127 #define Cy_DMA_Chnl_GetCurrentDescr Cy_DMA_Channel_GetCurrentDescriptor
2128 #define Cy_DMA_Chnl_SetPriority Cy_DMA_Channel_SetPriority
2129 #define Cy_DMA_Chnl_GetPriority Cy_DMA_Channel_GetPriority
2130 #define Cy_DMA_Chnl_GetInterruptStatus Cy_DMA_Channel_GetInterruptStatus
2131 #define Cy_DMA_Chnl_GetInterruptCause Cy_DMA_Channel_GetStatus
2132 #define Cy_DMA_Chnl_ClearInterrupt Cy_DMA_Channel_ClearInterrupt
2133 #define Cy_DMA_Chnl_SetInterrupt Cy_DMA_Channel_SetInterrupt
2134 #define Cy_DMA_Chnl_GetInterruptMask Cy_DMA_Channel_GetInterruptMask
2135 #define Cy_DMA_Chnl_GetInterruptStatusMasked Cy_DMA_Channel_GetInterruptStatusMasked
2136 #define Cy_DMA_Chnl_SetInterruptMask(base, channel) (Cy_DMA_Channel_SetInterruptMask(base, channel, CY_DMA_INTR_MASK))
2137
2138
2139 /*******************************************************************************
2140 * Function Name: Cy_DMA_Descr_SetTxfrWidth
2141 ****************************************************************************//**
2142 * This is a legacy API function. It is left here just for backward compatibility.
2143 * Do not use it in new designs.
2144 *******************************************************************************/
Cy_DMA_Descr_SetTxfrWidth(cy_stc_dma_descr_t * descriptor,uint32_t dataElementSize,uint32_t srcTxfrWidth,uint32_t dstTxfrWidth)2145 __STATIC_INLINE void Cy_DMA_Descr_SetTxfrWidth(cy_stc_dma_descr_t * descriptor,
2146 uint32_t dataElementSize,
2147 uint32_t srcTxfrWidth,
2148 uint32_t dstTxfrWidth)
2149 {
2150 uint32_t regValue;
2151 regValue = descriptor->ctl & ((uint32_t)(~(DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Msk |
2152 DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Msk |
2153 DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Msk)));
2154
2155 descriptor->ctl = regValue |
2156 _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE, dataElementSize) |
2157 _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE, srcTxfrWidth) |
2158 _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE, dstTxfrWidth);
2159 }
2160
2161 #endif /* CY_DMA_BWC */
2162
2163 /** \endcond */
2164
2165 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 10.8')
2166
2167 #if defined(__cplusplus)
2168 }
2169 #endif
2170
2171 #endif /* CY_IP_M4CPUSS_DMA, CY_IP_MXDW */
2172
2173 #endif /* (CY_DMA_H) */
2174
2175 /** \} group_dma */
2176
2177
2178 /* [] END OF FILE */
2179
