1 /***************************************************************************//**
2 * \file cy_ctb.c
3 * \version 2.20
4 *
5 * \brief
6 * Provides the public functions for the CTB driver.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2017-2020 Cypress Semiconductor Corporation
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25 #include "cy_ctb.h"
26
27 #ifdef CY_IP_MXS40PASS
28
29 #ifdef CY_IP_MXS40PASS_CTB
30
31 #if defined(__cplusplus)
32 extern "C" {
33 #endif
34 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 11.3', 121, \
35 'CTBM_Type will typecast to either CTBM_V1_Type or CTBM_V2_Type but not both on PDL initialization based on the target device at compile time.')
36 static uint32_t cy_ctb_oa0Sw; /**< Opamp0 routing control register storage */
37 static uint32_t cy_ctb_oa1Sw; /**< Opamp1 routing control register storage */
38 static uint32_t cy_ctb_ctdSw; /**< CTDAC/CTB routing control register storage */
39
40 #define OA0_SW_Msk (CTBM_OA0_SW_OA0P_A00_Msk | \
41 CTBM_OA0_SW_OA0P_A20_Msk | \
42 CTBM_OA0_SW_OA0P_A30_Msk | \
43 CTBM_OA0_SW_OA0M_A11_Msk | \
44 CTBM_OA0_SW_OA0M_A81_Msk )
45
46 #define OA1_SW_Msk (CTBM_OA1_SW_OA1P_A03_Msk | \
47 CTBM_OA1_SW_OA1P_A13_Msk | \
48 CTBM_OA1_SW_OA1P_A43_Msk | \
49 CTBM_OA1_SW_OA1P_A73_Msk | \
50 CTBM_OA1_SW_OA1M_A22_Msk | \
51 CTBM_OA1_SW_OA1M_A82_Msk )
52
53 #define OA0_CTD_SW_Msk (CTBM_CTD_SW_CTDH_CA0_Msk | \
54 CTBM_CTD_SW_CTDH_CIS_Msk | \
55 CTBM_CTD_SW_CTDH_ILR_Msk )
56
57 #define OA1_CTD_SW_Msk (CTBM_CTD_SW_CTDS_CRS_Msk | \
58 CTBM_CTD_SW_CTDS_COR_Msk )
59
60 #define CTD_SW_Msk (OA0_CTD_SW_Msk | \
61 OA1_CTD_SW_Msk)
62
63
64 /***************************************
65 * Fast Config Selections
66 ***************************************/
67 const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Unused =
68 {
69 /*.oa0Power */ CY_CTB_POWER_OFF,
70 /*.oa0Mode */ CY_CTB_MODE_OPAMP1X,
71 /*.oa0SwitchCtrl */ CY_CTB_DEINIT,
72 /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
73 };
74
75 const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Comp =
76 {
77 /*.oa0Power */ CY_CTB_POWER_MEDIUM,
78 /*.oa0Mode */ CY_CTB_MODE_COMP,
79 /*.oa0SwitchCtrl */ CY_CTB_DEINIT,
80 /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
81 };
82
83 const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp1x =
84 {
85 /*.oa0Power */ CY_CTB_POWER_MEDIUM,
86 /*.oa0Mode */ CY_CTB_MODE_OPAMP1X,
87 /*.oa0SwitchCtrl */ CY_CTB_DEINIT,
88 /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
89 };
90
91 const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp10x =
92 {
93 /*.oa0Power */ CY_CTB_POWER_MEDIUM,
94 /*.oa0Mode */ CY_CTB_MODE_OPAMP10X,
95 /*.oa0SwitchCtrl */ CY_CTB_DEINIT,
96 /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
97 };
98
99 const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Diffamp =
100 {
101 /*.oa0Power */ CY_CTB_POWER_MEDIUM,
102 /*.oa0Mode */ CY_CTB_MODE_OPAMP10X,
103 /*.oa0SwitchCtrl */ (uint32_t) CY_CTB_SW_OA0_POS_PIN0_MASK | (uint32_t) CY_CTB_SW_OA0_NEG_PIN1_MASK,
104 /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK,
105 };
106
107 const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out =
108 {
109 /*.oa0Power */ CY_CTB_POWER_MEDIUM,
110 /*.oa0Mode */ CY_CTB_MODE_OPAMP10X,
111 /*.oa0SwitchCtrl */ (uint32_t) CY_CTB_SW_OA0_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK,
112 /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK,
113 };
114
115 const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out_SH =
116 {
117 /*.oa0Power */ CY_CTB_POWER_MEDIUM,
118 /*.oa0Mode */ CY_CTB_MODE_OPAMP10X,
119 /*.oa0SwitchCtrl */ (uint32_t) CY_CTB_SW_OA0_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK,
120 /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK | (uint32_t) CY_CTB_SW_CTD_CHOLD_CONNECT_MASK,
121 };
122
123 const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Unused =
124 {
125 /*.oa1Power */ CY_CTB_POWER_OFF,
126 /*.oa1Mode */ CY_CTB_MODE_OPAMP1X,
127 /*.oa1SwitchCtrl */ CY_CTB_DEINIT,
128 /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
129 };
130
131 const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Comp =
132 {
133 /*.oa1Power */ CY_CTB_POWER_MEDIUM,
134 /*.oa1Mode */ CY_CTB_MODE_COMP,
135 /*.oa1SwitchCtrl */ CY_CTB_DEINIT,
136 /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
137 };
138
139 const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp1x =
140 {
141 /*.oa1Power */ CY_CTB_POWER_MEDIUM,
142 /*.oa1Mode */ CY_CTB_MODE_OPAMP1X,
143 /*.oa1SwitchCtrl */ CY_CTB_DEINIT,
144 /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
145 };
146
147 const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp10x =
148 {
149 /*.oa1Power */ CY_CTB_POWER_MEDIUM,
150 /*.oa1Mode */ CY_CTB_MODE_OPAMP10X,
151 /*.oa1SwitchCtrl */ CY_CTB_DEINIT,
152 /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
153 };
154
155 const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Diffamp =
156 {
157 /*.oa1Power */ CY_CTB_POWER_MEDIUM,
158 /*.oa1Mode */ CY_CTB_MODE_OPAMP10X,
159 /*.oa1SwitchCtrl */ (uint32_t) CY_CTB_SW_OA1_POS_PIN7_MASK | (uint32_t) CY_CTB_SW_OA1_NEG_PIN4_MASK,
160 /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
161 };
162
163 const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref =
164 {
165 /*.oa1Power */ CY_CTB_POWER_MEDIUM,
166 /*.oa1Mode */ CY_CTB_MODE_OPAMP1X,
167 /*.oa1SwitchCtrl */ (uint32_t) CY_CTB_SW_OA1_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA1_POS_AREF_MASK,
168 /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_REF_OA1_OUT_MASK,
169 };
170
171 const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5 =
172 {
173 /*.oa1Power */ CY_CTB_POWER_MEDIUM,
174 /*.oa1Mode */ CY_CTB_MODE_OPAMP1X,
175 /*.oa1SwitchCtrl */ (uint32_t) CY_CTB_SW_OA1_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA1_POS_PIN5_MASK,
176 /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_REF_OA1_OUT_MASK,
177 };
178
179
180 /*******************************************************************************
181 * Function Name: Cy_CTB_Enable
182 ****************************************************************************//**
183 *
184 * Power up the CTB hardware block.
185 *
186 * \param base
187 * Pointer to structure describing registers
188 *
189 * \return None
190 *
191 *******************************************************************************/
Cy_CTB_Enable(CTBM_Type * base)192 void Cy_CTB_Enable(CTBM_Type *base)
193 {
194 CTBM_CTB_CTRL(base) |= CTBM_CTB_CTRL_ENABLED_Msk;
195
196 if ((uint32_t)CY_CTB_POWER_OFF != (CTBM_OA_RES0_CTRL_OA0_PWR_MODE_Msk & CTBM_OA_RES0_CTRL(base)))
197 {
198 CTBM_OA0_SW(base) = cy_ctb_oa0Sw;
199 CTBM_CTD_SW(base) = OA0_CTD_SW_Msk & cy_ctb_ctdSw;
200 }
201
202 if ((uint32_t)CY_CTB_POWER_OFF != (CTBM_OA_RES1_CTRL_OA1_PWR_MODE_Msk & CTBM_OA_RES1_CTRL(base)))
203 {
204 CTBM_OA1_SW(base) = cy_ctb_oa1Sw;
205 CTBM_CTD_SW(base) = OA1_CTD_SW_Msk & cy_ctb_ctdSw;
206 }
207 }
208
209
210 /*******************************************************************************
211 * Function Name: Cy_CTB_Disable
212 ****************************************************************************//**
213 *
214 * Power down the CTB hardware block.
215 *
216 * \param base
217 * Pointer to structure describing registers
218 *
219 * \return None
220 *
221 *******************************************************************************/
Cy_CTB_Disable(CTBM_Type * base)222 void Cy_CTB_Disable(CTBM_Type *base)
223 {
224 CTBM_CTB_CTRL(base) &= (~CTBM_CTB_CTRL_ENABLED_Msk);
225
226 if ((uint32_t)CY_CTB_POWER_OFF != (CTBM_OA_RES0_CTRL_OA0_PWR_MODE_Msk & CTBM_OA_RES0_CTRL(base)))
227 {
228 cy_ctb_oa0Sw = OA0_SW_Msk & CTBM_OA0_SW(base);
229 cy_ctb_ctdSw &= ~OA0_CTD_SW_Msk;
230 cy_ctb_ctdSw |= OA0_CTD_SW_Msk & CTBM_CTD_SW(base);
231
232 CTBM_OA0_SW_CLEAR(base) = cy_ctb_oa0Sw;
233 CTBM_CTD_SW_CLEAR(base) = cy_ctb_ctdSw;
234 }
235
236 if ((uint32_t)CY_CTB_POWER_OFF != (CTBM_OA_RES1_CTRL_OA1_PWR_MODE_Msk & CTBM_OA_RES1_CTRL(base)))
237 {
238 cy_ctb_oa1Sw = OA1_SW_Msk & CTBM_OA1_SW(base);
239 cy_ctb_ctdSw &= ~OA1_CTD_SW_Msk;
240 cy_ctb_ctdSw |= OA1_CTD_SW_Msk & CTBM_CTD_SW(base);
241
242 CTBM_OA1_SW_CLEAR(base) = cy_ctb_oa1Sw;
243 CTBM_CTD_SW_CLEAR(base) = cy_ctb_ctdSw;
244 }
245 }
246
247 /*******************************************************************************
248 * Function Name: Cy_CTB_IsEnabled
249 ****************************************************************************//**
250 *
251 * Returns CTB enabled/disabled state.
252 *
253 *******************************************************************************/
254 static bool Cy_CTB_IsEnabled(const CTBM_Type *base);
Cy_CTB_IsEnabled(const CTBM_Type * base)255 static bool Cy_CTB_IsEnabled(const CTBM_Type *base)
256 {
257 return(_FLD2BOOL(CTBM_CTB_CTRL_ENABLED, CTBM_CTB_CTRL(base)));
258 }
259
260
261 /*******************************************************************************
262 * Function Name: Cy_CTB_Init
263 ****************************************************************************//**
264 *
265 * Initialize or restore the CTB and both opamps according to the
266 * provided settings. Parameters are usually set only once, at initialization.
267 *
268 * \note This function call disables a whole CTB block,
269 * call \ref Cy_CTB_Enable after this function call.
270 *
271 * \param base
272 * Pointer to structure describing registers
273 *
274 * \param config
275 * Pointer to structure containing configuration data for entire CTB
276 *
277 * \return
278 * Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM
279 *
280 * \funcusage
281 *
282 * The following code snippet configures Opamp0 as a comparator
283 * and Opamp1 as an opamp follower with 10x drive. The terminals
284 * are routed to external pins by closing the switches shown.
285 *
286 * \image html ctb_init_funcusage.png
287 * \image latex ctb_init_funcusage.png
288 *
289 * \snippet ctb/snippet/main.c SNIPPET_CTBINIT
290 *
291 *******************************************************************************/
Cy_CTB_Init(CTBM_Type * base,const cy_stc_ctb_config_t * config)292 cy_en_ctb_status_t Cy_CTB_Init(CTBM_Type *base, const cy_stc_ctb_config_t *config)
293 {
294 CY_ASSERT_L1(NULL != base);
295 CY_ASSERT_L1(NULL != config);
296
297 cy_en_ctb_status_t result;
298
299 if ((NULL == base) || (NULL == config))
300 {
301 result = CY_CTB_BAD_PARAM;
302 }
303 else
304 {
305 CY_ASSERT_L3(CY_CTB_DEEPSLEEP(config->deepSleep));
306
307 /* Enum checks for Opamp0 config */
308 CY_ASSERT_L3(CY_CTB_OAPOWER(config->oa0Power));
309 CY_ASSERT_L3(CY_CTB_OAMODE(config->oa0Mode));
310 CY_ASSERT_L3(CY_CTB_OAPUMP(config->oa0Pump));
311 CY_ASSERT_L3(CY_CTB_COMPEDGE(config->oa0CompEdge));
312 CY_ASSERT_L3(CY_CTB_COMPLEVEL(config->oa0CompLevel));
313 CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oa0CompBypass));
314 CY_ASSERT_L3(CY_CTB_COMPHYST(config->oa0CompHyst));
315
316 /* Enum checks for Opamp0 config */
317 CY_ASSERT_L3(CY_CTB_OAPOWER(config->oa1Power));
318 CY_ASSERT_L3(CY_CTB_OAMODE(config->oa1Mode));
319 CY_ASSERT_L3(CY_CTB_OAPUMP(config->oa1Pump));
320 CY_ASSERT_L3(CY_CTB_COMPEDGE(config->oa1CompEdge));
321 CY_ASSERT_L3(CY_CTB_COMPLEVEL(config->oa1CompLevel));
322 CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oa1CompBypass));
323 CY_ASSERT_L3(CY_CTB_COMPHYST(config->oa1CompHyst));
324
325 /* Boundary checks for analog routing switch masks */
326 CY_ASSERT_L2(CY_CTB_OA0SWITCH(config->oa0SwitchCtrl));
327 CY_ASSERT_L2(CY_CTB_OA1SWITCH(config->oa1SwitchCtrl));
328 CY_ASSERT_L2(CY_CTB_CTDSWITCH(config->ctdSwitchCtrl));
329
330 CTBM_CTB_CTRL(base) = (uint32_t) config->deepSleep;
331 CTBM_OA_RES0_CTRL(base) = (uint32_t) config->oa0Power \
332 | (uint32_t) config->oa0Mode \
333 | (uint32_t) config->oa0Pump \
334 | (uint32_t) config->oa0CompEdge \
335 | (uint32_t) config->oa0CompLevel \
336 | (uint32_t) config->oa0CompBypass \
337 | (uint32_t) config->oa0CompHyst \
338 | (uint32_t) ((CY_CTB_MODE_OPAMP1X == config->oa0Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE);
339
340 CTBM_OA_RES1_CTRL(base) = (uint32_t) config->oa1Power \
341 | (uint32_t) config->oa1Mode \
342 | (uint32_t) config->oa1Pump \
343 | (uint32_t) config->oa1CompEdge \
344 | (uint32_t) config->oa1CompLevel \
345 | (uint32_t) config->oa1CompBypass \
346 | (uint32_t) config->oa1CompHyst \
347 | (uint32_t) ((CY_CTB_MODE_OPAMP1X == config->oa1Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE);
348
349 CTBM_INTR_MASK(base) = (config->oa0CompIntrEn ? CTBM_INTR_MASK_COMP0_MASK_Msk : CY_CTB_DEINIT) \
350 | (config->oa1CompIntrEn ? CTBM_INTR_MASK_COMP1_MASK_Msk : CY_CTB_DEINIT);
351 CTBM_INTR(base) = (CTBM_INTR_MASK_COMP0_MASK_Msk | CTBM_INTR_MASK_COMP1_MASK_Msk);
352
353 CTBM_OA0_COMP_TRIM(base) = (uint32_t) ((config->oa0Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
354 CTBM_OA1_COMP_TRIM(base) = (uint32_t) ((config->oa1Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
355
356 if (config->configRouting)
357 {
358 cy_ctb_oa0Sw = OA0_SW_Msk & config->oa0SwitchCtrl;
359 cy_ctb_oa1Sw = OA1_SW_Msk & config->oa1SwitchCtrl;
360 cy_ctb_ctdSw = CTD_SW_Msk & config->ctdSwitchCtrl;
361
362 CTBM_OA0_SW(base) = config->oa0SwitchCtrl;
363 CTBM_OA1_SW(base) = config->oa1SwitchCtrl;
364 CTBM_CTD_SW(base) = config->ctdSwitchCtrl;
365 }
366
367 result = CY_CTB_SUCCESS;
368 }
369
370 return result;
371 }
372
373 /*******************************************************************************
374 * Function Name: Cy_CTB_OpampInit
375 ****************************************************************************//**
376 *
377 * Initialize each opamp separately without impacting analog routing.
378 * Intended for use by automatic analog routing and configuration tools
379 * to configure each opamp without having to integrate the settings with
380 * those of the other opamp first.
381 *
382 * Can also be used to configure both opamps to have the same settings.
383 *
384 * \param base
385 * Pointer to structure describing registers
386 *
387 * \param opampNum
388 * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
389 *
390 * \param config
391 * Pointer to structure containing configuration data
392 *
393 * \return
394 * Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM
395 *
396 * \funcusage
397 *
398 * \snippet ctb/snippet/main.c SNIPPET_OPAMPINIT
399 *
400 *******************************************************************************/
Cy_CTB_OpampInit(CTBM_Type * base,cy_en_ctb_opamp_sel_t opampNum,const cy_stc_ctb_opamp_config_t * config)401 cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, const cy_stc_ctb_opamp_config_t *config)
402 {
403 CY_ASSERT_L1(NULL != base);
404 CY_ASSERT_L1(NULL != config);
405
406 cy_en_ctb_status_t result;
407 uint32_t oaResCtrl;
408
409 if ((NULL == base) || (NULL == config))
410 {
411 result = CY_CTB_BAD_PARAM;
412 }
413 else
414 {
415 CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum));
416 CY_ASSERT_L3(CY_CTB_DEEPSLEEP(config->deepSleep));
417 CY_ASSERT_L3(CY_CTB_OAPOWER(config->oaPower));
418 CY_ASSERT_L3(CY_CTB_OAMODE(config->oaMode));
419 CY_ASSERT_L3(CY_CTB_OAPUMP(config->oaPump));
420 CY_ASSERT_L3(CY_CTB_COMPEDGE(config->oaCompEdge));
421 CY_ASSERT_L3(CY_CTB_COMPLEVEL(config->oaCompLevel));
422 CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oaCompBypass));
423 CY_ASSERT_L3(CY_CTB_COMPHYST(config->oaCompHyst));
424
425 CY_REG32_CLR_SET(CTBM_CTB_CTRL(base), CTBM_CTB_CTRL_DEEPSLEEP_ON, (CY_CTB_DEEPSLEEP_DISABLE != config->deepSleep) ? 1UL : 0UL);
426
427 /* The two opamp control registers are symmetrical */
428 oaResCtrl = (uint32_t) config->oaPower \
429 | (uint32_t) config->oaMode \
430 | (uint32_t) config->oaPump \
431 | (uint32_t) config->oaCompEdge \
432 | (uint32_t) config->oaCompLevel \
433 | (uint32_t) config->oaCompBypass \
434 | (uint32_t) config->oaCompHyst \
435 | (uint32_t) ((CY_CTB_MODE_OPAMP1X == config->oaMode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE);
436
437 if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH))
438 {
439 CTBM_OA_RES0_CTRL(base) = oaResCtrl;
440 CTBM_OA0_COMP_TRIM(base) = (uint32_t) ((config->oaMode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
441
442 /* The INTR_MASK register is shared between the two opamps */
443 CTBM_INTR_MASK(base) |= (config->oaCompIntrEn ? CTBM_INTR_MASK_COMP0_MASK_Msk : CY_CTB_DEINIT);
444 CTBM_INTR(base) |= CTBM_INTR_MASK_COMP0_MASK_Msk;
445 }
446
447 if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH))
448 {
449 CTBM_OA_RES1_CTRL(base) = oaResCtrl;
450 CTBM_OA1_COMP_TRIM(base) = (uint32_t) ((config->oaMode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
451
452 /* The INTR_MASK register is shared between the two opamps */
453 CTBM_INTR_MASK(base) |= (config->oaCompIntrEn ? CTBM_INTR_MASK_COMP1_MASK_Msk : CY_CTB_DEINIT);
454 CTBM_INTR(base) |= CTBM_INTR_MASK_COMP1_MASK_Msk;
455 }
456
457 result = CY_CTB_SUCCESS;
458 }
459
460 return result;
461 }
462
463 /*******************************************************************************
464 * Function Name: Cy_CTB_DeInit
465 ****************************************************************************//**
466 *
467 * Reset CTB registers back to power on reset defaults.
468 *
469 * \param base
470 * Pointer to structure describing registers
471 *
472 * \param deInitRouting
473 * If true, all analog routing switches are reset to their default state.
474 * If false, analog switch registers are untouched.
475 *
476 * \return
477 * Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM
478 *
479 *******************************************************************************/
Cy_CTB_DeInit(CTBM_Type * base,bool deInitRouting)480 cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting)
481 {
482 CY_ASSERT_L1(NULL != base);
483
484 cy_en_ctb_status_t result;
485
486 if (NULL == base)
487 {
488 result = CY_CTB_BAD_PARAM;
489 }
490 else
491 {
492 CTBM_CTB_CTRL(base) = CY_CTB_DEINIT;
493 CTBM_OA_RES0_CTRL(base) = CY_CTB_DEINIT;
494 CTBM_OA_RES1_CTRL(base) = CY_CTB_DEINIT;
495 CTBM_INTR_MASK(base) = CY_CTB_DEINIT;
496
497 if (deInitRouting)
498 {
499 CTBM_OA0_SW_CLEAR(base) = CY_CTB_DEINIT_OA0_SW;
500 CTBM_OA1_SW_CLEAR(base) = CY_CTB_DEINIT_OA1_SW;
501 CTBM_CTD_SW_CLEAR(base) = CY_CTB_DEINIT_CTD_SW;
502 }
503
504 result = CY_CTB_SUCCESS;
505 }
506
507 return result;
508 }
509
510 /*******************************************************************************
511 * Function Name: Cy_CTB_FastInit
512 ****************************************************************************//**
513 *
514 * Initialize each opamp of the CTB to one of the common use modes.
515 *
516 * This function provides a quick and easy method of configuring the CTB
517 * using pre-defined configurations.
518 * Only routing switches required for the selected mode are configured, leaving final input and output connections
519 * to the user.
520 * Additional use modes that relate to the \ref group_ctdac "CTDAC"
521 * are provided to support easy configuration of the CTDAC output buffer and input
522 * reference buffer.
523 *
524 * The fast configuration structures define the opamp power, mode, and routing.
525 * This function sets the other configuration options of the CTB to:
526 * - .deepSleep = CY_CTB_DEEPSLEEP_DISABLE
527 * - .oaPump = \ref CY_CTB_PUMP_ENABLE
528 * - .oaCompEdge = \ref CY_CTB_COMP_EDGE_BOTH
529 * - .oaCompLevel = \ref CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL
530 * - .oaCompBypass = \ref CY_CTB_COMP_BYPASS_SYNC
531 * - .oaCompHyst = \ref CY_CTB_COMP_HYST_10MV
532 * - .oaCompIntrEn = true
533 *
534 * \note This function call disables a whole CTB block,
535 * call \ref Cy_CTB_Enable after this function call.
536 *
537 * \param base
538 * Pointer to structure describing registers
539 *
540 * \param config0
541 * Pointer to structure containing configuration data for quick initialization
542 * of Opamp0. Defined your own or use one of the provided structures:
543 * - \ref Cy_CTB_Fast_Opamp0_Unused
544 * - \ref Cy_CTB_Fast_Opamp0_Comp
545 * - \ref Cy_CTB_Fast_Opamp0_Opamp1x
546 * - \ref Cy_CTB_Fast_Opamp0_Opamp10x
547 * - \ref Cy_CTB_Fast_Opamp0_Diffamp
548 * - \ref Cy_CTB_Fast_Opamp0_Vdac_Out
549 * - \ref Cy_CTB_Fast_Opamp0_Vdac_Out_SH
550 *
551 * \param config1
552 * Pointer to structure containing configuration data for quick initialization
553 * of Opamp1. Defined your own or use one of the provided structures:
554 * - \ref Cy_CTB_Fast_Opamp1_Unused
555 * - \ref Cy_CTB_Fast_Opamp1_Comp
556 * - \ref Cy_CTB_Fast_Opamp1_Opamp1x
557 * - \ref Cy_CTB_Fast_Opamp1_Opamp10x
558 * - \ref Cy_CTB_Fast_Opamp1_Diffamp
559 * - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref
560 * - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5
561 *
562 * \return
563 * Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM
564 *
565 * \funcusage
566 *
567 * \snippet ctb/snippet/main.c SNIPPET_FASTINIT
568 *
569 *******************************************************************************/
Cy_CTB_FastInit(CTBM_Type * base,const cy_stc_ctb_fast_config_oa0_t * config0,const cy_stc_ctb_fast_config_oa1_t * config1)570 cy_en_ctb_status_t Cy_CTB_FastInit(CTBM_Type *base, const cy_stc_ctb_fast_config_oa0_t *config0, const cy_stc_ctb_fast_config_oa1_t *config1)
571 {
572 CY_ASSERT_L1(NULL != base);
573 CY_ASSERT_L1(NULL != config0);
574 CY_ASSERT_L1(NULL != config1);
575
576 cy_en_ctb_status_t result;
577
578 if ((NULL == base) || (NULL == config0) || (NULL == config1))
579 {
580 result = CY_CTB_BAD_PARAM;
581 }
582 else
583 {
584 /* Enum and boundary checks for config0 */
585 CY_ASSERT_L3(CY_CTB_OAPOWER(config0->oa0Power));
586 CY_ASSERT_L3(CY_CTB_OAMODE(config0->oa0Mode));
587 CY_ASSERT_L2(CY_CTB_OA0SWITCH(config0->oa0SwitchCtrl));
588 CY_ASSERT_L2(CY_CTB_CTDSWITCH(config0->ctdSwitchCtrl));
589
590 /* Enum and boundary checks for config1 */
591 CY_ASSERT_L3(CY_CTB_OAPOWER(config1->oa1Power));
592 CY_ASSERT_L3(CY_CTB_OAMODE(config1->oa1Mode));
593 CY_ASSERT_L2(CY_CTB_OA1SWITCH(config1->oa1SwitchCtrl));
594 CY_ASSERT_L2(CY_CTB_CTDSWITCH(config1->ctdSwitchCtrl));
595
596 CTBM_CTB_CTRL(base) = (uint32_t) CY_CTB_DEEPSLEEP_DISABLE;
597
598 CTBM_OA_RES0_CTRL(base) = (uint32_t) config0->oa0Power \
599 | (uint32_t) config0->oa0Mode \
600 | (uint32_t) CY_CTB_PUMP_ENABLE \
601 | (uint32_t) CY_CTB_COMP_EDGE_BOTH \
602 | (uint32_t) CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL \
603 | (uint32_t) CY_CTB_COMP_BYPASS_SYNC \
604 | (uint32_t) CY_CTB_COMP_HYST_10MV \
605 | (uint32_t) ((CY_CTB_MODE_OPAMP1X == config0->oa0Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE);
606
607 CTBM_OA_RES1_CTRL(base) = (uint32_t) config1->oa1Power \
608 | (uint32_t) config1->oa1Mode \
609 | (uint32_t) CY_CTB_PUMP_ENABLE \
610 | (uint32_t) CY_CTB_COMP_EDGE_BOTH \
611 | (uint32_t) CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL \
612 | (uint32_t) CY_CTB_COMP_BYPASS_SYNC \
613 | (uint32_t) CY_CTB_COMP_HYST_10MV \
614 | (uint32_t) ((CY_CTB_MODE_OPAMP1X == config1->oa1Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE);
615
616 CTBM_INTR_MASK(base) = CTBM_INTR_MASK_COMP0_MASK_Msk | CTBM_INTR_MASK_COMP1_MASK_Msk;
617
618 CTBM_OA0_COMP_TRIM(base) = (uint32_t) ((config0->oa0Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
619 CTBM_OA1_COMP_TRIM(base) = (uint32_t) ((config1->oa1Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
620
621 cy_ctb_oa0Sw = OA0_SW_Msk & config0->oa0SwitchCtrl;
622 cy_ctb_oa1Sw = OA1_SW_Msk & config1->oa1SwitchCtrl;
623 cy_ctb_ctdSw = CTD_SW_Msk & (config0->ctdSwitchCtrl | config1->ctdSwitchCtrl);
624
625 CTBM_OA0_SW(base) = config0->oa0SwitchCtrl;
626 CTBM_OA1_SW(base) = config1->oa1SwitchCtrl;
627 CTBM_CTD_SW(base) = config0->ctdSwitchCtrl | config1->ctdSwitchCtrl;
628
629 result = CY_CTB_SUCCESS;
630 }
631
632 return result;
633 }
634
635 /*******************************************************************************
636 * Function Name: Cy_CTB_SetCurrentMode
637 ****************************************************************************//**
638 *
639 * High level function to configure the current modes of the opamps.
640 * This function configures all opamps of the CTB to the same current mode.
641 * These modes are differentiated by the reference current level, the opamp
642 * input range, and the Deep Sleep mode operation.
643 *
644 * - The reference current level is set using \ref Cy_CTB_SetIptatLevel
645 * - When 1 uA current level is used in Deep Sleep,
646 * - All generators in the AREF must be enabled in Deep Sleep. That is,
647 * \ref Cy_SysAnalog_SetDeepSleepMode is called with CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF.
648 * - When 100 nA current level is used,
649 * - \ref Cy_CTB_EnableRedirect is called to route the AREF IPTAT reference
650 * to the opamp IZTAT and disable the opamps IPTAT.
651 * - The IPTAT generator is enabled in Deep Sleep. That is,
652 * \ref Cy_SysAnalog_SetDeepSleepMode is called with CY_SYSANALOG_DEEPSLEEP_IPTAT_2
653 * unless it is already configured for CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF.
654 *
655 * \note
656 * The IPTAT level is a chip wide configuration so multiple
657 * opamps cannot operate at different IPTAT levels.
658 * When calling \ref Cy_CTB_SetCurrentMode for a CTB instance on the device,
659 * it should be called for all other CTB instances as well.
660 *
661 * <table class="doxtable">
662 * <tr>
663 * <th>Current Mode</th>
664 * <th>IPTAT Level</th>
665 * <th>Input Range</th>
666 * <th>Deep Sleep Operation</th>
667 * </tr>
668 * <tr>
669 * <td>\ref CY_CTB_CURRENT_HIGH_ACTIVE</td>
670 * <td>1 uA</td>
671 * <td>Rail-to-Rail (charge pump enabled)</td>
672 * <td>Disabled in Deep Sleep</td>
673 * </tr>
674 * <tr>
675 * <td>\ref CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP</td>
676 * <td>1 uA</td>
677 * <td>0 - VDDA-1.5 V (charge pump disabled)</td>
678 * <td>Enabled in Deep Sleep</td>
679 * </tr>
680 * <tr>
681 * <td>\ref CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP</td>
682 * <td>100 nA</td>
683 * <td>0 - VDDA-1.5 V (charge pump disabled)</td>
684 * <td>Enabled in Deep Sleep</td>
685 * </tr>
686 * </table>
687 *
688 * \note
689 * The output range of the opamp is 0.2 V to VDDA - 0.2 V (depending on output load).
690 *
691 * \param base
692 * Pointer to structure describing registers
693 *
694 * \param currentMode
695 * Current mode selection
696 *
697 * \return None
698 *
699 * \funcusage
700 *
701 * \snippet ctb/snippet/main.c CTB_SNIPPET_SET_CURRENT_MODE
702 *
703 *******************************************************************************/
Cy_CTB_SetCurrentMode(CTBM_Type * base,cy_en_ctb_current_mode_t currentMode)704 void Cy_CTB_SetCurrentMode(CTBM_Type *base, cy_en_ctb_current_mode_t currentMode)
705 {
706 CY_ASSERT_L3(CY_CTB_CURRENTMODE(currentMode));
707
708 cy_en_sysanalog_deep_sleep_t arefDeepSleep;
709
710 switch(currentMode)
711 {
712 case CY_CTB_CURRENT_HIGH_ACTIVE:
713
714 /* Does not disable AREF for Deep Sleep in case the AREF is used by other blocks */
715
716 /* Use a 1 uA IPTAT level and disable redirection */
717 Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_NORMAL);
718 Cy_CTB_DisableRedirect();
719
720 /* Disable Deep Sleep mode for the CTB - not opamp specific */
721 Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_DISABLE);
722
723 /* Enable Opamp0 pump */
724 CTBM_OA_RES0_CTRL(base) |= CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk;
725
726 /* Enable Opamp1 pump */
727 CTBM_OA_RES1_CTRL(base) |= CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk;
728
729 break;
730 case CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP:
731
732 /* All generators (IPTAT, IZTAT, and VREF) of the AREF block must be enabled for Deep Sleep */
733 Cy_SysAnalog_SetDeepSleepMode(CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF);
734
735 /* Use a 1 uA IPTAT level and disable redirection */
736 Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_NORMAL);
737 Cy_CTB_DisableRedirect();
738
739 /* Enable Deep Sleep mode for the CTB - not opamp specific */
740 Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_ENABLE);
741
742 /* Disable Opamp0 pump */
743 CTBM_OA_RES0_CTRL(base) &= ~CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk;
744
745 /* Disable Opamp1 pump */
746 CTBM_OA_RES1_CTRL(base) &= ~CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk;
747
748 break;
749 case CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP:
750 default:
751
752 /* The AREF IPTAT output for the opamps must be enabled in Deep Sleep.
753 * This means a minimum Deep Sleep mode setting of CY_SYSANALOG_DEEPSLEEP_IPTAT_2. */
754 arefDeepSleep = Cy_SysAnalog_GetDeepSleepMode();
755 if ((arefDeepSleep == CY_SYSANALOG_DEEPSLEEP_DISABLE) || (arefDeepSleep == CY_SYSANALOG_DEEPSLEEP_IPTAT_1))
756 {
757 Cy_SysAnalog_SetDeepSleepMode(CY_SYSANALOG_DEEPSLEEP_IPTAT_2);
758 }
759
760 /* Use a 100 nA IPTAT level and enable redirection */
761 Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_LOW);
762 Cy_CTB_EnableRedirect();
763
764 /* Enable Deep Sleep mode for the CTB - not opamp specific */
765 Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_ENABLE);
766
767 /* Disable Opamp0 pump */
768 CTBM_OA_RES0_CTRL(base) &= ~CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk;
769
770 /* Disable Opamp1 pump */
771 CTBM_OA_RES1_CTRL(base) &= ~CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk;
772 break;
773 }
774 }
775
776 /*******************************************************************************
777 * Function Name: Cy_CTB_SetDeepSleepMode
778 ****************************************************************************//**
779 *
780 * Enable or disable the entire CTB (not per opamp) in Deep Sleep mode.
781 *
782 * If enabled, the AREF block must also be enabled for Deep Sleep to provide
783 * the needed reference currents to the opamps (see \ref Cy_SysAnalog_SetDeepSleepMode).
784 * Additionally, ensure that only internal CTB switches are used for routing.
785 * Switches on AMUXBUSA and AMUXBUSB are not enabled in Deep Sleep.
786 * See the \ref group_ctb_dependencies section for more information.
787 *
788 * \note
789 * In Deep Sleep mode, the charge pumps are disabled so the input
790 * range of the opamps is reduced to 0 V to VDDA - 1.5 V.
791 *
792 * \param base
793 * Pointer to structure describing registers
794 *
795 * \param deepSleep
796 * \ref CY_CTB_DEEPSLEEP_DISABLE or \ref CY_CTB_DEEPSLEEP_ENABLE from
797 * \ref cy_en_ctb_deep_sleep_t.
798 *
799 * \return None
800 *
801 * \funcusage
802 *
803 * \snippet ctb/snippet/main.c CTB_SNIPPET_SET_DEEPSLEEP_MODE
804 *
805 *******************************************************************************/
Cy_CTB_SetDeepSleepMode(CTBM_Type * base,cy_en_ctb_deep_sleep_t deepSleep)806 void Cy_CTB_SetDeepSleepMode(CTBM_Type *base, cy_en_ctb_deep_sleep_t deepSleep)
807 {
808 CY_ASSERT_L3(CY_CTB_DEEPSLEEP(deepSleep));
809
810 CY_REG32_CLR_SET(CTBM_CTB_CTRL(base), CTBM_CTB_CTRL_DEEPSLEEP_ON, (CY_CTB_DEEPSLEEP_DISABLE != deepSleep) ? 1UL : 0UL);
811 }
812
813 /*******************************************************************************
814 * Function Name: Cy_CTB_SetOutputMode
815 ****************************************************************************//**
816 *
817 * Set the opamp output mode to 1x drive, 10x drive, or comparator mode.
818 *
819 * \param base
820 * Pointer to structure describing registers
821 *
822 * \param opampNum
823 * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
824 *
825 * \param mode
826 * Opamp mode selection. Select a value from \ref cy_en_ctb_mode_t.
827 *
828 * \return None
829 *
830 * \funcusage
831 *
832 * \snippet ctb/snippet/main.c CTB_SNIPPET_SET_OUTPUT_MODE
833 *
834 *******************************************************************************/
Cy_CTB_SetOutputMode(CTBM_Type * base,cy_en_ctb_opamp_sel_t opampNum,cy_en_ctb_mode_t mode)835 void Cy_CTB_SetOutputMode(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_mode_t mode)
836 {
837 CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum));
838 CY_ASSERT_L3(CY_CTB_OAMODE(mode));
839
840 uint32_t oaCtrlReg;
841
842 if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH))
843 {
844 /* Clear the three affected bits before setting them */
845 oaCtrlReg = CTBM_OA_RES0_CTRL(base) & ~(CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Msk | CTBM_OA_RES0_CTRL_OA0_COMP_EN_Msk | CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Msk);
846 CTBM_OA_RES0_CTRL(base) = oaCtrlReg | (uint32_t) mode | (uint32_t) ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_BOOST_DISABLE : CY_CTB_OPAMP_BOOST_ENABLE);
847 CTBM_OA0_COMP_TRIM(base) = (uint32_t) ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
848 }
849
850 if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH))
851 {
852 oaCtrlReg = CTBM_OA_RES1_CTRL(base) & ~(CTBM_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Msk | CTBM_OA_RES1_CTRL_OA1_COMP_EN_Msk | CTBM_OA_RES1_CTRL_OA1_BOOST_EN_Msk);
853 CTBM_OA_RES1_CTRL(base) = oaCtrlReg | (uint32_t) mode | (uint32_t) ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_BOOST_DISABLE : CY_CTB_OPAMP_BOOST_ENABLE);
854 CTBM_OA1_COMP_TRIM(base) = (uint32_t) ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
855 }
856 }
857
858 /*******************************************************************************
859 * Function Name: Cy_CTB_SetPower
860 ****************************************************************************//**
861 *
862 * Configure the power level and charge pump for a specific opamp.
863 *
864 * At higher power levels, the opamp consumes more current but provides more
865 * gain bandwidth.
866 * Enabling the charge pump increases current but provides
867 * rail-to-rail input range. Disabling the charge pump limits the input range to
868 * VDDA - 1.5 V.
869 * See the device datasheet for performance specifications.
870 *
871 * \param base
872 * Pointer to structure describing registers
873 *
874 * \param opampNum
875 * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
876 *
877 * \param power
878 * Power mode selection. Select a value from \ref cy_en_ctb_power_t.
879 *
880 * \param pump
881 * Enable or disable the charge pump. Select a value from \ref cy_en_ctb_pump_t.
882 *
883 * \return None
884 *
885 * \funcusage
886 *
887 * \snippet ctb/snippet/main.c CTB_SNIPPET_SET_POWER
888 *
889 *******************************************************************************/
Cy_CTB_SetPower(CTBM_Type * base,cy_en_ctb_opamp_sel_t opampNum,cy_en_ctb_power_t power,cy_en_ctb_pump_t pump)890 void Cy_CTB_SetPower(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_power_t power, cy_en_ctb_pump_t pump)
891 {
892 CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum));
893 CY_ASSERT_L3(CY_CTB_OAPOWER(power));
894 CY_ASSERT_L3(CY_CTB_OAPUMP(pump));
895
896 uint32_t oaCtrlReg;
897
898 if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH))
899 {
900
901 /* Clear the two affected bits before setting them */
902 oaCtrlReg = CTBM_OA_RES0_CTRL(base) & ~(CTBM_OA_RES0_CTRL_OA0_PWR_MODE_Msk | CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk);
903 CTBM_OA_RES0_CTRL(base) = oaCtrlReg | (uint32_t) power | (uint32_t) pump;
904
905 if (Cy_CTB_IsEnabled(base))
906 {
907 if (CY_CTB_POWER_OFF == power)
908 {
909 cy_ctb_oa0Sw = OA0_SW_Msk & CTBM_OA0_SW(base);
910 cy_ctb_ctdSw &= ~OA0_CTD_SW_Msk;
911 cy_ctb_ctdSw |= OA0_CTD_SW_Msk & CTBM_CTD_SW(base);
912
913 CTBM_OA0_SW_CLEAR(base) = cy_ctb_oa0Sw;
914 CTBM_CTD_SW_CLEAR(base) = OA0_CTD_SW_Msk & cy_ctb_ctdSw;
915 }
916 else
917 {
918 CTBM_OA0_SW(base) = cy_ctb_oa0Sw;
919 CTBM_CTD_SW(base) = OA0_CTD_SW_Msk & cy_ctb_ctdSw;
920 }
921 }
922 }
923
924 if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH))
925 {
926 oaCtrlReg = CTBM_OA_RES1_CTRL(base) & ~(CTBM_OA_RES1_CTRL_OA1_PWR_MODE_Msk | CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk);
927 CTBM_OA_RES1_CTRL(base) = oaCtrlReg | (uint32_t) power | (uint32_t) pump;
928
929 if (Cy_CTB_IsEnabled(base))
930 {
931 if (CY_CTB_POWER_OFF == power)
932 {
933 cy_ctb_oa1Sw = OA1_SW_Msk & CTBM_OA1_SW(base);
934 cy_ctb_ctdSw &= ~OA1_CTD_SW_Msk;
935 cy_ctb_ctdSw |= OA1_CTD_SW_Msk & CTBM_CTD_SW(base);
936
937 CTBM_OA1_SW_CLEAR(base) = cy_ctb_oa1Sw;
938 CTBM_CTD_SW_CLEAR(base) = OA1_CTD_SW_Msk & cy_ctb_ctdSw;
939 }
940 else
941 {
942 CTBM_OA1_SW(base) = cy_ctb_oa1Sw;
943 CTBM_CTD_SW(base) = OA1_CTD_SW_Msk & cy_ctb_ctdSw;
944 }
945 }
946 }
947 }
948
949
950 /*******************************************************************************
951 * Function Name: Cy_CTB_DACSampleAndHold
952 ****************************************************************************//**
953 *
954 * Perform sampling and holding of the CTDAC output.
955 * To perform a sample or a hold, a preparation step must first be executed to
956 * open the required switches. Because of this, each sample or hold
957 * requires three function calls:
958 *
959 * -# Call this function to prepare for a sample or hold
960 * -# Enable or disable the CTDAC output
961 * -# Call this function again to perform a sample or hold
962 *
963 * It takes 10 us to perform a sample of the CTDAC output to provide
964 * time for the capacitor to settle to the new value.
965 *
966 * \param base
967 * Pointer to structure describing registers
968 *
969 * \param mode
970 * Mode to prepare or perform a sample or hold, or disable the ability
971 *
972 * \return None
973 *
974 * \funcusage
975 *
976 * \snippet ctb/snippet/main.c CTB_SAMPLE_CODE_SNIPPET
977 *
978 * \funcusage
979 *
980 * \snippet ctb/snippet/main.c CTB_HOLD_CODE_SNIPPET
981 *
982 *******************************************************************************/
Cy_CTB_DACSampleAndHold(CTBM_Type * base,cy_en_ctb_sample_hold_mode_t mode)983 void Cy_CTB_DACSampleAndHold(CTBM_Type *base, cy_en_ctb_sample_hold_mode_t mode)
984 {
985 CY_ASSERT_L3(CY_CTB_SAMPLEHOLD(mode));
986
987 switch(mode)
988 {
989 case CY_CTB_SH_DISABLE:
990 CTBM_CTD_SW_CLEAR(base) = (uint32_t) CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK /* Open COB switch */
991 | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK /* Open CIS switch */
992 | (uint32_t) CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK /* Open ILR switch */
993 | (uint32_t) CY_CTB_SW_CTD_CHOLD_CONNECT_MASK; /* Open CHD switch */
994 CTBM_CTD_SW(base) = (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK; /* Close COS switch */
995 break;
996 case CY_CTB_SH_PREPARE_SAMPLE:
997 CTBM_CTD_SW_CLEAR(base) = (uint32_t) CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK /* Open COB switch */
998 | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK /* Open CIS switch */
999 | (uint32_t) CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK; /* Open ILR switch */
1000 CTBM_CTD_SW(base) = (uint32_t) CY_CTB_SW_CTD_CHOLD_CONNECT_MASK; /* Close CHD switch */
1001 break;
1002 case CY_CTB_SH_SAMPLE:
1003 CTBM_CTD_SW(base) = (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK; /* Close COS switch */
1004 break;
1005 case CY_CTB_SH_PREPARE_HOLD:
1006 CTBM_CTD_SW_CLEAR(base) = (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK /* Open COS switch */
1007 | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK; /* Open CIS switch */
1008 break;
1009 case CY_CTB_SH_HOLD:
1010 default:
1011 CTBM_CTD_SW(base) = (uint32_t) CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK /* Close COB switch to reduce leakage through COS switch */
1012 | (uint32_t) CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK; /* Close ILR switch to reduce leakage through CIS switch */
1013 break;
1014 }
1015 }
1016
1017 /*******************************************************************************
1018 * Function Name: Cy_CTB_OpampSetOffset
1019 ****************************************************************************//**
1020 *
1021 * Override the CTB opamp offset factory trim.
1022 * The trim is a six bit value and the MSB is a direction bit.
1023 *
1024 * <table class="doxtable">
1025 * <tr>
1026 * <th>Bit 5</th>
1027 * <th>Bits 4:0</th>
1028 * <th>Note</th>
1029 * </tr>
1030 * <tr>
1031 * <td>0</td>
1032 * <td>00000</td>
1033 * <td>Negative trim direction - minimum setting</td>
1034 * </tr>
1035 * <tr>
1036 * <td>0</td>
1037 * <td>11111</td>
1038 * <td>Negative trim direction - maximum setting</td>
1039 * </tr>
1040 * <tr>
1041 * <td>1</td>
1042 * <td>00000</td>
1043 * <td>Positive trim direction - minimum setting</td>
1044 * </tr>
1045 * <tr>
1046 * <td>1</td>
1047 * <td>11111</td>
1048 * <td>Positive trim direction - maximum setting</td>
1049 * </tr>
1050 * </table>
1051 *
1052 * \param base
1053 * Pointer to structure describing registers
1054 *
1055 * \param opampNum
1056 * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
1057 *
1058 * \param trim
1059 * Trim value from 0 to 63
1060 *
1061 * \return None
1062 *
1063 * \funcusage
1064 *
1065 * \snippet ctb/snippet/main.c CTB_SNIPPET_SET_OFFSET_TRIM
1066 *
1067 *******************************************************************************/
Cy_CTB_OpampSetOffset(CTBM_Type * base,cy_en_ctb_opamp_sel_t opampNum,uint32_t trim)1068 void Cy_CTB_OpampSetOffset(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim)
1069 {
1070 CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum));
1071 CY_ASSERT_L2(CY_CTB_TRIM(trim));
1072
1073 if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH))
1074 {
1075 CTBM_OA0_OFFSET_TRIM(base) = (trim << CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Pos) & CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Msk;
1076 }
1077
1078 if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH))
1079 {
1080 CTBM_OA1_OFFSET_TRIM(base) = (trim << CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Pos) & CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Msk;
1081 }
1082 }
1083
1084 /*******************************************************************************
1085 * Function Name: Cy_CTB_OpampGetOffset
1086 ****************************************************************************//**
1087 *
1088 * Return the current CTB opamp offset trim value.
1089 *
1090 * \param base
1091 * Pointer to structure describing registers
1092 *
1093 * \param opampNum
1094 * \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1
1095 *
1096 * \return Offset trim value
1097 *
1098 * \funcusage
1099 *
1100 * \snippet ctb/snippet/main.c CTB_SNIPPET_GET_OFFSET_TRIM
1101 *
1102 *******************************************************************************/
Cy_CTB_OpampGetOffset(const CTBM_Type * base,cy_en_ctb_opamp_sel_t opampNum)1103 uint32_t Cy_CTB_OpampGetOffset(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum)
1104 {
1105 CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(opampNum));
1106
1107 uint32_t trimReg;
1108
1109 if (opampNum == CY_CTB_OPAMP_0)
1110 {
1111 trimReg = CTBM_OA0_OFFSET_TRIM(base);
1112 }
1113 else
1114 {
1115 trimReg = CTBM_OA1_OFFSET_TRIM(base);
1116 }
1117
1118 return trimReg;
1119 }
1120
1121 /*******************************************************************************
1122 * Function Name: Cy_CTB_OpampSetSlope
1123 ****************************************************************************//**
1124 *
1125 * Override the CTB opamp slope factory trim.
1126 * The offset of the opamp will vary across temperature.
1127 * This trim compensates for the slope of the offset across temperature.
1128 * This compensation uses a bias current from the Analog Reference block.
1129 * To disable it, set the trim to 0.
1130 *
1131 * The trim is a six bit value and the MSB is a direction bit.
1132 *
1133 * <table class="doxtable">
1134 * <tr>
1135 * <th>Bit 5</th>
1136 * <th>Bits 4:0</th>
1137 * <th>Note</th>
1138 * </tr>
1139 * <tr>
1140 * <td>0</td>
1141 * <td>00000</td>
1142 * <td>Negative trim direction - minimum setting</td>
1143 * </tr>
1144 * <tr>
1145 * <td>0</td>
1146 * <td>11111</td>
1147 * <td>Negative trim direction - maximum setting</td>
1148 * </tr>
1149 * <tr>
1150 * <td>1</td>
1151 * <td>00000</td>
1152 * <td>Positive trim direction - minimum setting</td>
1153 * </tr>
1154 * <tr>
1155 * <td>1</td>
1156 * <td>11111</td>
1157 * <td>Positive trim direction - maximum setting</td>
1158 * </tr>
1159 * </table>
1160 *
1161 * \param base
1162 * Pointer to structure describing registers
1163 *
1164 * \param opampNum
1165 * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
1166 *
1167 * \param trim
1168 * Trim value from 0 to 63
1169 *
1170 * \return None
1171 *
1172 * \funcusage
1173 *
1174 * \snippet ctb/snippet/main.c CTB_SNIPPET_SET_SLOPE_TRIM
1175 *
1176 *******************************************************************************/
Cy_CTB_OpampSetSlope(CTBM_Type * base,cy_en_ctb_opamp_sel_t opampNum,uint32_t trim)1177 void Cy_CTB_OpampSetSlope(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim)
1178 {
1179 CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum));
1180 CY_ASSERT_L2(CY_CTB_TRIM(trim));
1181
1182 if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH))
1183 {
1184 CTBM_OA0_SLOPE_OFFSET_TRIM(base) = (trim << CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Pos) & CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Msk;
1185 }
1186
1187 if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH))
1188 {
1189 CTBM_OA1_SLOPE_OFFSET_TRIM(base) = (trim << CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Pos) & CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Msk;
1190 }
1191 }
1192
1193 /*******************************************************************************
1194 * Function Name: Cy_CTB_OpampGetSlope
1195 ****************************************************************************//**
1196 *
1197 * Return the CTB opamp slope trim value.
1198 *
1199 * \param base
1200 * Pointer to structure describing registers
1201 *
1202 * \param opampNum
1203 * \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1
1204 *
1205 * \return Slope trim value
1206 *
1207 * \funcusage
1208 *
1209 * \snippet ctb/snippet/main.c CTB_SNIPPET_GET_SLOPE_TRIM
1210 *
1211 *******************************************************************************/
Cy_CTB_OpampGetSlope(const CTBM_Type * base,cy_en_ctb_opamp_sel_t opampNum)1212 uint32_t Cy_CTB_OpampGetSlope(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum)
1213 {
1214 CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(opampNum));
1215
1216 uint32_t trimReg;
1217
1218 if (opampNum == CY_CTB_OPAMP_0)
1219 {
1220 trimReg = CTBM_OA0_SLOPE_OFFSET_TRIM(base);
1221 }
1222 else
1223 {
1224 trimReg = CTBM_OA1_SLOPE_OFFSET_TRIM(base);
1225 }
1226
1227 return trimReg;
1228 }
1229
1230 /*******************************************************************************
1231 * Function Name: Cy_CTB_SetAnalogSwitch
1232 ****************************************************************************//**
1233 *
1234 * Provide firmware control of the CTB switches. Each call to this function
1235 * can open a set of switches or close a set of switches in one register.
1236 *
1237 * \param base
1238 * Pointer to structure describing registers
1239 *
1240 * \param switchSelect
1241 * A value of the enum \ref cy_en_ctb_switch_register_sel_t to select the switch
1242 * register
1243 *
1244 * \param switchMask
1245 * The mask of the switches to either open or close.
1246 * The switch masks can be found in the following enums: \ref cy_en_ctb_oa0_switches_t,
1247 * \ref cy_en_ctb_oa1_switches_t, and \ref cy_en_ctb_ctd_switches_t.
1248 * Use the enum that is consistent with the provided register.
1249 *
1250 * \param state
1251 * \ref CY_CTB_SWITCH_OPEN or \ref CY_CTB_SWITCH_CLOSE
1252 *
1253 * \return None
1254 *
1255 * \funcusage
1256 *
1257 * \snippet ctb/snippet/main.c CTB_SNIPPET_SET_ANALOG_SWITCH
1258 *
1259 *******************************************************************************/
Cy_CTB_SetAnalogSwitch(CTBM_Type * base,cy_en_ctb_switch_register_sel_t switchSelect,uint32_t switchMask,cy_en_ctb_switch_state_t state)1260 void Cy_CTB_SetAnalogSwitch(CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_ctb_switch_state_t state)
1261 {
1262 CY_ASSERT_L3(CY_CTB_SWITCHSELECT(switchSelect));
1263 CY_ASSERT_L2(CY_CTB_SWITCHMASK(switchSelect, switchMask));
1264 CY_ASSERT_L3(CY_CTB_SWITCHSTATE(state));
1265
1266 __IOM uint32_t *switchReg;
1267 __IOM uint32_t *switchClearReg;
1268
1269 uint32_t * switchStoragePtr;
1270 uint32_t switchStorageMsk;
1271
1272 switch(switchSelect)
1273 {
1274 case CY_CTB_SWITCH_OA0_SW:
1275 switchReg = &CTBM_OA0_SW(base);
1276 switchClearReg = &CTBM_OA0_SW_CLEAR(base);
1277 switchStoragePtr = &cy_ctb_oa0Sw;
1278 switchStorageMsk = OA0_SW_Msk;
1279 break;
1280 case CY_CTB_SWITCH_OA1_SW:
1281 switchReg = &CTBM_OA1_SW(base);
1282 switchClearReg = &CTBM_OA1_SW_CLEAR(base);
1283 switchStoragePtr = &cy_ctb_oa1Sw;
1284 switchStorageMsk = OA1_SW_Msk;
1285 break;
1286 case CY_CTB_SWITCH_CTD_SW:
1287 default:
1288 switchReg = &CTBM_CTD_SW(base);
1289 switchClearReg = &CTBM_CTD_SW_CLEAR(base);
1290 switchStoragePtr = &cy_ctb_ctdSw;
1291 switchStorageMsk = CTD_SW_Msk;
1292 break;
1293 }
1294
1295 switch(state)
1296 {
1297 case CY_CTB_SWITCH_CLOSE:
1298 *switchReg = switchMask;
1299 *switchStoragePtr |= switchStorageMsk & switchMask;
1300 break;
1301 case CY_CTB_SWITCH_OPEN:
1302 default:
1303 *switchClearReg = switchMask;
1304 *switchStoragePtr &= ~(switchStorageMsk & switchMask);
1305 break;
1306 }
1307 }
1308
1309 /*******************************************************************************
1310 * Function Name: Cy_CTB_GetAnalogSwitch
1311 ****************************************************************************//**
1312 *
1313 * Return the open or closed state of the specified analog switch.
1314 *
1315 * \param base
1316 * Pointer to structure describing registers
1317 *
1318 * \param switchSelect
1319 * A value of the enum \ref cy_en_ctb_switch_register_sel_t to select the switch
1320 * register
1321 *
1322 * \return
1323 * The state of the switches in the provided register.
1324 * Compare this value to the switch masks in the following enums:
1325 * \ref cy_en_ctb_oa0_switches_t, \ref cy_en_ctb_oa1_switches_t, and \ref cy_en_ctb_ctd_switches_t.
1326 *
1327 * \funcusage
1328 *
1329 * \snippet ctb/snippet/main.c CTB_SNIPPET_GET_ANALOG_SWITCH
1330 *
1331 *******************************************************************************/
Cy_CTB_GetAnalogSwitch(const CTBM_Type * base,cy_en_ctb_switch_register_sel_t switchSelect)1332 uint32_t Cy_CTB_GetAnalogSwitch(const CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect)
1333 {
1334 CY_ASSERT_L3(CY_CTB_SWITCHSELECT(switchSelect));
1335
1336 uint32_t switchRegValue;
1337
1338 switch(switchSelect)
1339 {
1340 case CY_CTB_SWITCH_OA0_SW:
1341 switchRegValue = CTBM_OA0_SW(base);
1342 break;
1343 case CY_CTB_SWITCH_OA1_SW:
1344 switchRegValue = CTBM_OA1_SW(base);
1345 break;
1346 case CY_CTB_SWITCH_CTD_SW:
1347 default:
1348 switchRegValue = CTBM_CTD_SW(base);
1349 break;
1350 }
1351
1352 return switchRegValue;
1353 }
1354
1355 /*******************************************************************************
1356 * Function Name: Cy_CTB_CompSetConfig
1357 ****************************************************************************//**
1358 *
1359 * Configure the CTB comparator for pulse or level output, to bypass clock
1360 * synchronization, and to enable hysteresis.
1361 *
1362 * \param base
1363 * Pointer to structure describing registers
1364 *
1365 * \param compNum
1366 * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
1367 *
1368 * \param level
1369 * Configure output to produce a pulse or level output signal
1370
1371 * \param bypass
1372 * Configure output to be clock synchronized or unsynchronized
1373
1374 * \param hyst
1375 * Enable or disable input hysteresis
1376
1377 * \return None
1378 *
1379 * \funcusage
1380 *
1381 * \snippet ctb/snippet/main.c CTB_SNIPPET_COMP_SET_CONFIG
1382 *
1383 *******************************************************************************/
Cy_CTB_CompSetConfig(CTBM_Type * base,cy_en_ctb_opamp_sel_t compNum,cy_en_ctb_comp_level_t level,cy_en_ctb_comp_bypass_t bypass,cy_en_ctb_comp_hyst_t hyst)1384 void Cy_CTB_CompSetConfig(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_level_t level, cy_en_ctb_comp_bypass_t bypass, cy_en_ctb_comp_hyst_t hyst)
1385 {
1386 CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
1387 CY_ASSERT_L3(CY_CTB_COMPLEVEL(level));
1388 CY_ASSERT_L3(CY_CTB_COMPBYPASS(bypass));
1389 CY_ASSERT_L3(CY_CTB_COMPHYST(hyst));
1390
1391 uint32_t opampCtrlReg;
1392
1393 if ((compNum == CY_CTB_OPAMP_0) || (compNum == CY_CTB_OPAMP_BOTH))
1394 {
1395 opampCtrlReg = CTBM_OA_RES0_CTRL(base) & ~(CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk | CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk);
1396 CTBM_OA_RES0_CTRL(base) = opampCtrlReg | (uint32_t) level |(uint32_t) bypass | (uint32_t) hyst;
1397 }
1398
1399 if ((compNum == CY_CTB_OPAMP_1) || (compNum == CY_CTB_OPAMP_BOTH))
1400 {
1401 opampCtrlReg = CTBM_OA_RES1_CTRL(base) & ~(CTBM_OA_RES1_CTRL_OA1_HYST_EN_Msk | CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk);
1402 CTBM_OA_RES1_CTRL(base) = opampCtrlReg | (uint32_t) level |(uint32_t) bypass | (uint32_t) hyst;
1403 }
1404 }
1405
1406 /*******************************************************************************
1407 * Function Name: Cy_CTB_CompGetConfig
1408 ****************************************************************************//**
1409 *
1410 * Return the CTB comparator operating configuration as set by \ref Cy_CTB_CompSetConfig.
1411 *
1412 * \param base
1413 * Pointer to structure describing registers
1414 *
1415 * \param compNum
1416 * \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1
1417 *
1418 * \return
1419 * The comparator configuration.
1420 * Compare the register value with the masks in \ref cy_en_ctb_comp_level_t,
1421 * \ref cy_en_ctb_comp_bypass_t, and \ref cy_en_ctb_comp_hyst_t.
1422 *
1423 * \funcusage
1424 *
1425 * \snippet ctb/snippet/main.c CTB_SNIPPET_COMP_GET_CONFIG
1426 *
1427 *******************************************************************************/
Cy_CTB_CompGetConfig(const CTBM_Type * base,cy_en_ctb_opamp_sel_t compNum)1428 uint32_t Cy_CTB_CompGetConfig(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
1429 {
1430 CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(compNum));
1431
1432 uint32_t config;
1433
1434 if (compNum == CY_CTB_OPAMP_0)
1435 {
1436 config = CTBM_OA_RES0_CTRL(base) & (CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk | CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk);
1437 }
1438 else
1439 {
1440 config = CTBM_OA_RES1_CTRL(base) & (CTBM_OA_RES1_CTRL_OA1_HYST_EN_Msk | CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk);
1441 }
1442
1443 return config;
1444 }
1445
1446 /*******************************************************************************
1447 * Function Name: Cy_CTB_CompSetInterruptEdgeType
1448 ****************************************************************************//**
1449 *
1450 * Configure the type of edge that will trigger a comparator interrupt.
1451 *
1452 * \param base
1453 * Pointer to structure describing registers
1454 *
1455 * \param compNum
1456 * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
1457 *
1458 * \param edge
1459 * Edge type that will trigger an interrupt. Select a value from \ref cy_en_ctb_comp_edge_t.
1460 *
1461 * \return None
1462 *
1463 * \funcusage
1464 *
1465 * \snippet ctb/snippet/main.c CTB_SNIPPET_COMP_SET_INTERRUPT_EDGE_TYPE
1466 *
1467 *******************************************************************************/
Cy_CTB_CompSetInterruptEdgeType(CTBM_Type * base,cy_en_ctb_opamp_sel_t compNum,cy_en_ctb_comp_edge_t edge)1468 void Cy_CTB_CompSetInterruptEdgeType(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_edge_t edge)
1469 {
1470 CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
1471 CY_ASSERT_L3(CY_CTB_COMPEDGE(edge));
1472
1473 uint32_t opampCtrlReg;
1474
1475 if ((compNum == CY_CTB_OPAMP_0) || (compNum == CY_CTB_OPAMP_BOTH))
1476 {
1477 opampCtrlReg = CTBM_OA_RES0_CTRL(base) & ~(CTBM_OA_RES0_CTRL_OA0_COMPINT_Msk);
1478 CTBM_OA_RES0_CTRL(base) = opampCtrlReg | (uint32_t) edge;
1479 }
1480
1481 if ((compNum == CY_CTB_OPAMP_1) || (compNum == CY_CTB_OPAMP_BOTH))
1482 {
1483 opampCtrlReg = CTBM_OA_RES1_CTRL(base) & ~(CTBM_OA_RES1_CTRL_OA1_COMPINT_Msk);
1484 CTBM_OA_RES1_CTRL(base) = opampCtrlReg | (uint32_t) edge;
1485 }
1486 }
1487
1488 /*******************************************************************************
1489 * Function Name: Cy_CTB_CompGetStatus
1490 ****************************************************************************//**
1491 *
1492 * Return the comparator output status.
1493 * When the positive input voltage is greater than the negative input voltage,
1494 * the comparator status is high. Otherwise, the status is low.
1495 *
1496 * \param base
1497 * Pointer to structure describing registers
1498 *
1499 * \param compNum
1500 * \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1.
1501 * \ref CY_CTB_OPAMP_NONE and \ref CY_CTB_OPAMP_BOTH are invalid options.
1502 *
1503 * \return
1504 * The comparator status.
1505 * A value of 0 is returned if compNum is invalid.
1506 * - 0: Status is low
1507 * - 1: Status is high
1508 *
1509 * \funcusage
1510 *
1511 * \snippet ctb/snippet/main.c CTB_SNIPPET_COMP_GET_STATUS
1512 *
1513 *******************************************************************************/
Cy_CTB_CompGetStatus(const CTBM_Type * base,cy_en_ctb_opamp_sel_t compNum)1514 uint32_t Cy_CTB_CompGetStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
1515 {
1516 CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(compNum));
1517
1518 uint32_t compStatusResult;
1519
1520 if (CY_CTB_OPAMP_0 == compNum)
1521 {
1522 compStatusResult = (CTBM_COMP_STAT(base) & CTBM_COMP_STAT_OA0_COMP_Msk) >> CTBM_COMP_STAT_OA0_COMP_Pos;
1523 }
1524 else if (CY_CTB_OPAMP_1 == compNum)
1525 {
1526 compStatusResult = (CTBM_COMP_STAT(base) & CTBM_COMP_STAT_OA1_COMP_Msk) >> CTBM_COMP_STAT_OA1_COMP_Pos;
1527 }
1528 else
1529 {
1530 compStatusResult = 0UL;
1531 }
1532
1533 return compStatusResult;
1534 }
1535 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 11.3')
1536
1537 #if defined(__cplusplus)
1538 }
1539 #endif
1540
1541 #endif /* CY_IP_MXS40PASS_CTB */
1542
1543 #endif /* CY_IP_MXS40PASS */
1544
1545 /* [] END OF FILE */
1546
