1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 /**
22 * @file core1startup.c
23 * @brief Startup Code for MAX32665 Family CPU1
24 * @details These functions are called at the startup of the second ARM core (CPU1/Core1)
25 */
26 #include <string.h>
27 #include <stdio.h>
28 #include <stdlib.h>
29 #include "max32665.h"
30 #include "mxc_sys.h"
31 #include "gcr_regs.h"
32 #include "icc_regs.h"
33 #include "pwrseq_regs.h"
34
35 extern uint32_t __isr_vector_core1;
36
Core1_Start(void)37 void Core1_Start(void)
38 {
39 MXC_GCR->gp0 = (uint32_t)(&__isr_vector_core1);
40 MXC_GCR->perckcn1 &= ~MXC_F_GCR_PERCKCN1_CPU1D;
41 }
42
Core1_Stop(void)43 void Core1_Stop(void)
44 {
45 MXC_GCR->perckcn1 |= MXC_F_GCR_PERCKCN1_CPU1D;
46 }
47
Core1_Main(void)48 __weak int Core1_Main(void)
49 {
50 // The user should declare this in application code, so we'll just spin
51 while (1) {}
52 }
PreInit_Core1(void)53 __weak void PreInit_Core1(void)
54 {
55 return;
56 }
57
SystemInit_Core1(void)58 __weak void SystemInit_Core1(void)
59 {
60 /* Configure the interrupt controller to use the application vector table in
61 * the application space */
62 SCB->VTOR = (uint32_t)&__isr_vector_core1;
63
64 /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11
65 * Grant full access, per "Table B3-24 CPACR bit assignments".
66 * DDI0403D "ARMv7-M Architecture Reference Manual" */
67 SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
68 __DSB();
69 __ISB();
70
71 // Enable ICache1 Clock
72 MXC_GCR->perckcn1 &= ~(1 << 22);
73
74 // Invalidate cache and wait until ready
75 MXC_ICC1->invalidate = 1;
76 while (!(MXC_ICC1->cache_ctrl & MXC_F_ICC_CACHE_CTRL_RDY)) {}
77
78 // Enable Cache
79 MXC_ICC1->cache_ctrl |= MXC_F_ICC_CACHE_CTRL_EN;
80 while (!(MXC_ICC1->cache_ctrl & MXC_F_ICC_CACHE_CTRL_RDY)) {}
81 }
82
