1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_tim_ex.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef STM32L4xx_HAL_TIM_EX_H 38 #define STM32L4xx_HAL_TIM_EX_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l4xx_hal_def.h" 46 47 /** @addtogroup STM32L4xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup TIMEx 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types 57 * @{ 58 */ 59 60 /** 61 * @brief TIM Hall sensor Configuration Structure definition 62 */ 63 64 typedef struct 65 { 66 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 67 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 68 69 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 70 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 71 72 uint32_t IC1Filter; /*!< Specifies the input capture filter. 73 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 74 75 uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 76 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 77 } TIM_HallSensor_InitTypeDef; 78 79 /** 80 * @brief TIM Break/Break2 input configuration 81 */ 82 typedef struct 83 { 84 uint32_t Source; /*!< Specifies the source of the timer break input. 85 This parameter can be a value of @ref TIMEx_Break_Input_Source */ 86 uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. 87 This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ 88 uint32_t Polarity; /*!< Specifies the break input source polarity. 89 This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity 90 Not relevant when analog watchdog output of the DFSDM1 used as break input source */ 91 } 92 TIMEx_BreakInputConfigTypeDef; 93 94 /** 95 * @} 96 */ 97 /* End of exported types -----------------------------------------------------*/ 98 99 /* Exported constants --------------------------------------------------------*/ 100 /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants 101 * @{ 102 */ 103 104 /** @defgroup TIMEx_Remap TIM Extended Remapping 105 * @{ 106 */ 107 #define TIM_TIM1_ETR_ADC1_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ 108 #define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR1_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */ 109 #define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR1_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */ 110 #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ 111 #if defined (ADC3) 112 #define TIM_TIM1_ETR_ADC3_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ 113 #define TIM_TIM1_ETR_ADC3_AWD1 TIM1_OR1_ETR_ADC3_RMP_0 /* !< TIM1_ETR is connected to ADC3 AWD1 */ 114 #define TIM_TIM1_ETR_ADC3_AWD2 TIM1_OR1_ETR_ADC3_RMP_1 /* !< TIM1_ETR is connected to ADC3 AWD2 */ 115 #define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */ 116 #endif /* ADC3 */ 117 #define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 TI1 is connected to GPIO */ 118 #define TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /* !< TIM1 TI1 is connected to COMP1 */ 119 #define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ 120 #define TIM_TIM1_ETR_COMP1 TIM1_OR2_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */ 121 #if defined(COMP2) 122 #define TIM_TIM1_ETR_COMP2 TIM1_OR2_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */ 123 #endif /* COMP2 */ 124 125 #if defined (USB_OTG_FS) 126 #define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */ 127 #define TIM_TIM2_ITR1_OTG_FS_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to OTG_FS SOF */ 128 #else 129 #if defined(STM32L471xx) 130 #define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */ 131 #define TIM_TIM2_ITR1_NONE TIM2_OR1_ITR1_RMP /* !< No internal trigger on TIM2_ITR1 */ 132 #else 133 #define TIM_TIM2_ITR1_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */ 134 #define TIM_TIM2_ITR1_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */ 135 #endif /* STM32L471xx */ 136 #endif /* USB_OTG_FS */ 137 #define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */ 138 #define TIM_TIM2_ETR_LSE TIM2_OR1_ETR1_RMP /* !< TIM2_ETR is connected to LSE */ 139 #define TIM_TIM2_ETR_COMP1 TIM2_OR2_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */ 140 #if defined(COMP2) 141 #define TIM_TIM2_ETR_COMP2 TIM2_OR2_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */ 142 #endif /* COMP2 */ 143 #define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2 TI4 is connected to GPIO */ 144 #define TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /* !< TIM2 TI4 is connected to COMP1 output */ 145 #if defined(COMP2) 146 #define TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /* !< TIM2 TI4 is connected to COMP2 output */ 147 #define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */ 148 #endif /* COMP2 */ 149 150 #if defined (TIM3) 151 #define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3 TI1 is connected to GPIO */ 152 #define TIM_TIM3_TI1_COMP1 TIM3_OR1_TI1_RMP_0 /* !< TIM3 TI1 is connected to COMP1 output */ 153 #define TIM_TIM3_TI1_COMP2 TIM3_OR1_TI1_RMP_1 /* !< TIM3 TI1 is connected to COMP2 output */ 154 #define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */ 155 #define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */ 156 #define TIM_TIM3_ETR_COMP1 TIM3_OR2_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */ 157 #endif /* TIM3 */ 158 159 #if defined (TIM8) 160 #if defined(ADC2) && defined(ADC3) 161 #define TIM_TIM8_ETR_ADC2_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ 162 #define TIM_TIM8_ETR_ADC2_AWD1 TIM8_OR1_ETR_ADC2_RMP_0 /* !< TIM8_ETR is connected to ADC2 AWD1 */ 163 #define TIM_TIM8_ETR_ADC2_AWD2 TIM8_OR1_ETR_ADC2_RMP_1 /* !< TIM8_ETR is connected to ADC2 AWD2 */ 164 #define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */ 165 #define TIM_TIM8_ETR_ADC3_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ 166 #define TIM_TIM8_ETR_ADC3_AWD1 TIM8_OR1_ETR_ADC3_RMP_0 /* !< TIM8_ETR is connected to ADC3 AWD1 */ 167 #define TIM_TIM8_ETR_ADC3_AWD2 TIM8_OR1_ETR_ADC3_RMP_1 /* !< TIM8_ETR is connected to ADC3 AWD2 */ 168 #define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */ 169 #endif /* ADC2 && ADC3 */ 170 171 #define TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8 TI1 is connected to GPIO */ 172 #define TIM_TIM8_TI1_COMP2 TIM8_OR1_TI1_RMP /* !< TIM8 TI1 is connected to COMP1 */ 173 #define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */ 174 #define TIM_TIM8_ETR_COMP1 TIM8_OR2_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 output */ 175 #define TIM_TIM8_ETR_COMP2 TIM8_OR2_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 output */ 176 #endif /* TIM8 */ 177 178 #define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15 TI1 is connected to GPIO */ 179 #define TIM_TIM15_TI1_LSE TIM15_OR1_TI1_RMP /* !< TIM15 TI1 is connected to LSE */ 180 #define TIM_TIM15_ENCODERMODE_NONE 0x00000000U /* !< No redirection */ 181 #define TIM_TIM15_ENCODERMODE_TIM2 TIM15_OR1_ENCODER_MODE_0 /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ 182 #if defined (TIM3) 183 #define TIM_TIM15_ENCODERMODE_TIM3 TIM15_OR1_ENCODER_MODE_1 /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ 184 #endif /* TIM3 */ 185 #if defined (TIM4) 186 #define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ 187 #endif /* TIM4 */ 188 189 #define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */ 190 #define TIM_TIM16_TI1_LSI TIM16_OR1_TI1_RMP_0 /* !< TIM16 TI1 is connected to LSI */ 191 #define TIM_TIM16_TI1_LSE TIM16_OR1_TI1_RMP_1 /* !< TIM16 TI1 is connected to LSE */ 192 #define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */ 193 #if defined (TIM16_OR1_TI1_RMP_2) 194 #define TIM_TIM16_TI1_MSI TIM16_OR1_TI1_RMP_2 /* !< TIM16 TI1 is connected to MSI */ 195 #define TIM_TIM16_TI1_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to HSE div 32 */ 196 #define TIM_TIM16_TI1_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to MCO */ 197 #endif /* TIM16_OR1_TI1_RMP_2 */ 198 199 #if defined (TIM17) 200 #define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */ 201 #define TIM_TIM17_TI1_MSI TIM17_OR1_TI1_RMP_0 /* !< TIM17 TI1 is connected to MSI */ 202 #define TIM_TIM17_TI1_HSE_32 TIM17_OR1_TI1_RMP_1 /* !< TIM17 TI1 is connected to HSE div 32 */ 203 #define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */ 204 #endif /* TIM17 */ 205 /** 206 * @} 207 */ 208 209 /** @defgroup TIMEx_Break_Input TIM Extended Break input 210 * @{ 211 */ 212 #define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */ 213 #define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */ 214 /** 215 * @} 216 */ 217 218 /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source 219 * @{ 220 */ 221 #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ 222 #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ 223 #define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ 224 #if defined (DFSDM1_Channel0) 225 #define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ 226 #endif /* DFSDM1_Channel0 */ 227 /** 228 * @} 229 */ 230 231 /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling 232 * @{ 233 */ 234 #define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */ 235 #define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */ 236 /** 237 * @} 238 */ 239 240 /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity 241 * @{ 242 */ 243 #define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */ 244 #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */ 245 /** 246 * @} 247 */ 248 249 /** 250 * @} 251 */ 252 /* End of exported constants -------------------------------------------------*/ 253 254 /* Exported macro ------------------------------------------------------------*/ 255 /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros 256 * @{ 257 */ 258 259 /** 260 * @} 261 */ 262 /* End of exported macro -----------------------------------------------------*/ 263 264 /* Private macro -------------------------------------------------------------*/ 265 /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros 266 * @{ 267 */ 268 #define IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F)) 269 270 #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ 271 ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) 272 273 #if defined (DFSDM1_Channel0) 274 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ 275 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ 276 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ 277 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1)) 278 #else 279 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ 280 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ 281 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) 282 #endif /* DFSDM1_Channel0 */ 283 284 #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ 285 ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) 286 287 #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ 288 ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) 289 290 /** 291 * @} 292 */ 293 /* End of private macro ------------------------------------------------------*/ 294 295 /* Exported functions --------------------------------------------------------*/ 296 /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions 297 * @{ 298 */ 299 300 /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions 301 * @brief Timer Hall Sensor functions 302 * @{ 303 */ 304 /* Timer Hall Sensor functions **********************************************/ 305 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); 306 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); 307 308 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); 309 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); 310 311 /* Blocking mode: Polling */ 312 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); 313 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); 314 /* Non-Blocking mode: Interrupt */ 315 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); 316 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); 317 /* Non-Blocking mode: DMA */ 318 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 319 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); 320 /** 321 * @} 322 */ 323 324 /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions 325 * @brief Timer Complementary Output Compare functions 326 * @{ 327 */ 328 /* Timer Complementary Output Compare functions *****************************/ 329 /* Blocking mode: Polling */ 330 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 331 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 332 333 /* Non-Blocking mode: Interrupt */ 334 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 335 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 336 337 /* Non-Blocking mode: DMA */ 338 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 339 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 340 /** 341 * @} 342 */ 343 344 /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions 345 * @brief Timer Complementary PWM functions 346 * @{ 347 */ 348 /* Timer Complementary PWM functions ****************************************/ 349 /* Blocking mode: Polling */ 350 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 351 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 352 353 /* Non-Blocking mode: Interrupt */ 354 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 355 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 356 /* Non-Blocking mode: DMA */ 357 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 358 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 359 /** 360 * @} 361 */ 362 363 /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions 364 * @brief Timer Complementary One Pulse functions 365 * @{ 366 */ 367 /* Timer Complementary One Pulse functions **********************************/ 368 /* Blocking mode: Polling */ 369 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 370 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 371 372 /* Non-Blocking mode: Interrupt */ 373 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 374 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 375 /** 376 * @} 377 */ 378 379 /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions 380 * @brief Peripheral Control functions 381 * @{ 382 */ 383 /* Extended Control functions ************************************************/ 384 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); 385 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); 386 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); 387 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig); 388 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); 389 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); 390 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); 391 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); 392 /** 393 * @} 394 */ 395 396 /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions 397 * @brief Extended Callbacks functions 398 * @{ 399 */ 400 /* Extended Callback **********************************************************/ 401 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); 402 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); 403 void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); 404 /** 405 * @} 406 */ 407 408 /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions 409 * @brief Extended Peripheral State functions 410 * @{ 411 */ 412 /* Extended Peripheral State functions ***************************************/ 413 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); 414 /** 415 * @} 416 */ 417 418 /** 419 * @} 420 */ 421 /* End of exported functions -------------------------------------------------*/ 422 423 /* Private functions----------------------------------------------------------*/ 424 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions 425 * @{ 426 */ 427 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); 428 /** 429 * @} 430 */ 431 /* End of private functions --------------------------------------------------*/ 432 433 /** 434 * @} 435 */ 436 437 /** 438 * @} 439 */ 440 441 #ifdef __cplusplus 442 } 443 #endif 444 445 446 #endif /* STM32L4xx_HAL_TIM_EX_H */ 447 448 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 449
