1 /* 2 * Copyright 2020-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 /** 7 * @file Clock_Ip_Data.c 8 * @version 3.0.0 9 * 10 * @brief CLOCK driver implementations. 11 * @details CLOCK driver implementations. 12 * 13 * @addtogroup CLOCK_DRIVER Clock Ip Driver 14 * @{ 15 */ 16 17 #ifdef __cplusplus 18 extern "C"{ 19 #endif 20 21 22 /*================================================================================================== 23 * INCLUDE FILES 24 * 1) system and project includes 25 * 2) needed interfaces from external units 26 * 3) internal and external interfaces from this unit 27 ==================================================================================================*/ 28 29 30 #include "Clock_Ip_Private.h" 31 32 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT)) 33 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT) 34 #define USER_MODE_REG_PROT_ENABLED (STD_ON) 35 #include "RegLockMacros.h" 36 #endif 37 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */ 38 39 /*================================================================================================== 40 * SOURCE FILE VERSION INFORMATION 41 ==================================================================================================*/ 42 #define CLOCK_IP_DATA_VENDOR_ID_C 43 43 #define CLOCK_IP_DATA_AR_RELEASE_MAJOR_VERSION_C 4 44 #define CLOCK_IP_DATA_AR_RELEASE_MINOR_VERSION_C 7 45 #define CLOCK_IP_DATA_AR_RELEASE_REVISION_VERSION_C 0 46 #define CLOCK_IP_DATA_SW_MAJOR_VERSION_C 3 47 #define CLOCK_IP_DATA_SW_MINOR_VERSION_C 0 48 #define CLOCK_IP_DATA_SW_PATCH_VERSION_C 0 49 50 /*================================================================================================== 51 * FILE VERSION CHECKS 52 ==================================================================================================*/ 53 /* Check if Clock_Ip_Data.c file and Clock_Ip_Private.h file are of the same vendor */ 54 #if (CLOCK_IP_DATA_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID) 55 #error "Clock_Ip_Data.c and Clock_Ip_Private.h have different vendor ids" 56 #endif 57 58 /* Check if Clock_Ip_Data.c file and Clock_Ip_Private.h file are of the same Autosar version */ 59 #if ((CLOCK_IP_DATA_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \ 60 (CLOCK_IP_DATA_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \ 61 (CLOCK_IP_DATA_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \ 62 ) 63 #error "AutoSar Version Numbers of Clock_Ip_Data.c and Clock_Ip_Private.h are different" 64 #endif 65 66 /* Check if Clock_Ip_Data.c file and Clock_Ip_Private.h file are of the same Software version */ 67 #if ((CLOCK_IP_DATA_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \ 68 (CLOCK_IP_DATA_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \ 69 (CLOCK_IP_DATA_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \ 70 ) 71 #error "Software Version Numbers of Clock_Ip_Data.c and Clock_Ip_Private.h are different" 72 #endif 73 74 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT)) 75 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT) 76 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 77 /* Check if Clock_Ip_Data.c file and RegLockMacros.h file are of the same Autosar version */ 78 #if ((CLOCK_IP_DATA_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \ 79 (CLOCK_IP_DATA_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION)) 80 #error "AutoSar Version Numbers of Clock_Ip_Data.c and RegLockMacros.h are different" 81 #endif 82 #endif 83 #endif 84 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */ 85 86 /*================================================================================================== 87 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) 88 ==================================================================================================*/ 89 90 /*================================================================================================== 91 * LOCAL MACROS 92 ==================================================================================================*/ 93 94 95 #define CLOCK_IP_NO_CALLBACK 0U 96 #define CLOCK_IP_SWMUX_DIV 1U 97 #define CLOCK_IP_FIRCOSC 1U 98 #define CLOCK_IP_FAST_XOSC_CMU 1U 99 #define CLOCK_IP_PLL_MOD 1U 100 #define CLOCK_IP_GATE 1U 101 #define CLOCK_IP_PLL 2U 102 #define CLOCK_IP_HWMUX_DIV 2U 103 #define CLOCK_IP_FIRCOSC_STDBY 2U 104 #define CLOCK_IP_SLOW_XOSC 2U 105 #define CLOCK_IP_PLL_POSTDIV 3U 106 #define CLOCK_IP_HWMUX_PCFS 3U 107 #define CLOCK_IP_SIRCOSC_STDBY 3U 108 #define CLOCK_IP_PCFS_PLL_OUT 4U 109 #define CLOCK_IP_RTC_SEL 4U 110 #define CLOCK_IP_PLL_OUT 5U 111 #define CLOCK_IP_DIV_TRIGGER_CMU 6U 112 #define CLOCK_IP_DIV_TRIGGER 7U 113 #define CLOCK_IP_HWMUX_DIV_GATE 8U 114 115 #define CLOCK_IP_SCS_EXTENSION 0U 116 #define CLOCK_IP_CLKOUT_RUN_EXTENSION 1U 117 #define CLOCK_IP_CLKOUT_STANDBY_EXTENSION 2U 118 #if defined(CLOCK_IP_HAS_EMAC_RX_CLK) 119 #define CLOCK_IP_EMAC_RX_EXTENSION 3U 120 #endif 121 #if defined(CLOCK_IP_HAS_EMAC_TS_CLK) 122 #define CLOCK_IP_EMAC_TS_EXTENSION 4U 123 #endif 124 #if defined(CLOCK_IP_HAS_EMAC_TX_CLK) 125 #define CLOCK_IP_EMAC_TX_EXTENSION 5U 126 #endif 127 #if defined(CLOCK_IP_HAS_EMAC_TX_RMII_CLK) 128 #define CLOCK_IP_EMAC_TX_RMII_EXTENSION 6U 129 #endif 130 #define CLOCK_IP_FLEXCANA_EXTENSION 7U 131 #define CLOCK_IP_FLEXCANB_EXTENSION 8U 132 #if defined(CLOCK_IP_HAS_LFAST_REF_CLK) 133 #define CLOCK_IP_LFAST_REF_EXTENSION 9U 134 #endif 135 #if defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK) 136 #define CLOCK_IP_QSPI_2XSFIF_EXTENSION 10U 137 #elif defined(CLOCK_IP_HAS_QSPI_SFCK_CLK) 138 #define CLOCK_IP_QSPI_SFIF_EXTENSION 10U 139 #endif 140 #define CLOCK_IP_STMA_EXTENSION 11U 141 #if defined(CLOCK_IP_HAS_STMB_CLK) 142 #define CLOCK_IP_STMB_EXTENSION 12U 143 #endif 144 #if defined(CLOCK_IP_HAS_STMC_CLK) 145 #define CLOCK_IP_STMC_EXTENSION 13U 146 #endif 147 #if defined(CLOCK_IP_HAS_SWG_CLK) 148 #define CLOCK_IP_SWG_EXTENSION 14U 149 #endif 150 #define CLOCK_IP_TRACE_EXTENSION 15U 151 #define CLOCK_IP_AIPS_PLAT_EXTENSION 16U 152 #define CLOCK_IP_AIPS_SLOW_EXTENSION 17U 153 #define CLOCK_IP_HSE_EXTENSION 18U 154 #define CLOCK_IP_DCM_EXTENSION 19U 155 #if defined(CLOCK_IP_HAS_LBIST_CLK) 156 #define CLOCK_IP_LBIST_EXTENSION 20U 157 #endif 158 #if defined(CLOCK_IP_HAS_USDHC_CLK) 159 #define CLOCK_IP_USDHC_EXTENSION 21U 160 #endif 161 #define CLOCK_IP_CORE_EXTENSION 22U 162 #if defined(CLOCK_IP_HAS_QSPI_MEM_CLK) 163 #define CLOCK_IP_QSPI_MEM_EXTENSION 23U 164 #endif 165 #if defined(CLOCK_IP_HAS_STMD_CLK) 166 #define CLOCK_IP_STMD_EXTENSION 24U 167 #endif 168 #if defined(CLOCK_IP_HAS_GMAC0_RX_CLK) 169 #define CLOCK_IP_GMAC0_RX_EXTENSION 25U 170 #endif 171 #if defined(CLOCK_IP_HAS_GMAC0_TX_CLK) 172 #define CLOCK_IP_GMAC0_TX_EXTENSION 26U 173 #endif 174 #if defined(CLOCK_IP_HAS_GMAC_TS_CLK) 175 #define CLOCK_IP_GMAC_TS_EXTENSION 27U 176 #endif 177 #if defined(CLOCK_IP_HAS_GMAC0_TX_RMII_CLK) 178 #define CLOCK_IP_GMAC0_TX_RMII_EXTENSION 28U 179 #endif 180 #if defined(CLOCK_IP_HAS_GMAC1_RX_CLK) 181 #define CLOCK_IP_GMAC1_RX_EXTENSION 29U 182 #endif 183 #if defined(CLOCK_IP_HAS_GMAC1_TX_CLK) 184 #define CLOCK_IP_GMAC1_TX_EXTENSION 30U 185 #endif 186 #if defined(CLOCK_IP_HAS_GMAC1_RMII_CLK) 187 #define CLOCK_IP_GMAC1_RMII_EXTENSION 31U 188 #endif 189 #if defined(CLOCK_IP_HAS_AES_CLK) 190 #define CLOCK_IP_AES_EXTENSION 32U 191 #endif 192 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 193 #define CLOCK_IP_CM7_CORE_EXTENSION 33U 194 #endif 195 196 197 #define CLOCK_IP_PRT0_COL1_REQ40_INDEX 0U 198 #define CLOCK_IP_PRT0_COL1_REQ41_INDEX 1U 199 #if defined(CLOCK_IP_HAS_ADC2_CLK) 200 #define CLOCK_IP_PRT0_COL1_REQ42_INDEX 2U 201 #endif 202 #if defined(CLOCK_IP_HAS_ADC3_CLK) 203 #define CLOCK_IP_PRT0_COL1_REQ43_INDEX 3U 204 #endif 205 #if defined(CLOCK_IP_HAS_ADC4_CLK) 206 #define CLOCK_IP_PRT3_COL1_REQ52_INDEX 4U 207 #endif 208 #if defined(CLOCK_IP_HAS_ADC5_CLK) 209 #define CLOCK_IP_PRT3_COL1_REQ53_INDEX 5U 210 #endif 211 #if defined(CLOCK_IP_HAS_ADC6_CLK) 212 #define CLOCK_IP_PRT3_COL1_REQ54_INDEX 6U 213 #endif 214 #if defined(CLOCK_IP_HAS_AXBS_CLK) 215 #define CLOCK_IP_PRT1_COL0_REQ0_INDEX 7U 216 #endif 217 #if defined(CLOCK_IP_HAS_AXBS0_CLK) 218 #define CLOCK_IP_PRT1_COL0_REQ1_INDEX 8U 219 #endif 220 #if defined(CLOCK_IP_HAS_AXBS1_CLK) 221 #define CLOCK_IP_PRT1_COL0_REQ2_INDEX 9U 222 #endif 223 #define CLOCK_IP_PRT0_COL1_REQ33_INDEX 10U 224 #define CLOCK_IP_PRT1_COL2_REQ92_INDEX 11U 225 #define CLOCK_IP_PRT1_COL2_REQ93_INDEX 12U 226 #if defined(CLOCK_IP_HAS_CMP2_CLK) 227 #define CLOCK_IP_PRT2_COL1_REQ58_INDEX 13U 228 #endif 229 #define CLOCK_IP_PRT1_COL3_REQ96_INDEX 14U 230 #define CLOCK_IP_PRT1_COL1_REQ32_INDEX 15U 231 #define CLOCK_IP_PRT1_COL1_REQ33_INDEX 16U 232 #define CLOCK_IP_PRT1_COL0_REQ3_INDEX 17U 233 #define CLOCK_IP_PRT1_COL0_REQ4_INDEX 18U 234 #define CLOCK_IP_PRT1_COL0_REQ5_INDEX 19U 235 #define CLOCK_IP_PRT1_COL0_REQ6_INDEX 20U 236 #define CLOCK_IP_PRT1_COL0_REQ7_INDEX 21U 237 #define CLOCK_IP_PRT1_COL0_REQ8_INDEX 22U 238 #define CLOCK_IP_PRT1_COL0_REQ9_INDEX 23U 239 #define CLOCK_IP_PRT1_COL0_REQ10_INDEX 24U 240 #define CLOCK_IP_PRT1_COL0_REQ11_INDEX 25U 241 #define CLOCK_IP_PRT1_COL0_REQ12_INDEX 26U 242 #define CLOCK_IP_PRT1_COL0_REQ13_INDEX 27U 243 #define CLOCK_IP_PRT1_COL0_REQ14_INDEX 28U 244 #define CLOCK_IP_PRT1_COL0_REQ15_INDEX 29U 245 #if defined(CLOCK_IP_HAS_EDMA0_TCD12_CLK) 246 #define CLOCK_IP_PRT2_COL0_REQ4_INDEX 30U 247 #endif 248 #if defined(CLOCK_IP_HAS_EDMA0_TCD13_CLK) 249 #define CLOCK_IP_PRT2_COL0_REQ5_INDEX 31U 250 #endif 251 #if defined(CLOCK_IP_HAS_EDMA0_TCD14_CLK) 252 #define CLOCK_IP_PRT2_COL0_REQ6_INDEX 32U 253 #endif 254 #if defined(CLOCK_IP_HAS_EDMA0_TCD15_CLK) 255 #define CLOCK_IP_PRT2_COL0_REQ7_INDEX 33U 256 #endif 257 #if defined(CLOCK_IP_HAS_EDMA0_TCD16_CLK) 258 #define CLOCK_IP_PRT2_COL0_REQ8_INDEX 34U 259 #endif 260 #if defined(CLOCK_IP_HAS_EDMA0_TCD17_CLK) 261 #define CLOCK_IP_PRT2_COL0_REQ9_INDEX 35U 262 #endif 263 #if defined(CLOCK_IP_HAS_EDMA0_TCD18_CLK) 264 #define CLOCK_IP_PRT2_COL0_REQ10_INDEX 36U 265 #endif 266 #if defined(CLOCK_IP_HAS_EDMA0_TCD19_CLK) 267 #define CLOCK_IP_PRT2_COL0_REQ11_INDEX 37U 268 #endif 269 #if defined(CLOCK_IP_HAS_EDMA0_TCD20_CLK) 270 #define CLOCK_IP_PRT2_COL0_REQ12_INDEX 38U 271 #endif 272 #if defined(CLOCK_IP_HAS_EDMA0_TCD21_CLK) 273 #define CLOCK_IP_PRT2_COL0_REQ13_INDEX 39U 274 #endif 275 #if defined(CLOCK_IP_HAS_EDMA0_TCD22_CLK) 276 #define CLOCK_IP_PRT2_COL0_REQ14_INDEX 40U 277 #endif 278 #if defined(CLOCK_IP_HAS_EDMA0_TCD23_CLK) 279 #define CLOCK_IP_PRT2_COL0_REQ15_INDEX 41U 280 #endif 281 #if defined(CLOCK_IP_HAS_EDMA0_TCD24_CLK) 282 #define CLOCK_IP_PRT2_COL0_REQ16_INDEX 42U 283 #endif 284 #if defined(CLOCK_IP_HAS_EDMA0_TCD25_CLK) 285 #define CLOCK_IP_PRT2_COL0_REQ17_INDEX 43U 286 #endif 287 #if defined(CLOCK_IP_HAS_EDMA0_TCD26_CLK) 288 #define CLOCK_IP_PRT2_COL0_REQ18_INDEX 44U 289 #endif 290 #if defined(CLOCK_IP_HAS_EDMA0_TCD27_CLK) 291 #define CLOCK_IP_PRT2_COL0_REQ19_INDEX 45U 292 #endif 293 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 294 #define CLOCK_IP_PRT2_COL0_REQ20_INDEX 46U 295 #endif 296 #if defined(CLOCK_IP_HAS_EDMA0_TCD29_CLK) 297 #define CLOCK_IP_PRT2_COL0_REQ21_INDEX 47U 298 #endif 299 #if defined(CLOCK_IP_HAS_EDMA0_TCD30_CLK) 300 #define CLOCK_IP_PRT2_COL0_REQ22_INDEX 48U 301 #endif 302 #if defined(CLOCK_IP_HAS_EDMA0_TCD31_CLK) 303 #define CLOCK_IP_PRT2_COL0_REQ23_INDEX 49U 304 #endif 305 #define CLOCK_IP_PRT1_COL0_REQ22_INDEX 50U 306 #if defined(CLOCK_IP_HAS_EIM0_CLK) 307 #define CLOCK_IP_PRT2_COL2_REQ67_INDEX 51U 308 #endif 309 #if defined(CLOCK_IP_HAS_EIM1_CLK) 310 #define CLOCK_IP_PRT2_COL2_REQ68_INDEX 52U 311 #endif 312 #if defined(CLOCK_IP_HAS_EIM2_CLK) 313 #define CLOCK_IP_PRT2_COL2_REQ69_INDEX 53U 314 #endif 315 #if defined(CLOCK_IP_HAS_EMAC0_RX_CLK) 316 #define CLOCK_IP_PRT2_COL1_REQ32_INDEX 54U 317 #endif 318 #define CLOCK_IP_PRT0_COL1_REQ34_INDEX 55U 319 #if defined(CLOCK_IP_HAS_EMIOS1_CLK) 320 #define CLOCK_IP_PRT0_COL1_REQ35_INDEX 56U 321 #endif 322 #if defined(CLOCK_IP_HAS_EMIOS2_CLK) 323 #define CLOCK_IP_PRT0_COL1_REQ36_INDEX 57U 324 #endif 325 #define CLOCK_IP_PRT1_COL0_REQ23_INDEX 58U 326 #if defined(CLOCK_IP_HAS_ERM1_CLK) 327 #define CLOCK_IP_PRT0_COL0_REQ3_INDEX 59U 328 #endif 329 #if defined(CLOCK_IP_HAS_FCCU_CLK) 330 #define CLOCK_IP_PRT1_COL3_REQ97_INDEX 60U 331 #endif 332 #if defined(CLOCK_IP_HAS_FLASH0_CLK) 333 #define CLOCK_IP_PRT1_COL0_REQ26_INDEX 61U 334 #endif 335 #if defined(CLOCK_IP_HAS_FLASH0_ALT_CLK) 336 #define CLOCK_IP_PRT1_COL0_REQ27_INDEX 62U 337 #endif 338 #if defined(CLOCK_IP_HAS_FLASH1_CLK) 339 #define CLOCK_IP_PRT1_COL1_REQ59_INDEX 63U 340 #endif 341 #if defined(CLOCK_IP_HAS_FLASH1_ALT_CLK) 342 #define CLOCK_IP_PRT1_COL1_REQ60_INDEX 64U 343 #endif 344 #define CLOCK_IP_PRT1_COL2_REQ65_INDEX 65U 345 #define CLOCK_IP_PRT1_COL2_REQ66_INDEX 66U 346 #define CLOCK_IP_PRT1_COL2_REQ67_INDEX 67U 347 #if defined(CLOCK_IP_HAS_FLEXCAN3_CLK) 348 #define CLOCK_IP_PRT1_COL2_REQ68_INDEX 68U 349 #endif 350 #if defined(CLOCK_IP_HAS_FLEXCAN4_CLK) 351 #define CLOCK_IP_PRT1_COL2_REQ69_INDEX 69U 352 #endif 353 #if defined(CLOCK_IP_HAS_FLEXCAN5_CLK) 354 #define CLOCK_IP_PRT1_COL2_REQ70_INDEX 70U 355 #endif 356 #define CLOCK_IP_PRT1_COL2_REQ73_INDEX 71U 357 #if defined(CLOCK_IP_HAS_HSE_MU0_CLK) 358 #define CLOCK_IP_PRT1_COL3_REQ99_INDEX 72U 359 #endif 360 #if defined(CLOCK_IP_HAS_HSE_MU1_CLK) 361 #define CLOCK_IP_PRT2_COL1_REQ59_INDEX 73U 362 #endif 363 #if defined(CLOCK_IP_HAS_JDC_CLK) 364 #define CLOCK_IP_PRT1_COL3_REQ101_INDEX 74U 365 #endif 366 #define CLOCK_IP_PRT1_COL0_REQ31_INDEX 75U 367 #define CLOCK_IP_PRT0_COL1_REQ38_INDEX 76U 368 #define CLOCK_IP_PRT0_COL1_REQ39_INDEX 77U 369 #if defined(CLOCK_IP_HAS_LPI2C0_CLK) 370 #define CLOCK_IP_PRT1_COL2_REQ84_INDEX 78U 371 #endif 372 #define CLOCK_IP_PRT1_COL2_REQ85_INDEX 79U 373 #define CLOCK_IP_PRT1_COL2_REQ86_INDEX 80U 374 #define CLOCK_IP_PRT1_COL2_REQ87_INDEX 81U 375 #define CLOCK_IP_PRT1_COL2_REQ88_INDEX 82U 376 #define CLOCK_IP_PRT1_COL2_REQ89_INDEX 83U 377 #if defined(CLOCK_IP_HAS_LPSPI4_CLK) 378 #define CLOCK_IP_PRT2_COL1_REQ47_INDEX 84U 379 #endif 380 #if defined(CLOCK_IP_HAS_LPSPI5_CLK) 381 #define CLOCK_IP_PRT2_COL1_REQ48_INDEX 85U 382 #endif 383 #define CLOCK_IP_PRT1_COL2_REQ74_INDEX 86U 384 #define CLOCK_IP_PRT1_COL2_REQ75_INDEX 87U 385 #define CLOCK_IP_PRT1_COL2_REQ76_INDEX 88U 386 #define CLOCK_IP_PRT1_COL2_REQ77_INDEX 89U 387 #if defined(CLOCK_IP_HAS_LPUART4_CLK) 388 #define CLOCK_IP_PRT1_COL2_REQ78_INDEX 90U 389 #endif 390 #if defined(CLOCK_IP_HAS_LPUART5_CLK) 391 #define CLOCK_IP_PRT1_COL2_REQ79_INDEX 91U 392 #endif 393 #if defined(CLOCK_IP_HAS_LPUART6_CLK) 394 #define CLOCK_IP_PRT1_COL2_REQ80_INDEX 92U 395 #endif 396 #if defined(CLOCK_IP_HAS_LPUART7_CLK) 397 #define CLOCK_IP_PRT1_COL2_REQ81_INDEX 93U 398 #endif 399 #if defined(CLOCK_IP_HAS_LPUART8_CLK) 400 #define CLOCK_IP_PRT2_COL1_REQ35_INDEX 94U 401 #endif 402 #if defined(CLOCK_IP_HAS_LPUART9_CLK) 403 #define CLOCK_IP_PRT2_COL1_REQ36_INDEX 95U 404 #endif 405 #if defined(CLOCK_IP_HAS_LPUART10_CLK) 406 #define CLOCK_IP_PRT2_COL1_REQ37_INDEX 96U 407 #endif 408 #if defined(CLOCK_IP_HAS_LPUART11_CLK) 409 #define CLOCK_IP_PRT2_COL1_REQ38_INDEX 97U 410 #endif 411 #if defined(CLOCK_IP_HAS_LPUART12_CLK) 412 #define CLOCK_IP_PRT2_COL1_REQ39_INDEX 98U 413 #endif 414 #if defined(CLOCK_IP_HAS_LPUART13_CLK) 415 #define CLOCK_IP_PRT2_COL1_REQ40_INDEX 99U 416 #endif 417 #if defined(CLOCK_IP_HAS_LPUART14_CLK) 418 #define CLOCK_IP_PRT2_COL1_REQ41_INDEX 100U 419 #endif 420 #if defined(CLOCK_IP_HAS_LPUART15_CLK) 421 #define CLOCK_IP_PRT2_COL1_REQ42_INDEX 101U 422 #endif 423 #define CLOCK_IP_PRT1_COL0_REQ24_INDEX 102U 424 #if defined(CLOCK_IP_HAS_MU2A_CLK) 425 #define CLOCK_IP_PRT0_COL1_REQ46_INDEX 103U 426 #endif 427 #if defined(CLOCK_IP_HAS_MU2B_CLK) 428 #define CLOCK_IP_PRT0_COL1_REQ47_INDEX 104U 429 #endif 430 #define CLOCK_IP_PRT0_COL1_REQ44_INDEX 105U 431 #define CLOCK_IP_PRT0_COL1_REQ45_INDEX 106U 432 #if defined(CLOCK_IP_HAS_PIT2_CLK) 433 #define CLOCK_IP_PRT1_COL1_REQ63_INDEX 107U 434 #endif 435 #if defined(CLOCK_IP_HAS_PRAMC0_CLK) 436 #define CLOCK_IP_PRT1_COL0_REQ25_INDEX 108U 437 #endif 438 #if defined(CLOCK_IP_HAS_PRAMC1_CLK) 439 #define CLOCK_IP_PRT2_COL0_REQ25_INDEX 109U 440 #endif 441 #if defined(CLOCK_IP_HAS_QSPI0_CLK) 442 #define CLOCK_IP_PRT2_COL1_REQ51_INDEX 110U 443 #endif 444 #define CLOCK_IP_PRT1_COL1_REQ34_INDEX 111U 445 #if defined(CLOCK_IP_HAS_SAI0_CLK) 446 #define CLOCK_IP_PRT1_COL2_REQ91_INDEX 112U 447 #endif 448 #if defined(CLOCK_IP_HAS_SAI1_CLK) 449 #define CLOCK_IP_PRT2_COL1_REQ55_INDEX 113U 450 #endif 451 #if defined(CLOCK_IP_HAS_SEMA42_CLK) 452 #define CLOCK_IP_PRT2_COL0_REQ24_INDEX 114U 453 #endif 454 #define CLOCK_IP_PRT1_COL1_REQ42_INDEX 115U 455 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_0_CLK) 456 #define CLOCK_IP_PRT1_COL1_REQ36_INDEX 116U 457 #endif 458 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_1_CLK) 459 #define CLOCK_IP_PRT1_COL1_REQ37_INDEX 117U 460 #endif 461 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_0_CLK) 462 #define CLOCK_IP_PRT1_COL1_REQ38_INDEX 118U 463 #endif 464 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_1_CLK) 465 #define CLOCK_IP_PRT1_COL1_REQ39_INDEX 119U 466 #endif 467 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_0_CLK) 468 #define CLOCK_IP_PRT1_COL1_REQ40_INDEX 120U 469 #endif 470 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_1_CLK) 471 #define CLOCK_IP_PRT1_COL1_REQ41_INDEX 121U 472 #endif 473 #define CLOCK_IP_PRT1_COL3_REQ104_INDEX 122U 474 #define CLOCK_IP_PRT1_COL0_REQ29_INDEX 123U 475 #if defined(CLOCK_IP_HAS_STM1_CLK) 476 #define CLOCK_IP_PRT2_COL0_REQ29_INDEX 124U 477 #endif 478 #if defined(CLOCK_IP_HAS_STM2_CLK) 479 #define CLOCK_IP_PRT2_COL0_REQ30_INDEX 125U 480 #endif 481 #if defined(CLOCK_IP_HAS_SWG0_CLK) 482 #define CLOCK_IP_PRT3_COL1_REQ50_INDEX 126U 483 #endif 484 #if defined(CLOCK_IP_HAS_SWG1_CLK) 485 #define CLOCK_IP_PRT3_COL1_REQ51_INDEX 127U 486 #endif 487 #define CLOCK_IP_PRT1_COL0_REQ28_INDEX 128U 488 #if defined(CLOCK_IP_HAS_SWT1_CLK) 489 #define CLOCK_IP_PRT2_COL0_REQ27_INDEX 129U 490 #endif 491 #if defined(CLOCK_IP_HAS_TCM_CM7_0_CLK) 492 #define CLOCK_IP_PRT2_COL1_REQ62_INDEX 130U 493 #endif 494 #if defined(CLOCK_IP_HAS_TCM_CM7_1_CLK) 495 #define CLOCK_IP_PRT2_COL1_REQ63_INDEX 131U 496 #endif 497 #define CLOCK_IP_PRT1_COL2_REQ95_INDEX 132U 498 #define CLOCK_IP_PRT0_COL1_REQ32_INDEX 133U 499 #define CLOCK_IP_PRT1_COL1_REQ49_INDEX 134U 500 #define CLOCK_IP_PRT1_COL1_REQ45_INDEX 135U 501 #if defined(CLOCK_IP_HAS_XRDC_CLK) 502 #define CLOCK_IP_PRT1_COL0_REQ30_INDEX 136U 503 #endif 504 #if defined(CLOCK_IP_HAS_USDHC_CLK) 505 #define CLOCK_IP_PRT2_COL1_REQ57_INDEX 137U 506 #endif 507 #if defined(CLOCK_IP_HAS_FLEXCAN6_CLK) 508 #define CLOCK_IP_PRT1_COL2_REQ71_INDEX 138U 509 #endif 510 #if defined(CLOCK_IP_HAS_FLEXCAN7_CLK) 511 #define CLOCK_IP_PRT1_COL2_REQ72_INDEX 139U 512 #endif 513 #if defined(CLOCK_IP_HAS_SWT2_CLK) 514 #define CLOCK_IP_PRT2_COL0_REQ28_INDEX 140U 515 #endif 516 #if defined(CLOCK_IP_HAS_SIPI0_CLK) 517 #define CLOCK_IP_PRT2_COL1_REQ60_INDEX 141U 518 #endif 519 #if defined(CLOCK_IP_HAS_GMAC0_CLK) || defined(CLOCK_IP_HAS_GMAC0_RX_CLK) || defined(CLOCK_IP_HAS_GMAC0_TX_CLK) || defined(CLOCK_IP_HAS_GMAC_TS_CLK) 520 #define CLOCK_IP_PRT2_COL1_REQ33_INDEX 142U 521 #endif 522 #if defined(CLOCK_IP_HAS_EIM3_CLK) 523 #define CLOCK_IP_PRT2_COL2_REQ70_INDEX 143U 524 #endif 525 #if defined(CLOCK_IP_HAS_STM3_CLK) 526 #define CLOCK_IP_PRT2_COL0_REQ31_INDEX 144U 527 #endif 528 #if defined(CLOCK_IP_HAS_SWT3_CLK) 529 #define CLOCK_IP_PRT0_COL0_REQ28_INDEX 145U 530 #endif 531 #if defined(CLOCK_IP_HAS_GMAC1_CLK) || defined(CLOCK_IP_HAS_GMAC1_RX_CLK) || defined(CLOCK_IP_HAS_GMAC1_TX_CLK) || defined(CLOCK_IP_HAS_GMAC1_RMII_CLK) 532 #define CLOCK_IP_PRT2_COL1_REQ34_INDEX 146U 533 #endif 534 #if defined(CLOCK_IP_HAS_ADCBIST_CLK) 535 #define CLOCK_IP_PRT3_COL2_REQ65_INDEX 147U 536 #endif 537 #if defined(CLOCK_IP_HAS_BCTU1_CLK) 538 #define CLOCK_IP_PRT3_COL1_REQ49_INDEX 148U 539 #endif 540 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM0_CLK) 541 #define CLOCK_IP_PRT3_COL1_REQ58_INDEX 149U 542 #endif 543 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM1_CLK) 544 #define CLOCK_IP_PRT3_COL1_REQ59_INDEX 150U 545 #endif 546 #if defined(CLOCK_IP_HAS_COOLFLUX_DSP16L_CLK) 547 #define CLOCK_IP_PRT3_COL1_REQ55_INDEX 151U 548 #endif 549 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM0_CLK) 550 #define CLOCK_IP_PRT3_COL1_REQ56_INDEX 152U 551 #endif 552 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM1_CLK) 553 #define CLOCK_IP_PRT3_COL1_REQ57_INDEX 153U 554 #endif 555 #if defined(CLOCK_IP_HAS_DMAMUX2_CLK) 556 #define CLOCK_IP_PRT3_COL1_REQ40_INDEX 154U 557 #endif 558 #if defined(CLOCK_IP_HAS_DMAMUX3_CLK) 559 #define CLOCK_IP_PRT3_COL1_REQ41_INDEX 155U 560 #endif 561 #if defined(CLOCK_IP_HAS_DSPI_MSC_CLK) 562 #define CLOCK_IP_PRT2_COL2_REQ66_INDEX 156U 563 #endif 564 #if defined(CLOCK_IP_HAS_SDA_AP_CLK) 565 #define CLOCK_IP_PRT1_COL0_REQ21_INDEX 157U 566 #endif 567 #if defined(CLOCK_IP_HAS_EDMA1_CLK) 568 #define CLOCK_IP_PRT0_COL0_REQ4_INDEX 158U 569 #endif 570 #if defined(CLOCK_IP_HAS_EDMA1_TCD0_CLK) 571 #define CLOCK_IP_PRT0_COL0_REQ5_INDEX 159U 572 #endif 573 #if defined(CLOCK_IP_HAS_EDMA1_TCD1_CLK) 574 #define CLOCK_IP_PRT0_COL0_REQ6_INDEX 160U 575 #endif 576 #if defined(CLOCK_IP_HAS_EDMA1_TCD2_CLK) 577 #define CLOCK_IP_PRT0_COL0_REQ7_INDEX 161U 578 #endif 579 #if defined(CLOCK_IP_HAS_EDMA1_TCD3_CLK) 580 #define CLOCK_IP_PRT0_COL0_REQ8_INDEX 162U 581 #endif 582 #if defined(CLOCK_IP_HAS_EDMA1_TCD4_CLK) 583 #define CLOCK_IP_PRT0_COL0_REQ9_INDEX 163U 584 #endif 585 #if defined(CLOCK_IP_HAS_EDMA1_TCD5_CLK) 586 #define CLOCK_IP_PRT0_COL0_REQ10_INDEX 164U 587 #endif 588 #if defined(CLOCK_IP_HAS_EDMA1_TCD6_CLK) 589 #define CLOCK_IP_PRT0_COL0_REQ11_INDEX 165U 590 #endif 591 #if defined(CLOCK_IP_HAS_EDMA1_TCD7_CLK) 592 #define CLOCK_IP_PRT0_COL0_REQ12_INDEX 166U 593 #endif 594 #if defined(CLOCK_IP_HAS_EDMA1_TCD8_CLK) 595 #define CLOCK_IP_PRT0_COL0_REQ13_INDEX 167U 596 #endif 597 #if defined(CLOCK_IP_HAS_EDMA1_TCD9_CLK) 598 #define CLOCK_IP_PRT0_COL0_REQ14_INDEX 168U 599 #endif 600 #if defined(CLOCK_IP_HAS_EDMA1_TCD10_CLK) 601 #define CLOCK_IP_PRT0_COL0_REQ15_INDEX 169U 602 #endif 603 #if defined(CLOCK_IP_HAS_EDMA1_TCD11_CLK) 604 #define CLOCK_IP_PRT0_COL0_REQ16_INDEX 170U 605 #endif 606 #if defined(CLOCK_IP_HAS_EDMA1_TCD12_CLK) 607 #define CLOCK_IP_PRT0_COL0_REQ17_INDEX 171U 608 #endif 609 #if defined(CLOCK_IP_HAS_EDMA1_TCD13_CLK) 610 #define CLOCK_IP_PRT0_COL0_REQ18_INDEX 172U 611 #endif 612 #if defined(CLOCK_IP_HAS_EDMA1_TCD14_CLK) 613 #define CLOCK_IP_PRT0_COL0_REQ19_INDEX 173U 614 #endif 615 #if defined(CLOCK_IP_HAS_EDMA1_TCD15_CLK) 616 #define CLOCK_IP_PRT0_COL0_REQ20_INDEX 174U 617 #endif 618 #if defined(CLOCK_IP_HAS_EDMA1_TCD16_CLK) 619 #define CLOCK_IP_PRT3_COL0_REQ0_INDEX 175U 620 #endif 621 #if defined(CLOCK_IP_HAS_EDMA1_TCD17_CLK) 622 #define CLOCK_IP_PRT3_COL0_REQ1_INDEX 176U 623 #endif 624 #if defined(CLOCK_IP_HAS_EDMA1_TCD18_CLK) 625 #define CLOCK_IP_PRT3_COL0_REQ2_INDEX 177U 626 #endif 627 #if defined(CLOCK_IP_HAS_EDMA1_TCD19_CLK) 628 #define CLOCK_IP_PRT3_COL0_REQ3_INDEX 178U 629 #endif 630 #if defined(CLOCK_IP_HAS_EDMA1_TCD20_CLK) 631 #define CLOCK_IP_PRT3_COL0_REQ4_INDEX 179U 632 #endif 633 #if defined(CLOCK_IP_HAS_EDMA1_TCD21_CLK) 634 #define CLOCK_IP_PRT3_COL0_REQ5_INDEX 180U 635 #endif 636 #if defined(CLOCK_IP_HAS_EDMA1_TCD22_CLK) 637 #define CLOCK_IP_PRT3_COL0_REQ6_INDEX 181U 638 #endif 639 #if defined(CLOCK_IP_HAS_EDMA1_TCD23_CLK) 640 #define CLOCK_IP_PRT3_COL0_REQ7_INDEX 182U 641 #endif 642 #if defined(CLOCK_IP_HAS_EDMA1_TCD24_CLK) 643 #define CLOCK_IP_PRT3_COL0_REQ8_INDEX 183U 644 #endif 645 #if defined(CLOCK_IP_HAS_EDMA1_TCD25_CLK) 646 #define CLOCK_IP_PRT3_COL0_REQ9_INDEX 184U 647 #endif 648 #if defined(CLOCK_IP_HAS_EDMA1_TCD26_CLK) 649 #define CLOCK_IP_PRT3_COL0_REQ10_INDEX 185U 650 #endif 651 #if defined(CLOCK_IP_HAS_EDMA1_TCD27_CLK) 652 #define CLOCK_IP_PRT3_COL0_REQ11_INDEX 186U 653 #endif 654 #if defined(CLOCK_IP_HAS_EDMA1_TCD28_CLK) 655 #define CLOCK_IP_PRT3_COL0_REQ12_INDEX 187U 656 #endif 657 #if defined(CLOCK_IP_HAS_EDMA1_TCD29_CLK) 658 #define CLOCK_IP_PRT3_COL0_REQ13_INDEX 188U 659 #endif 660 #if defined(CLOCK_IP_HAS_EDMA1_TCD30_CLK) 661 #define CLOCK_IP_PRT3_COL0_REQ14_INDEX 189U 662 #endif 663 #if defined(CLOCK_IP_HAS_EDMA1_TCD31_CLK) 664 #define CLOCK_IP_PRT3_COL0_REQ15_INDEX 190U 665 #endif 666 #if defined(CLOCK_IP_HAS_EFLEX_PWM0_CLK) 667 #define CLOCK_IP_PRT3_COL1_REQ46_INDEX 191U 668 #endif 669 #if defined(CLOCK_IP_HAS_EFLEX_PWM1_CLK) 670 #define CLOCK_IP_PRT3_COL1_REQ47_INDEX 192U 671 #endif 672 #if defined(CLOCK_IP_HAS_ETPU_AB_REGISTERS_CLK) 673 #define CLOCK_IP_PRT3_COL1_REQ32_INDEX 193U 674 #endif 675 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM1_CLK) 676 #define CLOCK_IP_PRT3_COL1_REQ36_INDEX 194U 677 #endif 678 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM2_CLK) 679 #define CLOCK_IP_PRT3_COL1_REQ37_INDEX 195U 680 #endif 681 #if defined(CLOCK_IP_HAS_ETPU_RAM_MIRROR_CLK) 682 #define CLOCK_IP_PRT3_COL1_REQ35_INDEX 196U 683 #endif 684 #if defined(CLOCK_IP_HAS_ETPU_RAM_SDM_CLK) 685 #define CLOCK_IP_PRT3_COL1_REQ34_INDEX 197U 686 #endif 687 #if defined(CLOCK_IP_HAS_IGF0_CLK) 688 #define CLOCK_IP_PRT3_COL1_REQ44_INDEX 198U 689 #endif 690 #if defined(CLOCK_IP_HAS_LPUART_MSC_CLK) 691 #define CLOCK_IP_PRT2_COL2_REQ65_INDEX 199U 692 #endif 693 #if defined(CLOCK_IP_HAS_SDADC0_CLK) 694 #define CLOCK_IP_PRT3_COL1_REQ61_INDEX 200U 695 #endif 696 #if defined(CLOCK_IP_HAS_SDADC1_CLK) 697 #define CLOCK_IP_PRT3_COL1_REQ62_INDEX 201U 698 #endif 699 #if defined(CLOCK_IP_HAS_SDADC2_CLK) 700 #define CLOCK_IP_PRT3_COL1_REQ63_INDEX 202U 701 #endif 702 #if defined(CLOCK_IP_HAS_SDADC3_CLK) 703 #define CLOCK_IP_PRT3_COL2_REQ64_INDEX 203U 704 #endif 705 #if defined(CLOCK_IP_HAS_TRGMUX1_CLK) 706 #define CLOCK_IP_PRT3_COL1_REQ48_INDEX 204U 707 #endif 708 #if defined(CLOCK_IP_HAS_PIT3_CLK) 709 #define CLOCK_IP_PRT1_COL2_REQ64_INDEX 205U 710 #endif 711 #if defined(CLOCK_IP_HAS_AES_ACCEL_CLK) 712 #define CLOCK_IP_PRT1_COL3_REQ112_INDEX 206U 713 #endif 714 #if defined(CLOCK_IP_HAS_AES_APP0_CLK) 715 #define CLOCK_IP_PRT1_COL3_REQ113_INDEX 207U 716 #endif 717 #if defined(CLOCK_IP_HAS_AES_APP1_CLK) 718 #define CLOCK_IP_PRT1_COL3_REQ114_INDEX 208U 719 #endif 720 #if defined(CLOCK_IP_HAS_AES_APP2_CLK) 721 #define CLOCK_IP_PRT1_COL3_REQ115_INDEX 209U 722 #endif 723 #if defined(CLOCK_IP_HAS_AES_APP3_CLK) 724 #define CLOCK_IP_PRT2_COL2_REQ72_INDEX 210U 725 #endif 726 #if defined(CLOCK_IP_HAS_AES_APP4_CLK) 727 #define CLOCK_IP_PRT2_COL2_REQ73_INDEX 211U 728 #endif 729 #if defined(CLOCK_IP_HAS_AES_APP5_CLK) 730 #define CLOCK_IP_PRT2_COL2_REQ74_INDEX 212U 731 #endif 732 #if defined(CLOCK_IP_HAS_AES_APP6_CLK) 733 #define CLOCK_IP_PRT2_COL2_REQ75_INDEX 213U 734 #endif 735 #if defined(CLOCK_IP_HAS_AES_APP7_CLK) 736 #define CLOCK_IP_PRT2_COL2_REQ76_INDEX 214U 737 #endif 738 #if defined(CLOCK_IP_HAS_MU3A_CLK) 739 #define CLOCK_IP_PRT0_COL1_REQ49_INDEX 215U 740 #endif 741 #if defined(CLOCK_IP_HAS_MU3B_CLK) 742 #define CLOCK_IP_PRT0_COL1_REQ50_INDEX 216U 743 #endif 744 #if defined(CLOCK_IP_HAS_MU4A_CLK) 745 #define CLOCK_IP_PRT0_COL1_REQ51_INDEX 217U 746 #endif 747 #if defined(CLOCK_IP_HAS_MU4B_CLK) 748 #define CLOCK_IP_PRT0_COL1_REQ52_INDEX 218U 749 #endif 750 751 752 753 #define CLOCK_IP_FXOSC_INSTANCE 0U 754 #if defined(CLOCK_IP_HAS_SXOSC_CLK) 755 #define CLOCK_IP_SXOSC_INSTANCE 1U 756 #endif 757 758 #define CLOCK_IP_PLL_INSTANCE 0U 759 #if defined(CLOCK_IP_HAS_PLLAUX_CLK) 760 #define CLOCK_IP_PLLAUX_INSTANCE 1U 761 #endif 762 763 764 #define CLOCK_IP_CGM_0_INSTANCE 0U 765 766 #define CLOCK_IP_CMU_0_INSTANCE 0U 767 #define CLOCK_IP_CMU_3_INSTANCE 3U 768 #define CLOCK_IP_CMU_4_INSTANCE 4U 769 #define CLOCK_IP_CMU_5_INSTANCE 5U 770 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 771 #define CLOCK_IP_CMU_6_INSTANCE 6U 772 #endif 773 774 #define CLOCK_IP_DIV_0_INDEX 0U 775 #define CLOCK_IP_DIV_1_INDEX 1U 776 #define CLOCK_IP_DIV_2_INDEX 2U 777 #define CLOCK_IP_DIV_3_INDEX 3U 778 #define CLOCK_IP_DIV_4_INDEX 4U 779 #if defined(CLOCK_IP_HAS_LBIST_CLK) 780 #define CLOCK_IP_DIV_5_INDEX 5U 781 #endif 782 #if defined(CLOCK_IP_HAS_QSPI_MEM_CLK) 783 #define CLOCK_IP_DIV_6_INDEX 6U 784 #endif 785 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 786 #define CLOCK_IP_DIV_7_INDEX 7U 787 #endif 788 789 #define CLOCK_IP_PCFS_7_INDEX 7U 790 791 #define CLOCK_IP_PARTITION_0_INDEX 0U 792 #define CLOCK_IP_PARTITION_1_INDEX 1U 793 #if defined(CLOCK_IP_HAS_QSPI0_RAM_CLK) 794 #define CLOCK_IP_PARTITION_2_INDEX 2U 795 #endif 796 #if defined(CLOCK_IP_HAS_SWG1_CLK) 797 #define CLOCK_IP_PARTITION_3_INDEX 3U 798 #endif 799 800 #define CLOCK_IP_COLLECTION_0_INDEX 0U 801 #define CLOCK_IP_COLLECTION_1_INDEX 1U 802 #define CLOCK_IP_COLLECTION_2_INDEX 2U 803 #define CLOCK_IP_COLLECTION_3_INDEX 3U 804 805 #define CLOCK_IP_SEL_0_INDEX 0U 806 #define CLOCK_IP_SEL_1_INDEX 1U 807 #if defined(CLOCK_IP_HAS_STMB_CLK) 808 #define CLOCK_IP_SEL_2_INDEX 2U 809 #endif 810 #define CLOCK_IP_SEL_3_INDEX 3U 811 #define CLOCK_IP_SEL_4_INDEX 4U 812 #define CLOCK_IP_SEL_5_INDEX 5U 813 #define CLOCK_IP_SEL_6_INDEX 6U 814 #if defined(CLOCK_IP_HAS_EMAC_RX_CLK) || defined(CLOCK_IP_HAS_GMAC0_RX_CLK) 815 #define CLOCK_IP_SEL_7_INDEX 7U 816 #endif 817 #if defined(CLOCK_IP_HAS_EMAC_TX_CLK) || defined(CLOCK_IP_HAS_GMAC0_TX_CLK) 818 #define CLOCK_IP_SEL_8_INDEX 8U 819 #endif 820 #if defined(CLOCK_IP_HAS_EMAC_TS_CLK) || defined(CLOCK_IP_HAS_GMAC_TS_CLK) 821 #define CLOCK_IP_SEL_9_INDEX 9U 822 #endif 823 #if defined(CLOCK_IP_HAS_QSPI_SFCK_CLK) 824 #define CLOCK_IP_SEL_10_INDEX 10U 825 #endif 826 #define CLOCK_IP_SEL_11_INDEX 11U 827 #if defined(CLOCK_IP_HAS_EMAC_TX_RMII_CLK) || defined(CLOCK_IP_HAS_GMAC0_TX_RMII_CLK) 828 #define CLOCK_IP_SEL_12_INDEX 12U 829 #endif 830 #if defined(CLOCK_IP_HAS_STMC_CLK) 831 #define CLOCK_IP_SEL_13_INDEX 13U 832 #endif 833 #if defined(CLOCK_IP_HAS_USDHC_CLK) 834 #define CLOCK_IP_SEL_14_INDEX 14U 835 #endif 836 #if defined(CLOCK_IP_HAS_LFAST_REF_CLK) || defined(CLOCK_IP_HAS_GMAC1_RX_CLK) 837 #define CLOCK_IP_SEL_15_INDEX 15U 838 #endif 839 #if defined(CLOCK_IP_HAS_SWG_CLK) || defined(CLOCK_IP_HAS_GMAC1_TX_CLK) 840 #define CLOCK_IP_SEL_16_INDEX 16U 841 #endif 842 #if defined(CLOCK_IP_HAS_GMAC1_RMII_CLK) 843 #define CLOCK_IP_SEL_17_INDEX 17U 844 #endif 845 #if defined(CLOCK_IP_HAS_STMD_CLK) 846 #define CLOCK_IP_SEL_18_INDEX 18U 847 #endif 848 #if defined(CLOCK_IP_HAS_AES_CLK) 849 #define CLOCK_IP_SEL_19_INDEX 19U 850 #endif 851 852 #define PRTN0_COFB0_STAT_ADDRESS (uint32)(IP_MC_ME_BASE + 0x110U) 853 #define PRTN0_COFB0_CLKEN_ADDRESS (uint32)(IP_MC_ME_BASE + 0x130U) 854 855 #define CLOCK_IP_PLL_DIVIDER_COUNT 2U 856 #define CLOCK_IP_PLLAUX_DIVIDER_COUNT 3U 857 /*================================================================================================== 858 * LOCAL CONSTANTS 859 ==================================================================================================*/ 860 861 862 /*================================================================================================== 863 * LOCAL VARIABLES 864 ==================================================================================================*/ 865 866 867 /*================================================================================================== 868 * GLOBAL CONSTANTS 869 ==================================================================================================*/ 870 871 /* Clock start constant section data */ 872 #define MCU_START_SEC_CONST_8 873 #include "Mcu_MemMap.h" 874 875 const uint8 Clock_Ip_au8DividerCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 876 CLOCK_IP_NO_CALLBACK, /* No callback */ 877 CLOCK_IP_CGM_X_DE_DIV_STAT_WITHOUT_PHASE, /* CLOCK_IP_SWMUX_DIV */ 878 CLOCK_IP_CGM_X_DE_DIV_STAT_WITHOUT_PHASE, /* CLOCK_IP_HWMUX_DIV */ 879 CLOCK_IP_PLL_PLLDV_ODIV2_OUTPUT, /* CLOCK_IP_PLL_POSTDIV */ 880 CLOCK_IP_PLL_PLL0DIV_DE_DIV_OUTPUT, /* CLOCK_IP_PCFS_PLL_OUT */ 881 CLOCK_IP_PLL_PLL0DIV_DE_DIV_OUTPUT, /* CLOCK_IP_PLL_OUT */ 882 CLOCK_IP_CGM_X_DE_DIV_STAT_WITHOUT_PHASE, /* CLOCK_IP_DIV_TRIGGER_CMU */ 883 CLOCK_IP_CGM_X_DE_DIV_STAT_WITHOUT_PHASE, /* CLOCK_IP_DIV_TRIGGER */ 884 CLOCK_IP_CGM_X_DE_DIV_STAT_WITHOUT_PHASE, /* CLOCK_IP_HWMUX_DIV_GATE */ 885 }; 886 const uint8 Clock_Ip_au8DividerTriggerCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 887 CLOCK_IP_NO_CALLBACK, /* No callback */ 888 CLOCK_IP_NO_CALLBACK, /* No callback */ 889 CLOCK_IP_NO_CALLBACK, /* No callback */ 890 CLOCK_IP_NO_CALLBACK, /* No callback */ 891 CLOCK_IP_NO_CALLBACK, /* No callback */ 892 CLOCK_IP_NO_CALLBACK, /* No callback */ 893 CLOCK_IP_CGM_X_DIV_TRIG_CTRL_TCTL_HHEN_UPD_STAT, /* CLOCK_IP_DIV_TRIGGER_CMU */ 894 CLOCK_IP_CGM_X_DIV_TRIG_CTRL_TCTL_HHEN_UPD_STAT, /* CLOCK_IP_DIV_TRIGGER */ 895 CLOCK_IP_NO_CALLBACK, /* No callback */ 896 }; 897 const uint8 Clock_Ip_au8XoscCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 898 CLOCK_IP_NO_CALLBACK, /* No callback */ 899 CLOCK_IP_FXOSC_OSCON_BYP_EOCV_GM_SEL, /* CLOCK_IP_FAST_XOSC_CMU */ 900 #if defined(CLOCK_IP_SXOSC_OSCON_EOCV) 901 CLOCK_IP_SXOSC_OSCON_EOCV, /* CLOCK_IP_SLOW_XOSC */ 902 #else 903 CLOCK_IP_NO_CALLBACK, /* No callback */ 904 #endif 905 CLOCK_IP_NO_CALLBACK, /* No callback */ 906 CLOCK_IP_NO_CALLBACK, /* No callback */ 907 CLOCK_IP_NO_CALLBACK, /* No callback */ 908 CLOCK_IP_NO_CALLBACK, /* No callback */ 909 CLOCK_IP_NO_CALLBACK, /* No callback */ 910 CLOCK_IP_NO_CALLBACK, /* No callback */ 911 }; 912 const uint8 Clock_Ip_au8IrcoscCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 913 CLOCK_IP_NO_CALLBACK, /* No callback */ 914 #if defined(CLOCK_IP_FIRC_DIV_SEL_HSEb_CONFIG_REG_GPR) 915 CLOCK_IP_FIRC_DIV_SEL_HSEb_CONFIG_REG_GPR, /* CLOCK_IP_FIRCOSC */ 916 #else 917 CLOCK_IP_NO_CALLBACK, /* No callback */ 918 #endif 919 CLOCK_IP_FIRC_STDBY_ENABLE, /* CLOCK_IP_FIRCOSC_STDBY */ 920 CLOCK_IP_SIRC_STDBY_ENABLE, /* CLOCK_IP_SIRCOSC_STDBY */ 921 CLOCK_IP_NO_CALLBACK, /* No callback */ 922 CLOCK_IP_NO_CALLBACK, /* No callback */ 923 CLOCK_IP_NO_CALLBACK, /* No callback */ 924 CLOCK_IP_NO_CALLBACK, /* No callback */ 925 CLOCK_IP_NO_CALLBACK, /* No callback */ 926 }; 927 const uint8 Clock_Ip_au8GateCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 928 CLOCK_IP_NO_CALLBACK, /* No callback */ 929 CLOCK_IP_MC_ME_PARTITION_COFB_ENABLE_REQUEST, /* CLOCK_IP_GATE */ 930 CLOCK_IP_NO_CALLBACK, /* No callback */ 931 CLOCK_IP_NO_CALLBACK, /* No callback */ 932 CLOCK_IP_NO_CALLBACK, /* No callback */ 933 CLOCK_IP_NO_CALLBACK, /* No callback */ 934 CLOCK_IP_NO_CALLBACK, /* No callback */ 935 CLOCK_IP_NO_CALLBACK, /* No callback */ 936 CLOCK_IP_MC_ME_PARTITION_COFB_ENABLE_REQUEST, /* CLOCK_IP_HWMUX_DIV_GATE */ 937 }; 938 const uint8 Clock_Ip_au8FractionalDividerCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 939 CLOCK_IP_NO_CALLBACK, /* No callback */ 940 CLOCK_IP_NO_CALLBACK, /* No callback */ 941 CLOCK_IP_NO_CALLBACK, /* No callback */ 942 CLOCK_IP_NO_CALLBACK, /* No callback */ 943 CLOCK_IP_NO_CALLBACK, /* No callback */ 944 CLOCK_IP_NO_CALLBACK, /* No callback */ 945 CLOCK_IP_NO_CALLBACK, /* No callback */ 946 CLOCK_IP_NO_CALLBACK, /* No callback */ 947 CLOCK_IP_NO_CALLBACK, /* No callback */ 948 }; 949 const uint8 Clock_Ip_au8PllCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 950 CLOCK_IP_NO_CALLBACK, /* No callback */ 951 CLOCK_IP_PLL_RDIV_MFI_MFN_ODIV2_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE,/* CLOCK_IP_PLL_MOD */ 952 #if defined(CLOCK_IP_PLL_RDIV_MFI_MFN_ODIV2_SDMEN) 953 CLOCK_IP_PLL_RDIV_MFI_MFN_ODIV2_SDMEN, /* CLOCK_IP_PLL */ 954 #else 955 CLOCK_IP_NO_CALLBACK, /* No callback */ 956 #endif 957 CLOCK_IP_NO_CALLBACK, /* No callback */ 958 CLOCK_IP_NO_CALLBACK, /* No callback */ 959 CLOCK_IP_NO_CALLBACK, /* No callback */ 960 CLOCK_IP_NO_CALLBACK, /* No callback */ 961 CLOCK_IP_NO_CALLBACK, /* No callback */ 962 CLOCK_IP_NO_CALLBACK, /* No callback */ 963 }; 964 const uint8 Clock_Ip_au8SelectorCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 965 CLOCK_IP_NO_CALLBACK, /* No callback */ 966 CLOCK_IP_CGM_X_CSC_CSS_CS_GRIP, /* CLOCK_IP_SWMUX_DIV */ 967 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_SWIP, /* CLOCK_IP_HWMUX_DIV */ 968 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_RAMPDOWN_RAMPUP_SWIP, /* CLOCK_IP_HWMUX_PCFS */ 969 CLOCK_IP_RTC_RTCC_CLKSELECT, /* CLOCK_IP_RTC_SEL */ 970 CLOCK_IP_NO_CALLBACK, /* No callback */ 971 CLOCK_IP_NO_CALLBACK, /* No callback */ 972 CLOCK_IP_NO_CALLBACK, /* No callback */ 973 CLOCK_IP_CGM_X_CSC_CSS_CLK_SW_SWIP, /* CLOCK_IP_HWMUX_DIV_GATE */ 974 }; 975 const uint8 Clock_Ip_au8PcfsCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 976 CLOCK_IP_NO_CALLBACK, /* No callback */ 977 CLOCK_IP_NO_CALLBACK, /* No callback */ 978 CLOCK_IP_NO_CALLBACK, /* No callback */ 979 CLOCK_IP_NO_CALLBACK, /* No callback */ 980 CLOCK_IP_CGM_X_PCFS_SDUR_DIVC_DIVE_DIVS, /* CLOCK_IP_PCFS_PLL_OUT */ 981 CLOCK_IP_NO_CALLBACK, /* No callback */ 982 CLOCK_IP_NO_CALLBACK, /* No callback */ 983 CLOCK_IP_NO_CALLBACK, /* No callback */ 984 CLOCK_IP_NO_CALLBACK, /* No callback */ 985 }; 986 const uint8 Clock_Ip_au8CmuCallbackIndex[CLOCK_IP_ALL_CALLBACKS_COUNT] = { 987 CLOCK_IP_NO_CALLBACK, /* No callback */ 988 CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* CLOCK_IP_FAST_XOSC_CMU */ 989 CLOCK_IP_NO_CALLBACK, /* No callback */ 990 CLOCK_IP_NO_CALLBACK, /* No callback */ 991 CLOCK_IP_NO_CALLBACK, /* No callback */ 992 CLOCK_IP_NO_CALLBACK, /* No callback */ 993 CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* CLOCK_IP_DIV_TRIGGER_CMU */ 994 CLOCK_IP_NO_CALLBACK, /* No callback */ 995 CLOCK_IP_NO_CALLBACK, /* No callback */ 996 }; 997 998 999 1000 1001 /* Clock features mapping */ 1002 const uint8 Clock_Ip_au8ClockFeatures[CLOCK_IP_NAMES_NO][CLOCK_IP_FEATURES_NO] = 1003 /* 1004 *************************************************************************************************************************************************************************************************************************************************************** 1005 *********************************** *********************** *********************** E *************************** * **************** ***************** ********************** ***************** ************* 1006 *********************************** I *********************** C *********************** X *************************** * S **************** D ***************** ********************** ***************** ************* 1007 *********************************** N *********************** A *********************** T *************************** P * E **************** I ***************** G ********************** P ***************** ************* 1008 *********************************** S *********************** L *********************** E *************************** O * L **************** V ***************** A ********************** C ***************** C ************* 1009 *********************************** T *********************** L *********************** N *************************** W * E **************** I ***************** T ********************** F ***************** M ************* 1010 *********************************** A *********************** B *********************** S *************************** E * C **************** D ***************** E ********************** S ***************** U ************* 1011 *********************************** N *********************** A *********************** I *************************** R * T **************** E ***************** ********************** ***************** ************* 1012 *********************************** C *********************** C *********************** O *************************** * O **************** R ***************** ********************** ***************** ************* 1013 *********************************** E *********************** K *********************** N *************************** * R **************** ***************** ********************** ***************** ************* 1014 *********************************** *********************** *********************** *************************** * **************** ***************** ********************** ***************** ************* 1015 ******************************************************************************************************************************************************************************************************************************************************************/ 1016 { 1017 /* CLOCK_IS_OFF clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* CLOCK_IS_OFF clock */ 1018 /* FIRC_CLK clock */ {0U, CLOCK_IP_FIRCOSC, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* FIRC_CLK clock */ 1019 /* FIRC_STANDBY_CLK clock */ {0U, CLOCK_IP_FIRCOSC_STDBY, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* FIRC_STANDBY_CLK clock */ 1020 /* SIRC_CLK clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* SIRC_CLK clock */ 1021 /* SIRC_STANDBY_CLK clock */ {0U, CLOCK_IP_SIRCOSC_STDBY, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* SIRC_STANDBY_CLK clock */ 1022 /* FXOSC_CLK clock */ {CLOCK_IP_FXOSC_INSTANCE, CLOCK_IP_FAST_XOSC_CMU, 0U, 0U, 0U, 0U, 0U, 0U, CLOCK_IP_CMU_0_INSTANCE}, /* FXOSC_CLK clock */ 1023 #if defined(CLOCK_IP_HAS_SXOSC_CLK) 1024 /* SXOSC_CLK clock */ {CLOCK_IP_SXOSC_INSTANCE, CLOCK_IP_SLOW_XOSC, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* SXOSC_CLK clock */ 1025 #endif 1026 /* PLL_CLK clock */ {CLOCK_IP_PLL_INSTANCE, CLOCK_IP_PLL_MOD, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* PLL_CLK clock */ 1027 #if defined(CLOCK_IP_HAS_PLLAUX_CLK) 1028 /* PLLAUX_CLK clock */ {CLOCK_IP_PLLAUX_INSTANCE, CLOCK_IP_PLL, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* PLLAUX_CLK clock */ 1029 #endif 1030 /* PLL_POSTDIV_CLK clock */ {CLOCK_IP_PLL_INSTANCE, CLOCK_IP_PLL_POSTDIV, 0U, 0U, 0U, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* PLL_POSTDIV_CLK clock */ 1031 #if defined(CLOCK_IP_HAS_PLLAUX_POSTDIV_CLK) 1032 /* PLLAUX_POSTDIV_CLK clock */ {CLOCK_IP_PLLAUX_INSTANCE, CLOCK_IP_PLL_POSTDIV, 0U, 0U, 0U, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* PLLAUX_POSTDIV_CLK clock */ 1033 #endif 1034 /* PLL_PHI0_CLK clock */ {CLOCK_IP_PLL_INSTANCE, CLOCK_IP_PCFS_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_0_INDEX, 0U, CLOCK_IP_PCFS_7_INDEX, 0U}, /* PLL_PHI0_CLK clock */ 1035 /* PLL_PHI1_CLK clock */ {CLOCK_IP_PLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* PLL_PHI1_CLK clock */ 1036 #if defined(CLOCK_IP_HAS_PLLAUX_PHI0_CLK) 1037 /* PLLAUX_PHI0_CLK clock */ {CLOCK_IP_PLLAUX_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* PLLAUX_PHI0_CLK clock */ 1038 #endif 1039 #if defined(CLOCK_IP_HAS_PLLAUX_PHI1_CLK) 1040 /* PLLAUX_PHI1_CLK clock */ {CLOCK_IP_PLLAUX_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_1_INDEX, 0U, 0U, 0U}, /* PLLAUX_PHI1_CLK clock */ 1041 #endif 1042 #if defined(CLOCK_IP_HAS_PLLAUX_PHI2_CLK) 1043 /* PLLAUX_PHI2_CLK clock */ {CLOCK_IP_PLLAUX_INSTANCE, CLOCK_IP_PLL_OUT, 0U, 0U, 0U, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* PLLAUX_PHI2_CLK clock */ 1044 #endif 1045 #if defined(CLOCK_IP_HAS_EMAC_MII_RX_CLK) 1046 /* EMAC_MII_RX_CLK clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* EMAC_MII_RX_CLK clock */ 1047 #endif 1048 #if defined(CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK) 1049 /* EMAC_MII_RMII_TX_CLK clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* EMAC_MII_RMII_TX_CLK clock */ 1050 #endif 1051 #if defined(CLOCK_IP_HAS_GMAC0_MII_RX_CLK) 1052 /* GMAC0_MII_RX_CLK clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* GMAC0_MII_RX_CLK clock */ 1053 #endif 1054 #if defined(CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK) 1055 /* GMAC0_MII_RMII_TX_CLK clock */{0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* GMAC0_MII_RMII_TX_CLK clock */ 1056 #endif 1057 #if defined(CLOCK_IP_HAS_LFAST_REF_EXT_CLK) 1058 /* LFAST_EXT_REF_CLK clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* LFAST_EXT_REF_CLK clock */ 1059 #endif 1060 #if defined(CLOCK_IP_HAS_SWG_PAD_CLK) 1061 /* SWG_PAD_CLK clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* SWG_PAD_CLK clock */ 1062 #endif 1063 /* SCS_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_PCFS, CLOCK_IP_SCS_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* SCS_CLK clock */ 1064 /* CORE_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_DIV_TRIGGER_CMU, CLOCK_IP_CORE_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, CLOCK_IP_CMU_3_INSTANCE}, /* CORE_CLK clock */ 1065 /* AIPS_PLAT_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_DIV_TRIGGER_CMU, CLOCK_IP_AIPS_PLAT_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, CLOCK_IP_DIV_1_INDEX, 0U, 0U, CLOCK_IP_CMU_4_INSTANCE}, /* AIPS_PLAT_CLK clock */ 1066 /* AIPS_SLOW_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_DIV_TRIGGER, CLOCK_IP_AIPS_SLOW_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, CLOCK_IP_DIV_2_INDEX, 0U, 0U, 0U}, /* AIPS_SLOW_CLK clock */ 1067 /* HSE_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_DIV_TRIGGER_CMU, CLOCK_IP_HSE_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, CLOCK_IP_DIV_3_INDEX, 0U, 0U, CLOCK_IP_CMU_5_INSTANCE}, /* HSE_CLK clock */ 1068 /* DCM_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_DIV_TRIGGER, CLOCK_IP_DCM_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, CLOCK_IP_DIV_4_INDEX, 0U, 0U, 0U}, /* DCM_CLK clock */ 1069 #if defined(CLOCK_IP_HAS_LBIST_CLK) 1070 /* LBIST_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_DIV_TRIGGER, CLOCK_IP_LBIST_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, CLOCK_IP_DIV_5_INDEX, 0U, 0U, 0U}, /* LBIST_CLK clock */ 1071 #endif 1072 #if defined(CLOCK_IP_HAS_QSPI_MEM_CLK) 1073 /* QSPI_MEM_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_DIV_TRIGGER, CLOCK_IP_QSPI_MEM_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, CLOCK_IP_DIV_6_INDEX, 0U, 0U, 0U}, /* QSPI_MEM_CLK clock */ 1074 #endif 1075 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 1076 /* CM7_CORE_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_DIV_TRIGGER_CMU, CLOCK_IP_CM7_CORE_EXTENSION, 0U, CLOCK_IP_SEL_0_INDEX, CLOCK_IP_DIV_7_INDEX, 0U, 0U, CLOCK_IP_CMU_6_INSTANCE}, /* CM7_CORE_CLK clock */ 1077 #endif 1078 /* CLKOUT_RUN_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_SWMUX_DIV, CLOCK_IP_CLKOUT_RUN_EXTENSION, 0U, CLOCK_IP_SEL_6_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* CLKOUT_RUN_CLK clock */ 1079 /* THE_LAST_PRODUCER_CLK */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* THE_LAST_PRODUCER_CLK */ 1080 /* ADC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ40_INDEX,0U, 0U}, /* ADC0_CLK clock */ 1081 /* ADC1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ41_INDEX,0U, 0U}, /* ADC1_CLK clock */ 1082 #if defined(CLOCK_IP_HAS_ADC2_CLK) 1083 /* ADC2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ42_INDEX,0U, 0U}, /* ADC2_CLK clock */ 1084 #endif 1085 #if defined(CLOCK_IP_HAS_ADC3_CLK) 1086 /* ADC3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ43_INDEX,0U, 0U}, /* ADC3_CLK clock */ 1087 #endif 1088 #if defined(CLOCK_IP_HAS_ADC4_CLK) 1089 /* ADC4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ52_INDEX,0U, 0U}, /* ADC4_CLK clock */ 1090 #endif 1091 #if defined(CLOCK_IP_HAS_ADC5_CLK) 1092 /* ADC5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ53_INDEX,0U, 0U}, /* ADC5_CLK clock */ 1093 #endif 1094 #if defined(CLOCK_IP_HAS_ADC6_CLK) 1095 /* ADC6_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ54_INDEX,0U, 0U}, /* ADC6_CLK clock */ 1096 #endif 1097 #if defined(CLOCK_IP_HAS_ADCBIST_CLK) 1098 /* ADCBIST_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL2_REQ65_INDEX,0U, 0U}, /* ADCBIST_CLK clock */ 1099 #endif 1100 #if defined(CLOCK_IP_HAS_AES_ACCEL_CLK) 1101 /* AES_ACCEL_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL3_REQ112_INDEX,0U, 0U}, /* AES_ACCEL_CLK clock */ 1102 #endif 1103 #if defined(CLOCK_IP_HAS_AES_APP0_CLK) 1104 /* AES_APP0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL3_REQ113_INDEX,0U, 0U}, /* AES_APP0_CLK clock */ 1105 #endif 1106 #if defined(CLOCK_IP_HAS_AES_APP1_CLK) 1107 /* AES_APP1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL3_REQ114_INDEX,0U, 0U}, /* AES_APP1_CLK clock */ 1108 #endif 1109 #if defined(CLOCK_IP_HAS_AES_APP2_CLK) 1110 /* AES_APP2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL3_REQ115_INDEX,0U, 0U}, /* AES_APP2_CLK clock */ 1111 #endif 1112 #if defined(CLOCK_IP_HAS_AES_APP3_CLK) 1113 /* AES_APP3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL2_REQ72_INDEX,0U, 0U}, /* AES_APP3_CLK clock */ 1114 #endif 1115 #if defined(CLOCK_IP_HAS_AES_APP4_CLK) 1116 /* AES_APP4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL2_REQ73_INDEX,0U, 0U}, /* AES_APP4_CLK clock */ 1117 #endif 1118 #if defined(CLOCK_IP_HAS_AES_APP5_CLK) 1119 /* AES_APP5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL2_REQ74_INDEX,0U, 0U}, /* AES_APP5_CLK clock */ 1120 #endif 1121 #if defined(CLOCK_IP_HAS_AES_APP6_CLK) 1122 /* AES_APP6_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL2_REQ75_INDEX,0U, 0U}, /* AES_APP6_CLK clock */ 1123 #endif 1124 #if defined(CLOCK_IP_HAS_AES_APP7_CLK) 1125 /* AES_APP7_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL2_REQ76_INDEX,0U, 0U}, /* AES_APP7_CLK clock */ 1126 #endif 1127 #if defined(CLOCK_IP_HAS_AES_CLK) 1128 /* AES_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_AES_EXTENSION, 0U, CLOCK_IP_SEL_19_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* AES_CLK clock */ 1129 #endif 1130 #if defined(CLOCK_IP_HAS_AXBS_CLK) 1131 /* AXBS_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ0_INDEX,0U, 0U}, /* AXBS_CLK clock */ 1132 #endif 1133 #if defined(CLOCK_IP_HAS_AXBS0_CLK) 1134 /* AXBS0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ1_INDEX,0U, 0U}, /* AXBS0_CLK clock */ 1135 #endif 1136 #if defined(CLOCK_IP_HAS_AXBS1_CLK) 1137 /* AXBS1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ2_INDEX,0U, 0U}, /* AXBS1_CLK clock */ 1138 #endif 1139 /* BCTU0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ33_INDEX,0U, 0U}, /* BCTU0_CLK clock */ 1140 #if defined(CLOCK_IP_HAS_BCTU1_CLK) 1141 /* BCTU1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ49_INDEX,0U, 0U}, /* BCTU1_CLK clock */ 1142 #endif 1143 /* CLKOUT_STANDBY_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_SWMUX_DIV, CLOCK_IP_CLKOUT_STANDBY_EXTENSION,0U, CLOCK_IP_SEL_5_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* CLKOUT_STANDBY_CLK clock */ 1144 /* CMP0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ92_INDEX,0U, 0U}, /* CMP0_CLK clock */ 1145 #if defined(CLOCK_IP_HAS_CMP1_CLK) 1146 /* CMP1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ93_INDEX,0U, 0U}, /* CMP1_CLK clock */ 1147 #endif 1148 #if defined(CLOCK_IP_HAS_CMP2_CLK) 1149 /* CMP2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ58_INDEX,0U, 0U}, /* CMP2_CLK clock */ 1150 #endif 1151 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM0_CLK) 1152 /* COOLFLUX_D_RAM0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ58_INDEX,0U, 0U}, /* COOLFLUX_D_RAM0_CLK clock */ 1153 #endif 1154 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM1_CLK) 1155 /* COOLFLUX_D_RAM1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ59_INDEX,0U, 0U}, /* COOLFLUX_D_RAM1_CLK clock */ 1156 #endif 1157 #if defined(CLOCK_IP_HAS_COOLFLUX_DSP16L_CLK) 1158 /* COOLFLUX_DSP16L_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ55_INDEX,0U, 0U}, /* COOLFLUX_DSP16L_CLK clock */ 1159 #endif 1160 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM0_CLK) 1161 /* COOLFLUX_I_RAM0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ56_INDEX,0U, 0U}, /* COOLFLUX_I_RAM0_CLK clock */ 1162 #endif 1163 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM1_CLK) 1164 /* COOLFLUX_I_RAM1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ57_INDEX,0U, 0U}, /* COOLFLUX_I_RAM1_CLK clock */ 1165 #endif 1166 /* CRC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL3_REQ96_INDEX,0U, 0U}, /* CRC0_CLK clock */ 1167 /* DCM0_CLK clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* DCM0_CLK clock */ 1168 /* DMAMUX0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL1_REQ32_INDEX,0U, 0U}, /* DMAMUX0_CLK clock */ 1169 /* DMAMUX1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL1_REQ33_INDEX,0U, 0U}, /* DMAMUX1_CLK clock */ 1170 #if defined(CLOCK_IP_HAS_DMAMUX2_CLK) 1171 /* DMAMUX2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ40_INDEX,0U, 0U}, /* DMAMUX2_CLK clock */ 1172 #endif 1173 #if defined(CLOCK_IP_HAS_DMAMUX3_CLK) 1174 /* DMAMUX3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ41_INDEX,0U, 0U}, /* DMAMUX3_CLK clock */ 1175 #endif 1176 #if defined(CLOCK_IP_HAS_DSPI_MSC_CLK) 1177 /* DSPI_MSC_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL2_REQ66_INDEX,0U, 0U}, /* DSPI_MSC_CLK clock */ 1178 #endif 1179 /* EDMA0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ3_INDEX,0U, 0U}, /* EDMA0_CLK clock */ 1180 /* EDMA0_TCD0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ4_INDEX,0U, 0U}, /* EDMA0_TCD0_CLK clock */ 1181 /* EDMA0_TCD1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ5_INDEX,0U, 0U}, /* EDMA0_TCD1_CLK clock */ 1182 /* EDMA0_TCD2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ6_INDEX,0U, 0U}, /* EDMA0_TCD2_CLK clock */ 1183 /* EDMA0_TCD3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ7_INDEX,0U, 0U}, /* EDMA0_TCD3_CLK clock */ 1184 /* EDMA0_TCD4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ8_INDEX,0U, 0U}, /* EDMA0_TCD4_CLK clock */ 1185 /* EDMA0_TCD5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ9_INDEX,0U, 0U}, /* EDMA0_TCD5_CLK clock */ 1186 /* EDMA0_TCD6_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ10_INDEX,0U, 0U}, /* EDMA0_TCD6_CLK clock */ 1187 /* EDMA0_TCD7_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ11_INDEX,0U, 0U}, /* EDMA0_TCD7_CLK clock */ 1188 /* EDMA0_TCD8_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ12_INDEX,0U, 0U}, /* EDMA0_TCD8_CLK clock */ 1189 /* EDMA0_TCD9_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ13_INDEX,0U, 0U}, /* EDMA0_TCD9_CLK clock */ 1190 /* EDMA0_TCD10_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ14_INDEX,0U, 0U}, /* EDMA0_TCD10_CLK clock */ 1191 /* EDMA0_TCD11_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ15_INDEX,0U, 0U}, /* EDMA0_TCD11_CLK clock */ 1192 #if defined(CLOCK_IP_HAS_EDMA0_TCD12_CLK) 1193 /* EDMA0_TCD12_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ4_INDEX,0U, 0U}, /* EDMA0_TCD12_CLK clock */ 1194 #endif 1195 #if defined(CLOCK_IP_HAS_EDMA0_TCD13_CLK) 1196 /* EDMA0_TCD13_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ5_INDEX,0U, 0U}, /* EDMA0_TCD13_CLK clock */ 1197 #endif 1198 #if defined(CLOCK_IP_HAS_EDMA0_TCD14_CLK) 1199 /* EDMA0_TCD14_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ6_INDEX,0U, 0U}, /* EDMA0_TCD14_CLK clock */ 1200 #endif 1201 #if defined(CLOCK_IP_HAS_EDMA0_TCD15_CLK) 1202 /* EDMA0_TCD15_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ7_INDEX,0U, 0U}, /* EDMA0_TCD15_CLK clock */ 1203 #endif 1204 #if defined(CLOCK_IP_HAS_EDMA0_TCD16_CLK) 1205 /* EDMA0_TCD16_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ8_INDEX,0U, 0U}, /* EDMA0_TCD16_CLK clock */ 1206 #endif 1207 #if defined(CLOCK_IP_HAS_EDMA0_TCD17_CLK) 1208 /* EDMA0_TCD17_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ9_INDEX,0U, 0U}, /* EDMA0_TCD17_CLK clock */ 1209 #endif 1210 #if defined(CLOCK_IP_HAS_EDMA0_TCD18_CLK) 1211 /* EDMA0_TCD18_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ10_INDEX,0U, 0U}, /* EDMA0_TCD18_CLK clock */ 1212 #endif 1213 #if defined(CLOCK_IP_HAS_EDMA0_TCD19_CLK) 1214 /* EDMA0_TCD19_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ11_INDEX,0U, 0U}, /* EDMA0_TCD19_CLK clock */ 1215 #endif 1216 #if defined(CLOCK_IP_HAS_EDMA0_TCD20_CLK) 1217 /* EDMA0_TCD20_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ12_INDEX,0U, 0U}, /* EDMA0_TCD20_CLK clock */ 1218 #endif 1219 #if defined(CLOCK_IP_HAS_EDMA0_TCD21_CLK) 1220 /* EDMA0_TCD21_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ13_INDEX,0U, 0U}, /* EDMA0_TCD21_CLK clock */ 1221 #endif 1222 #if defined(CLOCK_IP_HAS_EDMA0_TCD22_CLK) 1223 /* EDMA0_TCD22_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ14_INDEX,0U, 0U}, /* EDMA0_TCD22_CLK clock */ 1224 #endif 1225 #if defined(CLOCK_IP_HAS_EDMA0_TCD23_CLK) 1226 /* EDMA0_TCD23_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ15_INDEX,0U, 0U}, /* EDMA0_TCD23_CLK clock */ 1227 #endif 1228 #if defined(CLOCK_IP_HAS_EDMA0_TCD24_CLK) 1229 /* EDMA0_TCD24_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ16_INDEX,0U, 0U}, /* EDMA0_TCD24_CLK clock */ 1230 #endif 1231 #if defined(CLOCK_IP_HAS_EDMA0_TCD25_CLK) 1232 /* EDMA0_TCD25_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ17_INDEX,0U, 0U}, /* EDMA0_TCD25_CLK clock */ 1233 #endif 1234 #if defined(CLOCK_IP_HAS_EDMA0_TCD26_CLK) 1235 /* EDMA0_TCD26_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ18_INDEX,0U, 0U}, /* EDMA0_TCD26_CLK clock */ 1236 #endif 1237 #if defined(CLOCK_IP_HAS_EDMA0_TCD27_CLK) 1238 /* EDMA0_TCD27_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ19_INDEX,0U, 0U}, /* EDMA0_TCD27_CLK clock */ 1239 #endif 1240 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 1241 /* EDMA0_TCD28_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ20_INDEX,0U, 0U}, /* EDMA0_TCD28_CLK clock */ 1242 #endif 1243 #if defined(CLOCK_IP_HAS_EDMA0_TCD29_CLK) 1244 /* EDMA0_TCD29_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ21_INDEX,0U, 0U}, /* EDMA0_TCD29_CLK clock */ 1245 #endif 1246 #if defined(CLOCK_IP_HAS_EDMA0_TCD30_CLK) 1247 /* EDMA0_TCD30_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ22_INDEX,0U, 0U}, /* EDMA0_TCD30_CLK clock */ 1248 #endif 1249 #if defined(CLOCK_IP_HAS_EDMA0_TCD31_CLK) 1250 /* EDMA0_TCD31_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ23_INDEX,0U, 0U}, /* EDMA0_TCD31_CLK clock */ 1251 #endif 1252 #if defined(CLOCK_IP_HAS_EDMA1_CLK) 1253 /* EDMA1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ4_INDEX, 0U, 0U}, /* EDMA1_CLK clock */ 1254 #endif 1255 #if defined(CLOCK_IP_HAS_EDMA1_TCD0_CLK) 1256 /* EDMA1_TCD0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ5_INDEX,0U, 0U}, /* EDMA1_TCD0_CLK clock */ 1257 #endif 1258 #if defined(CLOCK_IP_HAS_EDMA1_TCD1_CLK) 1259 /* EDMA1_TCD1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ6_INDEX,0U, 0U}, /* EDMA1_TCD1_CLK clock */ 1260 #endif 1261 #if defined(CLOCK_IP_HAS_EDMA1_TCD2_CLK) 1262 /* EDMA1_TCD2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ7_INDEX,0U, 0U}, /* EDMA1_TCD2_CLK clock */ 1263 #endif 1264 #if defined(CLOCK_IP_HAS_EDMA1_TCD3_CLK) 1265 /* EDMA1_TCD3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ8_INDEX,0U, 0U}, /* EDMA1_TCD3_CLK clock */ 1266 #endif 1267 #if defined(CLOCK_IP_HAS_EDMA1_TCD4_CLK) 1268 /* EDMA1_TCD4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ9_INDEX,0U, 0U}, /* EDMA1_TCD4_CLK clock */ 1269 #endif 1270 #if defined(CLOCK_IP_HAS_EDMA1_TCD5_CLK) 1271 /* EDMA1_TCD5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ10_INDEX,0U, 0U}, /* EDMA1_TCD5_CLK clock */ 1272 #endif 1273 #if defined(CLOCK_IP_HAS_EDMA1_TCD6_CLK) 1274 /* EDMA1_TCD6_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ11_INDEX,0U, 0U}, /* EDMA1_TCD6_CLK clock */ 1275 #endif 1276 #if defined(CLOCK_IP_HAS_EDMA1_TCD7_CLK) 1277 /* EDMA1_TCD7_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ12_INDEX,0U, 0U}, /* EDMA1_TCD7_CLK clock */ 1278 #endif 1279 #if defined(CLOCK_IP_HAS_EDMA1_TCD8_CLK) 1280 /* EDMA1_TCD8_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ13_INDEX,0U, 0U}, /* EDMA1_TCD8_CLK clock */ 1281 #endif 1282 #if defined(CLOCK_IP_HAS_EDMA1_TCD9_CLK) 1283 /* EDMA1_TCD9_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ14_INDEX,0U, 0U}, /* EDMA1_TCD9_CLK clock */ 1284 #endif 1285 #if defined(CLOCK_IP_HAS_EDMA1_TCD10_CLK) 1286 /* EDMA1_TCD10_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ15_INDEX,0U, 0U}, /* EDMA1_TCD10_CLK clock */ 1287 #endif 1288 #if defined(CLOCK_IP_HAS_EDMA1_TCD11_CLK) 1289 /* EDMA1_TCD11_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ16_INDEX,0U, 0U}, /* EDMA1_TCD11_CLK clock */ 1290 #endif 1291 #if defined(CLOCK_IP_HAS_EDMA1_TCD12_CLK) 1292 /* EDMA1_TCD12_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ17_INDEX,0U, 0U}, /* EDMA1_TCD12_CLK clock */ 1293 #endif 1294 #if defined(CLOCK_IP_HAS_EDMA1_TCD13_CLK) 1295 /* EDMA1_TCD13_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ18_INDEX,0U, 0U}, /* EDMA1_TCD13_CLK clock */ 1296 #endif 1297 #if defined(CLOCK_IP_HAS_EDMA1_TCD14_CLK) 1298 /* EDMA1_TCD14_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ19_INDEX,0U, 0U}, /* EDMA1_TCD14_CLK clock */ 1299 #endif 1300 #if defined(CLOCK_IP_HAS_EDMA1_TCD15_CLK) 1301 /* EDMA1_TCD15_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ20_INDEX,0U, 0U}, /* EDMA1_TCD15_CLK clock */ 1302 #endif 1303 #if defined(CLOCK_IP_HAS_EDMA1_TCD16_CLK) 1304 /* EDMA1_TCD16_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ0_INDEX,0U, 0U}, /* EDMA1_TCD16_CLK clock */ 1305 #endif 1306 #if defined(CLOCK_IP_HAS_EDMA1_TCD17_CLK) 1307 /* EDMA1_TCD17_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ1_INDEX,0U, 0U}, /* EDMA1_TCD17_CLK clock */ 1308 #endif 1309 #if defined(CLOCK_IP_HAS_EDMA1_TCD18_CLK) 1310 /* EDMA1_TCD18_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ2_INDEX,0U, 0U}, /* EDMA1_TCD18_CLK clock */ 1311 #endif 1312 #if defined(CLOCK_IP_HAS_EDMA1_TCD19_CLK) 1313 /* EDMA1_TCD19_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ3_INDEX,0U, 0U}, /* EDMA1_TCD19_CLK clock */ 1314 #endif 1315 #if defined(CLOCK_IP_HAS_EDMA1_TCD20_CLK) 1316 /* EDMA1_TCD20_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ4_INDEX,0U, 0U}, /* EDMA1_TCD20_CLK clock */ 1317 #endif 1318 #if defined(CLOCK_IP_HAS_EDMA1_TCD21_CLK) 1319 /* EDMA1_TCD21_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ5_INDEX,0U, 0U}, /* EDMA1_TCD21_CLK clock */ 1320 #endif 1321 #if defined(CLOCK_IP_HAS_EDMA1_TCD22_CLK) 1322 /* EDMA1_TCD22_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ6_INDEX,0U, 0U}, /* EDMA1_TCD22_CLK clock */ 1323 #endif 1324 #if defined(CLOCK_IP_HAS_EDMA1_TCD23_CLK) 1325 /* EDMA1_TCD23_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ7_INDEX,0U, 0U}, /* EDMA1_TCD23_CLK clock */ 1326 #endif 1327 #if defined(CLOCK_IP_HAS_EDMA1_TCD24_CLK) 1328 /* EDMA1_TCD24_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ8_INDEX,0U, 0U}, /* EDMA1_TCD24_CLK clock */ 1329 #endif 1330 #if defined(CLOCK_IP_HAS_EDMA1_TCD25_CLK) 1331 /* EDMA1_TCD25_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ9_INDEX,0U, 0U}, /* EDMA1_TCD25_CLK clock */ 1332 #endif 1333 #if defined(CLOCK_IP_HAS_EDMA1_TCD26_CLK) 1334 /* EDMA1_TCD26_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ10_INDEX,0U, 0U}, /* EDMA1_TCD26_CLK clock */ 1335 #endif 1336 #if defined(CLOCK_IP_HAS_EDMA1_TCD27_CLK) 1337 /* EDMA1_TCD27_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ11_INDEX,0U, 0U}, /* EDMA1_TCD27_CLK clock */ 1338 #endif 1339 #if defined(CLOCK_IP_HAS_EDMA1_TCD28_CLK) 1340 /* EDMA1_TCD28_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ12_INDEX,0U, 0U}, /* EDMA1_TCD28_CLK clock */ 1341 #endif 1342 #if defined(CLOCK_IP_HAS_EDMA1_TCD29_CLK) 1343 /* EDMA1_TCD29_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ13_INDEX,0U, 0U}, /* EDMA1_TCD29_CLK clock */ 1344 #endif 1345 #if defined(CLOCK_IP_HAS_EDMA1_TCD30_CLK) 1346 /* EDMA1_TCD30_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ14_INDEX,0U, 0U}, /* EDMA1_TCD30_CLK clock */ 1347 #endif 1348 #if defined(CLOCK_IP_HAS_EDMA1_TCD31_CLK) 1349 /* EDMA1_TCD31_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL0_REQ15_INDEX,0U, 0U}, /* EDMA1_TCD31_CLK clock */ 1350 #endif 1351 #if defined(CLOCK_IP_HAS_EFLEX_PWM0_CLK) 1352 /* EFLEX_PWM0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ46_INDEX,0U, 0U}, /* EFLEX_PWM0_CLK clock */ 1353 #endif 1354 #if defined(CLOCK_IP_HAS_EFLEX_PWM1_CLK) 1355 /* EFLEX_PWM1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ47_INDEX,0U, 0U}, /* EFLEX_PWM1_CLK clock */ 1356 #endif 1357 #if defined(CLOCK_IP_HAS_EIM_CLK) 1358 /* EIM_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ22_INDEX,0U, 0U}, /* EIM_CLK clock */ 1359 #endif 1360 #if defined(CLOCK_IP_HAS_EIM0_CLK) 1361 /* EIM0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL2_REQ67_INDEX,0U, 0U}, /* EIM0_CLK clock */ 1362 #endif 1363 #if defined(CLOCK_IP_HAS_EIM1_CLK) 1364 /* EIM1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL2_REQ68_INDEX,0U, 0U}, /* EIM1_CLK clock */ 1365 #endif 1366 #if defined(CLOCK_IP_HAS_EIM2_CLK) 1367 /* EIM2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL2_REQ69_INDEX,0U, 0U}, /* EIM2_CLK clock */ 1368 #endif 1369 #if defined(CLOCK_IP_HAS_EIM3_CLK) 1370 /* EIM3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL2_REQ70_INDEX,0U, 0U}, /* EIM3_CLK clock */ 1371 #endif 1372 #if defined(CLOCK_IP_HAS_EMAC_RX_CLK) 1373 /* EMAC_RX_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_EMAC_RX_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* EMAC_RX_CLK clock */ 1374 #endif 1375 #if defined(CLOCK_IP_HAS_EMAC0_RX_CLK) 1376 /* EMAC0_RX_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ32_INDEX,0U, 0U}, /* EMAC0_RX_CLK clock */ 1377 #endif 1378 #if defined(CLOCK_IP_HAS_EMAC_TS_CLK) 1379 /* EMAC_TS_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_EMAC_TS_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* EMAC_TS_CLK clock */ 1380 #endif 1381 #if defined(CLOCK_IP_HAS_EMAC0_TS_CLK) 1382 /* EMAC0_TS_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ32_INDEX,0U, 0U}, /* EMAC0_TS_CLK clock */ 1383 #endif 1384 #if defined(CLOCK_IP_HAS_EMAC_TX_CLK) 1385 /* EMAC_TX_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_EMAC_TX_EXTENSION, 0U, CLOCK_IP_SEL_8_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* EMAC_TX_CLK clock */ 1386 #endif 1387 #if defined(CLOCK_IP_HAS_EMAC0_TX_CLK) 1388 /* EMAC0_TX_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ32_INDEX,0U, 0U}, /* EMAC0_TX_CLK clock */ 1389 #endif 1390 #if defined(CLOCK_IP_HAS_EMAC_TX_RMII_CLK) 1391 /* EMAC_TX_RMII_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_EMAC_TX_RMII_EXTENSION, 0U, CLOCK_IP_SEL_12_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* EMAC_TX_RMII_CLK clock */ 1392 #endif 1393 #if defined(CLOCK_IP_HAS_EMAC0_TX_RMII_CLK) 1394 /* EMAC0_TX_RMII_CLK clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, /* EMAC0_TX_RMII_CLK clock */ 1395 #endif 1396 /* EMIOS0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ34_INDEX,0U, 0U}, /* EMIOS0_CLK clock */ 1397 #if defined(CLOCK_IP_HAS_EMIOS1_CLK) 1398 /* EMIOS1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ35_INDEX,0U, 0U}, /* EMIOS1_CLK clock */ 1399 #endif 1400 #if defined(CLOCK_IP_HAS_EMIOS2_CLK) 1401 /* EMIOS2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ36_INDEX,0U, 0U}, /* EMIOS2_CLK clock */ 1402 #endif 1403 /* ERM0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ23_INDEX,0U, 0U}, /* ERM0_CLK clock */ 1404 #if defined(CLOCK_IP_HAS_ERM1_CLK) 1405 /* ERM1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ3_INDEX,0U, 0U}, /* ERM1_CLK clock */ 1406 #endif 1407 #if defined(CLOCK_IP_HAS_ETPU_AB_REGISTERS_CLK) 1408 /* ETPU_AB_REGISTERS_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ32_INDEX,0U, 0U}, /* ETPU_AB_REGISTERS_CLK clock */ 1409 #endif 1410 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM1_CLK) 1411 /* ETPU_CODE_RAM1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ36_INDEX,0U, 0U}, /* ETPU_CODE_RAM1_CLK clock */ 1412 #endif 1413 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM2_CLK) 1414 /* ETPU_CODE_RAM2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ37_INDEX,0U, 0U}, /* ETPU_CODE_RAM2_CLK clock */ 1415 #endif 1416 #if defined(CLOCK_IP_HAS_ETPU_RAM_MIRROR_CLK) 1417 /* ETPU_RAM_MIRROR_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ35_INDEX,0U, 0U}, /* ETPU_RAM_MIRROR_CLK clock */ 1418 #endif 1419 #if defined(CLOCK_IP_HAS_ETPU_RAM_SDM_CLK) 1420 /* ETPU_RAM_SDM_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ34_INDEX,0U, 0U}, /* ETPU_RAM_SDM_CLK clock */ 1421 #endif 1422 #if defined(CLOCK_IP_HAS_FCCU_CLK) 1423 /* FCCU_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL3_REQ97_INDEX,0U, 0U}, /* FCCU_CLK clock */ 1424 #endif 1425 #if defined(CLOCK_IP_HAS_FLASH0_CLK) 1426 /* FLASH0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ26_INDEX,0U, 0U}, /* FLASH0_CLK clock */ 1427 #endif 1428 #if defined(CLOCK_IP_HAS_FLASH0_ALT_CLK) 1429 /* FLASH0_ALT_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ27_INDEX,0U, 0U}, /* FLASH0_ALT_CLK clock */ 1430 #endif 1431 #if defined(CLOCK_IP_HAS_FLASH1_CLK) 1432 /* FLASH1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL1_REQ59_INDEX,0U, 0U}, /* FLASH1_CLK clock */ 1433 #endif 1434 #if defined(CLOCK_IP_HAS_FLASH1_ALT_CLK) 1435 /* FLASH1_ALT_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL1_REQ60_INDEX,0U, 0U}, /* FLASH1_ALT_CLK clock */ 1436 #endif 1437 /* FLEXCANA_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_FLEXCANA_EXTENSION, 0U, CLOCK_IP_SEL_3_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* FLEXCANA_CLK clock */ 1438 /* FLEXCAN0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ65_INDEX,0U, 0U}, /* FLEXCAN0_CLK clock */ 1439 /* FLEXCAN1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ66_INDEX,0U, 0U}, /* FLEXCAN1_CLK clock */ 1440 /* FLEXCAN2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ67_INDEX,0U, 0U}, /* FLEXCAN2_CLK clock */ 1441 #if defined(CLOCK_IP_HAS_FLEXCANB_CLK) 1442 /* FLEXCANB_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_FLEXCANB_EXTENSION, 0U, CLOCK_IP_SEL_4_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* FLEXCANB_CLK clock */ 1443 #endif 1444 #if defined(CLOCK_IP_HAS_FLEXCAN3_CLK) 1445 /* FLEXCAN3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ68_INDEX,0U, 0U}, /* FLEXCAN3_CLK clock */ 1446 #endif 1447 #if defined(CLOCK_IP_HAS_FLEXCAN4_CLK) 1448 /* FLEXCAN4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ69_INDEX,0U, 0U}, /* FLEXCAN4_CLK clock */ 1449 #endif 1450 #if defined(CLOCK_IP_HAS_FLEXCAN5_CLK) 1451 /* FLEXCAN5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ70_INDEX,0U, 0U}, /* FLEXCAN5_CLK clock */ 1452 #endif 1453 #if defined(CLOCK_IP_HAS_FLEXCAN6_CLK) 1454 /* FLEXCAN6_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ71_INDEX,0U, 0U}, /* FLEXCAN6_CLK clock */ 1455 #endif 1456 #if defined(CLOCK_IP_HAS_FLEXCAN7_CLK) 1457 /* FLEXCAN7_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ72_INDEX,0U, 0U}, /* FLEXCAN7_CLK clock */ 1458 #endif 1459 /* FLEXIO0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ73_INDEX,0U, 0U}, /* FLEXIO0_CLK clock */ 1460 #if defined(CLOCK_IP_HAS_HSE_MU0_CLK) 1461 /* HSE_MU0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL3_REQ99_INDEX,0U, 0U}, /* HSE_MU0_CLK clock */ 1462 #endif 1463 #if defined(CLOCK_IP_HAS_HSE_MU1_CLK) 1464 /* HSE_MU1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ59_INDEX,0U, 0U}, /* HSE_MU1_CLK clock */ 1465 #endif 1466 #if defined(CLOCK_IP_HAS_JDC_CLK) 1467 /* JDC_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL3_REQ101_INDEX,0U, 0U}, /* JDC_CLK clock */ 1468 #endif 1469 #if defined(CLOCK_IP_HAS_IGF0_CLK) 1470 /* IGF0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ44_INDEX,0U, 0U}, /* IGF0_CLK clock */ 1471 #endif 1472 #if defined(CLOCK_IP_HAS_GMAC0_CLK) 1473 /* GMAC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ33_INDEX,0U, 0U}, /* GMAC0_CLK clock */ 1474 #endif 1475 #if defined(CLOCK_IP_HAS_GMAC1_CLK) 1476 /* GMAC1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ34_INDEX,0U, 0U}, /* GMAC1_CLK clock */ 1477 #endif 1478 #if defined(CLOCK_IP_HAS_GMAC0_RX_CLK) 1479 /* GMAC0_RX_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV_GATE, CLOCK_IP_GMAC0_RX_EXTENSION, 0U, CLOCK_IP_SEL_7_INDEX, CLOCK_IP_DIV_0_INDEX, CLOCK_IP_PRT2_COL1_REQ33_INDEX,0U, 0U}, /* GMAC0_RX_CLK clock */ 1480 #endif 1481 #if defined(CLOCK_IP_HAS_GMAC0_TX_CLK) 1482 /* GMAC0_TX_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV_GATE, CLOCK_IP_GMAC0_TX_EXTENSION, 0U, CLOCK_IP_SEL_8_INDEX, CLOCK_IP_DIV_0_INDEX, CLOCK_IP_PRT2_COL1_REQ33_INDEX,0U, 0U}, /* GMAC0_TX_CLK clock */ 1483 #endif 1484 #if defined(CLOCK_IP_HAS_GMAC_TS_CLK) 1485 /* GMAC_TS_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV_GATE, CLOCK_IP_GMAC_TS_EXTENSION, 0U, CLOCK_IP_SEL_9_INDEX, CLOCK_IP_DIV_0_INDEX, CLOCK_IP_PRT2_COL1_REQ33_INDEX,0U, 0U}, /* GMAC_TS_CLK clock */ 1486 #endif 1487 #if defined(CLOCK_IP_HAS_GMAC0_TX_RMII_CLK) 1488 /* GMAC0_TX_RMII_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_GMAC0_TX_RMII_EXTENSION, 0U, CLOCK_IP_SEL_12_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* GMAC0_TX_RMII_CLK clock */ 1489 #endif 1490 #if defined(CLOCK_IP_HAS_GMAC1_RX_CLK) 1491 /* GMAC1_RX_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV_GATE, CLOCK_IP_GMAC1_RX_EXTENSION, 0U, CLOCK_IP_SEL_15_INDEX, CLOCK_IP_DIV_0_INDEX, CLOCK_IP_PRT2_COL1_REQ34_INDEX,0U, 0U}, /* GMAC1_RX_CLK clock */ 1492 #endif 1493 #if defined(CLOCK_IP_HAS_GMAC1_TX_CLK) 1494 /* GMAC1_TX_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV_GATE, CLOCK_IP_GMAC1_TX_EXTENSION, 0U, CLOCK_IP_SEL_16_INDEX, CLOCK_IP_DIV_0_INDEX, CLOCK_IP_PRT2_COL1_REQ34_INDEX,0U, 0U}, /* GMAC1_TX_CLK clock */ 1495 #endif 1496 #if defined(CLOCK_IP_HAS_GMAC1_RMII_CLK) 1497 /* GMAC1_RMII_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV_GATE, CLOCK_IP_GMAC1_RMII_EXTENSION, 0U, CLOCK_IP_SEL_17_INDEX, CLOCK_IP_DIV_0_INDEX, CLOCK_IP_PRT2_COL1_REQ34_INDEX,0U, 0U}, /* GMAC1_RMII_CLK clock */ 1498 #endif 1499 /* INTM_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ31_INDEX,0U, 0U}, /* INTM_CLK clock */ 1500 /* LCU0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ38_INDEX,0U, 0U}, /* LCU0_CLK clock */ 1501 /* LCU1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ39_INDEX,0U, 0U}, /* LCU1_CLK clock */ 1502 #if defined(CLOCK_IP_HAS_LFAST_REF_CLK) 1503 /* LFAST_REF_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_LFAST_REF_EXTENSION, 0U, CLOCK_IP_SEL_15_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* LFAST_REF_CLK clock */ 1504 #endif 1505 #if defined(CLOCK_IP_HAS_LPI2C0_CLK) 1506 /* LPI2C0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ84_INDEX,0U, 0U}, /* LPI2C0_CLK clock */ 1507 #endif 1508 /* LPI2C1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ85_INDEX,0U, 0U}, /* LPI2C1_CLK clock */ 1509 /* LPSPI0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ86_INDEX,0U, 0U}, /* LPSPI0_CLK clock */ 1510 /* LPSPI1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ87_INDEX,0U, 0U}, /* LPSPI1_CLK clock */ 1511 /* LPSPI2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ88_INDEX,0U, 0U}, /* LPSPI2_CLK clock */ 1512 /* LPSPI3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ89_INDEX,0U, 0U}, /* LPSPI3_CLK clock */ 1513 #if defined(CLOCK_IP_HAS_LPSPI4_CLK) 1514 /* LPSPI4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ47_INDEX,0U, 0U}, /* LPSPI4_CLK clock */ 1515 #endif 1516 #if defined(CLOCK_IP_HAS_LPSPI5_CLK) 1517 /* LPSPI5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ48_INDEX,0U, 0U}, /* LPSPI5_CLK clock */ 1518 #endif 1519 /* LPUART0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ74_INDEX,0U, 0U}, /* LPUART0_CLK clock */ 1520 /* LPUART1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ75_INDEX,0U, 0U}, /* LPUART1_CLK clock */ 1521 /* LPUART2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ76_INDEX,0U, 0U}, /* LPUART2_CLK clock */ 1522 /* LPUART3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ77_INDEX,0U, 0U}, /* LPUART3_CLK clock */ 1523 #if defined(CLOCK_IP_HAS_LPUART4_CLK) 1524 /* LPUART4_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ78_INDEX,0U, 0U}, /* LPUART4_CLK clock */ 1525 #endif 1526 #if defined(CLOCK_IP_HAS_LPUART5_CLK) 1527 /* LPUART5_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ79_INDEX,0U, 0U}, /* LPUART5_CLK clock */ 1528 #endif 1529 #if defined(CLOCK_IP_HAS_LPUART6_CLK) 1530 /* LPUART6_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ80_INDEX,0U, 0U}, /* LPUART6_CLK clock */ 1531 #endif 1532 #if defined(CLOCK_IP_HAS_LPUART7_CLK) 1533 /* LPUART7_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ81_INDEX,0U, 0U}, /* LPUART7_CLK clock */ 1534 #endif 1535 #if defined(CLOCK_IP_HAS_LPUART8_CLK) 1536 /* LPUART8_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ35_INDEX,0U, 0U}, /* LPUART8_CLK clock */ 1537 #endif 1538 #if defined(CLOCK_IP_HAS_LPUART9_CLK) 1539 /* LPUART9_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ36_INDEX,0U, 0U}, /* LPUART9_CLK clock */ 1540 #endif 1541 #if defined(CLOCK_IP_HAS_LPUART10_CLK) 1542 /* LPUART10_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ37_INDEX,0U, 0U}, /* LPUART10_CLK clock */ 1543 #endif 1544 #if defined(CLOCK_IP_HAS_LPUART11_CLK) 1545 /* LPUART11_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ38_INDEX,0U, 0U}, /* LPUART11_CLK clock */ 1546 #endif 1547 #if defined(CLOCK_IP_HAS_LPUART12_CLK) 1548 /* LPUART12_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ39_INDEX,0U, 0U}, /* LPUART12_CLK clock */ 1549 #endif 1550 #if defined(CLOCK_IP_HAS_LPUART13_CLK) 1551 /* LPUART13_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ40_INDEX,0U, 0U}, /* LPUART13_CLK clock */ 1552 #endif 1553 #if defined(CLOCK_IP_HAS_LPUART14_CLK) 1554 /* LPUART14_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ41_INDEX,0U, 0U}, /* LPUART14_CLK clock */ 1555 #endif 1556 #if defined(CLOCK_IP_HAS_LPUART15_CLK) 1557 /* LPUART15_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ42_INDEX,0U, 0U}, /* LPUART15_CLK clock */ 1558 #endif 1559 #if defined(CLOCK_IP_HAS_LPUART_MSC_CLK) 1560 /* LPUART_MSC_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL2_REQ65_INDEX,0U, 0U}, /* LPUART_MSC_CLK clock */ 1561 #endif 1562 /* MSCM_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ24_INDEX,0U, 0U}, /* MSCM_CLK clock */ 1563 #if defined(CLOCK_IP_HAS_MU2A_CLK) 1564 /* MU2A_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ46_INDEX,0U, 0U}, /* MU2A_CLK clock */ 1565 #endif 1566 #if defined(CLOCK_IP_HAS_MU2B_CLK) 1567 /* MU2B_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ47_INDEX,0U, 0U}, /* MU2B_CLK clock */ 1568 #endif 1569 #if defined(CLOCK_IP_HAS_MU3A_CLK) 1570 /* MU3A_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ49_INDEX,0U, 0U}, /* MU3A_CLK clock */ 1571 #endif 1572 #if defined(CLOCK_IP_HAS_MU3B_CLK) 1573 /* MU3B_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ50_INDEX,0U, 0U}, /* MU3B_CLK clock */ 1574 #endif 1575 #if defined(CLOCK_IP_HAS_MU4A_CLK) 1576 /* MU4A_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ51_INDEX,0U, 0U}, /* MU4A_CLK clock */ 1577 #endif 1578 #if defined(CLOCK_IP_HAS_MU4B_CLK) 1579 /* MU4B_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ52_INDEX,0U, 0U}, /* MU4B_CLK clock */ 1580 #endif 1581 /* PIT0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ44_INDEX,0U, 0U}, /* PIT0_CLK clock */ 1582 /* PIT1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ45_INDEX,0U, 0U}, /* PIT1_CLK clock */ 1583 #if defined(CLOCK_IP_HAS_PIT2_CLK) 1584 /* PIT2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL1_REQ63_INDEX,0U, 0U}, /* PIT2_CLK clock */ 1585 #endif 1586 #if defined(CLOCK_IP_HAS_PIT3_CLK) 1587 /* PIT3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ64_INDEX,0U, 0U}, /* PIT3_CLK clock */ 1588 #endif 1589 #if defined(CLOCK_IP_HAS_PRAMC0_CLK) 1590 /* PRAMC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ25_INDEX,0U, 0U}, /* PRAMC0_CLK clock */ 1591 #endif 1592 #if defined(CLOCK_IP_HAS_PRAMC1_CLK) 1593 /* PRAMC1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ25_INDEX,0U, 0U}, /* PRAMC1_CLK clock */ 1594 #endif 1595 #if defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK) 1596 /* QSPI_2XSFIF_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_QSPI_2XSFIF_EXTENSION, 0U, CLOCK_IP_SEL_10_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* QSPI_2XSFIF_CLK clock */ 1597 #endif 1598 #if defined(CLOCK_IP_HAS_QSPI0_CLK) 1599 /* QSPI0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ51_INDEX,0U, 0U}, /* QSPI0_CLK clock */ 1600 #endif 1601 #if defined(CLOCK_IP_HAS_QSPI0_RAM_CLK) 1602 /* QSPI0_RAM_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ51_INDEX,0U, 0U}, /* QSPI0_RAM_CLK clock */ 1603 #endif 1604 #if defined(CLOCK_IP_HAS_QSPI0_TX_MEM_CLK) 1605 /* QSPI0_TX_MEM_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ51_INDEX,0U, 0U}, /* QSPI0_TX_MEM_CLK clock */ 1606 #endif 1607 #if defined(CLOCK_IP_HAS_QSPI_SFCK_CLK) && defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK) 1608 /* QSPI_SFCK_CLK clock */ {0U, CLOCK_IP_NO_CALLBACK, 0U, 0U, CLOCK_IP_SEL_10_INDEX, 0U, 0U, 0U, 0U}, /* QSPI_SFCK_CLK clock */ 1609 #endif 1610 #if defined(CLOCK_IP_HAS_QSPI_SFCK_CLK) && !defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK) 1611 /* QSPI_SFCK_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_QSPI_SFIF_EXTENSION, 0U, CLOCK_IP_SEL_10_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* QSPI_SFCK_CLK clock */ 1612 #endif 1613 /* RTC_CLK clock */ {0U, CLOCK_IP_RTC_SEL, 0U, 0U, CLOCK_IP_SEL_0_INDEX, 0U, 0U, 0U, 0U}, /* RTC_CLK clock */ 1614 /* RTC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL1_REQ34_INDEX,0U, 0U}, /* RTC0_CLK clock */ 1615 #if defined(CLOCK_IP_HAS_SAI0_CLK) 1616 /* SAI0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ91_INDEX,0U, 0U}, /* SAI0_CLK clock */ 1617 #endif 1618 #if defined(CLOCK_IP_HAS_SAI1_CLK) 1619 /* SAI1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ55_INDEX,0U, 0U}, /* SAI1_CLK clock */ 1620 #endif 1621 #if defined(CLOCK_IP_HAS_SDA_AP_CLK) 1622 /* SDA_AP_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ21_INDEX,0U, 0U}, /* SDA_AP_CLK clock */ 1623 #endif 1624 #if defined(CLOCK_IP_HAS_SDADC0_CLK) 1625 /* SDADC0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ61_INDEX,0U, 0U}, /* SDADC0_CLK clock */ 1626 #endif 1627 #if defined(CLOCK_IP_HAS_SDADC1_CLK) 1628 /* SDADC1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ62_INDEX,0U, 0U}, /* SDADC1_CLK clock */ 1629 #endif 1630 #if defined(CLOCK_IP_HAS_SDADC2_CLK) 1631 /* SDADC2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ63_INDEX,0U, 0U}, /* SDADC2_CLK clock */ 1632 #endif 1633 #if defined(CLOCK_IP_HAS_SDADC3_CLK) 1634 /* SDADC3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL2_REQ64_INDEX,0U, 0U}, /* SDADC3_CLK clock */ 1635 #endif 1636 #if defined(CLOCK_IP_HAS_SEMA42_CLK) 1637 /* SEMA42_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ24_INDEX,0U, 0U}, /* SEMA42_CLK clock */ 1638 #endif 1639 #if defined(CLOCK_IP_HAS_SIPI0_CLK) 1640 /* SIPI0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ60_INDEX,0U, 0U}, /* SIPI0_CLK clock */ 1641 #endif 1642 /* SIUL2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL1_REQ42_INDEX,0U, 0U}, /* SIUL2_CLK clock */ 1643 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_0_CLK) 1644 /* SIUL2_PDAC0_0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL1_REQ36_INDEX,0U, 0U}, /* SIUL2_PDAC0_0_CLK clock */ 1645 #endif 1646 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_1_CLK) 1647 /* SIUL2_PDAC0_1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL1_REQ37_INDEX,0U, 0U}, /* SIUL2_PDAC0_1_CLK clock */ 1648 #endif 1649 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_0_CLK) 1650 /* SIUL2_PDAC1_0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL1_REQ38_INDEX,0U, 0U}, /* SIUL2_PDAC1_0_CLK clock */ 1651 #endif 1652 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_1_CLK) 1653 /* SIUL2_PDAC1_1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL1_REQ39_INDEX,0U, 0U}, /* SIUL2_PDAC1_1_CLK clock */ 1654 #endif 1655 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_0_CLK) 1656 /* SIUL2_PDAC2_0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL1_REQ40_INDEX,0U, 0U}, /* SIUL2_PDAC2_0_CLK clock */ 1657 #endif 1658 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_1_CLK) 1659 /* SIUL2_PDAC2_1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL1_REQ41_INDEX,0U, 0U}, /* SIUL2_PDAC2_1_CLK clock */ 1660 #endif 1661 /* STCU0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL3_REQ104_INDEX,0U, 0U}, /* STCU0_CLK clock */ 1662 /* STMA_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_STMA_EXTENSION, 0U, CLOCK_IP_SEL_1_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* STMA_CLK clock */ 1663 /* STM0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ29_INDEX,0U, 0U}, /* STM0_CLK clock */ 1664 #if defined(CLOCK_IP_HAS_STMB_CLK) 1665 /* STMB_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_STMB_EXTENSION, 0U, CLOCK_IP_SEL_2_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* STMB_CLK clock */ 1666 #endif 1667 #if defined(CLOCK_IP_HAS_STM1_CLK) 1668 /* STM1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ29_INDEX,0U, 0U}, /* STM1_CLK clock */ 1669 #endif 1670 #if defined(CLOCK_IP_HAS_STMC_CLK) 1671 /* STMC_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_STMC_EXTENSION, 0U, CLOCK_IP_SEL_13_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* STMC_CLK clock */ 1672 #endif 1673 #if defined(CLOCK_IP_HAS_STM2_CLK) 1674 /* STM2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ30_INDEX,0U, 0U}, /* STM2_CLK clock */ 1675 #endif 1676 #if defined(CLOCK_IP_HAS_STMD_CLK) 1677 /* STMD_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_STMD_EXTENSION, 0U, CLOCK_IP_SEL_18_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* STMD_CLK clock */ 1678 #endif 1679 #if defined(CLOCK_IP_HAS_STM3_CLK) 1680 /* STM3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ31_INDEX,0U, 0U}, /* STM3_CLK clock */ 1681 #endif 1682 #if defined(CLOCK_IP_HAS_SWG_CLK) 1683 /* SWG_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV, CLOCK_IP_SWG_EXTENSION, 0U, CLOCK_IP_SEL_16_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* SWG_CLK clock */ 1684 #endif 1685 #if defined(CLOCK_IP_HAS_SWG0_CLK) 1686 /* SWG0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ50_INDEX,0U, 0U}, /* SWG0_CLK clock */ 1687 #endif 1688 #if defined(CLOCK_IP_HAS_SWG1_CLK) 1689 /* SWG1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ51_INDEX,0U, 0U}, /* SWG1_CLK clock */ 1690 #endif 1691 /* SWT0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ28_INDEX,0U, 0U}, /* SWT0_CLK clock */ 1692 #if defined(CLOCK_IP_HAS_SWT1_CLK) 1693 /* SWT1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ27_INDEX,0U, 0U}, /* SWT1_CLK clock */ 1694 #endif 1695 #if defined(CLOCK_IP_HAS_SWT2_CLK) 1696 /* SWT2_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL0_REQ28_INDEX,0U, 0U}, /* SWT2_CLK clock */ 1697 #endif 1698 #if defined(CLOCK_IP_HAS_SWT3_CLK) 1699 /* SWT3_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL0_REQ28_INDEX,0U, 0U}, /* SWT3_CLK clock */ 1700 #endif 1701 #if defined(CLOCK_IP_HAS_TCM_CM7_0_CLK) 1702 /* TCM_CM7_0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ62_INDEX,0U, 0U}, /* TCM_CM7_0_CLK clock */ 1703 #endif 1704 #if defined(CLOCK_IP_HAS_TCM_CM7_1_CLK) 1705 /* TCM_CM7_1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT2_COL1_REQ63_INDEX,0U, 0U}, /* TCM_CM7_1_CLK clock */ 1706 #endif 1707 /* TEMPSENSE_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL2_REQ95_INDEX,0U, 0U}, /* TEMPSENSE_CLK clock */ 1708 /* TRACE_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_SWMUX_DIV, CLOCK_IP_TRACE_EXTENSION, 0U, CLOCK_IP_SEL_11_INDEX, CLOCK_IP_DIV_0_INDEX, 0U, 0U, 0U}, /* TRACE_CLK clock */ 1709 /* TRGMUX0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT0_COL1_REQ32_INDEX,0U, 0U}, /* TRGMUX0_CLK clock */ 1710 #if defined(CLOCK_IP_HAS_TRGMUX1_CLK) 1711 /* TRGMUX1_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT3_COL1_REQ48_INDEX,0U, 0U}, /* TRGMUX1_CLK clock */ 1712 #endif 1713 #if defined(CLOCK_IP_HAS_TSENSE0_CLK) 1714 /* TSENSE0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL1_REQ49_INDEX,0U, 0U}, /* TSENSE0_CLK clock */ 1715 #endif 1716 #if defined(CLOCK_IP_HAS_USDHC_CLK) 1717 /* USDHC_CLK clock */ {CLOCK_IP_CGM_0_INSTANCE, CLOCK_IP_HWMUX_DIV_GATE, CLOCK_IP_USDHC_EXTENSION, 0U, CLOCK_IP_SEL_14_INDEX, CLOCK_IP_DIV_0_INDEX, CLOCK_IP_PRT2_COL1_REQ57_INDEX,0U, 0U}, /* USDHC_CLK clock */ 1718 #endif 1719 /* WKPU0_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL1_REQ45_INDEX,0U, 0U}, /* WKPU0_CLK clock */ 1720 #if defined(CLOCK_IP_HAS_XRDC_CLK) 1721 /* XRDC_CLK clock */ {0U, CLOCK_IP_GATE, 0U, 0U, 0U, 0U, CLOCK_IP_PRT1_COL0_REQ30_INDEX,0U, 0U}, /* XRDC_CLK clock */ 1722 #endif 1723 }; 1724 1725 1726 /*! 1727 * @brief Reset value of a software clock mux associated to a clock name 1728 */ 1729 const uint8 Clock_Ip_au8SoftwareMuxResetValue[CLOCK_IP_NAMES_NO] = { 1730 0U, /* CLOCK_IS_OFF clock */ 1731 0U, /* FIRC_CLK clock */ 1732 0U, /* FIRC_STANDBY_CLK clock */ 1733 0U, /* SIRC_CLK clock */ 1734 0U, /* SIRC_STANDBY_CLK clock */ 1735 0U, /* FXOSC_CLK clock */ 1736 #if defined(CLOCK_IP_HAS_SXOSC_CLK) 1737 0U, /* SXOSC_CLK clock */ 1738 #endif 1739 0U, /* PLL_CLK clock */ 1740 #if defined(CLOCK_IP_HAS_PLLAUX_CLK) 1741 0U, /* PLLAUX_CLK clock */ 1742 #endif 1743 0U, /* PLL_POSTDIV_CLK clock */ 1744 #if defined(CLOCK_IP_HAS_PLLAUX_POSTDIV_CLK) 1745 0U, /* PLLAUX_POSTDIV_CLK clock */ 1746 #endif 1747 0U, /* PLL_PHI0 clock */ 1748 0U, /* PLL_PHI1 clock */ 1749 #if defined(CLOCK_IP_HAS_PLLAUX_PHI0_CLK) 1750 0U, /* PLLAUX_PHI0_CLK clock */ 1751 #endif 1752 #if defined(CLOCK_IP_HAS_PLLAUX_PHI1_CLK) 1753 0U, /* PLLAUX_PHI1_CLK clock */ 1754 #endif 1755 #if defined(CLOCK_IP_HAS_PLLAUX_PHI2_CLK) 1756 0U, /* PLLAUX_PHI2_CLK clock */ 1757 #endif 1758 #if defined(CLOCK_IP_HAS_EMAC_MII_RX_CLK) 1759 0U, /* emac_mii_rx clock */ 1760 #endif 1761 #if defined(CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK) 1762 0U, /* emac_mii_rmii_tx clock */ 1763 #endif 1764 #if defined(CLOCK_IP_HAS_GMAC0_MII_RX_CLK) 1765 0U, /* GMAC0_mii_rx clock */ 1766 #endif 1767 #if defined(CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK) 1768 0U, /* GMAC0_mii_rmii_tx clock */ 1769 #endif 1770 #if defined(CLOCK_IP_HAS_LFAST_REF_EXT_CLK) 1771 0U, /* lfast_ext_ref clock */ 1772 #endif 1773 #if defined(CLOCK_IP_HAS_SWG_PAD_CLK) 1774 0U, /* swg_pad clock */ 1775 #endif 1776 0U, /* SCS_CLK clock */ 1777 0U, /* CORE_CLK clock */ 1778 0U, /* AIPS_PLAT_CLK clock */ 1779 0U, /* AIPS_SLOW_CLK clock */ 1780 0U, /* HSE_CLK clock */ 1781 0U, /* DCM_CLK clock */ 1782 #if defined(CLOCK_IP_HAS_LBIST_CLK) 1783 0U, /* LBIST_CLK clock */ 1784 #endif 1785 #if defined(CLOCK_IP_HAS_QSPI_MEM_CLK) 1786 0U, /* QSPI_MEM_CLK clock */ 1787 #endif 1788 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 1789 0U, /* CM7_CORE_CLK clock */ 1790 #endif 1791 0U, /* CLKOUT_RUN_CLK clock */ 1792 0U, /* THE_LAST_PRODUCER_CLK clock */ 1793 0U, /* ADC0_CLK clock */ 1794 0U, /* ADC1_CLK clock */ 1795 #if defined(CLOCK_IP_HAS_ADC2_CLK) 1796 0U, /* ADC2_CLK clock */ 1797 #endif 1798 #if defined(CLOCK_IP_HAS_ADC3_CLK) 1799 0U, /* ADC3_CLK clock */ 1800 #endif 1801 #if defined(CLOCK_IP_HAS_ADC4_CLK) 1802 0U, /* ADC4_CLK clock */ 1803 #endif 1804 #if defined(CLOCK_IP_HAS_ADC5_CLK) 1805 0U, /* ADC5_CLK clock */ 1806 #endif 1807 #if defined(CLOCK_IP_HAS_ADC6_CLK) 1808 0U, /* ADC6_CLK clock */ 1809 #endif 1810 #if defined(CLOCK_IP_HAS_ADCBIST_CLK) 1811 0U, /* ADCBIST_CLK clock */ 1812 #endif 1813 #if defined(CLOCK_IP_HAS_AES_ACCEL_CLK) 1814 0U, /* AES_ACCEL_CLK clock */ 1815 #endif 1816 #if defined(CLOCK_IP_HAS_AES_APP0_CLK) 1817 0U, /* AES_APP0_CLK clock */ 1818 #endif 1819 #if defined(CLOCK_IP_HAS_AES_APP1_CLK) 1820 0U, /* AES_APP1_CLK clock */ 1821 #endif 1822 #if defined(CLOCK_IP_HAS_AES_APP2_CLK) 1823 0U, /* AES_APP2_CLK clock */ 1824 #endif 1825 #if defined(CLOCK_IP_HAS_AES_APP3_CLK) 1826 0U, /* AES_APP3_CLK clock */ 1827 #endif 1828 #if defined(CLOCK_IP_HAS_AES_APP4_CLK) 1829 0U, /* AES_APP4_CLK clock */ 1830 #endif 1831 #if defined(CLOCK_IP_HAS_AES_APP5_CLK) 1832 0U, /* AES_APP5_CLK clock */ 1833 #endif 1834 #if defined(CLOCK_IP_HAS_AES_APP6_CLK) 1835 0U, /* AES_APP6_CLK clock */ 1836 #endif 1837 #if defined(CLOCK_IP_HAS_AES_APP7_CLK) 1838 0U, /* AES_APP7_CLK clock */ 1839 #endif 1840 #if defined(CLOCK_IP_HAS_AES_CLK) 1841 0U, /* AES_CLK clock */ 1842 #endif 1843 #if defined(CLOCK_IP_HAS_AXBS_CLK) 1844 0U, /* AXBS_CLK clock */ 1845 #endif 1846 #if defined(CLOCK_IP_HAS_AXBS0_CLK) 1847 0U, /* AXBS0_CLK clock */ 1848 #endif 1849 #if defined(CLOCK_IP_HAS_AXBS1_CLK) 1850 0U, /* AXBS1_CLK clock */ 1851 #endif 1852 0U, /* BCTU0_CLK clock */ 1853 #if defined(CLOCK_IP_HAS_BCTU1_CLK) 1854 0U, /* BCTU1_CLK clock */ 1855 #endif 1856 0U, /* CLKOUT_STANDBY_CLK clock */ 1857 0U, /* CMP0_CLK clock */ 1858 #if defined(CLOCK_IP_HAS_CMP1_CLK) 1859 0U, /* CMP1_CLK clock */ 1860 #endif 1861 #if defined(CLOCK_IP_HAS_CMP2_CLK) 1862 0U, /* CMP2_CLK clock */ 1863 #endif 1864 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM0_CLK) 1865 0U, /* COOLFLUX_D_RAM0_CLK clock */ 1866 #endif 1867 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM1_CLK) 1868 0U, /* COOLFLUX_D_RAM1_CLK clock */ 1869 #endif 1870 #if defined(CLOCK_IP_HAS_COOLFLUX_DSP16L_CLK) 1871 0U, /* COOLFLUX_DSP16L_CLK clock */ 1872 #endif 1873 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM0_CLK) 1874 0U, /* COOLFLUX_I_RAM0_CLK clock */ 1875 #endif 1876 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM1_CLK) 1877 0U, /* COOLFLUX_I_RAM1_CLK clock */ 1878 #endif 1879 0U, /* CRC0_CLK clock */ 1880 0U, /* DCM0_CLK clock */ 1881 0U, /* DMAMUX0_CLK clock */ 1882 0U, /* DMAMUX1_CLK clock */ 1883 #if defined(CLOCK_IP_HAS_DMAMUX2_CLK) 1884 0U, /* DMAMUX2_CLK clock */ 1885 #endif 1886 #if defined(CLOCK_IP_HAS_DMAMUX3_CLK) 1887 0U, /* DMAMUX3_CLK clock */ 1888 #endif 1889 #if defined(CLOCK_IP_HAS_DSPI_MSC_CLK) 1890 0U, /* DSPI_MSC_CLK clock */ 1891 #endif 1892 0U, /* EDMA0_CLK clock */ 1893 0U, /* EDMA0_TCD0_CLK clock */ 1894 0U, /* EDMA0_TCD1_CLK clock */ 1895 0U, /* EDMA0_TCD2_CLK clock */ 1896 0U, /* EDMA0_TCD3_CLK clock */ 1897 0U, /* EDMA0_TCD4_CLK clock */ 1898 0U, /* EDMA0_TCD5_CLK clock */ 1899 0U, /* EDMA0_TCD6_CLK clock */ 1900 0U, /* EDMA0_TCD7_CLK clock */ 1901 0U, /* EDMA0_TCD8_CLK clock */ 1902 0U, /* EDMA0_TCD9_CLK clock */ 1903 0U, /* EDMA0_TCD10_CLK clock */ 1904 0U, /* EDMA0_TCD11_CLK clock */ 1905 #if defined(CLOCK_IP_HAS_EDMA0_TCD12_CLK) 1906 0U, /* EDMA0_TCD12_CLK clock */ 1907 #endif 1908 #if defined(CLOCK_IP_HAS_EDMA0_TCD13_CLK) 1909 0U, /* EDMA0_TCD13_CLK clock */ 1910 #endif 1911 #if defined(CLOCK_IP_HAS_EDMA0_TCD14_CLK) 1912 0U, /* EDMA0_TCD14_CLK clock */ 1913 #endif 1914 #if defined(CLOCK_IP_HAS_EDMA0_TCD15_CLK) 1915 0U, /* EDMA0_TCD15_CLK clock */ 1916 #endif 1917 #if defined(CLOCK_IP_HAS_EDMA0_TCD16_CLK) 1918 0U, /* EDMA0_TCD16_CLK clock */ 1919 #endif 1920 #if defined(CLOCK_IP_HAS_EDMA0_TCD17_CLK) 1921 0U, /* EDMA0_TCD17_CLK clock */ 1922 #endif 1923 #if defined(CLOCK_IP_HAS_EDMA0_TCD18_CLK) 1924 0U, /* EDMA0_TCD18_CLK clock */ 1925 #endif 1926 #if defined(CLOCK_IP_HAS_EDMA0_TCD19_CLK) 1927 0U, /* EDMA0_TCD19_CLK clock */ 1928 #endif 1929 #if defined(CLOCK_IP_HAS_EDMA0_TCD20_CLK) 1930 0U, /* EDMA0_TCD20_CLK clock */ 1931 #endif 1932 #if defined(CLOCK_IP_HAS_EDMA0_TCD21_CLK) 1933 0U, /* EDMA0_TCD21_CLK clock */ 1934 #endif 1935 #if defined(CLOCK_IP_HAS_EDMA0_TCD22_CLK) 1936 0U, /* EDMA0_TCD22_CLK clock */ 1937 #endif 1938 #if defined(CLOCK_IP_HAS_EDMA0_TCD23_CLK) 1939 0U, /* EDMA0_TCD23_CLK clock */ 1940 #endif 1941 #if defined(CLOCK_IP_HAS_EDMA0_TCD24_CLK) 1942 0U, /* EDMA0_TCD24_CLK clock */ 1943 #endif 1944 #if defined(CLOCK_IP_HAS_EDMA0_TCD25_CLK) 1945 0U, /* EDMA0_TCD25_CLK clock */ 1946 #endif 1947 #if defined(CLOCK_IP_HAS_EDMA0_TCD26_CLK) 1948 0U, /* EDMA0_TCD26_CLK clock */ 1949 #endif 1950 #if defined(CLOCK_IP_HAS_EDMA0_TCD27_CLK) 1951 0U, /* EDMA0_TCD27_CLK clock */ 1952 #endif 1953 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 1954 0U, /* EDMA0_TCD28_CLK clock */ 1955 #endif 1956 #if defined(CLOCK_IP_HAS_EDMA0_TCD29_CLK) 1957 0U, /* EDMA0_TCD29_CLK clock */ 1958 #endif 1959 #if defined(CLOCK_IP_HAS_EDMA0_TCD30_CLK) 1960 0U, /* EDMA0_TCD30_CLK clock */ 1961 #endif 1962 #if defined(CLOCK_IP_HAS_EDMA0_TCD31_CLK) 1963 0U, /* EDMA0_TCD31_CLK clock */ 1964 #endif 1965 #if defined(CLOCK_IP_HAS_EDMA1_CLK) 1966 0U, /* EDMA1_CLK clock */ 1967 #endif 1968 #if defined(CLOCK_IP_HAS_EDMA1_TCD0_CLK) 1969 0U, /* EDMA1_TCD0_CLK clock */ 1970 #endif 1971 #if defined(CLOCK_IP_HAS_EDMA1_TCD1_CLK) 1972 0U, /* EDMA1_TCD1_CLK clock */ 1973 #endif 1974 #if defined(CLOCK_IP_HAS_EDMA1_TCD2_CLK) 1975 0U, /* EDMA1_TCD2_CLK clock */ 1976 #endif 1977 #if defined(CLOCK_IP_HAS_EDMA1_TCD3_CLK) 1978 0U, /* EDMA1_TCD3_CLK clock */ 1979 #endif 1980 #if defined(CLOCK_IP_HAS_EDMA1_TCD4_CLK) 1981 0U, /* EDMA1_TCD4_CLK clock */ 1982 #endif 1983 #if defined(CLOCK_IP_HAS_EDMA1_TCD5_CLK) 1984 0U, /* EDMA1_TCD5_CLK clock */ 1985 #endif 1986 #if defined(CLOCK_IP_HAS_EDMA1_TCD6_CLK) 1987 0U, /* EDMA1_TCD6_CLK clock */ 1988 #endif 1989 #if defined(CLOCK_IP_HAS_EDMA1_TCD7_CLK) 1990 0U, /* EDMA1_TCD7_CLK clock */ 1991 #endif 1992 #if defined(CLOCK_IP_HAS_EDMA1_TCD8_CLK) 1993 0U, /* EDMA1_TCD8_CLK clock */ 1994 #endif 1995 #if defined(CLOCK_IP_HAS_EDMA1_TCD9_CLK) 1996 0U, /* EDMA1_TCD9_CLK clock */ 1997 #endif 1998 #if defined(CLOCK_IP_HAS_EDMA1_TCD10_CLK) 1999 0U, /* EDMA1_TCD10_CLK clock */ 2000 #endif 2001 #if defined(CLOCK_IP_HAS_EDMA1_TCD11_CLK) 2002 0U, /* EDMA1_TCD11_CLK clock */ 2003 #endif 2004 #if defined(CLOCK_IP_HAS_EDMA1_TCD12_CLK) 2005 0U, /* EDMA1_TCD12_CLK clock */ 2006 #endif 2007 #if defined(CLOCK_IP_HAS_EDMA1_TCD13_CLK) 2008 0U, /* EDMA1_TCD13_CLK clock */ 2009 #endif 2010 #if defined(CLOCK_IP_HAS_EDMA1_TCD14_CLK) 2011 0U, /* EDMA1_TCD14_CLK clock */ 2012 #endif 2013 #if defined(CLOCK_IP_HAS_EDMA1_TCD15_CLK) 2014 0U, /* EDMA1_TCD15_CLK clock */ 2015 #endif 2016 #if defined(CLOCK_IP_HAS_EDMA1_TCD16_CLK) 2017 0U, /* EDMA1_TCD16_CLK clock */ 2018 #endif 2019 #if defined(CLOCK_IP_HAS_EDMA1_TCD17_CLK) 2020 0U, /* EDMA1_TCD17_CLK clock */ 2021 #endif 2022 #if defined(CLOCK_IP_HAS_EDMA1_TCD18_CLK) 2023 0U, /* EDMA1_TCD18_CLK clock */ 2024 #endif 2025 #if defined(CLOCK_IP_HAS_EDMA1_TCD19_CLK) 2026 0U, /* EDMA1_TCD19_CLK clock */ 2027 #endif 2028 #if defined(CLOCK_IP_HAS_EDMA1_TCD20_CLK) 2029 0U, /* EDMA1_TCD20_CLK clock */ 2030 #endif 2031 #if defined(CLOCK_IP_HAS_EDMA1_TCD21_CLK) 2032 0U, /* EDMA1_TCD21_CLK clock */ 2033 #endif 2034 #if defined(CLOCK_IP_HAS_EDMA1_TCD22_CLK) 2035 0U, /* EDMA1_TCD22_CLK clock */ 2036 #endif 2037 #if defined(CLOCK_IP_HAS_EDMA1_TCD23_CLK) 2038 0U, /* EDMA1_TCD23_CLK clock */ 2039 #endif 2040 #if defined(CLOCK_IP_HAS_EDMA1_TCD24_CLK) 2041 0U, /* EDMA1_TCD24_CLK clock */ 2042 #endif 2043 #if defined(CLOCK_IP_HAS_EDMA1_TCD25_CLK) 2044 0U, /* EDMA1_TCD25_CLK clock */ 2045 #endif 2046 #if defined(CLOCK_IP_HAS_EDMA1_TCD26_CLK) 2047 0U, /* EDMA1_TCD26_CLK clock */ 2048 #endif 2049 #if defined(CLOCK_IP_HAS_EDMA1_TCD27_CLK) 2050 0U, /* EDMA1_TCD27_CLK clock */ 2051 #endif 2052 #if defined(CLOCK_IP_HAS_EDMA1_TCD28_CLK) 2053 0U, /* EDMA1_TCD28_CLK clock */ 2054 #endif 2055 #if defined(CLOCK_IP_HAS_EDMA1_TCD29_CLK) 2056 0U, /* EDMA1_TCD29_CLK clock */ 2057 #endif 2058 #if defined(CLOCK_IP_HAS_EDMA1_TCD30_CLK) 2059 0U, /* EDMA1_TCD30_CLK clock */ 2060 #endif 2061 #if defined(CLOCK_IP_HAS_EDMA1_TCD31_CLK) 2062 0U, /* EDMA1_TCD31_CLK clock */ 2063 #endif 2064 #if defined(CLOCK_IP_HAS_EFLEX_PWM0_CLK) 2065 0U, /* EFLEX_PWM0_CLK clock */ 2066 #endif 2067 #if defined(CLOCK_IP_HAS_EFLEX_PWM1_CLK) 2068 0U, /* EFLEX_PWM1_CLK clock */ 2069 #endif 2070 #if defined(CLOCK_IP_HAS_EIM_CLK) 2071 0U, /* EIM_CLK clock */ 2072 #endif 2073 #if defined(CLOCK_IP_HAS_EIM0_CLK) 2074 0U, /* EIM0_CLK clock */ 2075 #endif 2076 #if defined(CLOCK_IP_HAS_EIM1_CLK) 2077 0U, /* EIM1_CLK clock */ 2078 #endif 2079 #if defined(CLOCK_IP_HAS_EIM2_CLK) 2080 0U, /* EIM2_CLK clock */ 2081 #endif 2082 #if defined(CLOCK_IP_HAS_EIM3_CLK) 2083 0U, /* EIM3_CLK clock */ 2084 #endif 2085 #if defined(CLOCK_IP_HAS_EMAC_RX_CLK) 2086 0U, /* EMAC_RX_CLK clock */ 2087 #endif 2088 #if defined(CLOCK_IP_HAS_EMAC0_RX_CLK) 2089 0U, /* EMAC0_RX_CLK clock */ 2090 #endif 2091 #if defined(CLOCK_IP_HAS_EMAC_TS_CLK) 2092 0U, /* EMAC_TS_CLK clock */ 2093 #endif 2094 #if defined(CLOCK_IP_HAS_EMAC0_TS_CLK) 2095 0U, /* EMAC0_TS_CLK clock */ 2096 #endif 2097 #if defined(CLOCK_IP_HAS_EMAC_TX_CLK) 2098 0U, /* EMAC_TX_CLK clock */ 2099 #endif 2100 #if defined(CLOCK_IP_HAS_EMAC0_TX_CLK) 2101 0U, /* EMAC0_TX_CLK clock */ 2102 #endif 2103 #if defined(CLOCK_IP_HAS_EMAC_TX_RMII_CLK) 2104 0U, /* EMAC_TX_RMII_CLK clock */ 2105 #endif 2106 #if defined(CLOCK_IP_HAS_EMAC0_TX_RMII_CLK) 2107 0U, /* EMAC0_TX_RMII_CLK clock */ 2108 #endif 2109 0U, /* EMIOS0_CLK clock */ 2110 #if defined(CLOCK_IP_HAS_EMIOS1_CLK) 2111 0U, /* EMIOS1_CLK clock */ 2112 #endif 2113 #if defined(CLOCK_IP_HAS_EMIOS2_CLK) 2114 0U, /* EMIOS2_CLK clock */ 2115 #endif 2116 0U, /* ERM0_CLK clock */ 2117 #if defined(CLOCK_IP_HAS_ERM1_CLK) 2118 0U, /* ERM1_CLK clock */ 2119 #endif 2120 #if defined(CLOCK_IP_HAS_ETPU_AB_REGISTERS_CLK) 2121 0U, /* ETPU_AB_REGISTERS_CLK clock*/ 2122 #endif 2123 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM1_CLK) 2124 0U, /* ETPU_CODE_RAM1_CLK clock */ 2125 #endif 2126 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM2_CLK) 2127 0U, /* ETPU_CODE_RAM2_CLK clock */ 2128 #endif 2129 #if defined(CLOCK_IP_HAS_ETPU_RAM_MIRROR_CLK) 2130 0U, /* ETPU_RAM_MIRROR_CLK clock */ 2131 #endif 2132 #if defined(CLOCK_IP_HAS_ETPU_RAM_SDM_CLK) 2133 0U, /* ETPU_RAM_SDM_CLK clock */ 2134 #endif 2135 #if defined(CLOCK_IP_HAS_FCCU_CLK) 2136 0U, /* FCCU_CLK clock */ 2137 #endif 2138 #if defined(CLOCK_IP_HAS_FLASH0_CLK) 2139 0U, /* FLASH0_CLK clock */ 2140 #endif 2141 #if defined(CLOCK_IP_HAS_FLASH0_ALT_CLK) 2142 0U, /* FLASH0_ALT_CLK clock */ 2143 #endif 2144 #if defined(CLOCK_IP_HAS_FLASH1_CLK) 2145 0U, /* FLASH1_CLK clock */ 2146 #endif 2147 #if defined(CLOCK_IP_HAS_FLASH1_ALT_CLK) 2148 0U, /* FLASH1_ALT_CLK clock */ 2149 #endif 2150 0U, /* FLEXCANA_CLK clock */ 2151 0U, /* FLEXCAN0_CLK clock */ 2152 0U, /* FLEXCAN1_CLK clock */ 2153 0U, /* FLEXCAN2_CLK clock */ 2154 #if defined(CLOCK_IP_HAS_FLEXCANB_CLK) 2155 0U, /* FLEXCANB_CLK clock */ 2156 #endif 2157 #if defined(CLOCK_IP_HAS_FLEXCAN3_CLK) 2158 0U, /* FLEXCAN3_CLK clock */ 2159 #endif 2160 #if defined(CLOCK_IP_HAS_FLEXCAN4_CLK) 2161 0U, /* FLEXCAN4_CLK clock */ 2162 #endif 2163 #if defined(CLOCK_IP_HAS_FLEXCAN5_CLK) 2164 0U, /* FLEXCAN5_CLK clock */ 2165 #endif 2166 #if defined(CLOCK_IP_HAS_FLEXCAN6_CLK) 2167 0U, /* FLEXCAN6_CLK clock */ 2168 #endif 2169 #if defined(CLOCK_IP_HAS_FLEXCAN7_CLK) 2170 0U, /* FLEXCAN7_CLK clock */ 2171 #endif 2172 0U, /* FLEXIO0_CLK clock */ 2173 #if defined(CLOCK_IP_HAS_HSE_MU0_CLK) 2174 0U, /* HSE_MU0_CLK clock */ 2175 #endif 2176 #if defined(CLOCK_IP_HAS_HSE_MU1_CLK) 2177 0U, /* HSE_MU1_CLK clock */ 2178 #endif 2179 #if defined(CLOCK_IP_HAS_JDC_CLK) 2180 0U, /* JDC_CLK clock */ 2181 #endif 2182 #if defined(CLOCK_IP_HAS_IGF0_CLK) 2183 0U, /* IGF0_CLK clock */ 2184 #endif 2185 #if defined(CLOCK_IP_HAS_GMAC0_CLK) 2186 0U, /* GMAC0_CLK clock */ 2187 #endif 2188 #if defined(CLOCK_IP_HAS_GMAC1_CLK) 2189 0U, /* GMAC1_CLK clock */ 2190 #endif 2191 #if defined(CLOCK_IP_HAS_GMAC0_RX_CLK) 2192 0U, /* GMAC0_RX_CLK clock */ 2193 #endif 2194 #if defined(CLOCK_IP_HAS_GMAC0_TX_CLK) 2195 0U, /* GMAC0_TX_CLK clock */ 2196 #endif 2197 #if defined(CLOCK_IP_HAS_GMAC_TS_CLK) 2198 0U, /* GMAC_TS_CLK clock */ 2199 #endif 2200 #if defined(CLOCK_IP_HAS_GMAC0_TX_RMII_CLK) 2201 0U, /* GMAC0_TX_RMII_CLK clock */ 2202 #endif 2203 #if defined(CLOCK_IP_HAS_GMAC1_RX_CLK) 2204 0U, /* GMAC1_RX_CLK clock */ 2205 #endif 2206 #if defined(CLOCK_IP_HAS_GMAC1_TX_CLK) 2207 0U, /* GMAC1_TX_CLK clock */ 2208 #endif 2209 #if defined(CLOCK_IP_HAS_GMAC1_RMII_CLK) 2210 0U, /* GMAC1_RMII_CLK clock */ 2211 #endif 2212 0U, /* INTM_CLK clock */ 2213 0U, /* LCU0_CLK clock */ 2214 0U, /* LCU1_CLK clock */ 2215 #if defined(CLOCK_IP_HAS_LFAST_REF_CLK) 2216 0U, /* LFAST_REF_CLK clock */ 2217 #endif 2218 #if defined(CLOCK_IP_HAS_LPI2C0_CLK) 2219 0U, /* LPI2C0_CLK clock */ 2220 #endif 2221 0U, /* LPI2C1_CLK clock */ 2222 0U, /* LPSPI0_CLK clock */ 2223 0U, /* LPSPI1_CLK clock */ 2224 0U, /* LPSPI2_CLK clock */ 2225 0U, /* LPSPI3_CLK clock */ 2226 #if defined(CLOCK_IP_HAS_LPSPI4_CLK) 2227 0U, /* LPSPI4_CLK clock */ 2228 #endif 2229 #if defined(CLOCK_IP_HAS_LPSPI5_CLK) 2230 0U, /* LPSPI5_CLK clock */ 2231 #endif 2232 0U, /* LPUART0_CLK clock */ 2233 0U, /* LPUART1_CLK clock */ 2234 0U, /* LPUART2_CLK clock */ 2235 0U, /* LPUART3_CLK clock */ 2236 #if defined(CLOCK_IP_HAS_LPUART4_CLK) 2237 0U, /* LPUART4_CLK clock */ 2238 #endif 2239 #if defined(CLOCK_IP_HAS_LPUART5_CLK) 2240 0U, /* LPUART5_CLK clock */ 2241 #endif 2242 #if defined(CLOCK_IP_HAS_LPUART6_CLK) 2243 0U, /* LPUART6_CLK clock */ 2244 #endif 2245 #if defined(CLOCK_IP_HAS_LPUART7_CLK) 2246 0U, /* LPUART7_CLK clock */ 2247 #endif 2248 #if defined(CLOCK_IP_HAS_LPUART8_CLK) 2249 0U, /* LPUART8_CLK clock */ 2250 #endif 2251 #if defined(CLOCK_IP_HAS_LPUART9_CLK) 2252 0U, /* LPUART9_CLK clock */ 2253 #endif 2254 #if defined(CLOCK_IP_HAS_LPUART10_CLK) 2255 0U, /* LPUART10_CLK clock */ 2256 #endif 2257 #if defined(CLOCK_IP_HAS_LPUART11_CLK) 2258 0U, /* LPUART11_CLK clock */ 2259 #endif 2260 #if defined(CLOCK_IP_HAS_LPUART12_CLK) 2261 0U, /* LPUART12_CLK clock */ 2262 #endif 2263 #if defined(CLOCK_IP_HAS_LPUART13_CLK) 2264 0U, /* LPUART13_CLK clock */ 2265 #endif 2266 #if defined(CLOCK_IP_HAS_LPUART14_CLK) 2267 0U, /* LPUART14_CLK clock */ 2268 #endif 2269 #if defined(CLOCK_IP_HAS_LPUART15_CLK) 2270 0U, /* LPUART15_CLK clock */ 2271 #endif 2272 #if defined(CLOCK_IP_HAS_LPUART_MSC_CLK) 2273 0U, /* LPUART_MSC_CLK clock */ 2274 #endif 2275 0U, /* MSCM_CLK clock */ 2276 #if defined(CLOCK_IP_HAS_MU2A_CLK) 2277 0U, /* MU2A_CLK clock */ 2278 #endif 2279 #if defined(CLOCK_IP_HAS_MU2B_CLK) 2280 0U, /* MU2B_CLK clock */ 2281 #endif 2282 #if defined(CLOCK_IP_HAS_MU3A_CLK) 2283 0U, /* MU3A_CLK clock */ 2284 #endif 2285 #if defined(CLOCK_IP_HAS_MU3B_CLK) 2286 0U, /* MU3B_CLK clock */ 2287 #endif 2288 #if defined(CLOCK_IP_HAS_MU4A_CLK) 2289 0U, /* MU4A_CLK clock */ 2290 #endif 2291 #if defined(CLOCK_IP_HAS_MU4B_CLK) 2292 0U, /* MU4B_CLK clock */ 2293 #endif 2294 0U, /* PIT0_CLK clock */ 2295 0U, /* PIT1_CLK clock */ 2296 #if defined(CLOCK_IP_HAS_PIT2_CLK) 2297 0U, /* PIT2_CLK clock */ 2298 #endif 2299 #if defined(CLOCK_IP_HAS_PIT3_CLK) 2300 0U, /* PIT3_CLK clock */ 2301 #endif 2302 #if defined(CLOCK_IP_HAS_PRAMC0_CLK) 2303 0U, /* PRAMC0_CLK clock */ 2304 #endif 2305 #if defined(CLOCK_IP_HAS_PRAMC1_CLK) 2306 0U, /* PRAMC1_CLK clock */ 2307 #endif 2308 #if defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK) 2309 0U, /* QSPI_2XSFIF_CLK clock */ 2310 #endif 2311 #if defined(CLOCK_IP_HAS_QSPI0_CLK) 2312 0U, /* QSPI0_CLK clock */ 2313 #endif 2314 #if defined(CLOCK_IP_HAS_QSPI0_RAM_CLK) 2315 0U, /* QSPI0_RAM_CLK clock */ 2316 #endif 2317 #if defined(CLOCK_IP_HAS_QSPI0_TX_MEM_CLK) 2318 0U, /* QSPI0_TX_MEM_CLK clock */ 2319 #endif 2320 #if defined(CLOCK_IP_HAS_QSPI_SFCK_CLK) 2321 0U, /* QSPI_SFCK_CLK clock */ 2322 #endif 2323 0U, /* RTC_CLK clock */ 2324 0U, /* RTC0_CLK clock */ 2325 #if defined(CLOCK_IP_HAS_SAI0_CLK) 2326 0U, /* SAI0_CLK clock */ 2327 #endif 2328 #if defined(CLOCK_IP_HAS_SAI1_CLK) 2329 0U, /* SAI1_CLK clock */ 2330 #endif 2331 #if defined(CLOCK_IP_HAS_SDA_AP_CLK) 2332 0U, /* SDA_AP_CLK clock */ 2333 #endif 2334 #if defined(CLOCK_IP_HAS_SDADC0_CLK) 2335 0U, /* SDADC0_CLK clock */ 2336 #endif 2337 #if defined(CLOCK_IP_HAS_SDADC1_CLK) 2338 0U, /* SDADC1_CLK clock */ 2339 #endif 2340 #if defined(CLOCK_IP_HAS_SDADC2_CLK) 2341 0U, /* SDADC2_CLK clock */ 2342 #endif 2343 #if defined(CLOCK_IP_HAS_SDADC3_CLK) 2344 0U, /* SDADC3_CLK clock */ 2345 #endif 2346 #if defined(CLOCK_IP_HAS_SEMA42_CLK) 2347 0U, /* SEMA42_CLK clock */ 2348 #endif 2349 #if defined(CLOCK_IP_HAS_SIPI0_CLK) 2350 0U, /* SIPI0_CLK clock */ 2351 #endif 2352 0U, /* SIUL2_CLK clock */ 2353 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_0_CLK) 2354 0U, /* SIUL2_PDAC0_0_CLK clock */ 2355 #endif 2356 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_1_CLK) 2357 0U, /* SIUL2_PDAC0_1_CLK clock */ 2358 #endif 2359 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_0_CLK) 2360 0U, /* SIUL2_PDAC1_0_CLK clock */ 2361 #endif 2362 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_1_CLK) 2363 0U, /* SIUL2_PDAC1_1_CLK clock */ 2364 #endif 2365 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_0_CLK) 2366 0U, /* SIUL2_PDAC2_0_CLK clock */ 2367 #endif 2368 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_1_CLK) 2369 0U, /* SIUL2_PDAC2_1_CLK clock */ 2370 #endif 2371 0U, /* STCU0_CLK clock */ 2372 0U, /* STMA_CLK clock */ 2373 0U, /* STM0_CLK clock */ 2374 #if defined(CLOCK_IP_HAS_STMB_CLK) 2375 0U, /* STMB_CLK clock */ 2376 #endif 2377 #if defined(CLOCK_IP_HAS_STM1_CLK) 2378 0U, /* STM1_CLK clock */ 2379 #endif 2380 #if defined(CLOCK_IP_HAS_STMC_CLK) 2381 0U, /* STMC_CLK clock */ 2382 #endif 2383 #if defined(CLOCK_IP_HAS_STM2_CLK) 2384 0U, /* STM2_CLK clock */ 2385 #endif 2386 #if defined(CLOCK_IP_HAS_STMD_CLK) 2387 0U, /* STMD_CLK clock */ 2388 #endif 2389 #if defined(CLOCK_IP_HAS_STM3_CLK) 2390 0U, /* STM3_CLK clock */ 2391 #endif 2392 #if defined(CLOCK_IP_HAS_SWG_CLK) 2393 0U, /* SWG_CLK clock */ 2394 #endif 2395 #if defined(CLOCK_IP_HAS_SWG0_CLK) 2396 0U, /* SWG0_CLK clock */ 2397 #endif 2398 #if defined(CLOCK_IP_HAS_SWG1_CLK) 2399 0U, /* SWG1_CLK clock */ 2400 #endif 2401 0U, /* SWT0_CLK clock */ 2402 #if defined(CLOCK_IP_HAS_SWT1_CLK) 2403 0U, /* SWT1_CLK clock */ 2404 #endif 2405 #if defined(CLOCK_IP_HAS_SWT2_CLK) 2406 0U, /* SWT2_CLK clock */ 2407 #endif 2408 #if defined(CLOCK_IP_HAS_SWT3_CLK) 2409 0U, /* SWT3_CLK clock */ 2410 #endif 2411 #if defined(CLOCK_IP_HAS_TCM_CM7_0_CLK) 2412 0U, /* TCM_CM7_0_CLK clock */ 2413 #endif 2414 #if defined(CLOCK_IP_HAS_TCM_CM7_1_CLK) 2415 0U, /* TCM_CM7_1_CLK clock */ 2416 #endif 2417 0U, /* TEMPSENSE_CLK clock */ 2418 0U, /* TRACE_CLK clock */ 2419 0U, /* TRGMUX0_CLK clock */ 2420 #if defined(CLOCK_IP_HAS_TRGMUX1_CLK) 2421 0U, /* TRGMUX1_CLK clock */ 2422 #endif 2423 #if defined(CLOCK_IP_HAS_TSENSE0_CLK) 2424 0U, /* TSENSE0_CLK clock */ 2425 #endif 2426 #if defined(CLOCK_IP_HAS_USDHC_CLK) 2427 0U, /* USDHC_CLK clock */ 2428 #endif 2429 0U, /* WKPU0_CLK clock */ 2430 #if defined(CLOCK_IP_HAS_XRDC_CLK) 2431 0U, /* XRDC_CLK clock */ 2432 #endif 2433 }; 2434 2435 /* Clock stop constant section data */ 2436 #define MCU_STOP_SEC_CONST_8 2437 #include "Mcu_MemMap.h" 2438 2439 2440 2441 2442 /* Clock start constant section data */ 2443 #define MCU_START_SEC_CONST_16 2444 #include "Mcu_MemMap.h" 2445 /*! 2446 * @brief Converts a clock name to a selector entry hardware value 2447 */ 2448 const uint16 Clock_Ip_au16SelectorEntryHardwareValue[CLOCK_IP_PRODUCERS_NO] = { 2449 0U, /*!< CLOCK_IS_OFF */ 2450 0U, /*!< FIRC_CLK */ 2451 0U, /*!< FIRC_STANDBY_CLK */ 2452 1U, /*!< SIRC_CLK */ 2453 0U, /*!< SIRC_STANDBY_CLK */ 2454 2U, /*!< FXOSC_CLK */ 2455 #if defined(CLOCK_IP_HAS_SXOSC_CLK) 2456 4U, /*!< SXOSC_CLK */ 2457 #endif 2458 0U, /*!< PLL_CLK */ 2459 #if defined(CLOCK_IP_HAS_PLLAUX_CLK) 2460 0U, /*!< PLLAUX_CLK */ 2461 #endif 2462 0U, /*!< PLL_POSTDIV_CLK */ 2463 #if defined(CLOCK_IP_HAS_PLLAUX_POSTDIV_CLK) 2464 0U, /*!< PLLAUX_POSTDIV_CLK */ 2465 #endif 2466 8U, /*!< PLL_PHI0 */ 2467 9U, /*!< PLL_PHI1 */ 2468 #if defined(CLOCK_IP_HAS_PLLAUX_PHI0_CLK) 2469 12U, /*!< PLLAUX_PHI0_CLK */ 2470 #endif 2471 #if defined(CLOCK_IP_HAS_PLLAUX_PHI1_CLK) 2472 13U, /*!< PLLAUX_PHI1_CLK */ 2473 #endif 2474 #if defined(CLOCK_IP_HAS_PLLAUX_PHI2_CLK) 2475 14U, /*!< PLLAUX_PHI2_CLK */ 2476 #endif 2477 #if defined(CLOCK_IP_HAS_EMAC_MII_RX_CLK) 2478 25U, /*!< emac_mii_rx */ 2479 #endif 2480 #if defined(CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK) 2481 24U, /*!< emac_mii_rmii_tx */ 2482 #endif 2483 #if defined(CLOCK_IP_HAS_GMAC0_MII_RX_CLK) 2484 25U, /*!< GMAC0_mii_rx */ 2485 #endif 2486 #if defined(CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK) 2487 24U, /*!< GMAC0_mii_rmii_tx */ 2488 #endif 2489 #if defined(CLOCK_IP_HAS_LFAST_REF_EXT_CLK) 2490 27U, /*!< lfast_ext_ref */ 2491 #endif 2492 #if defined(CLOCK_IP_HAS_SWG_PAD_CLK) 2493 28U, /*!< swg_pad */ 2494 #endif 2495 0U, /*!< SCS_CLK */ 2496 16U, /*!< CORE_CLK */ 2497 22U, /*!< AIPS_PLAT_CLK */ 2498 23U, /*!< AIPS_SLOW_CLK */ 2499 19U, /*!< HSE_CLK */ 2500 0U, /*!< DCM_CLK */ 2501 #if defined(CLOCK_IP_HAS_LBIST_CLK) 2502 0U, /*!< LBIST_CLK */ 2503 #endif 2504 #if defined(CLOCK_IP_HAS_QSPI_MEM_CLK) 2505 0U, /*!< QSPI_MEM_CLK */ 2506 #endif 2507 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 2508 0U, /*!< CM7_CORE_CLK */ 2509 #endif 2510 50U, /*!< CLKOUT_RUN_CLK */ 2511 }; 2512 /*! 2513 * @brief Converts a clock name to a RTC selector entry hardware value 2514 */ 2515 const uint16 Clock_Ip_au16SelectorEntryRtcHardwareValue[CLOCK_IP_PRODUCERS_NO] = { 2516 0U, /*!< CLOCK_IS_OFF */ 2517 2U, /*!< FIRC_CLK */ 2518 0U, /*!< FIRC_STANDBY_CLK */ 2519 1U, /*!< SIRC_CLK */ 2520 0U, /*!< SIRC_STANDBY_CLK */ 2521 3U, /*!< FXOSC_CLK */ 2522 #if defined(CLOCK_IP_HAS_SXOSC_CLK) 2523 0U, /*!< SXOSC_CLK */ 2524 #endif 2525 0U, /*!< PLL_CLK */ 2526 #if defined(CLOCK_IP_HAS_PLLAUX_CLK) 2527 0U, /*!< PLLAUX_CLK */ 2528 #endif 2529 0U, /*!< PLL_POSTDIV_CLK */ 2530 #if defined(CLOCK_IP_HAS_PLLAUX_POSTDIV_CLK) 2531 0U, /*!< PLLAUX_POSTDIV_CLK */ 2532 #endif 2533 0U, /*!< PLL_PHI0_CLK */ 2534 0U, /*!< PLL_PHI1_CLK */ 2535 #if defined(CLOCK_IP_HAS_PLLAUX_PHI0_CLK) 2536 0U, /*!< PLLAUX_PHI0_CLK */ 2537 #endif 2538 #if defined(CLOCK_IP_HAS_PLLAUX_PHI1_CLK) 2539 0U, /*!< PLLAUX_PHI1_CLK */ 2540 #endif 2541 #if defined(CLOCK_IP_HAS_PLLAUX_PHI2_CLK) 2542 0U, /*!< PLLAUX_PHI2_CLK */ 2543 #endif 2544 #if defined(CLOCK_IP_HAS_EMAC_MII_RX_CLK) 2545 0U, /*!< EMAC_MII_RX_CLK */ 2546 #endif 2547 #if defined(CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK) 2548 0U, /*!< EMAC_MII_RMII_TX_CLK */ 2549 #endif 2550 #if defined(CLOCK_IP_HAS_GMAC0_MII_RX_CLK) 2551 0U, /*!< GMAC0_MII_RX_CLK */ 2552 #endif 2553 #if defined(CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK) 2554 0U, /*!< GMAC0_MII_RMII_TX_CLK */ 2555 #endif 2556 #if defined(CLOCK_IP_HAS_LFAST_REF_EXT_CLK) 2557 0U, /*!< LFAST_EXT_REF_CLK */ 2558 #endif 2559 #if defined(CLOCK_IP_HAS_SWG_PAD_CLK) 2560 0U, /*!< SWG_PAD_CLK */ 2561 #endif 2562 0U, /*!< SCS_CLK */ 2563 0U, /*!< CORE_CLK */ 2564 0U, /*!< AIPS_PLAT_CLK */ 2565 0U, /*!< AIPS_SLOW_CLK */ 2566 0U, /*!< HSE_CLK */ 2567 0U, /*!< DCM_CLK */ 2568 #if defined(CLOCK_IP_HAS_LBIST_CLK) 2569 0U, /*!< LBIST_CLK */ 2570 #endif 2571 #if defined(CLOCK_IP_HAS_QSPI_MEM_CLK) 2572 0U, /*!< QSPI_MEM_CLK */ 2573 #endif 2574 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 2575 0U, /*!< CM7_CORE_CLK */ 2576 #endif 2577 0U, /*!< CLKOUT_RUN_CLK */ 2578 }; 2579 2580 /* Clock stop constant section data */ 2581 #define MCU_STOP_SEC_CONST_16 2582 #include "Mcu_MemMap.h" 2583 2584 2585 2586 2587 /* Clock start constant section data */ 2588 #define MCU_START_SEC_CONST_32 2589 #include "Mcu_MemMap.h" 2590 2591 #if (defined(CLOCK_IP_DEV_ERROR_DETECT)) 2592 #if (CLOCK_IP_DEV_ERROR_DETECT == STD_ON) 2593 /* Clock name types */ 2594 const uint32 Clock_Ip_au8ClockNameTypes[CLOCK_IP_NAMES_NO] = 2595 { 2596 /* CLOCK_IS_OFF clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* CLOCK_IS_OFF clock */ 2597 /* FIRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FIRC_CLK clock */ 2598 /* FIRC_STANDBY_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FIRC_STANDBY_CLK clock */ 2599 /* SIRC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SIRC_CLK clock */ 2600 /* SIRC_STANDBY_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SIRC_STANDBY_CLK clock */ 2601 /* FXOSC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FXOSC_CLK clock */ 2602 #if defined(CLOCK_IP_HAS_SXOSC_CLK) 2603 /* SXOSC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SXOSC_CLK clock */ 2604 #endif 2605 /* PLL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* PLL_CLK clock */ 2606 #if defined(CLOCK_IP_HAS_PLLAUX_CLK) 2607 /* PLLAUX_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* PLLAUX_CLK clock */ 2608 #endif 2609 /* PLL_POSTDIV_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* PLL_POSTDIV_CLK clock */ 2610 #if defined(CLOCK_IP_HAS_PLLAUX_POSTDIV_CLK) 2611 /* PLLAUX_POSTDIV_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* PLLAUX_POSTDIV_CLK clock */ 2612 #endif 2613 /* PLL_PHI0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* PLL_PHI0_CLK clock */ 2614 /* PLL_PHI1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* PLL_PHI1_CLK clock */ 2615 #if defined(CLOCK_IP_HAS_PLLAUX_PHI0_CLK) 2616 /* PLLAUX_PHI0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* PLLAUX_PHI0_CLK clock */ 2617 #endif 2618 #if defined(CLOCK_IP_HAS_PLLAUX_PHI1_CLK) 2619 /* PLLAUX_PHI1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* PLLAUX_PHI1_CLK clock */ 2620 #endif 2621 #if defined(CLOCK_IP_HAS_PLLAUX_PHI2_CLK) 2622 /* PLLAUX_PHI2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* PLLAUX_PHI2_CLK clock */ 2623 #endif 2624 #if defined(CLOCK_IP_HAS_EMAC_MII_RX_CLK) 2625 /* EMAC_MII_RX_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EMAC_MII_RX_CLK clock */ 2626 #endif 2627 #if defined(CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK) 2628 /* EMAC_MII_RMII_TX_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EMAC_MII_RMII_TX_CLK clock */ 2629 #endif 2630 #if defined(CLOCK_IP_HAS_GMAC0_MII_RX_CLK) 2631 /* GMAC0_MII_RX_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* GMAC0_MII_RX_CLK clock */ 2632 #endif 2633 #if defined(CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK) 2634 /* GMAC0_MII_RMII_TX_CLK clock*/ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* GMAC0_MII_RMII_TX_CLK clock */ 2635 #endif 2636 #if defined(CLOCK_IP_HAS_LFAST_REF_EXT_CLK) 2637 /* LFAST_EXT_REF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LFAST_EXT_REF_CLK clock */ 2638 #endif 2639 #if defined(CLOCK_IP_HAS_SWG_PAD_CLK) 2640 /* SWG_PAD_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SWG_PAD_CLK clock */ 2641 #endif 2642 /* SCS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SCS_CLK clock */ 2643 /* CORE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* CORE_CLK clock */ 2644 /* AIPS_PLAT_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* AIPS_PLAT_CLK clock */ 2645 /* AIPS_SLOW_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* AIPS_SLOW_CLK clock */ 2646 /* HSE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* HSE_CLK clock */ 2647 /* DCM_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* DCM_CLK clock */ 2648 #if defined(CLOCK_IP_HAS_LBIST_CLK) 2649 /* LBIST_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LBIST_CLK clock */ 2650 #endif 2651 #if defined(CLOCK_IP_HAS_QSPI_MEM_CLK) 2652 /* QSPI_MEM_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* QSPI_MEM_CLK clock */ 2653 #endif 2654 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 2655 /* CM7_CORE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* CM7_CORE_CLK clock */ 2656 #endif 2657 /* CLKOUT_RUN_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* CLKOUT_RUN_CLK clock */ 2658 /* THE_LAST_PRODUCER_CLK */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* THE_LAST_PRODUCER_CLK */ 2659 /* ADC0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* ADC0_CLK clock */ 2660 /* ADC1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* ADC1_CLK clock */ 2661 #if defined(CLOCK_IP_HAS_ADC2_CLK) 2662 /* ADC2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* ADC2_CLK clock */ 2663 #endif 2664 #if defined(CLOCK_IP_HAS_ADC3_CLK) 2665 /* ADC3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* ADC3_CLK clock */ 2666 #endif 2667 #if defined(CLOCK_IP_HAS_ADC4_CLK) 2668 /* ADC4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* ADC4_CLK clock */ 2669 #endif 2670 #if defined(CLOCK_IP_HAS_ADC5_CLK) 2671 /* ADC5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* ADC5_CLK clock */ 2672 #endif 2673 #if defined(CLOCK_IP_HAS_ADC6_CLK) 2674 /* ADC6_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* ADC6_CLK clock */ 2675 #endif 2676 #if defined(CLOCK_IP_HAS_ADCBIST_CLK) 2677 /* ADCBIST_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* ADCBIST_CLK clock */ 2678 #endif 2679 #if defined(CLOCK_IP_HAS_AES_ACCEL_CLK) 2680 /* AES_ACCEL_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* AES_ACCEL_CLK clock */ 2681 #endif 2682 #if defined(CLOCK_IP_HAS_AES_APP0_CLK) 2683 /* AES_APP0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* AES_APP0_CLK clock */ 2684 #endif 2685 #if defined(CLOCK_IP_HAS_AES_APP1_CLK) 2686 /* AES_APP1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* AES_APP1_CLK clock */ 2687 #endif 2688 #if defined(CLOCK_IP_HAS_AES_APP2_CLK) 2689 /* AES_APP2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* AES_APP2_CLK clock */ 2690 #endif 2691 #if defined(CLOCK_IP_HAS_AES_APP3_CLK) 2692 /* AES_APP3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* AES_APP3_CLK clock */ 2693 #endif 2694 #if defined(CLOCK_IP_HAS_AES_APP4_CLK) 2695 /* AES_APP4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* AES_APP4_CLK clock */ 2696 #endif 2697 #if defined(CLOCK_IP_HAS_AES_APP5_CLK) 2698 /* AES_APP5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* AES_APP5_CLK clock */ 2699 #endif 2700 #if defined(CLOCK_IP_HAS_AES_APP6_CLK) 2701 /* AES_APP6_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* AES_APP6_CLK clock */ 2702 #endif 2703 #if defined(CLOCK_IP_HAS_AES_APP7_CLK) 2704 /* AES_APP7_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* AES_APP7_CLK clock */ 2705 #endif 2706 #if defined(CLOCK_IP_HAS_AES_CLK) 2707 /* AES_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* AES_CLK clock */ 2708 #endif 2709 #if defined(CLOCK_IP_HAS_AXBS_CLK) 2710 /* AXBS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* AXBS_CLK clock */ 2711 #endif 2712 #if defined(CLOCK_IP_HAS_AXBS0_CLK) 2713 /* AXBS0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* AXBS0_CLK clock */ 2714 #endif 2715 #if defined(CLOCK_IP_HAS_AXBS1_CLK) 2716 /* AXBS1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* AXBS1_CLK clock */ 2717 #endif 2718 /* BCTU0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* BCTU0_CLK clock */ 2719 #if defined(CLOCK_IP_HAS_BCTU1_CLK) 2720 /* BCTU1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* BCTU1_CLK clock */ 2721 #endif 2722 /* CLKOUT_STANDBY_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* CLKOUT_STANDBY_CLK clock */ 2723 /* CMP0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* CMP0_CLK clock */ 2724 #if defined(CLOCK_IP_HAS_CMP1_CLK) 2725 /* CMP1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* CMP1_CLK clock */ 2726 #endif 2727 #if defined(CLOCK_IP_HAS_CMP2_CLK) 2728 /* CMP2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* CMP2_CLK clock */ 2729 #endif 2730 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM0_CLK) 2731 /* COOLFLUX_D_RAM0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* COOLFLUX_D_RAM0_CLK clock */ 2732 #endif 2733 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM1_CLK) 2734 /* COOLFLUX_D_RAM1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* COOLFLUX_D_RAM1_CLK clock */ 2735 #endif 2736 #if defined(CLOCK_IP_HAS_COOLFLUX_DSP16L_CLK) 2737 /* COOLFLUX_DSP16L_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* COOLFLUX_DSP16L_CLK clock */ 2738 #endif 2739 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM0_CLK) 2740 /* COOLFLUX_I_RAM0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* COOLFLUX_I_RAM0_CLK clock */ 2741 #endif 2742 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM1_CLK) 2743 /* COOLFLUX_I_RAM1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* COOLFLUX_I_RAM1_CLK clock */ 2744 #endif 2745 /* CRC0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* CRC0_CLK clock */ 2746 /* DCM0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* DCM0_CLK clock */ 2747 /* DMAMUX0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* DMAMUX0_CLK clock */ 2748 /* DMAMUX1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* DMAMUX1_CLK clock */ 2749 #if defined(CLOCK_IP_HAS_DMAMUX2_CLK) 2750 /* DMAMUX2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* DMAMUX2_CLK clock */ 2751 #endif 2752 #if defined(CLOCK_IP_HAS_DMAMUX3_CLK) 2753 /* DMAMUX3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* DMAMUX3_CLK clock */ 2754 #endif 2755 #if defined(CLOCK_IP_HAS_DSPI_MSC_CLK) 2756 /* DSPI_MSC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* DSPI_MSC_CLK clock */ 2757 #endif 2758 /* EDMA0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_CLK clock */ 2759 /* EDMA0_TCD0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD0_CLK clock */ 2760 /* EDMA0_TCD1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD1_CLK clock */ 2761 /* EDMA0_TCD2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD2_CLK clock */ 2762 /* EDMA0_TCD3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD3_CLK clock */ 2763 /* EDMA0_TCD4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD4_CLK clock */ 2764 /* EDMA0_TCD5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD5_CLK clock */ 2765 /* EDMA0_TCD6_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD6_CLK clock */ 2766 /* EDMA0_TCD7_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD7_CLK clock */ 2767 /* EDMA0_TCD8_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD8_CLK clock */ 2768 /* EDMA0_TCD9_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD9_CLK clock */ 2769 /* EDMA0_TCD10_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD10_CLK clock */ 2770 /* EDMA0_TCD11_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD11_CLK clock */ 2771 #if defined(CLOCK_IP_HAS_EDMA0_TCD12_CLK) 2772 /* EDMA0_TCD12_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD12_CLK clock */ 2773 #endif 2774 #if defined(CLOCK_IP_HAS_EDMA0_TCD13_CLK) 2775 /* EDMA0_TCD13_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD13_CLK clock */ 2776 #endif 2777 #if defined(CLOCK_IP_HAS_EDMA0_TCD14_CLK) 2778 /* EDMA0_TCD14_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD14_CLK clock */ 2779 #endif 2780 #if defined(CLOCK_IP_HAS_EDMA0_TCD15_CLK) 2781 /* EDMA0_TCD15_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD15_CLK clock */ 2782 #endif 2783 #if defined(CLOCK_IP_HAS_EDMA0_TCD16_CLK) 2784 /* EDMA0_TCD16_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD16_CLK clock */ 2785 #endif 2786 #if defined(CLOCK_IP_HAS_EDMA0_TCD17_CLK) 2787 /* EDMA0_TCD17_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD17_CLK clock */ 2788 #endif 2789 #if defined(CLOCK_IP_HAS_EDMA0_TCD18_CLK) 2790 /* EDMA0_TCD18_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD18_CLK clock */ 2791 #endif 2792 #if defined(CLOCK_IP_HAS_EDMA0_TCD19_CLK) 2793 /* EDMA0_TCD19_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD19_CLK clock */ 2794 #endif 2795 #if defined(CLOCK_IP_HAS_EDMA0_TCD20_CLK) 2796 /* EDMA0_TCD20_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD20_CLK clock */ 2797 #endif 2798 #if defined(CLOCK_IP_HAS_EDMA0_TCD21_CLK) 2799 /* EDMA0_TCD21_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD21_CLK clock */ 2800 #endif 2801 #if defined(CLOCK_IP_HAS_EDMA0_TCD22_CLK) 2802 /* EDMA0_TCD22_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD22_CLK clock */ 2803 #endif 2804 #if defined(CLOCK_IP_HAS_EDMA0_TCD23_CLK) 2805 /* EDMA0_TCD23_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD23_CLK clock */ 2806 #endif 2807 #if defined(CLOCK_IP_HAS_EDMA0_TCD24_CLK) 2808 /* EDMA0_TCD24_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD24_CLK clock */ 2809 #endif 2810 #if defined(CLOCK_IP_HAS_EDMA0_TCD25_CLK) 2811 /* EDMA0_TCD25_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD25_CLK clock */ 2812 #endif 2813 #if defined(CLOCK_IP_HAS_EDMA0_TCD26_CLK) 2814 /* EDMA0_TCD26_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD26_CLK clock */ 2815 #endif 2816 #if defined(CLOCK_IP_HAS_EDMA0_TCD27_CLK) 2817 /* EDMA0_TCD27_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD27_CLK clock */ 2818 #endif 2819 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 2820 /* EDMA0_TCD28_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD28_CLK clock */ 2821 #endif 2822 #if defined(CLOCK_IP_HAS_EDMA0_TCD29_CLK) 2823 /* EDMA0_TCD29_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD29_CLK clock */ 2824 #endif 2825 #if defined(CLOCK_IP_HAS_EDMA0_TCD30_CLK) 2826 /* EDMA0_TCD30_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD30_CLK clock */ 2827 #endif 2828 #if defined(CLOCK_IP_HAS_EDMA0_TCD31_CLK) 2829 /* EDMA0_TCD31_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA0_TCD31_CLK clock */ 2830 #endif 2831 #if defined(CLOCK_IP_HAS_EDMA1_CLK) 2832 /* EDMA1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_CLK clock */ 2833 #endif 2834 #if defined(CLOCK_IP_HAS_EDMA1_TCD0_CLK) 2835 /* EDMA1_TCD0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD0_CLK clock */ 2836 #endif 2837 #if defined(CLOCK_IP_HAS_EDMA1_TCD1_CLK) 2838 /* EDMA1_TCD1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD1_CLK clock */ 2839 #endif 2840 #if defined(CLOCK_IP_HAS_EDMA1_TCD2_CLK) 2841 /* EDMA1_TCD2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD2_CLK clock */ 2842 #endif 2843 #if defined(CLOCK_IP_HAS_EDMA1_TCD3_CLK) 2844 /* EDMA1_TCD3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD3_CLK clock */ 2845 #endif 2846 #if defined(CLOCK_IP_HAS_EDMA1_TCD4_CLK) 2847 /* EDMA1_TCD4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD4_CLK clock */ 2848 #endif 2849 #if defined(CLOCK_IP_HAS_EDMA1_TCD5_CLK) 2850 /* EDMA1_TCD5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD5_CLK clock */ 2851 #endif 2852 #if defined(CLOCK_IP_HAS_EDMA1_TCD6_CLK) 2853 /* EDMA1_TCD6_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD6_CLK clock */ 2854 #endif 2855 #if defined(CLOCK_IP_HAS_EDMA1_TCD7_CLK) 2856 /* EDMA1_TCD7_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD7_CLK clock */ 2857 #endif 2858 #if defined(CLOCK_IP_HAS_EDMA1_TCD8_CLK) 2859 /* EDMA1_TCD8_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD8_CLK clock */ 2860 #endif 2861 #if defined(CLOCK_IP_HAS_EDMA1_TCD9_CLK) 2862 /* EDMA1_TCD9_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD9_CLK clock */ 2863 #endif 2864 #if defined(CLOCK_IP_HAS_EDMA1_TCD10_CLK) 2865 /* EDMA1_TCD10_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD10_CLK clock */ 2866 #endif 2867 #if defined(CLOCK_IP_HAS_EDMA1_TCD11_CLK) 2868 /* EDMA1_TCD11_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD11_CLK clock */ 2869 #endif 2870 #if defined(CLOCK_IP_HAS_EDMA1_TCD12_CLK) 2871 /* EDMA1_TCD12_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD12_CLK clock */ 2872 #endif 2873 #if defined(CLOCK_IP_HAS_EDMA1_TCD13_CLK) 2874 /* EDMA1_TCD13_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD13_CLK clock */ 2875 #endif 2876 #if defined(CLOCK_IP_HAS_EDMA1_TCD14_CLK) 2877 /* EDMA1_TCD14_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD14_CLK clock */ 2878 #endif 2879 #if defined(CLOCK_IP_HAS_EDMA1_TCD15_CLK) 2880 /* EDMA1_TCD15_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD15_CLK clock */ 2881 #endif 2882 #if defined(CLOCK_IP_HAS_EDMA1_TCD16_CLK) 2883 /* EDMA1_TCD16_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD16_CLK clock */ 2884 #endif 2885 #if defined(CLOCK_IP_HAS_EDMA1_TCD17_CLK) 2886 /* EDMA1_TCD17_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD17_CLK clock */ 2887 #endif 2888 #if defined(CLOCK_IP_HAS_EDMA1_TCD18_CLK) 2889 /* EDMA1_TCD18_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD18_CLK clock */ 2890 #endif 2891 #if defined(CLOCK_IP_HAS_EDMA1_TCD19_CLK) 2892 /* EDMA1_TCD19_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD19_CLK clock */ 2893 #endif 2894 #if defined(CLOCK_IP_HAS_EDMA1_TCD20_CLK) 2895 /* EDMA1_TCD20_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD20_CLK clock */ 2896 #endif 2897 #if defined(CLOCK_IP_HAS_EDMA1_TCD21_CLK) 2898 /* EDMA1_TCD21_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD21_CLK clock */ 2899 #endif 2900 #if defined(CLOCK_IP_HAS_EDMA1_TCD22_CLK) 2901 /* EDMA1_TCD22_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD22_CLK clock */ 2902 #endif 2903 #if defined(CLOCK_IP_HAS_EDMA1_TCD23_CLK) 2904 /* EDMA1_TCD23_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD23_CLK clock */ 2905 #endif 2906 #if defined(CLOCK_IP_HAS_EDMA1_TCD24_CLK) 2907 /* EDMA1_TCD24_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD24_CLK clock */ 2908 #endif 2909 #if defined(CLOCK_IP_HAS_EDMA1_TCD25_CLK) 2910 /* EDMA1_TCD25_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD25_CLK clock */ 2911 #endif 2912 #if defined(CLOCK_IP_HAS_EDMA1_TCD26_CLK) 2913 /* EDMA1_TCD26_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD26_CLK clock */ 2914 #endif 2915 #if defined(CLOCK_IP_HAS_EDMA1_TCD27_CLK) 2916 /* EDMA1_TCD27_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD27_CLK clock */ 2917 #endif 2918 #if defined(CLOCK_IP_HAS_EDMA1_TCD28_CLK) 2919 /* EDMA1_TCD28_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD28_CLK clock */ 2920 #endif 2921 #if defined(CLOCK_IP_HAS_EDMA1_TCD29_CLK) 2922 /* EDMA1_TCD29_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD29_CLK clock */ 2923 #endif 2924 #if defined(CLOCK_IP_HAS_EDMA1_TCD30_CLK) 2925 /* EDMA1_TCD30_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD30_CLK clock */ 2926 #endif 2927 #if defined(CLOCK_IP_HAS_EDMA1_TCD31_CLK) 2928 /* EDMA1_TCD31_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EDMA1_TCD31_CLK clock */ 2929 #endif 2930 #if defined(CLOCK_IP_HAS_EFLEX_PWM0_CLK) 2931 /* EFLEX_PWM0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EFLEX_PWM0_CLK clock */ 2932 #endif 2933 #if defined(CLOCK_IP_HAS_EFLEX_PWM1_CLK) 2934 /* EFLEX_PWM1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EFLEX_PWM1_CLK clock */ 2935 #endif 2936 #if defined(CLOCK_IP_HAS_EIM_CLK) 2937 /* EIM_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EIM_CLK clock */ 2938 #endif 2939 #if defined(CLOCK_IP_HAS_EIM0_CLK) 2940 /* EIM0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EIM0_CLK clock */ 2941 #endif 2942 #if defined(CLOCK_IP_HAS_EIM1_CLK) 2943 /* EIM1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EIM1_CLK clock */ 2944 #endif 2945 #if defined(CLOCK_IP_HAS_EIM2_CLK) 2946 /* EIM2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EIM2_CLK clock */ 2947 #endif 2948 #if defined(CLOCK_IP_HAS_EIM3_CLK) 2949 /* EIM3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EIM3_CLK clock */ 2950 #endif 2951 #if defined(CLOCK_IP_HAS_EMAC_RX_CLK) 2952 /* EMAC_RX_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EMAC_RX_CLK clock */ 2953 #endif 2954 #if defined(CLOCK_IP_HAS_EMAC0_RX_CLK) 2955 /* EMAC0_RX_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EMAC0_RX_CLK clock */ 2956 #endif 2957 #if defined(CLOCK_IP_HAS_EMAC_TS_CLK) 2958 /* EMAC_TS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EMAC_TS_CLK clock */ 2959 #endif 2960 #if defined(CLOCK_IP_HAS_EMAC0_TS_CLK) 2961 /* EMAC0_TS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EMAC0_TS_CLK clock */ 2962 #endif 2963 #if defined(CLOCK_IP_HAS_EMAC_TX_CLK) 2964 /* EMAC_TX_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EMAC_TX_CLK clock */ 2965 #endif 2966 #if defined(CLOCK_IP_HAS_EMAC0_TX_CLK) 2967 /* EMAC0_TX_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EMAC0_TX_CLK clock */ 2968 #endif 2969 #if defined(CLOCK_IP_HAS_EMAC_TX_RMII_CLK) 2970 /* EMAC_TX_RMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EMAC_TX_RMII_CLK clock */ 2971 #endif 2972 #if defined(CLOCK_IP_HAS_EMAC0_TX_RMII_CLK) 2973 /* EMAC0_TX_RMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EMAC0_TX_RMII_CLK clock */ 2974 #endif 2975 /* EMIOS0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EMIOS0_CLK clock */ 2976 #if defined(CLOCK_IP_HAS_EMIOS1_CLK) 2977 /* EMIOS1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EMIOS1_CLK clock */ 2978 #endif 2979 #if defined(CLOCK_IP_HAS_EMIOS2_CLK) 2980 /* EMIOS2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* EMIOS2_CLK clock */ 2981 #endif 2982 /* ERM0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* ERM0_CLK clock */ 2983 #if defined(CLOCK_IP_HAS_ERM1_CLK) 2984 /* ERM1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* ERM1_CLK clock */ 2985 #endif 2986 #if defined(CLOCK_IP_HAS_ETPU_AB_REGISTERS_CLK) 2987 /* ETPU_AB_REGISTERS_CLK clock*/ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* ETPU_AB_REGISTERS_CLK clock*/ 2988 #endif 2989 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM1_CLK) 2990 /* ETPU_CODE_RAM1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* ETPU_CODE_RAM1_CLK clock */ 2991 #endif 2992 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM2_CLK) 2993 /* ETPU_CODE_RAM2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* ETPU_CODE_RAM2_CLK clock */ 2994 #endif 2995 #if defined(CLOCK_IP_HAS_ETPU_RAM_MIRROR_CLK) 2996 /* ETPU_RAM_MIRROR_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* ETPU_RAM_MIRROR_CLK clock */ 2997 #endif 2998 #if defined(CLOCK_IP_HAS_ETPU_RAM_SDM_CLK) 2999 /* ETPU_RAM_SDM_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* ETPU_RAM_SDM_CLK clock */ 3000 #endif 3001 #if defined(CLOCK_IP_HAS_FCCU_CLK) 3002 /* FCCU_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FCCU_CLK clock */ 3003 #endif 3004 #if defined(CLOCK_IP_HAS_FLASH0_CLK) 3005 /* FLASH0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FLASH0_CLK clock */ 3006 #endif 3007 #if defined(CLOCK_IP_HAS_FLASH0_ALT_CLK) 3008 /* FLASH0_ALT_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FLASH0_ALT_CLK clock */ 3009 #endif 3010 #if defined(CLOCK_IP_HAS_FLASH1_CLK) 3011 /* FLASH1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FLASH1_CLK clock */ 3012 #endif 3013 #if defined(CLOCK_IP_HAS_FLASH1_ALT_CLK) 3014 /* FLASH1_ALT_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FLASH1_ALT_CLK clock */ 3015 #endif 3016 /* FLEXCANA_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FLEXCANA_CLK clock */ 3017 /* FLEXCAN0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FLEXCAN0_CLK clock */ 3018 /* FLEXCAN1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FLEXCAN1_CLK clock */ 3019 /* FLEXCAN2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FLEXCAN2_CLK clock */ 3020 #if defined(CLOCK_IP_HAS_FLEXCANB_CLK) 3021 /* FLEXCANB_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FLEXCANB_CLK clock */ 3022 #endif 3023 #if defined(CLOCK_IP_HAS_FLEXCAN3_CLK) 3024 /* FLEXCAN3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FLEXCAN3_CLK clock */ 3025 #endif 3026 #if defined(CLOCK_IP_HAS_FLEXCAN4_CLK) 3027 /* FLEXCAN4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FLEXCAN4_CLK clock */ 3028 #endif 3029 #if defined(CLOCK_IP_HAS_FLEXCAN5_CLK) 3030 /* FLEXCAN5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FLEXCAN5_CLK clock */ 3031 #endif 3032 #if defined(CLOCK_IP_HAS_FLEXCAN6_CLK) 3033 /* FLEXCAN6_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FLEXCAN6_CLK clock */ 3034 #endif 3035 #if defined(CLOCK_IP_HAS_FLEXCAN7_CLK) 3036 /* FLEXCAN7_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FLEXCAN7_CLK clock */ 3037 #endif 3038 /* FLEXIO0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* FLEXIO0_CLK clock */ 3039 #if defined(CLOCK_IP_HAS_HSE_MU0_CLK) 3040 /* HSE_MU0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* HSE_MU0_CLK clock */ 3041 #endif 3042 #if defined(CLOCK_IP_HAS_HSE_MU1_CLK) 3043 /* HSE_MU1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* HSE_MU1_CLK clock */ 3044 #endif 3045 #if defined(CLOCK_IP_HAS_JDC_CLK) 3046 /* JDC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* JDC_CLK clock */ 3047 #endif 3048 #if defined(CLOCK_IP_HAS_IGF0_CLK) 3049 /* IGF0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* IGF0_CLK clock */ 3050 #endif 3051 #if defined(CLOCK_IP_HAS_GMAC0_CLK) 3052 /* GMAC0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* GMAC0_CLK clock */ 3053 #endif 3054 #if defined(CLOCK_IP_HAS_GMAC1_CLK) 3055 /* GMAC1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* GMAC1_CLK clock */ 3056 #endif 3057 #if defined(CLOCK_IP_HAS_GMAC0_RX_CLK) 3058 /* GMAC0_RX_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* GMAC0_RX_CLK clock */ 3059 #endif 3060 #if defined(CLOCK_IP_HAS_GMAC0_TX_CLK) 3061 /* GMAC0_TX_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* GMAC0_TX_CLK clock */ 3062 #endif 3063 #if defined(CLOCK_IP_HAS_GMAC_TS_CLK) 3064 /* GMAC_TS_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* GMAC_TS_CLK clock */ 3065 #endif 3066 #if defined(CLOCK_IP_HAS_GMAC0_TX_RMII_CLK) 3067 /* GMAC0_TX_RMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* GMAC0_TX_RMII_CLK clock */ 3068 #endif 3069 #if defined(CLOCK_IP_HAS_GMAC1_RX_CLK) 3070 /* GMAC1_RX_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* GMAC1_RX_CLK clock */ 3071 #endif 3072 #if defined(CLOCK_IP_HAS_GMAC1_TX_CLK) 3073 /* GMAC1_TX_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* GMAC1_TX_CLK clock */ 3074 #endif 3075 #if defined(CLOCK_IP_HAS_GMAC1_RMII_CLK) 3076 /* GMAC1_RMII_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* GMAC1_RMII_CLK clock */ 3077 #endif 3078 /* INTM_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* INTM_CLK clock */ 3079 /* LCU0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LCU0_CLK clock */ 3080 /* LCU1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LCU1_CLK clock */ 3081 #if defined(CLOCK_IP_HAS_LFAST_REF_CLK) 3082 /* LFAST_REF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LFAST_REF_CLK clock */ 3083 #endif 3084 #if defined(CLOCK_IP_HAS_LPI2C0_CLK) 3085 /* LPI2C0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPI2C0_CLK clock */ 3086 #endif 3087 /* LPI2C1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPI2C1_CLK clock */ 3088 /* LPSPI0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPSPI0_CLK clock */ 3089 /* LPSPI1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPSPI1_CLK clock */ 3090 /* LPSPI2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPSPI2_CLK clock */ 3091 /* LPSPI3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPSPI3_CLK clock */ 3092 #if defined(CLOCK_IP_HAS_LPSPI4_CLK) 3093 /* LPSPI4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPSPI4_CLK clock */ 3094 #endif 3095 #if defined(CLOCK_IP_HAS_LPSPI5_CLK) 3096 /* LPSPI5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPSPI5_CLK clock */ 3097 #endif 3098 /* LPUART0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART0_CLK clock */ 3099 /* LPUART1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART1_CLK clock */ 3100 /* LPUART2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART2_CLK clock */ 3101 /* LPUART3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART3_CLK clock */ 3102 #if defined(CLOCK_IP_HAS_LPUART4_CLK) 3103 /* LPUART4_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART4_CLK clock */ 3104 #endif 3105 #if defined(CLOCK_IP_HAS_LPUART5_CLK) 3106 /* LPUART5_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART5_CLK clock */ 3107 #endif 3108 #if defined(CLOCK_IP_HAS_LPUART6_CLK) 3109 /* LPUART6_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART6_CLK clock */ 3110 #endif 3111 #if defined(CLOCK_IP_HAS_LPUART7_CLK) 3112 /* LPUART7_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART7_CLK clock */ 3113 #endif 3114 #if defined(CLOCK_IP_HAS_LPUART8_CLK) 3115 /* LPUART8_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART8_CLK clock */ 3116 #endif 3117 #if defined(CLOCK_IP_HAS_LPUART9_CLK) 3118 /* LPUART9_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART9_CLK clock */ 3119 #endif 3120 #if defined(CLOCK_IP_HAS_LPUART10_CLK) 3121 /* LPUART10_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART10_CLK clock */ 3122 #endif 3123 #if defined(CLOCK_IP_HAS_LPUART11_CLK) 3124 /* LPUART11_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART11_CLK clock */ 3125 #endif 3126 #if defined(CLOCK_IP_HAS_LPUART12_CLK) 3127 /* LPUART12_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART12_CLK clock */ 3128 #endif 3129 #if defined(CLOCK_IP_HAS_LPUART13_CLK) 3130 /* LPUART13_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART13_CLK clock */ 3131 #endif 3132 #if defined(CLOCK_IP_HAS_LPUART14_CLK) 3133 /* LPUART14_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART14_CLK clock */ 3134 #endif 3135 #if defined(CLOCK_IP_HAS_LPUART15_CLK) 3136 /* LPUART15_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART15_CLK clock */ 3137 #endif 3138 #if defined(CLOCK_IP_HAS_LPUART_MSC_CLK) 3139 /* LPUART_MSC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* LPUART_MSC_CLK clock */ 3140 #endif 3141 /* MSCM_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* MSCM_CLK clock */ 3142 #if defined(CLOCK_IP_HAS_MU2A_CLK) 3143 /* MU2A_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* MU2A_CLK clock */ 3144 #endif 3145 #if defined(CLOCK_IP_HAS_MU2B_CLK) 3146 /* MU2B_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* MU2B_CLK clock */ 3147 #endif 3148 #if defined(CLOCK_IP_HAS_MU3A_CLK) 3149 /* MU3A_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* MU3A_CLK clock */ 3150 #endif 3151 #if defined(CLOCK_IP_HAS_MU3B_CLK) 3152 /* MU3B_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* MU3B_CLK clock */ 3153 #endif 3154 #if defined(CLOCK_IP_HAS_MU4A_CLK) 3155 /* MU4A_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* MU4A_CLK clock */ 3156 #endif 3157 #if defined(CLOCK_IP_HAS_MU4B_CLK) 3158 /* MU4B_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* MU4B_CLK clock */ 3159 #endif 3160 /* PIT0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* PIT0_CLK clock */ 3161 /* PIT1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* PIT1_CLK clock */ 3162 #if defined(CLOCK_IP_HAS_PIT2_CLK) 3163 /* PIT2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* PIT2_CLK clock */ 3164 #endif 3165 #if defined(CLOCK_IP_HAS_PIT3_CLK) 3166 /* PIT3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* PIT3_CLK clock */ 3167 #endif 3168 #if defined(CLOCK_IP_HAS_PRAMC0_CLK) 3169 /* PRAMC0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* PRAMC0_CLK clock */ 3170 #endif 3171 #if defined(CLOCK_IP_HAS_PRAMC1_CLK) 3172 /* PRAMC1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* PRAMC1_CLK clock */ 3173 #endif 3174 #if defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK) 3175 /* QSPI_2XSFIF_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* QSPI_2XSFIF_CLK clock */ 3176 #endif 3177 #if defined(CLOCK_IP_HAS_QSPI0_CLK) 3178 /* QSPI0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* QSPI0_CLK clock */ 3179 #endif 3180 #if defined(CLOCK_IP_HAS_QSPI0_RAM_CLK) 3181 /* QSPI0_RAM_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* QSPI0_RAM_CLK clock */ 3182 #endif 3183 #if defined(CLOCK_IP_HAS_QSPI0_TX_MEM_CLK) 3184 /* QSPI0_TX_MEM_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* QSPI0_TX_MEM_CLK clock */ 3185 #endif 3186 #if defined(CLOCK_IP_HAS_QSPI_SFCK_CLK) 3187 /* QSPI_SFCK_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* QSPI_SFCK_CLK clock */ 3188 #endif 3189 /* RTC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* RTC_CLK clock */ 3190 /* RTC0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* RTC0_CLK clock */ 3191 #if defined(CLOCK_IP_HAS_SAI0_CLK) 3192 /* SAI0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SAI0_CLK clock */ 3193 #endif 3194 #if defined(CLOCK_IP_HAS_SAI1_CLK) 3195 /* SAI1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SAI1_CLK clock */ 3196 #endif 3197 #if defined(CLOCK_IP_HAS_SDA_AP_CLK) 3198 /* SDA_AP_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SDA_AP_CLK clock */ 3199 #endif 3200 #if defined(CLOCK_IP_HAS_SDADC0_CLK) 3201 /* SDADC0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SDADC0_CLK clock */ 3202 #endif 3203 #if defined(CLOCK_IP_HAS_SDADC1_CLK) 3204 /* SDADC1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SDADC1_CLK clock */ 3205 #endif 3206 #if defined(CLOCK_IP_HAS_SDADC2_CLK) 3207 /* SDADC2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SDADC2_CLK clock */ 3208 #endif 3209 #if defined(CLOCK_IP_HAS_SDADC3_CLK) 3210 /* SDADC3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SDADC3_CLK clock */ 3211 #endif 3212 #if defined(CLOCK_IP_HAS_SEMA42_CLK) 3213 /* SEMA42_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SEMA42_CLK clock */ 3214 #endif 3215 #if defined(CLOCK_IP_HAS_SIPI0_CLK) 3216 /* SIPI0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SIPI0_CLK clock */ 3217 #endif 3218 /* SIUL2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SIUL2_CLK clock */ 3219 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_0_CLK) 3220 /* SIUL2_PDAC0_0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SIUL2_PDAC0_0_CLK clock */ 3221 #endif 3222 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_1_CLK) 3223 /* SIUL2_PDAC0_1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SIUL2_PDAC0_1_CLK clock */ 3224 #endif 3225 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_0_CLK) 3226 /* SIUL2_PDAC1_0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SIUL2_PDAC1_0_CLK clock */ 3227 #endif 3228 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_1_CLK) 3229 /* SIUL2_PDAC1_1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SIUL2_PDAC1_1_CLK clock */ 3230 #endif 3231 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_0_CLK) 3232 /* SIUL2_PDAC2_0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SIUL2_PDAC2_0_CLK clock */ 3233 #endif 3234 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_1_CLK) 3235 /* SIUL2_PDAC2_1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SIUL2_PDAC2_1_CLK clock */ 3236 #endif 3237 /* STCU0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* STCU0_CLK clock */ 3238 /* STMA_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* STMA_CLK clock */ 3239 /* STM0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* STM0_CLK clock */ 3240 #if defined(CLOCK_IP_HAS_STMB_CLK) 3241 /* STMB_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* STMB_CLK clock */ 3242 #endif 3243 #if defined(CLOCK_IP_HAS_STM1_CLK) 3244 /* STM1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* STM1_CLK clock */ 3245 #endif 3246 #if defined(CLOCK_IP_HAS_STMC_CLK) 3247 /* STMC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* STMC_CLK clock */ 3248 #endif 3249 #if defined(CLOCK_IP_HAS_STM2_CLK) 3250 /* STM2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* STM2_CLK clock */ 3251 #endif 3252 #if defined(CLOCK_IP_HAS_STMD_CLK) 3253 /* STMD_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* STMD_CLK clock */ 3254 #endif 3255 #if defined(CLOCK_IP_HAS_STM3_CLK) 3256 /* STM3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* STM3_CLK clock */ 3257 #endif 3258 #if defined(CLOCK_IP_HAS_SWG_CLK) 3259 /* SWG_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SWG_CLK clock */ 3260 #endif 3261 #if defined(CLOCK_IP_HAS_SWG0_CLK) 3262 /* SWG0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SWG0_CLK clock */ 3263 #endif 3264 #if defined(CLOCK_IP_HAS_SWG1_CLK) 3265 /* SWG1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SWG1_CLK clock */ 3266 #endif 3267 /* SWT0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SWT0_CLK clock */ 3268 #if defined(CLOCK_IP_HAS_SWT1_CLK) 3269 /* SWT1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SWT1_CLK clock */ 3270 #endif 3271 #if defined(CLOCK_IP_HAS_SWT2_CLK) 3272 /* SWT2_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SWT2_CLK clock */ 3273 #endif 3274 #if defined(CLOCK_IP_HAS_SWT3_CLK) 3275 /* SWT3_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* SWT3_CLK clock */ 3276 #endif 3277 #if defined(CLOCK_IP_HAS_TCM_CM7_0_CLK) 3278 /* TCM_CM7_0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* TCM_CM7_0_CLK clock */ 3279 #endif 3280 #if defined(CLOCK_IP_HAS_TCM_CM7_1_CLK) 3281 /* TCM_CM7_1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* TCM_CM7_1_CLK clock */ 3282 #endif 3283 /* TEMPSENSE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* TEMPSENSE_CLK clock */ 3284 /* TRACE_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* TRACE_CLK clock */ 3285 /* TRGMUX0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* TRGMUX0_CLK clock */ 3286 #if defined(CLOCK_IP_HAS_TRGMUX1_CLK) 3287 /* TRGMUX1_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* TRGMUX1_CLK clock */ 3288 #endif 3289 #if defined(CLOCK_IP_HAS_TSENSE0_CLK) 3290 /* TSENSE0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* TSENSE0_CLK clock */ 3291 #endif 3292 #if defined(CLOCK_IP_HAS_USDHC_CLK) 3293 /* USDHC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* USDHC_CLK clock */ 3294 #endif 3295 /* WKPU0_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* WKPU0_CLK clock */ 3296 #if defined(CLOCK_IP_HAS_XRDC_CLK) 3297 /* XRDC_CLK clock */ (CLOCK_IP_IRCOSC_OBJECT | CLOCK_IP_XOSC_OBJECT | CLOCK_IP_PLL_OBJECT | CLOCK_IP_SELECTOR_OBJECT | CLOCK_IP_DIVIDER_OBJECT | CLOCK_IP_DIVIDER_TRIGGER_OBJECT | CLOCK_IP_FRAC_DIV_OBJECT | CLOCK_IP_EXT_SIG_OBJECT | CLOCK_IP_GATE_OBJECT | CLOCK_IP_PCFS_OBJECT | CLOCK_IP_CMU_OBJECT) ,/* XRDC_CLK clock */ 3298 #endif 3299 }; 3300 #endif /* CLOCK_IP_DEV_ERROR_DETECT == STD_ON */ 3301 #endif /* CLOCK_IP_DEV_ERROR_DETECT */ 3302 3303 /* Clock stop constant section data */ 3304 #define MCU_STOP_SEC_CONST_32 3305 #include "Mcu_MemMap.h" 3306 3307 3308 /* Clock start constant section data */ 3309 #define MCU_START_SEC_CONST_UNSPECIFIED 3310 #include "Mcu_MemMap.h" 3311 3312 Clock_Ip_CgmMuxType* const Clock_Ip_apxCgm[CLOCK_IP_MC_CGM_INSTANCES_COUNT][CLOCK_IP_MC_CGM_MUXS_COUNT] = 3313 { 3314 { 3315 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_0_CSC)), 3316 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_1_CSC)), 3317 #if defined(CLOCK_IP_HAS_STMB_CLK) 3318 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_2_CSC)), 3319 #else 3320 NULL_PTR, 3321 #endif 3322 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_3_CSC)), 3323 #if defined(CLOCK_IP_HAS_FLEXCANB_CLK) 3324 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_4_CSC)), 3325 #else 3326 NULL_PTR, 3327 #endif 3328 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_5_CSC)), 3329 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_6_CSC)), 3330 #if (defined(CLOCK_IP_HAS_EMAC_RX_CLK) || defined(CLOCK_IP_HAS_GMAC0_RX_CLK)) 3331 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_7_CSC)), 3332 #else 3333 NULL_PTR, 3334 #endif 3335 #if (defined(CLOCK_IP_HAS_EMAC_TX_CLK) || defined(CLOCK_IP_HAS_GMAC0_TX_CLK)) 3336 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_8_CSC)), 3337 #else 3338 NULL_PTR, 3339 #endif 3340 #if defined(CLOCK_IP_HAS_EMAC_TS_CLK) || defined(CLOCK_IP_HAS_GMAC_TS_CLK) 3341 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_9_CSC)), 3342 #else 3343 NULL_PTR, 3344 #endif 3345 #if (defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK) || defined(CLOCK_IP_HAS_QSPI_SFCK_CLK)) 3346 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_10_CSC)), 3347 #else 3348 NULL_PTR, 3349 #endif 3350 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_11_CSC)), 3351 #if defined(CLOCK_IP_HAS_EMAC_TX_RMII_CLK) 3352 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_12_CSC)), 3353 #else 3354 NULL_PTR, 3355 #endif 3356 #if defined(CLOCK_IP_HAS_STMC_CLK) 3357 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_13_CSC)), 3358 #else 3359 NULL_PTR, 3360 #endif 3361 #if defined(CLOCK_IP_HAS_USDHC_CLK) 3362 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_14_CSC)), 3363 #else 3364 NULL_PTR, 3365 #endif 3366 #if (defined(CLOCK_IP_HAS_LFAST_REF_CLK) || defined(CLOCK_IP_HAS_GMAC1_RX_CLK)) 3367 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_15_CSC)), 3368 #else 3369 NULL_PTR, 3370 #endif 3371 #if (defined(CLOCK_IP_HAS_SWG_CLK) || defined(CLOCK_IP_HAS_GMAC1_TX_CLK)) 3372 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_16_CSC)), 3373 #else 3374 NULL_PTR, 3375 #endif 3376 #if defined(CLOCK_IP_HAS_GMAC1_RMII_CLK) 3377 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_17_CSC)), 3378 #else 3379 NULL_PTR, 3380 #endif 3381 #if defined(CLOCK_IP_HAS_STMD_CLK) 3382 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_18_CSC)), 3383 #else 3384 NULL_PTR, 3385 #endif 3386 #if defined(CLOCK_IP_HAS_AES_CLK) 3387 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_19_CSC)), 3388 #else 3389 NULL_PTR, 3390 #endif 3391 }, 3392 }; 3393 volatile Clock_Ip_CgmPcfsType* const Clock_Ip_apxCgmPcfs[CLOCK_IP_MC_CGM_INSTANCES_COUNT] = 3394 { 3395 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM->PCFS_SDUR)), 3396 }; 3397 3398 Clock_Ip_ExtOSCType* const Clock_Ip_apxXosc[CLOCK_IP_XOSC_INSTANCES_ARRAY_SIZE] = 3399 { 3400 (Clock_Ip_ExtOSCType*)IP_FXOSC, 3401 #ifdef IP_SXOSC 3402 (Clock_Ip_ExtOSCType*)IP_SXOSC, 3403 #else 3404 NULL_PTR, 3405 #endif 3406 }; 3407 3408 Clock_Ip_PllType const Clock_Ip_apxPll[CLOCK_IP_PLL_INSTANCES_ARRAY_SIZE] = { 3409 { 3410 IP_PLL, 3411 CLOCK_IP_PLL_DIVIDER_COUNT, 3412 }, 3413 #if defined(CLOCK_IP_HAS_PLLAUX_CLK) 3414 { 3415 IP_PLL_AUX, 3416 CLOCK_IP_PLLAUX_DIVIDER_COUNT, 3417 }, 3418 #else 3419 { 3420 NULL_PTR, 3421 0, 3422 }, 3423 #endif 3424 }; 3425 3426 Clock_Ip_ClockMonitorType* const Clock_Ip_apxCmu[CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE] = 3427 { 3428 (Clock_Ip_ClockMonitorType*)IP_CMU_0, 3429 NULL_PTR, 3430 NULL_PTR, 3431 (Clock_Ip_ClockMonitorType*)IP_CMU_3, 3432 (Clock_Ip_ClockMonitorType*)IP_CMU_4, 3433 (Clock_Ip_ClockMonitorType*)IP_CMU_5, 3434 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 3435 (Clock_Ip_ClockMonitorType*)IP_CMU_6, 3436 #else 3437 NULL_PTR, 3438 #endif 3439 }; 3440 3441 Clock_Ip_NameType const Clock_Ip_aeCmuNames[CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE] = 3442 { 3443 FXOSC_CLK, 3444 RESERVED_CLK, 3445 RESERVED_CLK, 3446 CORE_CLK, 3447 AIPS_PLAT_CLK, 3448 HSE_CLK, 3449 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 3450 CM7_CORE_CLK, 3451 #else 3452 RESERVED_CLK, 3453 #endif 3454 }; 3455 3456 Clock_Ip_CmuInfoType const Clock_Ip_axCmuInfo[CLOCK_IP_CMU_INFO_SIZE] = { 3457 3458 /* CLOCK_IP_CMU_0_INSTANCE */ 3459 { 3460 FXOSC_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3461 FIRC_CLK, /* Name of the reference clock */ 3462 AIPS_SLOW_CLK, /* Name of the bus clock */ 3463 (Clock_Ip_ClockMonitorType*)IP_CMU_0, /* Cmu instance */ 3464 }, 3465 /* Reserved cmu instance */ 3466 { 3467 RESERVED_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3468 RESERVED_CLK, /* Name of the reference clock */ 3469 RESERVED_CLK, /* Name of the bus clock */ 3470 NULL_PTR, /* Cmu instance */ 3471 }, 3472 /* Reserved cmu instance */ 3473 { 3474 RESERVED_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3475 RESERVED_CLK, /* Name of the reference clock */ 3476 RESERVED_CLK, /* Name of the bus clock */ 3477 NULL_PTR, /* Cmu instance */ 3478 }, 3479 /* CLOCK_IP_CMU_3_INSTANCE */ 3480 { 3481 CORE_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3482 FXOSC_CLK, /* Name of the reference clock */ 3483 AIPS_SLOW_CLK, /* Name of the bus clock */ 3484 (Clock_Ip_ClockMonitorType*)IP_CMU_3, /* Cmu instance */ 3485 }, 3486 /* CLOCK_IP_CMU_4_INSTANCE */ 3487 { 3488 AIPS_PLAT_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3489 FIRC_CLK, /* Name of the reference clock */ 3490 AIPS_SLOW_CLK, /* Name of the bus clock */ 3491 (Clock_Ip_ClockMonitorType*)IP_CMU_4, /* Cmu instance */ 3492 }, 3493 /* CLOCK_IP_CMU_5_INSTANCE */ 3494 { 3495 HSE_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3496 FIRC_CLK, /* Name of the reference clock */ 3497 AIPS_SLOW_CLK, /* Name of the bus clock */ 3498 (Clock_Ip_ClockMonitorType*)IP_CMU_5, /* Cmu instance */ 3499 }, 3500 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 3501 /* CLOCK_IP_CMU_6_INSTANCE */ 3502 { 3503 CM7_CORE_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3504 FXOSC_CLK, /* Name of the reference clock */ 3505 AIPS_SLOW_CLK, /* Name of the bus clock */ 3506 (Clock_Ip_ClockMonitorType*)IP_CMU_6, /* Cmu instance */ 3507 }, 3508 #else 3509 /* Reserved cmu instance */ 3510 { 3511 RESERVED_CLK, /* Name of the clock that supports cmu (clock monitor) */ 3512 RESERVED_CLK, /* Name of the reference clock */ 3513 RESERVED_CLK, /* Name of the bus clock */ 3514 NULL_PTR, /* Cmu instance */ 3515 }, 3516 #endif 3517 }; 3518 3519 volatile Clock_Ip_McmePartitionSetType* const Clock_Ip_apxMcMeSetPartitions[CLOCK_IP_MC_ME_PARTITIONS_COUNT] = 3520 { 3521 (volatile Clock_Ip_McmePartitionSetType*)(PRTN0_COFB0_CLKEN_ADDRESS), 3522 3523 (volatile Clock_Ip_McmePartitionSetType*)( ((volatile uint8*)&(IP_MC_ME->PRTN1_COFB0_CLKEN)) ), 3524 #if (!(defined(CLOCK_IP_DERIVATIVE_001) || defined(CLOCK_IP_DERIVATIVE_002))) 3525 (volatile Clock_Ip_McmePartitionSetType*)( ((volatile uint8*)&(IP_MC_ME->PRTN2_COFB0_CLKEN)) ), 3526 #else 3527 NULL_PTR, 3528 #endif 3529 #ifdef CLOCK_IP_DERIVATIVE_006 3530 (volatile Clock_Ip_McmePartitionSetType*)( ((volatile uint8*)&(IP_MC_ME->PRTN3_COFB0_CLKEN)) ), 3531 #else 3532 NULL_PTR, 3533 #endif 3534 3535 }; 3536 3537 volatile const Clock_Ip_McmePartitionGetType* const Clock_Ip_apxMcMeGetPartitions[CLOCK_IP_MC_ME_PARTITIONS_COUNT] = 3538 { 3539 (volatile const Clock_Ip_McmePartitionGetType*)(PRTN0_COFB0_STAT_ADDRESS), 3540 3541 (volatile const Clock_Ip_McmePartitionGetType*)( ((volatile const uint8*)&(IP_MC_ME->PRTN1_COFB0_STAT)) ), 3542 #if (!(defined(CLOCK_IP_DERIVATIVE_001) || defined(CLOCK_IP_DERIVATIVE_002))) 3543 (volatile const Clock_Ip_McmePartitionGetType*)( ((volatile const uint8*)&(IP_MC_ME->PRTN2_COFB0_STAT)) ), 3544 #else 3545 NULL_PTR, 3546 #endif 3547 #ifdef CLOCK_IP_DERIVATIVE_006 3548 (volatile const Clock_Ip_McmePartitionGetType*)( ((volatile const uint8*)&(IP_MC_ME->PRTN3_COFB0_STAT)) ), 3549 #else 3550 NULL_PTR, 3551 #endif 3552 }; 3553 3554 volatile Clock_Ip_McmePartitionTriggerType* const Clock_Ip_apxMcMeTriggerPartitions[CLOCK_IP_MC_ME_PARTITIONS_COUNT] = 3555 { 3556 (volatile Clock_Ip_McmePartitionTriggerType*)( ((volatile uint8*)&(IP_MC_ME->PRTN0_PCONF)) ), 3557 3558 (volatile Clock_Ip_McmePartitionTriggerType*)( ((volatile uint8*)&(IP_MC_ME->PRTN1_PCONF)) ), 3559 #if (!(defined(CLOCK_IP_DERIVATIVE_001) || defined(CLOCK_IP_DERIVATIVE_002))) 3560 (volatile Clock_Ip_McmePartitionTriggerType*)( ((volatile uint8*)&(IP_MC_ME->PRTN2_PCONF)) ), 3561 #else 3562 NULL_PTR, 3563 #endif 3564 #ifdef CLOCK_IP_DERIVATIVE_006 3565 (volatile Clock_Ip_McmePartitionTriggerType*)( ((volatile uint8*)&(IP_MC_ME->PRTN3_PCONF)) ), 3566 #else 3567 NULL_PTR, 3568 #endif 3569 }; 3570 3571 const Clock_Ip_ClockNameSourceType Clock_Ip_aeSourceTypeClockName[CLOCK_IP_PRODUCERS_NO] = { 3572 UKNOWN_TYPE, /*!< CLOCK_IS_OFF */ 3573 IRCOSC_TYPE, /*!< FIRC_CLK */ 3574 IRCOSC_TYPE, /*!< FIRC_STANDBY_CLK */ 3575 IRCOSC_TYPE, /*!< SIRC_CLK */ 3576 IRCOSC_TYPE, /*!< SIRC_STANDBY_CLK */ 3577 XOSC_TYPE, /*!< FXOSC_CLK */ 3578 #if defined(CLOCK_IP_HAS_SXOSC_CLK) 3579 XOSC_TYPE, /*!< SXOSC_CLK */ 3580 #endif 3581 PLL_TYPE, /*!< PLL_CLK */ 3582 #if defined(CLOCK_IP_HAS_PLLAUX_CLK) 3583 PLL_TYPE, /*!< PLLAUX_CLK */ 3584 #endif 3585 PLL_TYPE, /*!< PLL_POSTDIV_CLK */ 3586 #if defined(CLOCK_IP_HAS_PLLAUX_POSTDIV_CLK) 3587 PLL_TYPE, /*!< PLLAUX_POSTDIV_CLK */ 3588 #endif 3589 PLL_TYPE, /*!< PLL_PHI0 */ 3590 PLL_TYPE, /*!< PLL_PHI1 */ 3591 #if defined(CLOCK_IP_HAS_PLLAUX_PHI0_CLK) 3592 PLL_TYPE, /*!< PLLAUX_PHI0_CLK */ 3593 #endif 3594 #if defined(CLOCK_IP_HAS_PLLAUX_PHI1_CLK) 3595 PLL_TYPE, /*!< PLLAUX_PHI1_CLK */ 3596 #endif 3597 #if defined(CLOCK_IP_HAS_PLLAUX_PHI2_CLK) 3598 PLL_TYPE, /*!< PLLAUX_PHI2_CLK */ 3599 #endif 3600 #if defined(CLOCK_IP_HAS_EMAC_MII_RX_CLK) 3601 EXT_CLK_TYPE, /*!< emac_mii_rx */ 3602 #endif 3603 #if defined(CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK) 3604 EXT_CLK_TYPE, /*!< emac_mii_rmii_tx */ 3605 #endif 3606 #if defined(CLOCK_IP_HAS_GMAC0_MII_RX_CLK) 3607 EXT_CLK_TYPE, /*!< GMAC0_mii_rx */ 3608 #endif 3609 #if defined(CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK) 3610 EXT_CLK_TYPE, /*!< GMAC0_mii_rmii_tx */ 3611 #endif 3612 #if defined(CLOCK_IP_HAS_LFAST_REF_EXT_CLK) 3613 EXT_CLK_TYPE, /*!< lfast_ext_ref */ 3614 #endif 3615 #if defined(CLOCK_IP_HAS_SWG_PAD_CLK) 3616 EXT_CLK_TYPE, /*!< swg_pad */ 3617 #endif 3618 UKNOWN_TYPE, /*!< SCS_CLK */ 3619 UKNOWN_TYPE, /*!< CORE_CLK */ 3620 UKNOWN_TYPE, /*!< AIPS_PLAT_CLK */ 3621 UKNOWN_TYPE, /*!< AIPS_SLOW_CLK */ 3622 UKNOWN_TYPE, /*!< HSE_CLK */ 3623 UKNOWN_TYPE, /*!< DCM_CLK */ 3624 #if defined(CLOCK_IP_HAS_LBIST_CLK) 3625 UKNOWN_TYPE, /*!< LBIST_CLK */ 3626 #endif 3627 #if defined(CLOCK_IP_HAS_QSPI_MEM_CLK) 3628 UKNOWN_TYPE, /*!< QSPI_MEM_CLK */ 3629 #endif 3630 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 3631 UKNOWN_TYPE, /*!< CM7_CORE_CLK */ 3632 #endif 3633 UKNOWN_TYPE, /*!< CLKOUT_RUN_CLK */ 3634 }; 3635 3636 3637 const Clock_Ip_NameType Clock_Ip_aeHwPllName[CLOCK_IP_HARDWARE_PLL_ARRAY_SIZE] = 3638 { 3639 PLL_CLK, /* PLL_CLK clock */ 3640 #if defined(CLOCK_IP_HAS_PLLAUX_CLK) 3641 PLLAUX_CLK /* PLLAUX_CLK clock */ 3642 #endif 3643 }; 3644 3645 const Clock_Ip_NameType Clock_Ip_aeHwDfsName[CLOCK_IP_HARDWARE_DFS_ARRAY_SIZE] = 3646 { 3647 RESERVED_CLK, /* RESERVED_CLK Clock */ 3648 }; 3649 3650 const Clock_Ip_ClockExtensionType Clock_Ip_axFeatureExtensions[CLOCK_IP_EXTENSIONS_SIZE] = { 3651 /* Selector value mask Selector value shift Divider value mask Divider value shift */ 3652 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, 0U, 0U}, /* CLOCK_IP_SCS_EXTENSION */ 3653 {MC_CGM_MUX_6_CSC_SELCTL_MASK, MC_CGM_MUX_6_CSC_SELCTL_SHIFT, MC_CGM_MUX_6_DC_0_DIV_MASK, MC_CGM_MUX_6_DC_0_DIV_SHIFT}, /* CLOCK_IP_CLKOUT_RUN_EXTENSION */ 3654 {MC_CGM_MUX_5_CSC_SELCTL_MASK, MC_CGM_MUX_5_CSC_SELCTL_SHIFT, MC_CGM_MUX_5_DC_0_DIV_MASK, MC_CGM_MUX_5_DC_0_DIV_SHIFT}, /* CLOCK_IP_CLKOUT_STANDBY_EXTENSION */ 3655 #if defined(CLOCK_IP_HAS_EMAC_RX_CLK) 3656 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, MC_CGM_MUX_7_DC_0_DIV_MASK, MC_CGM_MUX_7_DC_0_DIV_SHIFT}, /* CLOCK_IP_EMAC_RX_EXTENSION */ 3657 #else 3658 {0U, 0U, 0U, 0U}, 3659 #endif 3660 #if defined(CLOCK_IP_HAS_EMAC_TS_CLK) 3661 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_0_DIV_MASK, MC_CGM_MUX_9_DC_0_DIV_SHIFT}, /* CLOCK_IP_EMAC_TS_EXTENSION */ 3662 #else 3663 {0U, 0U, 0U, 0U}, 3664 #endif 3665 #if defined(CLOCK_IP_HAS_EMAC_TX_CLK) 3666 {MC_CGM_MUX_8_CSC_SELCTL_MASK, MC_CGM_MUX_8_CSC_SELCTL_SHIFT, MC_CGM_MUX_8_DC_0_DIV_MASK, MC_CGM_MUX_8_DC_0_DIV_SHIFT}, /* CLOCK_IP_EMAC_TX_EXTENSION */ 3667 #else 3668 {0U, 0U, 0U, 0U}, 3669 #endif 3670 #if defined(CLOCK_IP_HAS_EMAC_TX_RMII_CLK) 3671 {MC_CGM_MUX_12_CSC_SELCTL_MASK, MC_CGM_MUX_12_CSC_SELCTL_SHIFT, MC_CGM_MUX_12_DC_0_DIV_MASK, MC_CGM_MUX_12_DC_0_DIV_SHIFT}, /* CLOCK_IP_EMAC_TX_RMII_EXTENSION */ 3672 #else 3673 {0U, 0U, 0U, 0U}, 3674 #endif 3675 {MC_CGM_MUX_3_CSC_SELCTL_MASK, MC_CGM_MUX_3_CSC_SELCTL_SHIFT, MC_CGM_MUX_3_DC_0_DIV_MASK, MC_CGM_MUX_3_DC_0_DIV_SHIFT}, /* CLOCK_IP_FLEXCANA_EXTENSION */ 3676 #if defined(CLOCK_IP_HAS_FLEXCANB_CLK) 3677 {MC_CGM_MUX_4_CSC_SELCTL_MASK, MC_CGM_MUX_4_CSC_SELCTL_SHIFT, MC_CGM_MUX_4_DC_0_DIV_MASK, MC_CGM_MUX_4_DC_0_DIV_SHIFT}, /* CLOCK_IP_FLEXCANB_EXTENSION */ 3678 #else 3679 {0U, 0U, 0U, 0U}, 3680 #endif 3681 #if defined(CLOCK_IP_HAS_LFAST_REF_CLK) 3682 {MC_CGM_MUX_15_CSC_SELCTL_MASK, MC_CGM_MUX_15_CSC_SELCTL_SHIFT, MC_CGM_MUX_15_DC_0_DIV_MASK, MC_CGM_MUX_15_DC_0_DIV_SHIFT}, /* CLOCK_IP_LFAST_REF_EXTENSION */ 3683 #else 3684 {0U, 0U, 0U, 0U}, 3685 #endif 3686 #if defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK) 3687 {MC_CGM_MUX_10_CSC_SELCTL_MASK, MC_CGM_MUX_10_CSC_SELCTL_SHIFT, MC_CGM_MUX_10_DC_0_DIV_MASK, MC_CGM_MUX_10_DC_0_DIV_SHIFT}, /* CLOCK_IP_QSPI_2XSFIF_EXTENSION */ 3688 #elif defined(CLOCK_IP_HAS_QSPI_SFCK_CLK) 3689 {MC_CGM_MUX_10_CSC_SELCTL_MASK, MC_CGM_MUX_10_CSC_SELCTL_SHIFT, MC_CGM_MUX_10_DC_0_DIV_MASK, MC_CGM_MUX_10_DC_0_DIV_SHIFT}, /* CLOCK_IP_QSPI_SFCK_EXTENSION */ 3690 #else 3691 {0U, 0U, 0U, 0U}, 3692 #endif 3693 {MC_CGM_MUX_1_CSC_SELCTL_MASK, MC_CGM_MUX_1_CSC_SELCTL_SHIFT, MC_CGM_MUX_1_DC_0_DIV_MASK, MC_CGM_MUX_1_DC_0_DIV_SHIFT}, /* CLOCK_IP_STMA_EXTENSION */ 3694 #if defined(CLOCK_IP_HAS_STMB_CLK) 3695 {MC_CGM_MUX_2_CSC_SELCTL_MASK, MC_CGM_MUX_2_CSC_SELCTL_SHIFT, MC_CGM_MUX_2_DC_0_DIV_MASK, MC_CGM_MUX_2_DC_0_DIV_SHIFT}, /* CLOCK_IP_STMB_EXTENSION */ 3696 #else 3697 {0U, 0U, 0U, 0U}, 3698 #endif 3699 #if defined(CLOCK_IP_HAS_STMC_CLK) 3700 {MC_CGM_MUX_13_CSC_SELCTL_MASK, MC_CGM_MUX_13_CSC_SELCTL_SHIFT, MC_CGM_MUX_13_DC_0_DIV_MASK, MC_CGM_MUX_13_DC_0_DIV_SHIFT}, /* CLOCK_IP_STMC_EXTENSION */ 3701 #else 3702 {0U, 0U, 0U, 0U}, 3703 #endif 3704 #if defined(CLOCK_IP_HAS_SWG_CLK) 3705 {MC_CGM_MUX_16_CSC_SELCTL_MASK, MC_CGM_MUX_16_CSC_SELCTL_SHIFT, MC_CGM_MUX_16_DC_0_DIV_MASK, MC_CGM_MUX_16_DC_0_DIV_SHIFT}, /* CLOCK_IP_SWG_EXTENSION */ 3706 #else 3707 {0U, 0U, 0U, 0U}, 3708 #endif 3709 {MC_CGM_MUX_11_CSC_SELCTL_MASK, MC_CGM_MUX_11_CSC_SELCTL_SHIFT, MC_CGM_MUX_11_DC_0_DIV_MASK, MC_CGM_MUX_11_DC_0_DIV_SHIFT}, /* CLOCK_IP_TRACE_EXTENSION */ 3710 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, MC_CGM_MUX_0_DC_1_DIV_MASK, MC_CGM_MUX_0_DC_1_DIV_SHIFT}, /* CLOCK_IP_AIPS_PLAT_EXTENSION */ 3711 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, MC_CGM_MUX_0_DC_2_DIV_MASK, MC_CGM_MUX_0_DC_2_DIV_SHIFT}, /* CLOCK_IP_AIPS_SLOW_EXTENSION */ 3712 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, MC_CGM_MUX_0_DC_3_DIV_MASK, MC_CGM_MUX_0_DC_3_DIV_SHIFT}, /* CLOCK_IP_HSE_EXTENSION */ 3713 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, MC_CGM_MUX_0_DC_4_DIV_MASK, MC_CGM_MUX_0_DC_4_DIV_SHIFT}, /* CLOCK_IP_DCM_EXTENSION */ 3714 #if defined(CLOCK_IP_HAS_LBIST_CLK) 3715 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, MC_CGM_MUX_0_DC_5_DIV_MASK, MC_CGM_MUX_0_DC_5_DIV_SHIFT}, /* CLOCK_IP_LBIST_EXTENSION */ 3716 #else 3717 {0U, 0U, 0U, 0U}, 3718 #endif 3719 #if defined(CLOCK_IP_HAS_USDHC_CLK) 3720 {MC_CGM_MUX_14_CSC_SELCTL_MASK, MC_CGM_MUX_14_CSC_SELCTL_SHIFT, MC_CGM_MUX_14_DC_0_DIV_MASK, MC_CGM_MUX_14_DC_0_DIV_SHIFT}, /* CLOCK_IP_USDHC_EXTENSION */ 3721 #else 3722 {0U, 0U, 0U, 0U}, 3723 #endif 3724 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, MC_CGM_MUX_0_DC_0_DIV_MASK, MC_CGM_MUX_0_DC_0_DIV_SHIFT}, /* CLOCK_IP_CORE_EXTENSION */ 3725 #if defined(CLOCK_IP_HAS_QSPI_MEM_CLK) 3726 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, MC_CGM_MUX_0_DC_6_DIV_MASK, MC_CGM_MUX_0_DC_6_DIV_SHIFT}, /* CLOCK_IP_QSPI_MEM_EXTENSION */ 3727 #else 3728 {0U, 0U, 0U, 0U}, 3729 #endif 3730 #if defined(CLOCK_IP_HAS_STMD_CLK) 3731 {MC_CGM_MUX_18_CSC_SELCTL_MASK, MC_CGM_MUX_18_CSC_SELCTL_SHIFT, MC_CGM_MUX_18_DC_0_DIV_MASK, MC_CGM_MUX_18_DC_0_DIV_SHIFT}, /* CLOCK_IP_STMD_EXTENSION */ 3732 #else 3733 {0U, 0U, 0U, 0U}, 3734 #endif 3735 #if defined(CLOCK_IP_HAS_GMAC0_RX_CLK) 3736 {MC_CGM_MUX_7_CSC_SELCTL_MASK, MC_CGM_MUX_7_CSC_SELCTL_SHIFT, MC_CGM_MUX_7_DC_0_DIV_MASK, MC_CGM_MUX_7_DC_0_DIV_SHIFT}, /* CLOCK_IP_GMAC0_RX_EXTENSION */ 3737 #else 3738 {0U, 0U, 0U, 0U}, 3739 #endif 3740 #if defined(CLOCK_IP_HAS_GMAC0_TX_CLK) 3741 {MC_CGM_MUX_8_CSC_SELCTL_MASK, MC_CGM_MUX_8_CSC_SELCTL_SHIFT, MC_CGM_MUX_8_DC_0_DIV_MASK, MC_CGM_MUX_8_DC_0_DIV_SHIFT}, /* CLOCK_IP_GMAC0_TX_EXTENSION */ 3742 #else 3743 {0U, 0U, 0U, 0U}, 3744 #endif 3745 #if defined(CLOCK_IP_HAS_GMAC_TS_CLK) 3746 {MC_CGM_MUX_9_CSC_SELCTL_MASK, MC_CGM_MUX_9_CSC_SELCTL_SHIFT, MC_CGM_MUX_9_DC_0_DIV_MASK, MC_CGM_MUX_9_DC_0_DIV_SHIFT}, /* CLOCK_IP_GMAC_TS_EXTENSION */ 3747 #else 3748 {0U, 0U, 0U, 0U}, 3749 #endif 3750 #if defined(CLOCK_IP_HAS_GMAC0_TX_RMII_CLK) 3751 {MC_CGM_MUX_12_CSC_SELCTL_MASK, MC_CGM_MUX_12_CSC_SELCTL_SHIFT, MC_CGM_MUX_12_DC_0_DIV_MASK, MC_CGM_MUX_12_DC_0_DIV_SHIFT}, /* CLOCK_IP_GMAC0_TX_RMII_EXTENSION */ 3752 #else 3753 {0U, 0U, 0U, 0U}, 3754 #endif 3755 #if defined(CLOCK_IP_HAS_GMAC1_RX_CLK) 3756 {MC_CGM_MUX_15_CSC_SELCTL_MASK, MC_CGM_MUX_15_CSC_SELCTL_SHIFT, MC_CGM_MUX_15_DC_0_DIV_MASK, MC_CGM_MUX_15_DC_0_DIV_SHIFT}, /* CLOCK_IP_GMAC1_RX_EXTENSION */ 3757 #else 3758 {0U, 0U, 0U, 0U}, 3759 #endif 3760 #if defined(CLOCK_IP_HAS_GMAC1_TX_CLK) 3761 {MC_CGM_MUX_16_CSC_SELCTL_MASK, MC_CGM_MUX_16_CSC_SELCTL_SHIFT, MC_CGM_MUX_16_DC_0_DIV_MASK, MC_CGM_MUX_16_DC_0_DIV_SHIFT}, /* CLOCK_IP_GMAC1_TX_EXTENSION */ 3762 #else 3763 {0U, 0U, 0U, 0U}, 3764 #endif 3765 #if defined(CLOCK_IP_HAS_GMAC1_RMII_CLK) 3766 {MC_CGM_MUX_17_CSC_SELCTL_MASK, MC_CGM_MUX_17_CSC_SELCTL_SHIFT, MC_CGM_MUX_17_DC_0_DIV_MASK, MC_CGM_MUX_17_DC_0_DIV_SHIFT}, /* CLOCK_IP_GMAC1_RMII_EXTENSION */ 3767 #else 3768 {0U, 0U, 0U, 0U}, 3769 #endif 3770 #if defined(CLOCK_IP_HAS_AES_CLK) 3771 {MC_CGM_MUX_19_CSC_SELCTL_MASK, MC_CGM_MUX_19_CSC_SELCTL_SHIFT, MC_CGM_MUX_19_DC_0_DIV_MASK, MC_CGM_MUX_19_DC_0_DIV_SHIFT}, /* CLOCK_IP_AES_EXTENSION */ 3772 #else 3773 {0U, 0U, 0U, 0U}, 3774 #endif 3775 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK) 3776 {MC_CGM_MUX_0_CSC_SELCTL_MASK, MC_CGM_MUX_0_CSC_SELCTL_SHIFT, MC_CGM_MUX_0_DC_7_DIV_MASK, MC_CGM_MUX_0_DC_7_DIV_SHIFT}, /* CLOCK_IP_CM7_CORE_EXTENSION */ 3777 #else 3778 {0U, 0U, 0U, 0U}, 3779 #endif 3780 3781 }; 3782 3783 3784 Clock_Ip_GateInfoType const Clock_Ip_axGateInfo[CLOCK_IP_GATE_INFO_SIZE] = { 3785 /* Partition value index Selector value index Request value shift Request value mask */ 3786 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ40_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ40_MASK}, /* ADC0_CLK clock */ 3787 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ41_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ41_MASK}, /* ADC1_CLK clock */ 3788 #if defined(CLOCK_IP_HAS_ADC2_CLK) 3789 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ42_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ42_MASK}, /* ADC2_CLK clock */ 3790 #else 3791 {0U, 0U, 0U, 0U}, /* ADC2_CLK clock */ 3792 #endif 3793 #if defined(CLOCK_IP_HAS_ADC3_CLK) 3794 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ43_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ43_MASK}, /* ADC3_CLK clock */ 3795 #else 3796 {0U, 0U, 0U, 0U}, /* ADC3_CLK clock */ 3797 #endif 3798 #if defined(CLOCK_IP_HAS_ADC4_CLK) 3799 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ52_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ52_MASK}, /* ADC4_CLK clock */ 3800 #else 3801 {0U, 0U, 0U, 0U}, /* ADC4_CLK clock */ 3802 #endif 3803 #if defined(CLOCK_IP_HAS_ADC5_CLK) 3804 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ53_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ53_MASK}, /* ADC5_CLK clock */ 3805 #else 3806 {0U, 0U, 0U, 0U}, /* ADC5_CLK clock */ 3807 #endif 3808 #if defined(CLOCK_IP_HAS_ADC6_CLK) 3809 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ54_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ54_MASK}, /* ADC6_CLK clock */ 3810 #else 3811 {0U, 0U, 0U, 0U}, /* ADC6_CLK clock */ 3812 #endif 3813 #if defined(CLOCK_IP_HAS_AXBS_CLK) 3814 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ0_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ0_MASK}, /* AXBS_CLK clock */ 3815 #else 3816 {0U, 0U, 0U, 0U}, /* AXBS_CLK clock */ 3817 #endif 3818 #if defined(CLOCK_IP_HAS_AXBS0_CLK) 3819 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ1_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ1_MASK}, /* AXBS0_CLK clock */ 3820 #else 3821 {0U, 0U, 0U, 0U}, /* AXBS0_CLK clock */ 3822 #endif 3823 #if defined(CLOCK_IP_HAS_AXBS1_CLK) 3824 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ2_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ2_MASK}, /* AXBS1_CLK clock */ 3825 #else 3826 {0U, 0U, 0U, 0U}, /* AXBS1_CLK clock */ 3827 #endif 3828 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ33_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ33_MASK}, /* BCTU0_CLK clock */ 3829 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ92_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ92_MASK}, /* CMP0_CLK clock */ 3830 #if defined(CLOCK_IP_HAS_CMP1_CLK) 3831 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ93_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ93_MASK}, /* CMP1_CLK clock */ 3832 #else 3833 {0U, 0U, 0U, 0U}, /* CMP1_CLK clock */ 3834 #endif 3835 #if defined(CLOCK_IP_HAS_CMP2_CLK) 3836 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ58_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ58_MASK}, /* CMP2_CLK clock */ 3837 #else 3838 {0U, 0U, 0U, 0U}, /* CMP2_CLK clock */ 3839 #endif 3840 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_3_INDEX, MC_ME_PRTN1_COFB3_CLKEN_REQ96_SHIFT, MC_ME_PRTN1_COFB3_CLKEN_REQ96_MASK}, /* CRC0_CLK clock */ 3841 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN1_COFB1_CLKEN_REQ32_SHIFT, MC_ME_PRTN1_COFB1_CLKEN_REQ32_MASK}, /* DMAMUX0_CLK clock */ 3842 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN1_COFB1_CLKEN_REQ33_SHIFT, MC_ME_PRTN1_COFB1_CLKEN_REQ33_MASK}, /* DMAMUX1_CLK clock */ 3843 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ3_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ3_MASK}, /* EDMA0_CLK clock */ 3844 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ4_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ4_MASK}, /* EDMA0_TCD0_CLK clock */ 3845 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ5_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ5_MASK}, /* EDMA0_TCD1_CLK clock */ 3846 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ6_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ6_MASK}, /* EDMA0_TCD2_CLK clock */ 3847 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ7_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ7_MASK}, /* EDMA0_TCD3_CLK clock */ 3848 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ8_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ8_MASK}, /* EDMA0_TCD4_CLK clock */ 3849 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ9_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ9_MASK}, /* EDMA0_TCD5_CLK clock */ 3850 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ10_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ10_MASK}, /* EDMA0_TCD6_CLK clock */ 3851 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ11_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ11_MASK}, /* EDMA0_TCD7_CLK clock */ 3852 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ12_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ12_MASK}, /* EDMA0_TCD8_CLK clock */ 3853 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ13_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ13_MASK}, /* EDMA0_TCD9_CLK clock */ 3854 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ14_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ14_MASK}, /* EDMA0_TCD10_CLK clock */ 3855 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ15_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ15_MASK}, /* EDMA0_TCD11_CLK clock */ 3856 #if defined(CLOCK_IP_HAS_EDMA0_TCD12_CLK) 3857 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ4_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ4_MASK}, /* EDMA0_TCD12_CLK clock */ 3858 #else 3859 {0U, 0U, 0U, 0U}, /* EDMA0_TCD12_CLK clock */ 3860 #endif 3861 #if defined(CLOCK_IP_HAS_EDMA0_TCD13_CLK) 3862 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ5_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ5_MASK}, /* EDMA0_TCD13_CLK clock */ 3863 #else 3864 {0U, 0U, 0U, 0U}, /* EDMA0_TCD13_CLK clock */ 3865 #endif 3866 #if defined(CLOCK_IP_HAS_EDMA0_TCD14_CLK) 3867 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ6_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ6_MASK}, /* EDMA0_TCD14_CLK clock */ 3868 #else 3869 {0U, 0U, 0U, 0U}, /* EDMA0_TCD14_CLK clock */ 3870 #endif 3871 #if defined(CLOCK_IP_HAS_EDMA0_TCD15_CLK) 3872 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ7_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ7_MASK}, /* EDMA0_TCD15_CLK clock */ 3873 #else 3874 {0U, 0U, 0U, 0U}, /* EDMA0_TCD15_CLK clock */ 3875 #endif 3876 #if defined(CLOCK_IP_HAS_EDMA0_TCD16_CLK) 3877 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ8_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ8_MASK}, /* EDMA0_TCD16_CLK clock */ 3878 #else 3879 {0U, 0U, 0U, 0U}, /* EDMA0_TCD16_CLK clock */ 3880 #endif 3881 #if defined(CLOCK_IP_HAS_EDMA0_TCD17_CLK) 3882 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ9_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ9_MASK}, /* EDMA0_TCD17_CLK clock */ 3883 #else 3884 {0U, 0U, 0U, 0U}, /* EDMA0_TCD17_CLK clock */ 3885 #endif 3886 #if defined(CLOCK_IP_HAS_EDMA0_TCD18_CLK) 3887 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ10_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ10_MASK}, /* EDMA0_TCD18_CLK clock */ 3888 #else 3889 {0U, 0U, 0U, 0U}, /* EDMA0_TCD18_CLK clock */ 3890 #endif 3891 #if defined(CLOCK_IP_HAS_EDMA0_TCD19_CLK) 3892 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ11_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ11_MASK}, /* EDMA0_TCD19_CLK clock */ 3893 #else 3894 {0U, 0U, 0U, 0U}, /* EDMA0_TCD19_CLK clock */ 3895 #endif 3896 #if defined(CLOCK_IP_HAS_EDMA0_TCD20_CLK) 3897 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ12_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ12_MASK}, /* EDMA0_TCD20_CLK clock */ 3898 #else 3899 {0U, 0U, 0U, 0U}, /* EDMA0_TCD20_CLK clock */ 3900 #endif 3901 #if defined(CLOCK_IP_HAS_EDMA0_TCD21_CLK) 3902 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ13_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ13_MASK}, /* EDMA0_TCD21_CLK clock */ 3903 #else 3904 {0U, 0U, 0U, 0U}, /* EDMA0_TCD21_CLK clock */ 3905 #endif 3906 #if defined(CLOCK_IP_HAS_EDMA0_TCD22_CLK) 3907 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ14_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ14_MASK}, /* EDMA0_TCD22_CLK clock */ 3908 #else 3909 {0U, 0U, 0U, 0U}, /* EDMA0_TCD22_CLK clock */ 3910 #endif 3911 #if defined(CLOCK_IP_HAS_EDMA0_TCD23_CLK) 3912 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ15_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ15_MASK}, /* EDMA0_TCD23_CLK clock */ 3913 #else 3914 {0U, 0U, 0U, 0U}, /* EDMA0_TCD23_CLK clock */ 3915 #endif 3916 #if defined(CLOCK_IP_HAS_EDMA0_TCD24_CLK) 3917 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ16_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ16_MASK}, /* EDMA0_TCD24_CLK clock */ 3918 #else 3919 {0U, 0U, 0U, 0U}, /* EDMA0_TCD24_CLK clock */ 3920 #endif 3921 #if defined(CLOCK_IP_HAS_EDMA0_TCD25_CLK) 3922 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ17_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ17_MASK}, /* EDMA0_TCD25_CLK clock */ 3923 #else 3924 {0U, 0U, 0U, 0U}, /* EDMA0_TCD25_CLK clock */ 3925 #endif 3926 #if defined(CLOCK_IP_HAS_EDMA0_TCD26_CLK) 3927 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ18_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ18_MASK}, /* EDMA0_TCD26_CLK clock */ 3928 #else 3929 {0U, 0U, 0U, 0U}, /* EDMA0_TCD26_CLK clock */ 3930 #endif 3931 #if defined(CLOCK_IP_HAS_EDMA0_TCD27_CLK) 3932 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ19_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ19_MASK}, /* EDMA0_TCD27_CLK clock */ 3933 #else 3934 {0U, 0U, 0U, 0U}, /* EDMA0_TCD27_CLK clock */ 3935 #endif 3936 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK) 3937 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ20_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ20_MASK}, /* EDMA0_TCD28_CLK clock */ 3938 #else 3939 {0U, 0U, 0U, 0U}, /* EDMA0_TCD28_CLK clock */ 3940 #endif 3941 #if defined(CLOCK_IP_HAS_EDMA0_TCD29_CLK) 3942 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ21_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ21_MASK}, /* EDMA0_TCD29_CLK clock */ 3943 #else 3944 {0U, 0U, 0U, 0U}, /* EDMA0_TCD29_CLK clock */ 3945 #endif 3946 #if defined(CLOCK_IP_HAS_EDMA0_TCD30_CLK) 3947 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ22_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ22_MASK}, /* EDMA0_TCD30_CLK clock */ 3948 #else 3949 {0U, 0U, 0U, 0U}, /* EDMA0_TCD30_CLK clock */ 3950 #endif 3951 #if defined(CLOCK_IP_HAS_EDMA0_TCD31_CLK) 3952 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ23_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ23_MASK}, /* EDMA0_TCD31_CLK clock */ 3953 #else 3954 {0U, 0U, 0U, 0U}, /* EDMA0_TCD31_CLK clock */ 3955 #endif 3956 #if defined(CLOCK_IP_HAS_EIM_CLK) 3957 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ22_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ22_MASK}, /* EIM_CLK clock */ 3958 #else 3959 {0U, 0U, 0U, 0U}, /* EIM_CLK clock */ 3960 #endif 3961 #if defined(CLOCK_IP_HAS_EIM0_CLK) 3962 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN2_COFB2_CLKEN_REQ67_SHIFT, MC_ME_PRTN2_COFB2_CLKEN_REQ67_MASK}, /* EIM0_CLK clock */ 3963 #else 3964 {0U, 0U, 0U, 0U}, /* EIM0_CLK clock */ 3965 #endif 3966 #if defined(CLOCK_IP_HAS_EIM1_CLK) 3967 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN2_COFB2_CLKEN_REQ68_SHIFT, MC_ME_PRTN2_COFB2_CLKEN_REQ68_MASK}, /* EIM1_CLK clock */ 3968 #else 3969 {0U, 0U, 0U, 0U}, /* EIM1_CLK clock */ 3970 #endif 3971 #if defined(CLOCK_IP_HAS_EIM2_CLK) 3972 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN2_COFB2_CLKEN_REQ69_SHIFT, MC_ME_PRTN2_COFB2_CLKEN_REQ69_MASK}, /* EIM2_CLK clock */ 3973 #else 3974 {0U, 0U, 0U, 0U}, /* EIM2_CLK clock */ 3975 #endif 3976 #if defined(CLOCK_IP_HAS_EMAC0_RX_CLK) 3977 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ32_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ32_MASK}, /* EMAC0_RX_CLK clock */ 3978 #else 3979 {0U, 0U, 0U, 0U}, /* EMAC0_RX_CLK clock */ 3980 #endif 3981 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ34_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ34_MASK}, /* EMIOS0_CLK clock */ 3982 #if defined(CLOCK_IP_HAS_EMIOS1_CLK) 3983 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ35_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ35_MASK}, /* EMIOS1_CLK clock */ 3984 #else 3985 {0U, 0U, 0U, 0U}, /* EMIOS1_CLK clock */ 3986 #endif 3987 #if defined(CLOCK_IP_HAS_EMIOS2_CLK) 3988 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ36_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ36_MASK}, /* EMIOS2_CLK clock */ 3989 #else 3990 {0U, 0U, 0U, 0U}, /* EMIOS2_CLK clock */ 3991 #endif 3992 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ23_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ23_MASK}, /* ERM0_CLK clock */ 3993 #if defined(CLOCK_IP_HAS_ERM1_CLK) 3994 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ3_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ3_MASK}, /* ERM1_CLK clock */ 3995 #else 3996 {0U, 0U, 0U, 0U}, /* ERM1_CLK clock */ 3997 #endif 3998 #if defined(CLOCK_IP_HAS_FCCU_CLK) 3999 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_3_INDEX, MC_ME_PRTN1_COFB3_CLKEN_REQ97_SHIFT, MC_ME_PRTN1_COFB3_CLKEN_REQ97_MASK}, /* FCCU_CLK clock */ 4000 #else 4001 {0U, 0U, 0U, 0U}, /* FCCU_CLK clock */ 4002 #endif 4003 #if defined(CLOCK_IP_HAS_FLASH0_CLK) 4004 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ26_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ26_MASK}, /* FLASH0_CLK clock */ 4005 #else 4006 {0U, 0U, 0U, 0U}, /* FLASH0_CLK clock */ 4007 #endif 4008 #if defined(CLOCK_IP_HAS_FLASH0_ALT_CLK) 4009 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ27_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ27_MASK}, /* FLASH0_ALT_CLK clock */ 4010 #else 4011 {0U, 0U, 0U, 0U}, /* FLASH0_ALT_CLK clock */ 4012 #endif 4013 #if defined(CLOCK_IP_HAS_FLASH1_CLK) 4014 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN1_COFB1_CLKEN_REQ59_SHIFT, MC_ME_PRTN1_COFB1_CLKEN_REQ59_MASK}, /* FLASH1_CLK clock */ 4015 #else 4016 {0U, 0U, 0U, 0U}, /* FLASH1_CLK clock */ 4017 #endif 4018 #if defined(CLOCK_IP_HAS_FLASH1_ALT_CLK) 4019 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN1_COFB1_CLKEN_REQ60_SHIFT, MC_ME_PRTN1_COFB1_CLKEN_REQ60_MASK}, /* FLASH1_ALT_CLK clock */ 4020 #else 4021 {0U, 0U, 0U, 0U}, /* FLASH1_ALT_CLK clock */ 4022 #endif 4023 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ65_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ65_MASK}, /* FLEXCAN0_CLK clock */ 4024 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ66_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ66_MASK}, /* FLEXCAN1_CLK clock */ 4025 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ67_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ67_MASK}, /* FLEXCAN2_CLK clock */ 4026 #if defined(CLOCK_IP_HAS_FLEXCAN3_CLK) 4027 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ68_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ68_MASK}, /* FLEXCAN3_CLK clock */ 4028 #else 4029 {0U, 0U, 0U, 0U}, /* FLEXCAN3_CLK clock */ 4030 #endif 4031 #if defined(CLOCK_IP_HAS_FLEXCAN4_CLK) 4032 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ69_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ69_MASK}, /* FLEXCAN4_CLK clock */ 4033 #else 4034 {0U, 0U, 0U, 0U}, /* FLEXCAN4_CLK clock */ 4035 #endif 4036 #if defined(CLOCK_IP_HAS_FLEXCAN5_CLK) 4037 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ70_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ70_MASK}, /* FLEXCAN5_CLK clock */ 4038 #else 4039 {0U, 0U, 0U, 0U}, /* FLEXCAN5_CLK clock */ 4040 #endif 4041 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ73_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ73_MASK}, /* FLEXIO0_CLK clock */ 4042 #if defined(CLOCK_IP_HAS_HSE_MU0_CLK) 4043 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_3_INDEX, MC_ME_PRTN1_COFB3_CLKEN_REQ99_SHIFT, MC_ME_PRTN1_COFB3_CLKEN_REQ99_MASK}, /* HSE_MU0_CLK clock */ 4044 #else 4045 {0U, 0U, 0U, 0U}, /* HSE_MU0_CLK clock */ 4046 #endif 4047 #if defined(CLOCK_IP_HAS_HSE_MU1_CLK) 4048 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ59_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ59_MASK}, /* HSE_MU1_CLK clock */ 4049 #else 4050 {0U, 0U, 0U, 0U}, /* HSE_MU1_CLK clock */ 4051 #endif 4052 #if defined(CLOCK_IP_HAS_JDC_CLK) 4053 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_3_INDEX, MC_ME_PRTN1_COFB3_CLKEN_REQ101_SHIFT, MC_ME_PRTN1_COFB3_CLKEN_REQ101_MASK}, /* JDC_CLK clock */ 4054 #else 4055 {0U, 0U, 0U, 0U}, /* JDC_CLK clock */ 4056 #endif 4057 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ31_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ31_MASK}, /* INTM_CLK clock */ 4058 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ38_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ38_MASK}, /* LCU0_CLK clock */ 4059 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ39_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ39_MASK}, /* LCU1_CLK clock */ 4060 #if defined(CLOCK_IP_HAS_LPI2C0_CLK) 4061 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ84_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ84_MASK}, /* LPI2C0_CLK clock */ 4062 #else 4063 {0U, 0U, 0U, 0U}, /* LPI2C0_CLK clock */ 4064 #endif 4065 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ85_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ85_MASK}, /* LPI2C1_CLK clock */ 4066 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ86_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ86_MASK}, /* LPSPI0_CLK clock */ 4067 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ87_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ87_MASK}, /* LPSPI1_CLK clock */ 4068 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ88_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ88_MASK}, /* LPSPI2_CLK clock */ 4069 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ89_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ89_MASK}, /* LPSPI3_CLK clock */ 4070 #if defined(CLOCK_IP_HAS_LPSPI4_CLK) 4071 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ47_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ47_MASK}, /* LPSPI4_CLK clock */ 4072 #else 4073 {0U, 0U, 0U, 0U}, /* LPSPI4_CLK clock */ 4074 #endif 4075 #if defined(CLOCK_IP_HAS_LPSPI5_CLK) 4076 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ48_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ48_MASK}, /* LPSPI5_CLK clock */ 4077 #else 4078 {0U, 0U, 0U, 0U}, /* LPSPI5_CLK clock */ 4079 #endif 4080 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ74_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ74_MASK}, /* LPUART0_CLK clock */ 4081 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ75_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ75_MASK}, /* LPUART1_CLK clock */ 4082 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ76_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ76_MASK}, /* LPUART2_CLK clock */ 4083 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ77_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ77_MASK}, /* LPUART3_CLK clock */ 4084 #if defined(CLOCK_IP_HAS_LPUART4_CLK) 4085 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ78_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ78_MASK}, /* LPUART4_CLK clock */ 4086 #else 4087 {0U, 0U, 0U, 0U}, /* LPUART4_CLK clock */ 4088 #endif 4089 #if defined(CLOCK_IP_HAS_LPUART5_CLK) 4090 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ79_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ79_MASK}, /* LPUART5_CLK clock */ 4091 #else 4092 {0U, 0U, 0U, 0U}, /* LPUART5_CLK clock */ 4093 #endif 4094 #if defined(CLOCK_IP_HAS_LPUART6_CLK) 4095 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ80_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ80_MASK}, /* LPUART6_CLK clock */ 4096 #else 4097 {0U, 0U, 0U, 0U}, /* LPUART6_CLK clock */ 4098 #endif 4099 #if defined(CLOCK_IP_HAS_LPUART7_CLK) 4100 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ81_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ81_MASK}, /* LPUART7_CLK clock */ 4101 #else 4102 {0U, 0U, 0U, 0U}, /* LPUART7_CLK clock */ 4103 #endif 4104 #if defined(CLOCK_IP_HAS_LPUART8_CLK) 4105 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ35_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ35_MASK}, /* LPUART8_CLK clock */ 4106 #else 4107 {0U, 0U, 0U, 0U}, /* LPUART8_CLK clock */ 4108 #endif 4109 #if defined(CLOCK_IP_HAS_LPUART9_CLK) 4110 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ36_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ36_MASK}, /* LPUART9_CLK clock */ 4111 #else 4112 {0U, 0U, 0U, 0U}, /* LPUART9_CLK clock */ 4113 #endif 4114 #if defined(CLOCK_IP_HAS_LPUART10_CLK) 4115 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ37_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ37_MASK}, /* LPUART10_CLK clock */ 4116 #else 4117 {0U, 0U, 0U, 0U}, /* LPUART10_CLK clock */ 4118 #endif 4119 #if defined(CLOCK_IP_HAS_LPUART11_CLK) 4120 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ38_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ38_MASK}, /* LPUART11_CLK clock */ 4121 #else 4122 {0U, 0U, 0U, 0U}, /* LPUART11_CLK clock */ 4123 #endif 4124 #if defined(CLOCK_IP_HAS_LPUART12_CLK) 4125 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ39_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ39_MASK}, /* LPUART12_CLK clock */ 4126 #else 4127 {0U, 0U, 0U, 0U}, /* LPUART12_CLK clock */ 4128 #endif 4129 #if defined(CLOCK_IP_HAS_LPUART13_CLK) 4130 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ40_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ40_MASK}, /* LPUART13_CLK clock */ 4131 #else 4132 {0U, 0U, 0U, 0U}, /* LPUART13_CLK clock */ 4133 #endif 4134 #if defined(CLOCK_IP_HAS_LPUART14_CLK) 4135 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ41_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ41_MASK}, /* LPUART14_CLK clock */ 4136 #else 4137 {0U, 0U, 0U, 0U}, /* LPUART14_CLK clock */ 4138 #endif 4139 #if defined(CLOCK_IP_HAS_LPUART15_CLK) 4140 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ42_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ42_MASK}, /* LPUART15_CLK clock */ 4141 #else 4142 {0U, 0U, 0U, 0U}, /* LPUART15_CLK clock */ 4143 #endif 4144 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ24_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ24_MASK}, /* MSCM_CLK clock */ 4145 #if defined(CLOCK_IP_HAS_MU2A_CLK) 4146 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ46_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ46_MASK}, /* MU2A_CLK clock */ 4147 #else 4148 {0U, 0U, 0U, 0U}, /* MU2A_CLK clock */ 4149 #endif 4150 #if defined(CLOCK_IP_HAS_MU2B_CLK) 4151 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ47_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ47_MASK}, /* MU2B_CLK clock */ 4152 #else 4153 {0U, 0U, 0U, 0U}, /* MU2B_CLK clock */ 4154 #endif 4155 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ44_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ44_MASK}, /* PIT0_CLK clock */ 4156 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ45_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ45_MASK}, /* PIT1_CLK clock */ 4157 #if defined(CLOCK_IP_HAS_PIT2_CLK) 4158 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN1_COFB1_CLKEN_REQ63_SHIFT, MC_ME_PRTN1_COFB1_CLKEN_REQ63_MASK}, /* PIT2_CLK clock */ 4159 #else 4160 {0U, 0U, 0U, 0U}, /* PIT2_CLK clock */ 4161 #endif 4162 #if defined(CLOCK_IP_HAS_PRAMC0_CLK) 4163 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ25_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ25_MASK}, /* PRAMC0_CLK clock */ 4164 #else 4165 {0U, 0U, 0U, 0U}, /* PRAMC0_CLK clock */ 4166 #endif 4167 #if defined(CLOCK_IP_HAS_PRAMC1_CLK) 4168 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ25_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ25_MASK}, /* PRAMC1_CLK clock */ 4169 #else 4170 {0U, 0U, 0U, 0U}, /* PRAMC1_CLK clock */ 4171 #endif 4172 #if defined(CLOCK_IP_HAS_QSPI0_CLK) 4173 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ51_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ51_MASK}, /* QSPI0_CLK clock */ 4174 #else 4175 {0U, 0U, 0U, 0U}, /* QSPI0_CLK clock */ 4176 #endif 4177 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN1_COFB1_CLKEN_REQ34_SHIFT, MC_ME_PRTN1_COFB1_CLKEN_REQ34_MASK}, /* RTC0_CLK clock */ 4178 #if defined(CLOCK_IP_HAS_SAI0_CLK) 4179 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ91_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ91_MASK}, /* SAI0_CLK clock */ 4180 #else 4181 {0U, 0U, 0U, 0U}, /* SAI0_CLK clock */ 4182 #endif 4183 #if defined(CLOCK_IP_HAS_SAI1_CLK) 4184 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ55_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ55_MASK}, /* SAI1_CLK clock */ 4185 #else 4186 {0U, 0U, 0U, 0U}, /* SAI1_CLK clock */ 4187 #endif 4188 #if defined(CLOCK_IP_HAS_SEMA42_CLK) 4189 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ24_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ24_MASK}, /* SEMA42_CLK clock */ 4190 #else 4191 {0U, 0U, 0U, 0U}, /* SEMA42_CLK clock */ 4192 #endif 4193 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN1_COFB1_CLKEN_REQ42_SHIFT, MC_ME_PRTN1_COFB1_CLKEN_REQ42_MASK}, /* SIUL2_CLK clock */ 4194 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_0_CLK) 4195 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN1_COFB1_CLKEN_REQ36_SHIFT, MC_ME_PRTN1_COFB1_CLKEN_REQ36_MASK}, /* SIUL2_PDAC0_0_CLK clock */ 4196 #else 4197 {0U, 0U, 0U, 0U}, /* SIUL2_PDAC0_0_CLK clock */ 4198 #endif 4199 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_1_CLK) 4200 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN1_COFB1_CLKEN_REQ37_SHIFT, MC_ME_PRTN1_COFB1_CLKEN_REQ37_MASK}, /* SIUL2_PDAC0_1_CLK clock */ 4201 #else 4202 {0U, 0U, 0U, 0U}, /* SIUL2_PDAC0_1_CLK clock */ 4203 #endif 4204 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_0_CLK) 4205 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN1_COFB1_CLKEN_REQ38_SHIFT, MC_ME_PRTN1_COFB1_CLKEN_REQ38_MASK}, /* SIUL2_PDAC1_0_CLK clock */ 4206 #else 4207 {0U, 0U, 0U, 0U}, /* SIUL2_PDAC1_0_CLK clock */ 4208 #endif 4209 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_1_CLK) 4210 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN1_COFB1_CLKEN_REQ39_SHIFT, MC_ME_PRTN1_COFB1_CLKEN_REQ39_MASK}, /* SIUL2_PDAC1_1_CLK clock */ 4211 #else 4212 {0U, 0U, 0U, 0U}, /* SIUL2_PDAC1_1_CLK clock */ 4213 #endif 4214 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_0_CLK) 4215 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN1_COFB1_CLKEN_REQ40_SHIFT, MC_ME_PRTN1_COFB1_CLKEN_REQ40_MASK}, /* SIUL2_PDAC2_0_CLK clock */ 4216 #else 4217 {0U, 0U, 0U, 0U}, /* SIUL2_PDAC2_0_CLK clock */ 4218 #endif 4219 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_1_CLK) 4220 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN1_COFB1_CLKEN_REQ41_SHIFT, MC_ME_PRTN1_COFB1_CLKEN_REQ41_MASK}, /* SIUL2_PDAC2_1_CLK clock */ 4221 #else 4222 {0U, 0U, 0U, 0U}, /* SIUL2_PDAC2_1_CLK clock */ 4223 #endif 4224 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_3_INDEX, MC_ME_PRTN1_COFB3_CLKEN_REQ104_SHIFT, MC_ME_PRTN1_COFB3_CLKEN_REQ104_MASK}, /* STCU0_CLK clock */ 4225 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ29_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ29_MASK}, /* STM0_CLK clock */ 4226 #if defined(CLOCK_IP_HAS_STM1_CLK) 4227 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ29_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ29_MASK}, /* STM1_CLK clock */ 4228 #else 4229 {0U, 0U, 0U, 0U}, /* STM1_CLK clock */ 4230 #endif 4231 #if defined(CLOCK_IP_HAS_STM2_CLK) 4232 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ30_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ30_MASK}, /* STM2_CLK clock */ 4233 #else 4234 {0U, 0U, 0U, 0U}, /* STM2_CLK clock */ 4235 #endif 4236 #if defined(CLOCK_IP_HAS_SWG0_CLK) 4237 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ50_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ50_MASK}, /* SWG0_CLK clock */ 4238 #else 4239 {0U, 0U, 0U, 0U}, /* SWG0_CLK clock */ 4240 #endif 4241 #if defined(CLOCK_IP_HAS_SWG1_CLK) 4242 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ51_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ51_MASK}, /* SWG1_CLK clock */ 4243 #else 4244 {0U, 0U, 0U, 0U}, /* SWG1_CLK clock */ 4245 #endif 4246 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ28_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ28_MASK}, /* SWT0_CLK clock */ 4247 #if defined(CLOCK_IP_HAS_SWT1_CLK) 4248 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ27_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ27_MASK}, /* SWT1_CLK clock */ 4249 #else 4250 {0U, 0U, 0U, 0U}, /* SWT1_CLK clock */ 4251 #endif 4252 #if defined(CLOCK_IP_HAS_TCM_CM7_0_CLK) 4253 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ62_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ62_MASK}, /* TCM_CM7_0_CLK clock */ 4254 #else 4255 {0U, 0U, 0U, 0U}, /* TCM_CM7_0_CLK clock */ 4256 #endif 4257 #if defined(CLOCK_IP_HAS_TCM_CM7_1_CLK) 4258 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ63_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ63_MASK}, /* TCM_CM7_1_CLK clock */ 4259 #else 4260 {0U, 0U, 0U, 0U}, /* TCM_CM7_1_CLK clock */ 4261 #endif 4262 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ95_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ95_MASK}, /* TEMPSENSE_CLK clock */ 4263 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ32_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ32_MASK}, /* TRGMUX0_CLK clock */ 4264 #if defined(CLOCK_IP_HAS_TSENSE0_CLK) 4265 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN1_COFB1_CLKEN_REQ49_SHIFT, MC_ME_PRTN1_COFB1_CLKEN_REQ49_MASK}, /* TSENSE0_CLK clock */ 4266 #else 4267 {0U, 0U, 0U, 0U}, /* TSENSE0_CLK clock */ 4268 #endif 4269 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN1_COFB1_CLKEN_REQ45_SHIFT, MC_ME_PRTN1_COFB1_CLKEN_REQ45_MASK}, /* WKPU0_CLK clock */ 4270 #if defined(CLOCK_IP_HAS_XRDC_CLK) 4271 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ30_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ30_MASK}, /* XRDC_CLK clock */ 4272 #else 4273 {0U, 0U, 0U, 0U}, /* XRDC_CLK clock */ 4274 #endif 4275 #if defined(CLOCK_IP_HAS_USDHC_CLK) 4276 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ57_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ57_MASK}, /* USDHC_CLK clock */ 4277 #else 4278 {0U, 0U, 0U, 0U}, /* USDHC_CLK clock */ 4279 #endif 4280 #if defined(CLOCK_IP_HAS_FLEXCAN6_CLK) 4281 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ71_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ71_MASK}, /* FLEXCAN6_CLK clock */ 4282 #else 4283 {0U, 0U, 0U, 0U}, /* FLEXCAN6_CLK clock */ 4284 #endif 4285 #if defined(CLOCK_IP_HAS_FLEXCAN7_CLK) 4286 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ72_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ72_MASK}, /* FLEXCAN7_CLK clock */ 4287 #else 4288 {0U, 0U, 0U, 0U}, /* FLEXCAN7_CLK clock */ 4289 #endif 4290 #if defined(CLOCK_IP_HAS_SWT2_CLK) 4291 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ28_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ28_MASK}, /* SWT2_CLK clock */ 4292 #else 4293 {0U, 0U, 0U, 0U}, /* SWT2_CLK clock */ 4294 #endif 4295 #if defined(CLOCK_IP_HAS_SIPI0_CLK) 4296 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ60_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ60_MASK}, /* SIPI0_CLK clock */ 4297 #else 4298 {0U, 0U, 0U, 0U}, /* SIPI0_CLK clock */ 4299 #endif 4300 #if defined(CLOCK_IP_HAS_GMAC0_CLK) || defined(CLOCK_IP_HAS_GMAC0_RX_CLK) || defined(CLOCK_IP_HAS_GMAC0_TX_CLK) || defined(CLOCK_IP_HAS_GMAC_TS_CLK) 4301 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ33_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ33_MASK}, /* GMAC0_CLK clock */ 4302 #else 4303 {0U, 0U, 0U, 0U}, /* GMAC0_CLK clock */ 4304 #endif 4305 #if defined(CLOCK_IP_HAS_EIM3_CLK) 4306 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN2_COFB2_CLKEN_REQ70_SHIFT, MC_ME_PRTN2_COFB2_CLKEN_REQ70_MASK}, /* EIM3_CLK clock */ 4307 #else 4308 {0U, 0U, 0U, 0U}, /* EIM3_CLK clock */ 4309 #endif 4310 #if defined(CLOCK_IP_HAS_STM3_CLK) 4311 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN2_COFB0_CLKEN_REQ31_SHIFT, MC_ME_PRTN2_COFB0_CLKEN_REQ31_MASK}, /* STM3_CLK clock */ 4312 #else 4313 {0U, 0U, 0U, 0U}, /* STM3_CLK clock */ 4314 #endif 4315 #if defined(CLOCK_IP_HAS_SWT3_CLK) 4316 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ28_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ28_MASK}, /* SWT3_CLK clock */ 4317 #else 4318 {0U, 0U, 0U, 0U}, /* SWT3_CLK clock */ 4319 #endif 4320 #if defined(CLOCK_IP_HAS_GMAC1_CLK) || defined(CLOCK_IP_HAS_GMAC1_RX_CLK) || defined(CLOCK_IP_HAS_GMAC1_TX_CLK) || defined(CLOCK_IP_HAS_GMAC1_RMII_CLK) 4321 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN2_COFB1_CLKEN_REQ34_SHIFT, MC_ME_PRTN2_COFB1_CLKEN_REQ34_MASK}, /* GMAC1_CLK clock */ 4322 #else 4323 {0U, 0U, 0U, 0U}, /* GMAC1_CLK clock */ 4324 #endif 4325 #if defined(CLOCK_IP_HAS_ADCBIST_CLK) 4326 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN3_COFB2_CLKEN_REQ65_SHIFT, MC_ME_PRTN3_COFB2_CLKEN_REQ65_MASK}, /* ADCBIST_CLK clock */ 4327 #else 4328 {0U, 0U, 0U, 0U}, /* ADCBIST_CLK clock */ 4329 #endif 4330 #if defined(CLOCK_IP_HAS_BCTU1_CLK) 4331 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ49_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ49_MASK}, /* BCTU1_CLK clock */ 4332 #else 4333 {0U, 0U, 0U, 0U}, /* BCTU1_CLK clock */ 4334 #endif 4335 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM0_CLK) 4336 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ58_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ58_MASK}, /* COOLFLUX_D_RAM0_CLK clock */ 4337 #else 4338 {0U, 0U, 0U, 0U}, /* COOLFLUX_D_RAM0_CLK clock */ 4339 #endif 4340 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM1_CLK) 4341 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ59_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ59_MASK}, /* COOLFLUX_D_RAM1_CLK clock */ 4342 #else 4343 {0U, 0U, 0U, 0U}, /* COOLFLUX_D_RAM1_CLK clock */ 4344 #endif 4345 #if defined(CLOCK_IP_HAS_COOLFLUX_DSP16L_CLK) 4346 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ55_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ55_MASK}, /* COOLFLUX_DSP16L_CLK clock */ 4347 #else 4348 {0U, 0U, 0U, 0U}, /* COOLFLUX_DSP16L_CLK clock */ 4349 #endif 4350 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM0_CLK) 4351 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ56_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ56_MASK}, /* COOLFLUX_I_RAM0_CLK clock */ 4352 #else 4353 {0U, 0U, 0U, 0U}, /* COOLFLUX_I_RAM0_CLK clock */ 4354 #endif 4355 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM1_CLK) 4356 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ57_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ57_MASK}, /* COOLFLUX_I_RAM1_CLK clock */ 4357 #else 4358 {0U, 0U, 0U, 0U}, /* COOLFLUX_I_RAM1_CLK clock */ 4359 #endif 4360 #if defined(CLOCK_IP_HAS_DMAMUX2_CLK) 4361 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ40_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ40_MASK}, /* DMAMUX2_CLK clock */ 4362 #else 4363 {0U, 0U, 0U, 0U}, /* DMAMUX2_CLK clock */ 4364 #endif 4365 #if defined(CLOCK_IP_HAS_DMAMUX3_CLK) 4366 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ41_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ41_MASK}, /* DMAMUX3_CLK clock */ 4367 #else 4368 {0U, 0U, 0U, 0U}, /* DMAMUX3_CLK clock */ 4369 #endif 4370 #if defined(CLOCK_IP_HAS_DSPI_MSC_CLK) 4371 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN2_COFB2_CLKEN_REQ66_SHIFT, MC_ME_PRTN2_COFB2_CLKEN_REQ66_MASK}, /* DSPI_MSC_CLK clock */ 4372 #else 4373 {0U, 0U, 0U, 0U}, /* DSPI_MSC_CLK clock */ 4374 #endif 4375 #if defined(CLOCK_IP_HAS_SDA_AP_CLK) 4376 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN1_COFB0_CLKEN_REQ21_SHIFT, MC_ME_PRTN1_COFB0_CLKEN_REQ21_MASK}, /* SDA_AP_CLK clock */ 4377 #else 4378 {0U, 0U, 0U, 0U}, /* SDA_AP_CLK clock */ 4379 #endif 4380 #if defined(CLOCK_IP_HAS_EDMA1_CLK) 4381 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ4_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ4_MASK}, /* EDMA1_CLK clock */ 4382 #else 4383 {0U, 0U, 0U, 0U}, /* EDMA1_CLK clock */ 4384 #endif 4385 #if defined(CLOCK_IP_HAS_EDMA1_TCD0_CLK) 4386 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ5_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ5_MASK}, /* EDMA1_TCD0_CLK clock */ 4387 #else 4388 {0U, 0U, 0U, 0U}, /* EDMA1_TCD0_CLK clock */ 4389 #endif 4390 #if defined(CLOCK_IP_HAS_EDMA1_TCD1_CLK) 4391 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ6_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ6_MASK}, /* EDMA1_TCD1_CLK clock */ 4392 #else 4393 {0U, 0U, 0U, 0U}, /* EDMA1_TCD1_CLK clock */ 4394 #endif 4395 #if defined(CLOCK_IP_HAS_EDMA1_TCD2_CLK) 4396 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ7_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ7_MASK}, /* EDMA1_TCD2_CLK clock */ 4397 #else 4398 {0U, 0U, 0U, 0U}, /* EDMA1_TCD2_CLK clock */ 4399 #endif 4400 #if defined(CLOCK_IP_HAS_EDMA1_TCD3_CLK) 4401 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ8_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ8_MASK}, /* EDMA1_TCD3_CLK clock */ 4402 #else 4403 {0U, 0U, 0U, 0U}, /* EDMA1_TCD3_CLK clock */ 4404 #endif 4405 #if defined(CLOCK_IP_HAS_EDMA1_TCD4_CLK) 4406 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ9_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ9_MASK}, /* EDMA1_TCD4_CLK clock */ 4407 #else 4408 {0U, 0U, 0U, 0U}, /* EDMA1_TCD4_CLK clock */ 4409 #endif 4410 #if defined(CLOCK_IP_HAS_EDMA1_TCD5_CLK) 4411 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ10_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ10_MASK}, /* EDMA1_TCD5_CLK clock */ 4412 #else 4413 {0U, 0U, 0U, 0U}, /* EDMA1_TCD5_CLK clock */ 4414 #endif 4415 #if defined(CLOCK_IP_HAS_EDMA1_TCD6_CLK) 4416 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ11_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ11_MASK}, /* EDMA1_TCD6_CLK clock */ 4417 #else 4418 {0U, 0U, 0U, 0U}, /* EDMA1_TCD6_CLK clock */ 4419 #endif 4420 #if defined(CLOCK_IP_HAS_EDMA1_TCD7_CLK) 4421 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ12_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ12_MASK}, /* EDMA1_TCD7_CLK clock */ 4422 #else 4423 {0U, 0U, 0U, 0U}, /* EDMA1_TCD7_CLK clock */ 4424 #endif 4425 #if defined(CLOCK_IP_HAS_EDMA1_TCD8_CLK) 4426 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ13_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ13_MASK}, /* EDMA1_TCD8_CLK clock */ 4427 #else 4428 {0U, 0U, 0U, 0U}, /* EDMA1_TCD8_CLK clock */ 4429 #endif 4430 #if defined(CLOCK_IP_HAS_EDMA1_TCD9_CLK) 4431 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ14_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ14_MASK}, /* EDMA1_TCD9_CLK clock */ 4432 #else 4433 {0U, 0U, 0U, 0U}, /* EDMA1_TCD9_CLK clock */ 4434 #endif 4435 #if defined(CLOCK_IP_HAS_EDMA1_TCD10_CLK) 4436 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ15_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ15_MASK}, /* EDMA1_TCD10_CLK clock */ 4437 #else 4438 {0U, 0U, 0U, 0U}, /* EDMA1_TCD10_CLK clock */ 4439 #endif 4440 #if defined(CLOCK_IP_HAS_EDMA1_TCD11_CLK) 4441 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ16_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ16_MASK}, /* EDMA1_TCD11_CLK clock */ 4442 #else 4443 {0U, 0U, 0U, 0U}, /* EDMA1_TCD11_CLK clock */ 4444 #endif 4445 #if defined(CLOCK_IP_HAS_EDMA1_TCD12_CLK) 4446 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ17_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ17_MASK}, /* EDMA1_TCD12_CLK clock */ 4447 #else 4448 {0U, 0U, 0U, 0U}, /* EDMA1_TCD12_CLK clock */ 4449 #endif 4450 #if defined(CLOCK_IP_HAS_EDMA1_TCD13_CLK) 4451 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ18_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ18_MASK}, /* EDMA1_TCD13_CLK clock */ 4452 #else 4453 {0U, 0U, 0U, 0U}, /* EDMA1_TCD13_CLK clock */ 4454 #endif 4455 #if defined(CLOCK_IP_HAS_EDMA1_TCD14_CLK) 4456 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ19_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ19_MASK}, /* EDMA1_TCD14_CLK clock */ 4457 #else 4458 {0U, 0U, 0U, 0U}, /* EDMA1_TCD14_CLK clock */ 4459 #endif 4460 #if defined(CLOCK_IP_HAS_EDMA1_TCD15_CLK) 4461 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN0_COFB0_CLKEN_REQ20_SHIFT, MC_ME_PRTN0_COFB0_CLKEN_REQ20_MASK}, /* EDMA1_TCD15_CLK clock */ 4462 #else 4463 {0U, 0U, 0U, 0U}, /* EDMA1_TCD15_CLK clock */ 4464 #endif 4465 #if defined(CLOCK_IP_HAS_EDMA1_TCD16_CLK) 4466 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ0_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ0_MASK}, /* EDMA1_TCD16_CLK clock */ 4467 #else 4468 {0U, 0U, 0U, 0U}, /* EDMA1_TCD16_CLK clock */ 4469 #endif 4470 #if defined(CLOCK_IP_HAS_EDMA1_TCD17_CLK) 4471 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ1_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ1_MASK}, /* EDMA1_TCD17_CLK clock */ 4472 #else 4473 {0U, 0U, 0U, 0U}, /* EDMA1_TCD17_CLK clock */ 4474 #endif 4475 #if defined(CLOCK_IP_HAS_EDMA1_TCD18_CLK) 4476 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ2_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ2_MASK}, /* EDMA1_TCD18_CLK clock */ 4477 #else 4478 {0U, 0U, 0U, 0U}, /* EDMA1_TCD18_CLK clock */ 4479 #endif 4480 #if defined(CLOCK_IP_HAS_EDMA1_TCD19_CLK) 4481 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ3_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ3_MASK}, /* EDMA1_TCD19_CLK clock */ 4482 #else 4483 {0U, 0U, 0U, 0U}, /* EDMA1_TCD19_CLK clock */ 4484 #endif 4485 #if defined(CLOCK_IP_HAS_EDMA1_TCD20_CLK) 4486 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ4_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ4_MASK}, /* EDMA1_TCD20_CLK clock */ 4487 #else 4488 {0U, 0U, 0U, 0U}, /* EDMA1_TCD20_CLK clock */ 4489 #endif 4490 #if defined(CLOCK_IP_HAS_EDMA1_TCD21_CLK) 4491 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ5_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ5_MASK}, /* EDMA1_TCD21_CLK clock */ 4492 #else 4493 {0U, 0U, 0U, 0U}, /* EDMA1_TCD21_CLK clock */ 4494 #endif 4495 #if defined(CLOCK_IP_HAS_EDMA1_TCD22_CLK) 4496 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ6_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ6_MASK}, /* EDMA1_TCD22_CLK clock */ 4497 #else 4498 {0U, 0U, 0U, 0U}, /* EDMA1_TCD22_CLK clock */ 4499 #endif 4500 #if defined(CLOCK_IP_HAS_EDMA1_TCD23_CLK) 4501 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ7_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ7_MASK}, /* EDMA1_TCD23_CLK clock */ 4502 #else 4503 {0U, 0U, 0U, 0U}, /* EDMA1_TCD23_CLK clock */ 4504 #endif 4505 #if defined(CLOCK_IP_HAS_EDMA1_TCD24_CLK) 4506 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ8_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ8_MASK}, /* EDMA1_TCD24_CLK clock */ 4507 #else 4508 {0U, 0U, 0U, 0U}, /* EDMA1_TCD24_CLK clock */ 4509 #endif 4510 #if defined(CLOCK_IP_HAS_EDMA1_TCD25_CLK) 4511 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ9_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ9_MASK}, /* EDMA1_TCD25_CLK clock */ 4512 #else 4513 {0U, 0U, 0U, 0U}, /* EDMA1_TCD25_CLK clock */ 4514 #endif 4515 #if defined(CLOCK_IP_HAS_EDMA1_TCD26_CLK) 4516 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ10_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ10_MASK}, /* EDMA1_TCD26_CLK clock */ 4517 #else 4518 {0U, 0U, 0U, 0U}, /* EDMA1_TCD26_CLK clock */ 4519 #endif 4520 #if defined(CLOCK_IP_HAS_EDMA1_TCD27_CLK) 4521 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ11_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ11_MASK}, /* EDMA1_TCD27_CLK clock */ 4522 #else 4523 {0U, 0U, 0U, 0U}, /* EDMA1_TCD27_CLK clock */ 4524 #endif 4525 #if defined(CLOCK_IP_HAS_EDMA1_TCD28_CLK) 4526 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ12_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ12_MASK}, /* EDMA1_TCD28_CLK clock */ 4527 #else 4528 {0U, 0U, 0U, 0U}, /* EDMA1_TCD28_CLK clock */ 4529 #endif 4530 #if defined(CLOCK_IP_HAS_EDMA1_TCD29_CLK) 4531 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ13_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ13_MASK}, /* EDMA1_TCD29_CLK clock */ 4532 #else 4533 {0U, 0U, 0U, 0U}, /* EDMA1_TCD29_CLK clock */ 4534 #endif 4535 #if defined(CLOCK_IP_HAS_EDMA1_TCD30_CLK) 4536 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ14_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ14_MASK}, /* EDMA1_TCD30_CLK clock */ 4537 #else 4538 {0U, 0U, 0U, 0U}, /* EDMA1_TCD30_CLK clock */ 4539 #endif 4540 #if defined(CLOCK_IP_HAS_EDMA1_TCD31_CLK) 4541 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_0_INDEX, MC_ME_PRTN3_COFB0_CLKEN_REQ15_SHIFT, MC_ME_PRTN3_COFB0_CLKEN_REQ15_MASK}, /* EDMA1_TCD31_CLK clock */ 4542 #else 4543 {0U, 0U, 0U, 0U}, /* EDMA1_TCD31_CLK clock */ 4544 #endif 4545 #if defined(CLOCK_IP_HAS_EFLEX_PWM0_CLK) 4546 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ46_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ46_MASK}, /* EFLEX_PWM0_CLK clock */ 4547 #else 4548 {0U, 0U, 0U, 0U}, /* EFLEX_PWM0_CLK clock */ 4549 #endif 4550 #if defined(CLOCK_IP_HAS_EFLEX_PWM1_CLK) 4551 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ47_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ47_MASK}, /* EFLEX_PWM1_CLK clock */ 4552 #else 4553 {0U, 0U, 0U, 0U}, /* EFLEX_PWM1_CLK clock */ 4554 #endif 4555 #if defined(CLOCK_IP_HAS_ETPU_AB_REGISTERS_CLK) 4556 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ32_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ32_MASK}, /* ETPU_AB_REGISTERS_CLK clock*/ 4557 #else 4558 {0U, 0U, 0U, 0U}, /* ETPU_AB_REGISTERS_CLK clock*/ 4559 #endif 4560 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM1_CLK) 4561 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ36_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ36_MASK}, /* ETPU_CODE_RAM1_CLK clock */ 4562 #else 4563 {0U, 0U, 0U, 0U}, /* ETPU_CODE_RAM1_CLK clock */ 4564 #endif 4565 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM2_CLK) 4566 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ37_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ37_MASK}, /* ETPU_CODE_RAM2_CLK clock */ 4567 #else 4568 {0U, 0U, 0U, 0U}, /* ETPU_CODE_RAM2_CLK clock */ 4569 #endif 4570 #if defined(CLOCK_IP_HAS_ETPU_RAM_MIRROR_CLK) 4571 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ35_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ35_MASK}, /* ETPU_RAM_MIRROR_CLK clock */ 4572 #else 4573 {0U, 0U, 0U, 0U}, /* ETPU_RAM_MIRROR_CLK clock */ 4574 #endif 4575 #if defined(CLOCK_IP_HAS_ETPU_RAM_SDM_CLK) 4576 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ34_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ34_MASK}, /* ETPU_RAM_SDM_CLK clock */ 4577 #else 4578 {0U, 0U, 0U, 0U}, /* ETPU_RAM_SDM_CLK clock */ 4579 #endif 4580 #if defined(CLOCK_IP_HAS_IGF0_CLK) 4581 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ44_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ44_MASK}, /* IGF0_CLK clock */ 4582 #else 4583 {0U, 0U, 0U, 0U}, /* IGF0_CLK clock */ 4584 #endif 4585 #if defined(CLOCK_IP_HAS_LPUART_MSC_CLK) 4586 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN2_COFB2_CLKEN_REQ65_SHIFT, MC_ME_PRTN2_COFB2_CLKEN_REQ65_MASK}, /* LPUART_MSC_CLK clock */ 4587 #else 4588 {0U, 0U, 0U, 0U}, /* LPUART_MSC_CLK clock */ 4589 #endif 4590 #if defined(CLOCK_IP_HAS_SDADC0_CLK) 4591 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ61_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ61_MASK}, /* SDADC0_CLK clock */ 4592 #else 4593 {0U, 0U, 0U, 0U}, /* SDADC0_CLK clock */ 4594 #endif 4595 #if defined(CLOCK_IP_HAS_SDADC1_CLK) 4596 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ62_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ62_MASK}, /* SDADC1_CLK clock */ 4597 #else 4598 {0U, 0U, 0U, 0U}, /* SDADC1_CLK clock */ 4599 #endif 4600 #if defined(CLOCK_IP_HAS_SDADC2_CLK) 4601 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ63_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ63_MASK}, /* SDADC2_CLK clock */ 4602 #else 4603 {0U, 0U, 0U, 0U}, /* SDADC2_CLK clock */ 4604 #endif 4605 #if defined(CLOCK_IP_HAS_SDADC3_CLK) 4606 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN3_COFB2_CLKEN_REQ64_SHIFT, MC_ME_PRTN3_COFB2_CLKEN_REQ64_MASK}, /* SDADC3_CLK clock */ 4607 #else 4608 {0U, 0U, 0U, 0U}, /* SDADC3_CLK clock */ 4609 #endif 4610 #if defined(CLOCK_IP_HAS_TRGMUX1_CLK) 4611 {CLOCK_IP_PARTITION_3_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN3_COFB1_CLKEN_REQ48_SHIFT, MC_ME_PRTN3_COFB1_CLKEN_REQ48_MASK}, /* TRGMUX1_CLK clock */ 4612 #else 4613 {0U, 0U, 0U, 0U}, /* TRGMUX1_CLK clock */ 4614 #endif 4615 #if defined(CLOCK_IP_HAS_PIT3_CLK) 4616 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN1_COFB2_CLKEN_REQ64_SHIFT, MC_ME_PRTN1_COFB2_CLKEN_REQ64_MASK}, /* PIT3_CLK clock */ 4617 #else 4618 {0U, 0U, 0U, 0U}, /* PIT3_CLK clock */ 4619 #endif 4620 #if defined(CLOCK_IP_HAS_AES_ACCEL_CLK) 4621 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_3_INDEX, MC_ME_PRTN1_COFB3_CLKEN_REQ112_SHIFT, MC_ME_PRTN1_COFB3_CLKEN_REQ112_MASK}, /* AES_ACCEL_CLK clock */ 4622 #else 4623 {0U, 0U, 0U, 0U}, /* AES_ACCEL_CLK clock */ 4624 #endif 4625 #if defined(CLOCK_IP_HAS_AES_APP0_CLK) 4626 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_3_INDEX, MC_ME_PRTN1_COFB3_CLKEN_REQ113_SHIFT, MC_ME_PRTN1_COFB3_CLKEN_REQ113_MASK}, /* AES_APP0_CLK clock */ 4627 #else 4628 {0U, 0U, 0U, 0U}, /* AES_APP0_CLK clock */ 4629 #endif 4630 #if defined(CLOCK_IP_HAS_AES_APP1_CLK) 4631 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_3_INDEX, MC_ME_PRTN1_COFB3_CLKEN_REQ114_SHIFT, MC_ME_PRTN1_COFB3_CLKEN_REQ114_MASK}, /* AES_APP1_CLK clock */ 4632 #else 4633 {0U, 0U, 0U, 0U}, /* AES_APP1_CLK clock */ 4634 #endif 4635 #if defined(CLOCK_IP_HAS_AES_APP2_CLK) 4636 {CLOCK_IP_PARTITION_1_INDEX, CLOCK_IP_COLLECTION_3_INDEX, MC_ME_PRTN1_COFB3_CLKEN_REQ115_SHIFT, MC_ME_PRTN1_COFB3_CLKEN_REQ115_MASK}, /* AES_APP2_CLK clock */ 4637 #else 4638 {0U, 0U, 0U, 0U}, /* AES_APP2_CLK clock */ 4639 #endif 4640 #if defined(CLOCK_IP_HAS_AES_APP3_CLK) 4641 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN2_COFB2_CLKEN_REQ72_SHIFT, MC_ME_PRTN2_COFB2_CLKEN_REQ72_MASK}, /* AES_APP3_CLK clock */ 4642 #else 4643 {0U, 0U, 0U, 0U}, /* AES_APP3_CLK clock */ 4644 #endif 4645 #if defined(CLOCK_IP_HAS_AES_APP4_CLK) 4646 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN2_COFB2_CLKEN_REQ73_SHIFT, MC_ME_PRTN2_COFB2_CLKEN_REQ73_MASK}, /* AES_APP4_CLK clock */ 4647 #else 4648 {0U, 0U, 0U, 0U}, /* AES_APP4_CLK clock */ 4649 #endif 4650 #if defined(CLOCK_IP_HAS_AES_APP5_CLK) 4651 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN2_COFB2_CLKEN_REQ74_SHIFT, MC_ME_PRTN2_COFB2_CLKEN_REQ74_MASK}, /* AES_APP5_CLK clock */ 4652 #else 4653 {0U, 0U, 0U, 0U}, /* AES_APP5_CLK clock */ 4654 #endif 4655 #if defined(CLOCK_IP_HAS_AES_APP6_CLK) 4656 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN2_COFB2_CLKEN_REQ75_SHIFT, MC_ME_PRTN2_COFB2_CLKEN_REQ75_MASK}, /* AES_APP6_CLK clock */ 4657 #else 4658 {0U, 0U, 0U, 0U}, /* AES_APP6_CLK clock */ 4659 #endif 4660 #if defined(CLOCK_IP_HAS_AES_APP7_CLK) 4661 {CLOCK_IP_PARTITION_2_INDEX, CLOCK_IP_COLLECTION_2_INDEX, MC_ME_PRTN2_COFB2_CLKEN_REQ76_SHIFT, MC_ME_PRTN2_COFB2_CLKEN_REQ76_MASK}, /* AES_APP7_CLK clock */ 4662 #else 4663 {0U, 0U, 0U, 0U}, /* AES_APP7_CLK clock */ 4664 #endif 4665 #if defined(CLOCK_IP_HAS_MU3A_CLK) 4666 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ49_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ49_MASK}, /* MU3A_CLK clock */ 4667 #else 4668 {0U, 0U, 0U, 0U}, /* MU3A_CLK clock */ 4669 #endif 4670 #if defined(CLOCK_IP_HAS_MU3B_CLK) 4671 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ50_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ50_MASK}, /* MU3B_CLK clock */ 4672 #else 4673 {0U, 0U, 0U, 0U}, /* MU3B_CLK clock */ 4674 #endif 4675 #if defined(CLOCK_IP_HAS_MU4A_CLK) 4676 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ51_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ51_MASK}, /* MU4A_CLK clock */ 4677 #else 4678 {0U, 0U, 0U, 0U}, /* MU4A_CLK clock */ 4679 #endif 4680 #if defined(CLOCK_IP_HAS_MU4B_CLK) 4681 {CLOCK_IP_PARTITION_0_INDEX, CLOCK_IP_COLLECTION_1_INDEX, MC_ME_PRTN0_COFB1_CLKEN_REQ52_SHIFT, MC_ME_PRTN0_COFB1_CLKEN_REQ52_MASK}, /* MU4B_CLK clock */ 4682 #else 4683 {0U, 0U, 0U, 0U}, /* MU4B_CLK clock */ 4684 #endif 4685 4686 }; 4687 4688 4689 /* Clock stop constant section data */ 4690 #define MCU_STOP_SEC_CONST_UNSPECIFIED 4691 #include "Mcu_MemMap.h" 4692 4693 /*================================================================================================== 4694 * GLOBAL VARIABLES 4695 ==================================================================================================*/ 4696 4697 /*================================================================================================== 4698 * LOCAL FUNCTION PROTOTYPES 4699 ==================================================================================================*/ 4700 4701 /*================================================================================================== 4702 * LOCAL FUNCTIONS 4703 ==================================================================================================*/ 4704 4705 /*================================================================================================== 4706 * GLOBAL FUNCTIONS 4707 ==================================================================================================*/ 4708 4709 4710 4711 4712 #ifdef __cplusplus 4713 } 4714 #endif 4715 4716 /** @} */ 4717
